Package substrate with optimized under-bump structure

Abstract

The utility model provides a kind of encapsulation substrate of optimization anti-pad structure, encapsulation substrate includes: in the vertical direction of encapsulation substrate, sequentially stacked multiple wiring layers;The high-speed differential signal transmission from the chip carried by encapsulation substrate to the solder ball of encapsulation substrate wiring structure;Wiring structure includes: it is arranged between adjacent two wiring layers, for transmitting high-speed differential signal between adjacent two wiring layers in the pair of via holes;Anti-pad is set around the pair of via holes on each wiring layer;Wherein, anti-pad electrically isolates the pair of via holes and the wiring layer where it is, and the parameter and / or structure of the anti-pad of each wiring layer are optimized setting, to adjust the via impedance of each wiring layer.The utility model can adjust the impedance of via by designing optimization to the structure and / or parameter of anti-pad, to eliminate or reduce the impedance mutation on high-speed differential signal line.

Description

Technical Field

[0001] This utility model relates to the field of circuit design technology, and in particular to a packaging substrate with an optimized anti-solder pad structure. Background Technology

[0002] A packaging substrate acts as a bridge between a chip and a PCB (Printed Circuit Board), providing electrical connections between them. Packaging substrates can have single-layer, double-layer, and multi-layer structures; for example, a packaging substrate may have eight routing layers. To electrically connect the chip to the PCB, the pads (lead connection points or solder pads) on the chip need to be connected to the solder balls on the packaging substrate via traces. Connecting the pads on the chip to the solder balls requires traces to traverse the multi-layer structure of the packaging substrate.

[0003] By placing vias on each layer of the packaging substrate, traces can cross the layers of the packaging substrate through these vias. Vias include microvias and plated through holes (PTHs); microvias are very small vias (e.g., less than 0.1 mm in diameter) suitable for connecting adjacent layers; PTH holes have relatively larger diameters (e.g., greater than 0.1 mm) and penetrate the entire packaging substrate. Vias are used to connect conductive paths between different layers.

[0004] Figure 1 The structure of the packaging substrate is shown.

[0005] like Figure 1 As shown, the packaging substrate includes multiple wiring layers (such as CU-1, CU-2, CU-3, CU-4, CU-5, CU-6, CU-7, CU-8) and dielectric layers disposed between two wiring layers. Vias in each wiring layer need to penetrate the wiring layer and the dielectric layer adjacent to and below that wiring layer. It should be noted that a dielectric layer is disposed between every two wiring layers in the packaging substrate. Figure 1 Only the dielectric layer between routing layers CU-1 and CU-2 is marked; the dielectric layers between other routing layers are not marked.

[0006] In a package substrate, traces are interconnected across layers via vias in each layer of the package substrate. To provide electrical isolation to the vias, a hollowing-out process is typically performed around the vias in each layer of the package substrate to create a copper-free area (an area without copper foil coverage) around the vias. This copper-free area is called an antipad.

[0007] Figure 2A A schematic diagram of a via in a traditional two-bar model is shown. Figure 2AIn this process, anti-pads 20 are provided around the via 10 to electrically isolate the via 10. Figure 2B Showing Figure 2A The diagram shows the via dimensions of the dual-rod model. d is the center distance between the two holes, r is the radius of the hole, w is the width of the anti-pad, b is the length of the anti-pad, and Dk is the equivalent dielectric constant Er.

[0008] for Figure 2A and Figure 2B The via impedance of the two-bar model shown is defined as follows:

[0009]

[0010] Based on the above formula, the via impedance is determined by the dielectric constant Er of the medium, the radius r of the via, the center distance d between the two vias, and the parameters of the antipad (antipad width w and antipad length b).

[0011] High-speed differential signals are a form of signal used for high-speed data transmission between circuits. High-speed differential signals are transmitted using high-speed differential signal lines. These lines appear in pairs, typically routed adjacent to each other, and transmit signals with opposite polarities. To ensure signal quality, high-speed differential signal lines have stringent routing requirements. For example, the lengths of the two signal lines must match, right-angle routing must be avoided, sufficient spacing must be maintained from other signal lines to prevent interference, and vias that could cause impedance discontinuities must be avoided. Within the package substrate, high-speed differential signal lines are typically routed in two types: surface traces (microstrip lines) and intermediate layer traces (strip lines). For example, if the packaging substrate includes 8 wiring layers, in the case of surface wiring, a high-speed differential signal line is provided on the surface of the first wiring layer of the packaging substrate, and the high-speed differential signal transmitted by the high-speed differential signal line of the first wiring layer goes from the first wiring layer to the eighth wiring layer through vias; in the case of wiring from an intermediate layer, such as from the third wiring layer, a high-speed differential signal line is provided on the surface of the third wiring layer of the packaging substrate, and the transmitted high-speed differential signal goes from the third wiring layer to the eighth wiring layer through vias. Utility Model Content

[0012] For a pair of high-speed differential signal lines, they are interconnected across layers in the package substrate through different vias (microvias and plated through-holes). Changes in conductor material and shape at the vias can cause impedance abrupt changes on the high-speed differential signal lines. Furthermore, to connect the high-speed differential signal lines from the chip to the solder balls on the package substrate, they must pass through several vias. These vias also cause impedance abrupt changes in the high-speed differential signal lines, thus affecting the transmission quality of the high-speed differential signals.

[0013] This utility model embodiment provides a packaging substrate, including:

[0014] Multiple wiring layers are stacked sequentially in the vertical direction of the packaging substrate;

[0015] The wiring structure that transmits high-speed differential signals from the chip carried by the packaging substrate to the solder balls of the packaging substrate;

[0016] The routing structure includes: a pair of vias disposed between two adjacent routing layers for transmitting the high-speed differential signal between the two adjacent routing layers;

[0017] Anti-pads are provided around pairs of vias on each routing layer; wherein the anti-pads electrically isolate the pairs of vias from the routing layer in which they are located, and the parameters and / or structure of the anti-pads of each routing layer are optimized to adjust the via impedance of each routing layer.

[0018] Optionally, the anti-pad region corresponding to the anti-pad includes two arc-shaped regions and a rectangular region connecting the two arc-shaped regions;

[0019] The line connecting the centers of the circles of the two arc-shaped regions coincides with the line connecting the centers of the paired through holes. Furthermore, the two chords of the two arc-shaped regions coincide with the two opposite first sides of the rectangular region, and the arcs of the two arc-shaped regions connect with the opposite vertices of the rectangular region.

[0020] Optionally, a pair of high-speed differential signal lines are laid on the surface of the target routing layer in the plurality of routing layers. The pair of high-speed differential signal lines enter the anti-pad parallel to the direction perpendicular to the second side of the rectangular region, and then turn to connect to one of the vias in the pair on the target routing layer. The second side of the rectangular region is perpendicular to the first side.

[0021] Optionally, the target routing layer is the first routing layer among the plurality of routing layers, and the first routing layer is the routing layer directly adjacent to the chip;

[0022] A pair of high-speed differential signal lines laid on the target trace layer connect the chip and the pair of vias on the target trace layer.

[0023] Optionally, the target routing layer is the Nth routing layer among the plurality of routing layers. The Nth routing layer is different from the first routing layer and different from the last routing layer. The first routing layer is the routing layer directly adjacent to the chip, and the last routing layer is the routing layer directly adjacent to the solder ball.

[0024] A pair of high-speed differential signal lines laid on the target routing layer connects the upper layer pair of vias and the lower layer pair of vias. The upper layer pair of vias connects the Nth routing layer and the (N-1)th routing layer, and the lower layer pair of vias connects the Nth routing layer and the (N+1)th routing layer.

[0025] Optionally, the paired vias arranged in the packaging substrate include paired microvias and paired PTH vias;

[0026] A conductor structure for connecting pairs of PTH vias and pairs of microvias is arranged inside the anti-pad of the Mth routing layer among the plurality of routing layers. The Mth routing layer among the plurality of routing layers is connected to the previous routing layer through pairs of PTH vias and to the next routing layer through pairs of microvias.

[0027] Optionally, the anti-pads in the plurality of routing layers include irregular anti-pads, which are located in at least one of the target routing layer, the adjacent routing layer of the target routing layer, and / or the routing layer associated with the two types of vias.

[0028] The anti-pad region of the irregular anti-pad includes the target area covered by metal.

[0029] Optionally, the projections of the anti-pads of each trace layer in the packaging substrate overlap in both the vertical and horizontal centerlines.

[0030] Optionally, multiple ground holes are provided around the anti-pad of each trace layer, forming a ring structure evenly distributed around the anti-pad.

[0031] Optionally, the center points of paired vias provided in two adjacent wiring layers in the packaging substrate may be aligned or misaligned in the vertical direction.

[0032] Optionally, the anti-pads of the multiple trace layers have the same structure and parameters.

[0033] Optionally, the plurality of routing layers include a first routing layer, a second routing layer, a third routing layer, a fourth routing layer, a fifth routing layer, a sixth routing layer, a seventh routing layer, and an eighth routing layer arranged from top to bottom, wherein the eighth routing layer is connected to the solder ball;

[0034] A via connecting the first routing layer and the second routing layer is a first via, a via connecting the second routing layer and the third routing layer is a second via, and a via connecting the third routing layer and the fourth routing layer is a third via;

[0035] The via connecting the fourth routing layer and the fifth routing layer is the fourth via;

[0036] The via connecting the fifth and sixth routing layers is the fifth via, the via connecting the sixth and seventh routing layers is the sixth via, and the via connecting the seventh and eighth routing layers is the seventh via.

[0037] Optionally, the first via, the second via, the third via, the fifth via, the sixth via, and the seventh via are all microvias, and the fourth via is a PTH via.

[0038] Optionally, the center points of the first via, the second via, the third via, and the fifth via are aligned in the vertical direction;

[0039] The center points of the third via and the fourth via are not aligned in the vertical direction;

[0040] The center points of the fifth via and the sixth via are not aligned in the vertical direction, while the center points of the sixth via and the seventh via are aligned in the vertical direction.

[0041] Optionally, the distance between the paired first via, second via, and third via is 290 μm;

[0042] The distance between the pairs of fourth vias is 650 μm;

[0043] The distance between the paired fifth vias is 290 μm;

[0044] The distance between the paired sixth and seventh vias is 500 μm.

[0045] Optionally, a first conductor structure is arranged between the third via and the fourth via inside the anti-pad of the fourth trace layer, a second conductor structure is arranged between the fourth via and the fifth via inside the anti-pad of the fifth trace layer, and a third conductor structure is arranged between the fifth via and the sixth via inside the anti-pad of the sixth trace layer.

[0046] The high-speed differential signal is transmitted from the third via to the fourth via through the first conductor structure laid on the fourth trace layer, and is transmitted vertically along the fourth via to reach the fifth trace layer.

[0047] The high-speed differential signal is transmitted from the fourth via to the fifth via through the second conductor structure laid on the fifth trace layer, and is transmitted vertically along the fifth via to reach the sixth trace layer.

[0048] The high-speed differential signal is transmitted from the fifth via to the sixth via through the third conductor structure laid on the sixth trace layer, and is transmitted vertically along the sixth via to reach the seventh trace layer.

[0049] Optionally, the target routing layer is the first routing layer. The high-speed differential signal from the chip is transmitted along the high-speed differential signal lines laid on the surface of the first routing layer to the paired first vias, and then sequentially through the paired first vias, the paired second vias, the paired third vias, the paired fourth vias, the paired fifth vias, the paired sixth vias, and the paired seventh vias to the eighth routing layer, so as to reach the solder ball.

[0050] Optionally, the anti-pads of the multiple trace layers have the same anti-pad parameters, wherein the anti-pad parameters include the anti-pad width and the anti-pad hole center distance; the anti-pad width is 690um and the anti-pad hole center distance is 650um.

[0051] Optionally, the anti-pad provided in the second trace layer is an irregular anti-pad, and the anti-pad area corresponding to the irregular anti-pad includes a first target area. The first target area is covered with metal and is rectangular, and is located at a position directly below the horizontal trace area of ​​the first trace layer.

[0052] Optionally, the anti-pad width of the anti-pad corresponding to the first trace layer is 300um and the center distance between the anti-pad holes is 650um;

[0053] The second trace layer corresponds to the same anti-pad width and anti-pad double hole center distance as the first trace layer;

[0054] The anti-pad of the third trace layer has a center-to-center distance of 650µm and a width of 580µm.

[0055] The anti-pad width and anti-pad center distance of the anti-pad corresponding to the fourth trace layer are the same as those of the third trace layer.

[0056] The anti-pad center distance of the anti-pad corresponding to the fifth trace layer is the same as that of the fourth trace layer, and the anti-pad width of the anti-pad corresponding to the fifth trace layer is 700um.

[0057] The anti-pad width and anti-pad center distance of the anti-pad corresponding to the sixth trace layer are the same as those of the fifth trace layer.

[0058] The antipad width and antipad center distance of the antipads of the seventh and eighth routing layers are the same as those of the sixth routing layer.

[0059] Optionally, the anti-pad of the fourth trace layer is an irregularly shaped anti-pad. The anti-pad region corresponding to the irregularly shaped anti-pad includes two second target regions positioned opposite each other relative to the anti-pad centerline. The second target regions are covered with metal and are trapezoidal, with their upper edges close to the anti-pad centerline and their lower edges far from the anti-pad centerline; and / or

[0060] The anti-pad of the fifth trace layer is an irregular anti-pad. The anti-pad area corresponding to the irregular anti-pad includes two third target areas set opposite to the anti-pad center line. The third target areas are covered with metal, are trapezoidal, and have their upper side close to the anti-pad center line and their lower side far away from the anti-pad center line.

[0061] Optionally, the anti-pad width of the anti-pad corresponding to the first trace layer is 320um and the center distance between the anti-pad holes is 650um;

[0062] The second trace layer corresponds to the same anti-pad width and anti-pad double hole center distance as the first trace layer;

[0063] The anti-pad of the third trace layer has a center-to-center distance of 650µm and a width of 690µm.

[0064] The anti-pad width and anti-pad center distance of the fourth trace layer are the same as those of the third trace layer. The upper edge of the second target area is 187um and the center distance of the upper edge from the center point of the anti-pad is 170um.

[0065] The fifth routing layer has the same antipad parameters and antipad structure as the fourth routing layer;

[0066] The anti-pad width of the anti-pad corresponding to the sixth trace layer is 700um, and the center distance between the two anti-pad holes is 650um.

[0067] The antipad width and antipad center distance of the antipads of the seventh and eighth routing layers are the same as those of the sixth routing layer.

[0068] Optionally, the target trace layer is the third trace layer, and a pair of high-speed differential signal lines are arranged on the surface of the third trace layer along the horizontal direction of the packaging substrate. The pair of high-speed differential signal lines transmit the high-speed differential signal from the chip to a pair of third vias.

[0069] The high-speed differential signal transmitted to the paired third via is transmitted sequentially through the paired fourth via, the paired fifth via, the paired sixth via, and the paired seventh via to the eighth trace layer, so as to reach the solder ball.

[0070] Optionally, for each of the third to eighth routing layers, the anti-pad width is 680µm and the anti-pad center distance is 650µm.

[0071] Optionally, the antipad width of the antipad corresponding to the second trace layer is 520um and the center distance between the antipad holes is 650um;

[0072] The anti-pads of the third routing layer and the second routing layer correspond to the same parameters;

[0073] The anti-pad of the fourth trace layer has a center-to-center distance of 650µm and a width of 650µm.

[0074] The anti-pad of the fifth trace layer has a center-to-center distance of 650µm and a width of 680µm.

[0075] The anti-pad width of the anti-pad corresponding to the sixth trace layer is 650um, and the center distance between the two anti-pad holes is 650um.

[0076] The anti-pad width of the anti-pads of the seventh and eighth routing layers is 680um, and the center-to-center distance between the anti-pad holes is 650um.

[0077] Optionally, the anti-pad of the fourth trace layer is an irregular anti-pad, and the anti-pad area corresponding to the irregular anti-pad includes a fourth target area. The fourth target area is covered with metal and is rectangular, and is located at a position directly below the horizontal trace area of ​​the third trace layer.

[0078] Optionally, the anti-pad of the second trace layer is an irregularly shaped anti-pad, and the anti-pad area corresponding to the irregularly shaped anti-pad includes a fifth target area and a sixth target area, wherein the fifth target area and the sixth target area are arranged opposite to each other on both sides of the anti-pad center line; the fifth target area is covered with metal and is rectangular, and the sixth target area is covered with metal and is trapezoidal; the fifth target area is located at a relative position directly above the horizontal trace area of ​​the third trace layer; the upper edge of the trapezoid corresponding to the sixth target area is close to the anti-pad center line;

[0079] The anti-pad of the third trace layer is an irregular anti-pad. The anti-pad area corresponding to the irregular anti-pad includes a seventh target area. The seventh target area is arranged on both sides of the anti-pad center line opposite to the horizontal trace on the surface of the third trace layer. The seventh target area is covered with metal and is trapezoidal. The upper edge of the trapezoid corresponding to the seventh target area is close to the anti-pad center line.

[0080] The anti-pad of the fourth trace layer is an irregularly shaped anti-pad. The anti-pad area corresponding to the irregularly shaped anti-pad includes two eighth target areas positioned opposite each other relative to the anti-pad centerline. The eighth target areas are covered with metal and are trapezoidal, with their upper edges close to the anti-pad centerline and their lower edges far from the anti-pad centerline; and / or

[0081] The anti-pad of the fifth trace layer is an irregular anti-pad. The anti-pad area corresponding to the irregular anti-pad includes two ninth target areas set opposite to the anti-pad center line. The ninth target area is covered with metal and is trapezoidal, with its upper side close to the anti-pad center line and its lower side far away from the anti-pad center line.

[0082] Optionally, the antipad width of the antipad corresponding to the third trace layer is 680um and the center distance between the antipad holes is 650um;

[0083] The second trace layer and the third trace layer have the same anti-pad width and anti-pad double hole center distance;

[0084] The anti-pad of the fourth trace layer has a center-to-center distance of 650µm and a width of 640µm. The upper edge of the trapezoid of the eighth target area is 245µm and the center of the upper edge is 102µm away from the center point of the anti-pad.

[0085] The fifth routing layer has the same antipad parameters and antipad structure as the fourth routing layer;

[0086] The parameters of the anti-solder pads of the sixth routing layer are the same as those of the fourth routing layer;

[0087] The parameters of the anti-solder pads of the seventh and eighth routing layers are the same as those of the fourth routing layer.

[0088] According to an embodiment of the present invention, a pair of vias is provided between adjacent routing layers of the packaging substrate, a routing structure is formed on the packaging substrate to transmit high-speed differential signals from the chip to solder balls of the packaging substrate, and anti-pads are provided around the pair of vias on each routing layer for electrically isolating the pair of vias from the routing layer on which they are located. The parameters and / or structure of the anti-pads of each routing layer are optimized. By optimizing the structure and / or parameters of the anti-pads, the impedance of the vias can be adjusted, thereby eliminating or reducing impedance abrupt changes on the high-speed differential signal lines. Attached Figure Description

[0089] Figure 1 The structure of the packaging substrate is shown;

[0090] Figure 2A This diagram illustrates the vias in a traditional two-bar model.

[0091] Figure 2B Showing Figure 2A A schematic diagram of the through-hole dimensions for the dual-rod model shown;

[0092] Figure 3 This invention illustrates a schematic diagram of the via layout in each layer of the packaging substrate when the high-speed differential signal line is surface-mounted, as provided in an embodiment of the present invention.

[0093] Figure 4 Showing Figure 3 The diagram shows the projection from the first routing layer to the eighth routing layer in the structure shown.

[0094] Figure 5A Showing Figure 3 Projection view of the first routing layer under the anti-pad design method 2 in the structure shown;

[0095] Figure 5B Showing Figure 3 Projection view of the second routing layer under the anti-pad design method 2 in the structure shown;

[0096] Figure 5C Showing Figure 3 The projection view of the third routing layer under the anti-pad design method 2 in the structure shown;

[0097] Figure 5D Showing Figure 3 The projection view of the fourth routing layer under the anti-pad design method 2 in the structure shown;

[0098] Figure 5E Showing Figure 3 The projection view of the fifth routing layer under the anti-pad design method 2 in the structure shown;

[0099] Figure 5F Showing Figure 3 Projection view of the sixth routing layer in anti-pad design method two under the structure shown;

[0100] Figure 5G Showing Figure 3 Projection view of the seventh routing layer in anti-pad design method two under the structure shown;

[0101] Figure 5H Showing Figure 3 Projection view of the eighth routing layer under anti-pad design method two in the structure shown;

[0102] Figure 6A Showing Figure 3 Projection view of the first routing layer under the anti-pad design method 3 in the structure shown;

[0103] Figure 6B Showing Figure 3 Projection view of the second routing layer under the anti-pad design method 3 in the structure shown;

[0104] Figure 6C Showing Figure 3 The projection diagram of the third routing layer under the anti-pad design method 3 in the structure shown;

[0105] Figure 6D Showing Figure 3The projection diagram of the fourth routing layer in anti-pad design method three under the structure shown;

[0106] Figure 7A A comparison chart of insertion loss for three anti-pad design methods when routing high-speed differential signal lines on the surface;

[0107] Figure 7B A comparison chart of return loss for three anti-pad design methods when routing high-speed differential signal lines on the surface;

[0108] Figure 7C Impedance comparison diagram for three anti-pad design methods when routing high-speed differential signal lines on the surface;

[0109] Figure 8 This invention provides a schematic diagram illustrating the via layout of each layer in the packaging substrate when routing the third layer of a high-speed differential signal line.

[0110] Figure 9 Showing Figure 8 The projection diagram of the third routing layer to the eighth routing layer in the structure shown;

[0111] Figure 10A exhibit Figure 8 Projection view of the second routing layer under the anti-pad design method 2 in the structure shown;

[0112] Figure 10B exhibit Figure 8 The projection view of the third routing layer under the anti-pad design method 2 in the structure shown;

[0113] Figure 10C exhibit Figure 8 The projection view of the fourth routing layer under the anti-pad design method 2 in the structure shown;

[0114] Figure 10D exhibit Figure 8 The projection view of the fifth routing layer under the anti-pad design method 2 in the structure shown;

[0115] Figure 10E exhibit Figure 8 Projection view of the sixth routing layer in anti-pad design method two under the structure shown;

[0116] Figure 10F exhibit Figure 8 Projection view of the seventh routing layer in anti-pad design method two under the structure shown;

[0117] Figure 10G exhibit Figure 8 Projection view of the eighth routing layer under anti-pad design method two in the structure shown;

[0118] Figure 11A exhibit Figure 8 The projection diagram of the third routing layer under the anti-pad design method 3 in the structure shown;

[0119] Figure 11B exhibit Figure 8 Projection view of the second routing layer under the anti-pad design method 3 in the structure shown;

[0120] Figure 11C exhibit Figure 8 The projection diagram of the fourth routing layer in anti-pad design method three under the structure shown;

[0121] Figure 11D exhibit Figure 8 The projection diagram of the sixth routing layer in anti-pad design method three under the structure shown;

[0122] Figure 12A A comparison chart of insertion loss for three anti-pad design methods when routing high-speed differential signal lines on the third layer;

[0123] Figure 12B A comparison chart of return loss for three anti-pad design methods when routing high-speed differential signal lines on the third layer;

[0124] Figure 12C This is a comparison diagram of the impedance of three anti-pad design methods when routing high-speed differential signal lines on the third layer. Detailed Implementation

[0125] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present utility model.

[0126] Figure 3 This illustration shows a schematic diagram of the via layout of each layer in the packaging substrate when the high-speed differential signal line is surface-mounted according to an embodiment of the present invention.

[0127] like Figure 3 As shown, the packaging substrate includes a first wiring layer 11, a second wiring layer 12, a third wiring layer 13, a fourth wiring layer 14, a fifth wiring layer 15, a sixth wiring layer 16, a seventh wiring layer 17, and an eighth wiring layer 18 stacked vertically from top to bottom; a dielectric layer is disposed between each adjacent wiring layer. Figure 3Only the dielectric layer 40 between the second routing layer 12 and the third routing layer 13, and the dielectric layer 40 between the third routing layer 13 and the fourth routing layer 14 are labeled. The dielectric layers between other adjacent routing layers are not labeled. For simplicity, all dielectric layers in this embodiment are represented by "40", but it should be understood that the dielectric layers between different adjacent routing layers are different dielectric layers.

[0128] A pair of vias are provided in the first wiring layer 11, with the two vias facing each other and spaced apart. The pair of vias in the first wiring layer 11 penetrate the first wiring layer 11 and the dielectric layer 40 provided between the first wiring layer 11 and the second wiring layer 12, connecting to the second wiring layer 12. A pair of high-speed differential signal lines led from the chip are routed along the horizontal direction of the packaging substrate on the surface of the first wiring layer 11 of the packaging substrate. The high-speed differential signal transmitted from the chip by the high-speed differential signal lines passes through the pair of vias in the first wiring layer 11, through the first wiring layer 11 and the dielectric layer 40 between the first wiring layer 11 and the second wiring layer 12, to the second wiring layer 12.

[0129] A pair of vias is also provided in the second routing layer 12, with the pair of vias positioned opposite each other and spaced apart. These vias penetrate the second routing layer 12 and the dielectric layer 40 between the second routing layer 12 and the third routing layer 13, connecting to the third routing layer 13. The pair of high-speed differential signals traveling to the second routing layer 12 pass through the pair of vias in the second routing layer 12, through the second routing layer 12 and the dielectric layer 40 between the second routing layer 12 and the third routing layer 13, and travel from the second routing layer 12 to the third routing layer 13.

[0130] A pair of vias is also provided in the third routing layer 13. The pair of vias in the third routing layer 13 are opposite to each other and spaced apart. The pair of vias passes through the third routing layer 13 and the dielectric layer 40 provided between the third routing layer 13 and the fourth routing layer 14, and connects to the fourth routing layer 14. The pair of high-speed differential signals that reach the third routing layer 13 pass through the pair of vias in the third routing layer 13, through the third routing layer 13 and the dielectric layer 40 between the third routing layer 13 and the fourth routing layer 14, and from the third routing layer 13 to the fourth routing layer 14.

[0131] A pair of vias is provided in the fourth routing layer 14. The pair of vias in the fourth routing layer 14 are opposite to each other and spaced apart. The pair of vias passes through the fourth routing layer 14 and the dielectric layer 40 between the fourth routing layer 14 and the fifth routing layer 15, and connects to the fifth routing layer 15. The pair of high-speed differential signals that reach the fourth routing layer 14 pass through the pair of vias in the fourth routing layer 14, through the fourth routing layer 14 and the dielectric layer 40 between the fourth routing layer 14 and the fifth routing layer 15, and from the fourth routing layer 14 to the fifth routing layer 15.

[0132] A pair of vias is also provided in the fifth routing layer 15. The pair of vias in the fifth routing layer 15 are opposite to each other and spaced apart. The pair of vias passes through the fifth routing layer 15 and the dielectric layer 40 between the fifth routing layer 15 and the sixth routing layer 16, and connects to the sixth routing layer 16. The pair of high-speed differential signals that reach the fifth routing layer 15 pass through the pair of vias in the fifth routing layer 15, through the fifth routing layer 15 and the dielectric layer 40 between the fifth routing layer 15 and the sixth routing layer 16, and from the fifth routing layer 15 to the sixth routing layer 16.

[0133] A pair of vias is also provided in the sixth routing layer 16. The pair of vias in the sixth routing layer 16 are opposite to each other and spaced apart. The pair of vias passes through the sixth routing layer 16 and the dielectric layer 40 provided between the sixth routing layer 16 and the seventh routing layer 17, and connects to the seventh routing layer 17. The pair of high-speed differential signals that reach the sixth routing layer 16 pass through the pair of vias in the sixth routing layer 16, through the sixth routing layer 16 and the dielectric layer 40 between the sixth routing layer 16 and the seventh routing layer 17, and from the sixth routing layer 16 to the seventh routing layer 17.

[0134] A pair of vias is also provided in the seventh routing layer 17. The pair of vias in the seventh routing layer 17 are opposite to each other and spaced apart. The pair of vias passes through the seventh routing layer 17 and the dielectric layer 40 provided between the seventh routing layer 17 and the eighth routing layer 18, and connects to the eighth routing layer 18. The pair of high-speed differential signals that reach the seventh routing layer 17 pass through the pair of vias in the seventh routing layer 17, through the seventh routing layer 17 and the dielectric layer 40 between the seventh routing layer 17 and the eighth routing layer 18, and from the seventh routing layer 17 to the eighth routing layer 18.

[0135] Solder balls 30 are placed below the eighth routing layer 18. High-speed differential signals from the chip pass through the vias in each layer of the packaging substrate, through each routing layer, and reach the solder balls 30 on the packaging substrate.

[0136] For example, in a package substrate, the center points of paired vias on adjacent routing layers may be aligned or misaligned in the vertical direction. For instance, the center points of paired vias on the first routing layer 11, the second routing layer 12, and the third routing layer 13 are aligned in the vertical direction. The center points of vias on the fourth routing layer 14 and the third routing layer 13 are misaligned in the vertical direction. For example, the distance between the center points of the horizontal projections of the vias on the fourth routing layer 14 and the vias on the third routing layer 13 is not zero. The center points of vias on the fifth routing layer 15 and the sixth routing layer 16 are misaligned in the vertical direction. The center points of vias on the sixth routing layer 16 and the seventh routing layer 17 are aligned in the vertical direction. For example, the center distance between pairs of vias on the first routing layer 11, the second routing layer 12, and the third routing layer 13 is 290um; the center distance between pairs of vias on the fourth routing layer 14 is 650um; the center distance between pairs of vias on the fifth routing layer 15 is 290um; and the center distance between pairs of vias on the sixth routing layer 16 and the seventh routing layer 17 is 500um.

[0137] As another example, when the center points of paired vias on two adjacent routing layers are not aligned in the vertical direction, after the high-speed differential signal travels from the upper routing layer to the lower routing layer, it first propagates horizontally along the surface of the lower routing layer. This is achieved by routing a conductor structure or providing horizontal traces on the surface of the lower routing layer for high-speed differential signal transmission. After the high-speed differential signal travels from the via position on the upper routing layer to the via position on the lower routing layer, it continues to travel downwards through the via on the lower routing layer. For example, the vias on the fourth routing layer 14 and the vias on the third routing layer 13 are not aligned in the vertical direction. After a pair of high-speed differential signals reach the fourth routing layer 14 through a pair of vias on the third routing layer 13, they first transmit signals along a horizontally arranged conductor structure on the surface of the fourth routing layer 14. After moving from the corresponding via position on the third routing layer 13 to the via position on the fourth routing layer 14, they continue to transmit through the vias on the fourth routing layer 14.

[0138] As another example, vias include microvias 101 and PTH vias 102. Different vias are provided on different routing layers in the package substrate. For example, the paired vias provided on the first routing layer 11, the second routing layer 12, and the third routing layer 13 are all microvias 101. The paired vias provided on the fourth routing layer 14 are PTH vias 102. The paired vias provided on the fifth routing layer 15, the sixth routing layer 16, and the seventh routing layer 17 are also microvias 101. It should be noted that in Figure 3Only the paired vias (such as microvia 101) set in the first routing layer 11 and the paired vias (such as PTH via 102) set in the fourth routing layer 14 are marked; the paired vias set in other routing layers are not marked.

[0139] As another example, a cutout area is provided on the surface of the first wiring layer 11 at a position away from the paired via area. Figure 3 (Not marked in the text) This cutout area has no metal covering and no vias are provided in this cutout area. This cutout area is used to attach a chip that leads out a pair of high-speed differential signal lines. After the chip is attached to this area, the pins on the chip used to transmit high-speed differential signals are connected to a pair of vias provided on the first trace layer 11 through a pair of high-speed differential signal lines along the surface of the first trace layer 11.

[0140] exist Figure 3 In the via layout structure shown, the via impedance of each routing layer is adjusted by optimizing the structure and parameters of the anti-pad of the via in each routing layer, so as to eliminate or reduce impedance abrupt changes on the high-speed differential signal line.

[0141] This invention allows for the optimization of the structure and parameters of the anti-soldering pads of vias in each routing layer of the packaging substrate through various methods. Three methods are briefly described below as examples.

[0142] Method 1: Set the parameters of the anti-pads corresponding to the vias on each routing layer of the package substrate to be the same. For example... Figure 3 The structure shown has the same structure and parameters for the anti-pads corresponding to the paired vias in each of the first to eighth routing layers 18.

[0143] Figure 4 Showing Figure 3 The diagram shows the projection of the first routing layer 11 to the eighth routing layer 18 in the structure shown. Figure 4 As shown, the anti-pad region includes two arc-shaped regions and a rectangular region connecting the two arc-shaped regions; the line connecting the centers of the circles of the two arc-shaped regions coincides with the line connecting the centers of the paired vias; the two chords of the two arc-shaped regions coincide with the two opposite sides of the rectangular region, and the arcs of the two arc-shaped regions connect with the opposite vertices of the rectangular region, such as the two chords of the two arc-shaped regions coinciding with the two opposite sides of the rectangular region. In this embodiment of the invention, when optimizing the structure and parameters of the anti-pad corresponding to the vias, the following anti-pad parameters can be optimized: anti-pad width W and anti-pad double-hole center distance S; wherein, the anti-pad width W is the length of the two chords of the two arc-shaped regions or the length of the opposite sides of the rectangular region, and the anti-pad double-hole center distance S is the length of the opposite sides of the rectangular region or the distance between the two chords of the two arc-shaped regions.

[0144] When a pair of high-speed differential signal lines from the chip are routed horizontally along the surface of the first trace layer 11 of the package substrate, the pair of high-speed differential signal lines are parallel to each other and perpendicular to the opposite sides of the rectangular area. They enter the anti-pad from the middle of one side and turn to the via near the middle of the anti-pad. It should be noted that the pair of high-speed differential signal lines cannot turn at right angles or larger angles.

[0145] exist Figure 4 In the package substrate, the anti-pads corresponding to the vias of each routing layer overlap in both the vertical and horizontal centerlines. The parameters of the anti-pads corresponding to the vias of each routing layer in the package substrate are as follows: the anti-pad width W is 690um, and the anti-pad center distance S is 650um.

[0146] Method 2: In Figure 3 Under the via layout structure shown, the anti-pad structure and parameters are optimized. For example, in... Figure 3 In the structure shown, the parameters of the anti-pads corresponding to the vias in each of the first routing layers 11 to the eighth routing layers 18 are individually optimized. The parameters of the anti-pads corresponding to the vias in each routing layer are as follows: Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G as well as Figure 5H As shown.

[0147] like Figure 5A As shown, the parameters of the anti-pads corresponding to the pair of microvias set in the first routing layer 11 are: anti-pad width W is 300um, and the center distance S between the two anti-pad holes is 650um. Figure 5A The distance S1 between the centers of the two micropores in a pair is 290 μm.

[0148] like Figure 5B As shown, the anti-pads corresponding to the pair of microvias in the second routing layer 12 have the same parameters as the anti-pads corresponding to the pair of microvias in the first routing layer 11: the anti-pad width W is 300µm, and the center-to-center distance S between the two anti-pad holes is 650µm. Figure 5B The distance S1 between the centers of the two paired micropores is 290 μm. For example... Figure 3In the structure shown, a pair of high-speed differential signal lines start from the first trace layer 11, and there is a section of trace in the horizontal direction on the surface of the first trace layer 11. To avoid affecting the signal quality transmitted by the trace in the horizontal direction on the surface of the first trace layer 11, a rectangular area is set in the anti-pad of the second trace layer 12 at a position relative to the horizontal trace in the anti-pad of the first trace layer 11. This rectangular area is not hollowed out, but is covered with metal such as copper foil. By setting a metal layer, the high conductivity and low resistivity of the metal layer can be utilized to avoid affecting the signal quality transmitted by the trace in the horizontal direction on the surface of the first trace layer 11. Of course, the size and shape of this rectangular area can be flexibly adjusted according to actual needs, and are not limited here. Since the high-speed differential signal lines from the chip are routed horizontally along the surface of the first trace layer 11 of the package substrate, a rectangular region or other shaped metal region set in the anti-pad of the second trace layer 12 is located below the horizontal trace position of the first trace layer 11. This metal region is formed at that position to adjust the impedance caused by the high-speed differential signal lines passing through vias. In this embodiment, such an anti-pad with an uncut, metal-covered area is called an irregular anti-pad. The structure of an irregular anti-pad can vary; for example, it can be a rectangular or trapezoidal region with an uncut, metal-covered area. Furthermore, the position of the uncut, metal-covered area within the anti-pad region can also be varied.

[0149] For the third routing layer 13, such as Figure 5C As shown, the center distance S between the anti-pad holes is kept consistent with the previous two trace layers and is set to 650um, while the anti-pad width W is increased and set to 580um. Figure 5C The distance S1 between the centers of the two micropores in the middle is 290um, consistent with the previous two wiring layers.

[0150] like Figure 3 In the structure shown, the third routing layer 13 has a pair of microvias 101 that penetrate the third routing layer 13 and the dielectric layer 40 between the third routing layer 13 and the fourth routing layer 14, connecting to the fourth routing layer 14. The fourth routing layer 14 has a pair of PTH vias 102. The anti-pads of the fourth routing layer 14 contain the corresponding pair of microvias 101 from the third routing layer 13 and the pair of PTH vias 102 from the fourth routing layer 14. Figure 5D As shown, the parameters of the anti-pad set on the fourth routing layer 14 are as follows: the anti-pad width W is consistent with that of the third routing layer 13 and is set to 580um; the anti-pad double hole center distance S is consistent with that of the first three routing layers and is set to 650um. Figure 5DThe distance S1 between the centers of the two pairs of microvias is 290um, consistent with the first three trace layers. The center distance K between the microvias and PTH holes is 180um. The distance S2 between the centers of the two pairs of PTH holes is 290um + 180um * 2 = 650um, which is consistent with the center distance S of the anti-pad double holes.

[0151] like Figure 3 The structure shown also includes a pair of microvias 101 and a pair of PTH vias 102 on the anti-pad of the fifth routing layer 15. (As shown...) Figure 5E As shown, the parameters of the anti-pad set on the fifth routing layer 15 are as follows: the anti-pad width W is increased compared to the fourth routing layer 14 and is set to 700um; the anti-pad double hole center distance S is kept consistent with the first four routing layers and is set to 650um. Figure 5E The distance S1 between the centers of two pairs of microvias is 290um, consistent with the first four trace layers; the center distance K between the microvias and PTH holes is 180um, and the distance S2 between the centers of two pairs of PTH holes is 290um + 180um * 2 = 650um, which is consistent with the center distance S of the anti-pad double hole.

[0152] For the sixth routing layer 16, the microvia 101 connecting the fifth routing layer 15 and the sixth routing layer 16 and the microvia 101 connecting the sixth routing layer 16 and the seventh routing layer 17 are not aligned in the vertical direction at their center points. There are two pairs of microvia 101 on the anti-pad of the sixth routing layer 16. For example... Figure 5F As shown, the parameters of the anti-pad set on the sixth routing layer 16 are as follows: the anti-pad width W is the same as that of the fifth routing layer 15, and the anti-pad width W is set to 700um; the anti-pad double hole center distance S is kept consistent with the first five routing layers and is set to 650um. Figure 5F The pair of microvias connecting the fifth routing layer 15 and the sixth routing layer 16 have a distance S1 between the centers of the two microvias of 290um. The pair of microvias connecting the sixth routing layer 16 and the seventh routing layer 17 have a distance S1' between the centers of the two microvias of 500um. The distance N between the centers of two microvias on the same side is 105um.

[0153] For the seventh routing layer 17, such as Figure 5G As shown, the width W of the anti-pad is consistent with the sixth routing layer 16 and is set to 700um; the center distance S of the anti-pad double hole is consistent with the first six routing layers and is set to 650um. Figure 5G The middle layer connects the paired microvias of the sixth routing layer 16 and the seventh routing layer 17, and the distance S1' between the centers of the two microvias is 500um.

[0154] For the eighth routing layer 18, such as Figure 5HAs shown, the width W of the anti-pad is consistent with the seventh routing layer 17, set to 700um; the center-to-center distance S between the anti-pad vias is consistent with the first seven routing layers, set to 650um. The paired microvias connecting the seventh routing layer 17 and the eighth routing layer 18 have a center-to-center distance S1' of 500um. Figure 5H In the anti-pad, the two larger circles formed are the projections of the solder ball pads onto the anti-pad.

[0155] In this embodiment, in addition to providing vias within the antipad, vias, such as ground vias, are also provided around the antipad. By providing vias around the antipad, the capacitive impedance of the vias within the antipad is changed, thereby adjusting the impedance of the vias.

[0156] It should be noted that in the embodiments of this utility model, the projections of the anti-solder pads of each trace layer in the packaging substrate overlap in both the vertical and horizontal center lines.

[0157] The following example illustrates the scenario of setting vias around antipads:

[0158] like Figure 5A As shown, a plurality of vias are arranged around the anti-pad of the first routing layer 11, and these vias are referred to as the first surrounding vias. The first surrounding vias penetrate the first routing layer 11 and connect to the second routing layer 12. Figure 5B The second wiring layer 12 shown is... Figure 5A The parameters of the anti-pads on the first routing layer 11 shown are consistent. Figure 5B A first surrounding via also appears around the anti-pad of the second routing layer 12 shown. The first surrounding via connects the first routing layer 11 and the second routing layer 12 around the anti-pad. For example... Figure 5B and Figure 5C As shown, the parameters of the anti-pads of the second routing layer 12 and the third routing layer 13 differ. The width W of the anti-pad of the third routing layer 13 is increased. A ring of vias is also provided on the outer side of the anti-pad of the second routing layer 12, opposite to the outer side of the anti-pad of the third routing layer 13. These vias are called second surrounding vias. On the second routing layer 12, the second surrounding vias are farther from the anti-pad than the first surrounding vias. The second surrounding vias penetrate the second routing layer 12 and connect to the third routing layer 13. Figure 5C A second surrounding via also appears around the antipad of the third routing layer 13 shown. The second surrounding via connects the second routing layer 12 and the third routing layer 13 around the antipad.

[0159] like Figure 5C and Figure 5D As shown, the anti-pad width W and the anti-pad center distance S of the fourth routing layer 14 and the third routing layer 13 are consistent. The second surrounding via also penetrates the third routing layer 13 to connect to the fourth routing layer 14. Figure 5D The fourth routing layer 14 shown has a second surrounding via around the antipad, which connects the second routing layer 12, the third routing layer 13, and the fourth routing layer 14.

[0160] like Figure 5D As shown, a ring of vias is provided around the anti-pad of the fourth routing layer 14, opposite to the anti-pad of the fifth routing layer 15. These vias are referred to as third surrounding vias. On the fourth routing layer 14, the third surrounding vias are farther from the anti-pad than the second surrounding vias, and are also larger in size. The third surrounding vias penetrate the fourth routing layer 14 and connect to the fifth routing layer 15. Figure 5E A third surrounding via also appears around the antipad of the fifth routing layer 15 shown. The third surrounding via surrounds the antipad to connect the fourth routing layer 14 and the fifth routing layer 15.

[0161] like Figure 5E As shown, a ring of vias is also provided around the anti-pad on the outer side of the fifth routing layer 15, and these vias are referred to as the fourth surrounding vias. On the fifth routing layer 15, the fourth surrounding vias are closer to the anti-pad than the third surrounding vias, and the size of the fourth surrounding vias is smaller than that of the third surrounding vias. The fourth surrounding vias penetrate from the fifth routing layer 15 to the sixth routing layer 16. Figure 5F A fourth surrounding via also appears around the antipad of the sixth routing layer 16 shown. The fourth surrounding via is located around the antipad to connect the fifth routing layer 15 and the sixth routing layer 16.

[0162] like Figure 5F , 5G As shown in 5H, the anti-pad width W and anti-pad center distance S of the anti-pads of the sixth routing layer 16, the seventh routing layer 17, and the eighth routing layer 18 are all the same. The fourth surrounding via penetrates the sixth routing layer 16, the seventh routing layer 17, and the eighth routing layer 18. Figure 5G A fourth via appears around the anti-pad of the seventh routing layer 17, as shown. Figure 5H A fourth surrounding via appears around the antipad of the eighth routing layer 18 shown. The fourth surrounding via connects the fifth routing layer 15, the sixth routing layer 16, the seventh routing layer 17 and the eighth routing layer 18 around the antipad.

[0163] It should be noted that in the above examples, the second surrounding via can extend from the second routing layer 12 to the fourth routing layer 14, and the fourth surrounding via can extend from the fifth routing layer 15 to the eighth routing layer 18. For example, the center points of the surrounding vias connecting the second routing layer 12 to the fourth routing layer 14 are aligned in the vertical direction, and the center points of the surrounding vias connecting the fifth routing layer 15 to the eighth routing layer 18 are also aligned in the vertical direction. In practical applications, when setting vias around the antipad, the vias connecting adjacent routing layers can be set according to actual needs. That is, the center points of vias on different layers can be aligned or misaligned in the vertical direction, and are not limited to the situations listed above.

[0164] By setting vias around the antipad, impedance can be adjusted using vias to further reduce impedance abrupt changes on high-speed differential signal lines.

[0165] Method 3: In Figure 3 Under the via layout structure shown, the anti-pad structure and parameters are optimized. For example, the anti-pads in some of the routing layers from the first routing layer 11 to the eighth routing layer 18 are designed as irregular structures. It should be noted that when the anti-pad structure and parameters of each routing layer of the package substrate are optimized using method three, the center lines of the projections of the anti-pads of each routing layer in the package substrate overlap in both the vertical and horizontal directions.

[0166] For the first routing layer 11, such as Figure 6A As shown, the anti-pad width W is set to 320um, and the anti-pad center distance S is set to 650um. Figure 6A The distance S1 between the centers of the two micropores in a pair is 290 μm.

[0167] For the second routing layer 12, such as Figure 6B As shown, the antipad width W and the antipad center distance S of the second trace layer 12 and the adjacent first trace layer 11 are set to be the same, such as the antipad width W being 320um and the antipad center distance S being 650um. Figure 6B The distance S1 between the centers of the two paired microvias is 290um. The anti-pad in the second routing layer 12 is an irregularly shaped anti-pad, as shown in the image. Figure 5B Similarly, a rectangular area covered with copper foil is provided in the anti-pad area. This rectangular area is positioned directly below the horizontal trace position in the anti-pad of the first trace layer 11, so as to adjust the impedance by setting a metal area at that position. For example, it can adjust the impedance change caused by the first trace layer 11 being hollowed out.

[0168] For the third routing layer 13, such as Figure 6CAs shown, the center distance S between the anti-pad holes is kept consistent with the previous two trace layers and is set to 650um, while the anti-pad width W is increased and set to 690um. Figure 6C The distance S1 between the centers of the two micropores in the middle is 290um, consistent with the previous two wiring layers.

[0169] For the fourth routing layer 14, such as Figure 6D As shown, the width W of the anti-pad is consistent with that of the third trace layer 13, and is set to 690um. The center distance S between the two holes of the anti-pad is consistent with that of the first three trace layers, and is set to 650um. Figure 6D The distance S1 between the centers of the two paired microvias in the fourth routing layer is 290um, consistent with the first three routing layers. The center distance K between the microvias and PTH holes is 180um. The distance S2 between the centers of the two paired PTH holes is 290um + 180um * 2 = 650um, consistent with the center distance S between the two holes on the anti-pad. The anti-pad of the fourth routing layer 14 is an irregularly shaped anti-pad. For example, two symmetrical, uncut trapezoidal areas are set opposite each other within the rectangular area of ​​the anti-pad, and the trapezoidal areas are covered with copper foil. The two trapezoidal areas are symmetrically arranged along the center line of the anti-pad, and the lower sides of the two trapezoidal areas coincide with the left and right sides of the rectangular area, respectively. The upper side of the trapezoidal area is a = 187um, and the distance c from the center of the upper side of the trapezoid to the center point of the anti-pad is 170um. The impedance of the vias is adjusted by setting trapezoidal areas on the anti-pad of the fourth routing layer 14 to reduce impedance abrupt changes.

[0170] The anti-pad of the fifth routing layer 15 is designed exactly the same as that of the anti-pad of the fourth routing layer 14. As an optional implementation, the irregular anti-pads of the fourth routing layer 14 and the fifth routing layer 15 can also be designed in other shapes, such as setting other shaped metal covering areas such as rectangles, squares, circles, irregular polygons, etc. in the anti-pad area.

[0171] For the sixth routing layer 16, the seventh routing layer 17, and the eighth routing layer 18, the anti-pad structure and parameter settings in Method 3 are the same as those in Method 2, and will not be elaborated further here. In Method 3, vias also need to be set around the anti-pads. The setting of vias around the anti-pads is similar to that in Method 2. It should be noted that since the anti-pad width W from the third routing layer 13 to the eighth routing layer 18 is not significantly different, and the center distance S between the two anti-pad holes remains consistent, vias can be set from the third routing layer 13 through the eighth routing layer 18. Of course, these can also be flexibly set according to actual needs, and will not be further elaborated here.

[0172] Figure 7A This is a comparison chart of insertion loss for three anti-pad design methods when routing high-speed differential signal lines on the surface.

[0173] Figure 7AIn the graph, the horizontal axis represents frequency, and the vertical axis represents insertion loss. At the same frequency, the closer the insertion loss is to 0, the better the effect. Based on the comparison of Method 1, Method 2, and Method 3, it can be seen that in the frequency range of 0 to 10 GHz, the difference in insertion loss between Method 1, Method 2, and Method 3 is not significant. In the frequency range of 10 to 32 GHz, for any given frequency value, the insertion loss of Method 3 is always closest to 0, followed by Method 2, while the insertion loss of Method 1 is always far from 0. Therefore, the effect of Method 3 is better than that of Method 2 and Method 3.

[0174] Figure 7B This is a comparison chart showing the return loss of three anti-pad design methods when routing high-speed differential signal lines on the surface.

[0175] Figure 7B The horizontal axis represents frequency, and the vertical axis represents return loss. At the same frequency, the further the return loss is from 0, the better the performance. Based on the comparison of Method 1, Method 2, and Method 3, it can be seen that: in the frequency range of 0 to 1.8 GHz, Method 3 has better return loss than Method 2; in the frequency range of 1.8 to 15 GHz, Method 2 has better return loss than Method 3; in the frequency range of 15 to 32 GHz, Method 3 has better return loss than Method 2; and in the frequency range of 0 to 32 GHz, the return loss of both Method 3 and Method 2 is consistently better than that of Method 1. For comparing the return loss of Method 2 and Method 3, for example, one or more reference frequencies can be set, and the effects of the two methods can be compared based on these reference frequencies. For example, with reference frequencies of 16 GHz and 28 GHz, at both reference frequencies, the return loss of Method 3 is better than that of Method 2, indicating that Method 3 is superior to Method 2. For another example... Figure 7B The diagram shown illustrates the frequency sweep range. In actual use, devices or products cannot operate across the entire frequency sweep; instead, they operate within a specific frequency band. The comparison of return loss between Method 2 and Method 3 allows for comparison of the return loss between Method 2 and Method 3 within the actual operating range of the product. For example, when operating between 15GHz and 20GHz, Method 3 performs better than Method 2.

[0176] Figure 7C This is a comparison diagram of impedances for three anti-pad design methods when routing high-speed differential signal lines on the surface.

[0177] Figure 7C The horizontal axis represents time, and the vertical axis represents impedance. The smaller the impedance change, the better the effect. Based on the comparison of Method 1, Method 2, and Method 3, it can be seen that Method 3 has the smallest impedance change, followed by Method 2, while Method 1 has the largest impedance change. Therefore, Method 3 is better than Method 2, and Method 2 is better than Method 1.

[0178] Based on the above Figure 7A , Figure 7B as well as Figure 7C As can be seen from the data, regardless of insertion loss, return loss, or impedance matching, method three performs best, method two second best, and method one performs worst.

[0179] Figure 8 This illustration shows a schematic diagram of the via layout in each layer of the packaging substrate when the high-speed differential signal line is routed on the third layer according to an embodiment of this utility model.

[0180] In the vertical direction of the packaging substrate, a third wiring layer 13, a fourth wiring layer 14, a fifth wiring layer 15, a sixth wiring layer 16, a seventh wiring layer 17, and an eighth wiring layer 18 are stacked sequentially from top to bottom. The packaging substrate also includes a first wiring layer and a second wiring layer arranged sequentially on top of the third wiring layer. Figure 8 The first and second routing layers are not shown. A dielectric layer is placed between each adjacent routing layer. Figure 8 The dielectric layer 40 between the third routing layer 13 and the fourth routing layer 14, and between the fifth routing layer 15 and the sixth routing layer 16 is only marked. The dielectric layers between other adjacent routing layers are not marked.

[0181] A pair of vias are provided in the third routing layer 13. The pair of vias in the third routing layer 13 are opposite to each other and spaced apart. The pair of vias penetrate the third routing layer 13 and the dielectric layer 40 provided between the third routing layer 13 and the fourth routing layer 14 and connect to the fourth routing layer 14.

[0182] The third routing layer 13 includes paired vias (referred to as vias M) connecting the third routing layer 13 and the fourth routing layer 14. Figure 8 In addition to the vias shown in the third routing layer, a pair of vias (referred to as vias P) connecting the second and third routing layers 13 are also provided. Figure 8 (Not shown in the image) The area where via P is located is far from the area where via M is located, and a cut-out area is set around via P. The high-speed differential signal provided by the chip on the surface of the first trace layer is connected to the third trace layer 13 through vias connecting the first trace layer and the second trace layer, and the second trace layer and the third trace layer 13. On the third trace layer 13, a pair of high-speed differential signal lines corresponding to the high-speed differential signal are connected to the pair of vias P and the pair of vias M, so that the high-speed differential signal is transmitted to the pair of vias M through the pair of high-speed differential signal lines, and then transmitted to the fourth trace layer 14 through the pair of vias M set on the third trace layer 13 and the dielectric layer 40 between the third trace layer 13 and the fourth trace layer 14.

[0183] When the pair of high-speed differential signal lines are routed along the horizontal direction of the package substrate on the surface of the third trace layer 13 of the package substrate, the pair of high-speed differential signal lines are parallel to each other and perpendicular to the side of the anti-pad rectangular area. They enter the anti-pad from the middle position of the side and turn to the via near the middle position. Similarly, they cannot turn at a right angle or a larger angle.

[0184] A pair of vias is provided in the fourth routing layer 14, the pair of vias being opposite to each other and spaced apart. The pair of vias penetrates the fourth routing layer 14 and the dielectric layer 40 provided between the fourth routing layer 14 and the fifth routing layer 15, connecting to the fifth routing layer 15. A pair of vias is also provided in the fifth routing layer 15, the pair of vias being opposite to each other and spaced apart. The pair of vias penetrates the fifth routing layer 15 and the dielectric layer 40 provided between the fifth routing layer 15 and the sixth routing layer 16, connecting to the sixth routing layer. Layer 16; A pair of vias are also provided in the sixth routing layer 16, the pair of vias are opposite to each other and spaced apart, and the dielectric layer 40 provided between the sixth routing layer 16 and the seventh routing layer 17 is connected to the seventh routing layer 17; A pair of vias are also provided in the seventh routing layer 17, the pair of vias are opposite to each other and spaced apart, and the dielectric layer 40 provided between the seventh routing layer 17 and the eighth routing layer 18 is connected to the eighth routing layer 18.

[0185] The paired high-speed differential signals reaching the fourth routing layer 14 are transmitted to the eighth routing layer 18 via paired vias connecting the fourth routing layer 14 to the fifth routing layer 15, the fifth routing layer 15 to the sixth routing layer 16, the sixth routing layer 16 to the seventh routing layer 17, and the seventh routing layer 17 to the eighth routing layer 18. Solder balls 30 are located below the eighth routing layer 18. The high-speed differential signals from the chip pass through the vias through each routing layer and are transmitted to the solder balls 30 on the packaging substrate, thus allowing the signals to be transmitted to the PCB board.

[0186] In a package substrate, pairs of vias on adjacent routing layers may have their center points aligned or misaligned in the vertical direction. For example, in... Figure 8 In the structure shown, the center points of the paired vias on the third routing layer 13 and the paired vias on the fourth routing layer 14 are not aligned in the vertical direction. The center points of the paired vias on the fourth routing layer 14 and the paired vias on the fifth routing layer 15 are not aligned in the vertical direction. The center points of the paired vias on the fifth routing layer 15 and the paired vias on the sixth routing layer 16 are not aligned in the vertical direction. The center points of the paired vias on the sixth routing layer 16 and the paired vias on the seventh routing layer 17 are aligned in the vertical direction.

[0187] For cases where the center points of paired vias on two adjacent routing layers are not aligned in the vertical direction, such as... Figure 8 In the adjacent fourth routing layer 14 and fifth routing layer 15, and the adjacent fifth routing layer 15 and sixth routing layer 16, after the high-speed differential signal is transmitted from the adjacent upper routing layer to the lower routing layer, it needs to be transmitted horizontally first, and then transmitted vertically through the via after reaching the via position.

[0188] Different vias can be set in different wiring layers of the packaging substrate. Figure 8 In this configuration, vias are divided into two categories: microvias 101 and PTH vias 102. Microvias 101 connect the third routing layer 13 and the fourth routing layer 14; PTH vias 102 connect the fourth routing layer 14 and the fifth routing layer 15; and microvias 101 connect the fifth routing layer 15 and the sixth routing layer 16, the sixth routing layer 16 and the seventh routing layer 17, and the seventh routing layer 17 and the eighth routing layer 18. Figure 8 The label indicates the microvia 101 provided on the third routing layer 13, the PTH via 102 provided on the fourth routing layer 14, and the microvia 101 provided on the fifth routing layer 15 and the sixth routing layer 16.

[0189] exist Figure 8 In the via layout structure shown, the via impedance can be adjusted by reasonably setting the via size of each routing layer and the structure and parameters of the antipad corresponding to the via, thereby eliminating or reducing impedance changes on high-speed differential signal lines.

[0190] exist Figure 8 As shown in the via layout structure, the via size and the structure and parameters of the corresponding anti-pads in each routing layer of the package substrate can be optimized in various ways. Three methods are briefly introduced below as examples.

[0191] Method 1: Set the parameters of the anti-soldering pads corresponding to the vias in the third to eighth routing layers 18 of the packaging substrate to be the same.

[0192] like Figure 8 In the structure shown, from the third routing layer 13 to the eighth routing layer 18, the width W of the anti-pad corresponding to the paired vias in each routing layer remains consistent, and the center distance S between the anti-pads corresponding to the paired vias in each routing layer remains consistent. Figure 9 Showing Figure 8 The diagram shows a projection of the third routing layer 13 to the eighth routing layer 18 in the structure shown. Figure 9 In the package substrate, the anti-pads corresponding to the vias of each routing layer overlap in both the vertical and horizontal directions. For each routing layer from the third to the eighth routing layer 18 in the package substrate, the parameters for the anti-pads corresponding to the vias are: anti-pad width W is 680µm, and the anti-pad center-to-center distance S is 650µm.

[0193] Method 2: Optimize the anti-pad structure and parameters, such as setting different parameters and / or structures for the anti-pads corresponding to the vias in some of the wiring layers from the second to the eighth wiring layer 18 in the package substrate.

[0194] like Figure 10A As shown, the parameters of the anti-pad corresponding to the second routing layer are: anti-pad width W is 520um, and the anti-pad center distance S is 650um. It should be noted that the anti-pad of the second routing layer is not set around the paired vias. This anti-pad is located directly above the anti-pad formed by the third routing layer 13 and is the same size, used for impedance adjustment.

[0195] like Figure 10B As shown, the parameters of the anti-pads corresponding to the pair of microvias set in the third routing layer 13 are: anti-pad width W is 520um, and anti-pad center distance S is 650um. Figure 10B The distance S1 between the centers of the two microvias in the pair is 290um. After the high-speed differential signal from the chip is transmitted to the third wiring layer 13 through the first and second wiring layers, a pair of high-speed differential signal lines are arranged on the surface of the third wiring layer 13 along the horizontal direction of the packaging substrate. The high-speed differential signal transmitted to the third wiring layer 13 is transmitted to the pair of vias provided on the third wiring layer 13 through the arranged pair of high-speed differential signal lines, so that the high-speed differential signal continues to be transmitted through the vias.

[0196] like Figure 8 In the structure shown, the third routing layer 13 to the fourth routing layer 14 are connected by a pair of microvias 101, and the fourth routing layer 14 to the fifth routing layer 15 are connected by a pair of PTH vias 102. A pair of microvias 101 and a pair of PTH vias 102 exist on the anti-pad of the fourth routing layer 14. Figure 10C As shown, the parameters of the antipad set on the fourth routing layer 14 are as follows: the antipad width W is increased compared with the third routing layer 13, the antipad width W of the fourth routing layer 14 is set to 650um, and the antipad double hole center distance S is kept consistent with the previous routing layer and set to 650um. Figure 10CThe distance S1 between the centers of the two paired microvias is maintained at 290um, the center distance K between the microvias and PTH holes is 180um, and the distance S2 between the centers of the two paired PTH holes is 290um + 180um * 2 = 650um, consistent with the center distance S between the anti-pad and the dual-hole. Since the high-speed differential signal lines are routed on the surface of the third routing layer 13, to avoid affecting the signal quality transmitted by the horizontal routing on the surface of the third routing layer 13, the anti-pad on the fourth routing layer is an irregularly shaped anti-pad. For example, in the anti-pad of the fourth routing layer 14, a rectangular area is set relative to the horizontal routing in the anti-pad of the third routing layer 13 (directly below the horizontal routing position of the third routing layer 13). This rectangular area is covered with copper foil. By setting a metal layer, the high conductivity and low resistivity of the metal layer can be utilized to avoid affecting the signal quality transmitted by the horizontal routing on the surface of the third routing layer 13. Of course, the size and shape of this rectangular area can be flexibly adjusted according to actual needs, and are not limited here. By forming a metal region below the horizontal trace position of the third trace layer 11, the impedance caused by the high-speed differential signal line passing through the via can be adjusted.

[0197] like Figure 8 In the structure shown, the fourth routing layer 14 to the fifth routing layer 15 are connected by a pair of PTH vias 102, and the fifth routing layer 15 to the sixth routing layer 16 are connected by a pair of microvias 101. A pair of microvias 101 and a pair of PTH vias 102 exist on the anti-pad of the fifth routing layer 15. Figure 10D As shown, the parameters of the antipad set on the fifth routing layer 15 are as follows: the antipad width W is increased compared to the fourth routing layer 14, the antipad width W of the fifth routing layer 15 is set to 680um, and the antipad double hole center distance S is kept consistent with the previous routing layer and set to 650um. Figure 10D The distance S1 between the centers of the two paired microvias is kept at 290um, the center distance K between the microvia and the PTH hole is 180um, and the distance S2 between the centers of the two paired PTH holes is 290um + 180um * 2 = 650um, which is consistent with the center distance S of the anti-pad double hole.

[0198] like Figure 8 In the structure shown, the microvia 101 connecting the fifth routing layer 15 and the sixth routing layer 16 is not aligned vertically with the microvia 101 connecting the sixth routing layer 16 and the seventh routing layer 17. There are two pairs of microvia 101 on the anti-pad of the sixth routing layer 16. For example... Figure 10E As shown, the parameters of the anti-pad set on the sixth routing layer 16 are: the anti-pad width W is kept consistent with the fourth routing layer 14 and set to 650um, and the anti-pad double hole center distance S is kept consistent with the previous routing layer and set to 650um. Figure 10EThe distance S1 between the centers of two pairs of microvias connecting the fifth routing layer 15 and the sixth routing layer 16 is kept at 290um, the distance S1' between the centers of two pairs of microvias connecting the seventh routing layer 17 and the sixth routing layer 16 is 500um, and the center distance N between two microvias on the same side is 105um.

[0199] For the seventh routing layer 17, such as Figure 10F As shown, the anti-pad width W is increased compared to the sixth routing layer 16, and the anti-pad width W of the seventh routing layer 17 is set to 680um; the center distance S between the anti-pad vias remains consistent with the first six routing layers and is set to 650um. The distance S1' between the centers of the paired microvias connecting the sixth routing layer 16 to the seventh routing layer 17 is 500um.

[0200] For the eighth routing layer 18, such as Figure 10G As shown, the width W of the anti-pad is consistent with the seventh routing layer 17, set to 680um; the center-to-center distance S between the anti-pad vias is consistent with the first seven routing layers, set to 650um. The distance S1' between the centers of the paired microvias connecting the seventh routing layer 17 to the eighth routing layer 18 is 500um. Figure 10G In the anti-pad, the two larger circles formed are the projections of the solder ball pads onto the anti-pad.

[0201] In this embodiment, in addition to vias on the anti-pad, vias, such as ground vias, are also provided around the anti-pad. By providing vias around the anti-pad, the capacitive impedance of the vias within the anti-pad is changed, thereby adjusting the via impedance. It should be noted that in this embodiment, the projections of the anti-pads of each routing layer in the package substrate overlap in both the vertical and horizontal centerlines.

[0202] The following example illustrates the scenario of setting vias around antipads:

[0203] like Figure 10A and Figure 10B As shown, the width W of the anti-pad in the second routing layer 12 and the center distance S between the anti-pad vias in the third routing layer 13 are consistent. A ring of vias surrounds the anti-pad in the second routing layer 12; these vias are referred to as the fifth surrounding vias. The fifth surrounding vias penetrate the second routing layer 12 and connect to the third routing layer 13. Figure 10B A fifth surrounding via appears around the antipad of the third routing layer 13 shown. The fifth surrounding via connects the second routing layer 12 and the third routing layer 13 around the antipad.

[0204] like Figure 10B and Figure 10CAs shown, the antipad center distance S and the distance S1 between the two microvia centers of the antipad of the fourth routing layer 14 and the third routing layer 13 are consistent, and the antipad width W of the fourth routing layer 14 is increased. Figure 10C A fifth surrounding via appears around the antipad of the fourth routing layer 14 shown. The fifth surrounding via connects the second routing layer 12, the third routing layer 13 and the fourth routing layer 14 around the antipad.

[0205] like Figure 10C and Figure 10D As shown, the antipads of the fourth routing layer 14 and the fifth routing layer 15 have different sizes, with the width W of the antipad of the fifth routing layer 15 being slightly increased. Figure 10D A fifth surrounding via appears around the anti-pad of the fifth routing layer 15. Furthermore, a ring of multiple surrounding vias is formed on the outer side of the anti-pad of the fourth routing layer 14, opposite to the outer side of the anti-pad of the fifth routing layer 15; these vias are referred to as the sixth surrounding vias. On the fourth routing layer 14, the sixth surrounding vias are farther from the anti-pad than the fifth surrounding vias, and the sixth surrounding vias are larger in size than the fifth surrounding vias. Figure 10D The fifth routing layer 15 shown has a fifth surrounding via and a sixth surrounding via around the antipad. The fifth surrounding via and the sixth surrounding via connect the fourth routing layer 14 and the fifth routing layer 15 around the antipad.

[0206] like Figure 10D and Figure 10E As shown, the anti-pad center distance S and the distance S1 between the centers of the two microvias are the same for the sixth routing layer 16 and the fifth routing layer 15. The anti-pad width W of the sixth routing layer 16 is slightly smaller than that of the fifth routing layer 15. Figure 10E A fifth surrounding via appears around the antipad of the sixth routing layer 16 shown. The fifth surrounding via connects the fifth routing layer 15 and the sixth routing layer 16 around the antipad.

[0207] like Figure 10E , Figure 10F as well as Figure 10G As shown, the anti-pad center distance S and the distance S1' between the centers of the two microvias are consistent for the anti-pads of the sixth routing layer 16 and the seventh routing layer 17. The width of the anti-pad in the seventh routing layer 17 is slightly increased, consistent with that of the fifth routing layer 15. The anti-pad width W, the anti-pad center distance S, and the distance S1' between the centers of the two microvias are all consistent for the anti-pads of the seventh routing layer 17 and the eighth routing layer 18. Figure 10F A fifth via appears around the anti-pad of the seventh routing layer 17, as shown. Figure 10GA fifth surrounding via appears around the antipad of the eighth routing layer 18 shown. The fifth surrounding via connects the sixth routing layer 16, the seventh routing layer 17 and the eighth routing layer 18 around the antipad.

[0208] It should be noted that in the example above, the fifth surrounding via can directly penetrate from the second routing layer to the eighth routing layer 18. For example, the center points of the surrounding vias connecting the second and eighth routing layers 18 are aligned in the vertical direction. In practical applications, when setting vias around the antipad, the vias connecting adjacent routing layers can be set according to actual needs. That is, the center points of vias on different layers can be aligned or misaligned in the vertical direction, and are not limited to the situations listed above.

[0209] By setting vias around the antipad, impedance can be adjusted using vias to further reduce impedance abrupt changes on high-speed differential signal lines.

[0210] Method 3: In Figure 8 Under the via layout structure shown, the anti-pad structure and parameters are optimized. For example, the anti-pads in at least some of the routing layers from the second to the eighth routing layer 18 are designed with irregular shapes.

[0211] For the third routing layer 13, such as Figure 11A As shown, the anti-pad width W is set to 680um, and the anti-pad double hole center distance S is set to 650um. Figure 11A The distance S1 between the centers of the two paired microvias is 290um. High-speed differential signals from the chip are transmitted to the third routing layer 13 via the first and second routing layers. High-speed differential signal lines are then laid out horizontally along the surface of the third routing layer 13, allowing the high-speed differential signals to continue transmission through the vias. Because horizontal traces are laid out on the third routing layer 13, a trapezoidal region with uncut copper foil covering the anti-pad area is provided for impedance adjustment. The trapezoidal region is positioned opposite the horizontal traces on both sides of the anti-pad centerline, with the lower edge of the trapezoidal region coinciding with the side edge of the rectangular region of the anti-pad, and the upper edge of the trapezoidal region close to the anti-pad centerline. The upper edge of the trapezoidal area is a = 245um, and the distance from the center of the upper edge of the trapezoid to the center point of the anti-solder pad is c = 102um. By setting a trapezoidal area covering the copper foil, the impedance change caused by the removal of the third trace layer 13 can be avoided.

[0212] For the second routing layer, its anti-pad width W and anti-pad double-hole center distance S are consistent with those of the third routing layer 13. For example... Figure 11BAs shown, a rectangular area and a trapezoidal area are set in the anti-pad of the second trace layer. Both areas are covered with copper foil. The trapezoidal area of ​​the second trace layer is set opposite to the trapezoidal area in the anti-pad of the third trace layer 13 and has the same size. The rectangular area of ​​the second trace layer is set directly above the horizontal trace position of the third trace layer 13. The impedance change is adjusted by setting the trapezoidal metal area and the rectangular metal area opposite to the center line of the anti-pad of the second trace layer.

[0213] For the fourth routing layer 14, such as Figure 11C As shown, the anti-pad width W is set to 640µm, and the center-to-center distance S between the two vias remains unchanged at 650µm. The anti-pad of the fourth routing layer 14 contains a pair of microvias 101 corresponding to the third routing layer 13 and a pair of PTH vias 102 provided in the fourth routing layer 14. The distance S1 between the centers of the two microvias in the pair is 290µm, consistent with the third routing layer 13. The center-to-center distance K between the microvias and the PTH vias is 180µm. The distance S2 between the centers of the two PTH vias in the pair is 290µm + 180µm * 2 = 650µm, consistent with the center-to-center distance S of the anti-pad. Two trapezoidal regions symmetrically arranged around the center line of the anti-pad in the fourth routing layer 14 are formed, constituting an irregularly shaped anti-pad. The dimensions of the trapezoidal regions are the same as those of the trapezoidal regions in the third routing layer 13: the upper edge a = 245µm, and the distance c from the center of the upper edge of the trapezoid to the center point of the anti-pad is 102µm. One of the trapezoidal regions in this routing layer perfectly matches the trapezoidal region in the third routing layer 13. The trapezoidal metal region newly introduced in the fourth routing layer 14 compared to the third routing layer 13 can serve as a reference for the signals in the third routing layer 13, avoiding impedance abrupt changes in the transmission lines connected to signal vias.

[0214] For the fifth routing layer 15, the anti-pad design is consistent with that of the fourth routing layer 14. The anti-pad width W is set to 640µm, and the center-to-center distance S between the two vias is set to 650µm. The fifth routing layer 15 is connected to the sixth routing layer 16 via microvia 101, and the fourth routing layer 14 is connected to the fifth routing layer 15 via PTH via 102. Microvia 101 and PTH via 102 exist on the fifth routing layer 15. The distance S1 between the centers of a pair of microvias is maintained at 290µm, and the distance S2 between the centers of a pair of PTH vias is maintained at 650µm, consistent with the center-to-center distance S of the anti-pad. The anti-pad of the fifth routing layer 15 has two trapezoidal regions covered with metal layers that are symmetrical about the center line of the anti-pad, forming an irregular anti-pad; the upper edge of the trapezoidal region a = 245µm, and the distance c from the center of the upper edge of the trapezoid to the center point of the anti-pad is 102µm.

[0215] For the sixth routing layer 16, such as Figure 11DAs shown, the anti-pad width W is set to 640µm, and the center-to-center distance S between the anti-pad vias remains unchanged at 650µm. The microvia 101 connecting the fifth and sixth routing layers 15 and the microvia 101 connecting the sixth and seventh routing layers 17 are not aligned vertically. There are two pairs of microvia 101 on the sixth routing layer 16. The distance S1 between the centers of the pairs of microvias connecting the fifth and sixth routing layers 15 remains 290µm, the distance S1' between the centers of the pairs of microvias connecting the seventh and sixth routing layers 17 is 500µm, and the center-to-center distance N between two microvias on the same side is 105µm.

[0216] For the seventh and eighth routing layers 17 and 18, the anti-pad design is consistent with that of the sixth routing layer 16, with an anti-pad width W of 640µm and an anti-pad via center-to-center distance S of 650µm. Furthermore, on the seventh and eighth routing layers 17 and 18, the distance S1' between the centers of paired vias is 500µm. Figure 8 In the third embodiment of the structure shown, the case of setting vias around the anti-pad is similar to that in the second embodiment, and will not be further elaborated here.

[0217] Figure 12A This is a comparison chart showing the insertion loss of three anti-pad design methods when routing high-speed differential signal lines on the third layer.

[0218] Figure 12A In the graph, the horizontal axis represents frequency, and the vertical axis represents insertion loss. At the same frequency, the closer the insertion loss is to zero, the better the effect. Based on the comparison of Method 1, Method 2, and Method 3, it can be seen that the insertion loss of Method 3 is consistently better than that of Method 1, and the insertion loss of Method 2 is better than that of Method 1 in most frequency ranges. Therefore, the insertion loss of both Method 3 and Method 2 is better than that of Method 1. For Method 2 and Method 3, one or more reference frequencies are selected to identify the effect of insertion loss of Method 2 and Method 3. For example, the reference frequencies are 19GHz and 28GHz. At these two reference frequencies, the insertion loss of Method 3 is better than that of Method 2, confirming that Method 3 is better than Method 2. Based on the above analysis, the following conclusions can be drawn: Method 3 is better than Method 2, and Method 2 is better than Method 1.

[0219] Figure 12B This is a comparison chart showing the return loss of three anti-pad design methods when routing high-speed differential signal lines on the third layer.

[0220] Figure 12BIn the graph, the horizontal axis represents frequency, and the vertical axis represents return loss. At the same frequency, the further the return loss is from 0, the better the performance. Based on the comparison of Method 1, Method 2, and Method 3, it can be seen that in most frequency ranges, Method 3 and Method 2 have better return loss than Method 1; in the frequency range of 1 to 13 GHz, Method 2 has better return loss than Method 3; in the frequency range of 13 to 32 GHz, Method 3 has better return loss than Method 2; after selecting a reference frequency (e.g., 16 GHz and 28 GHz), at both reference frequencies, Method 3 has better return loss than Method 2, confirming that Method 3 is superior to Method 2. Based on the above analysis, the following conclusions can be drawn: Method 3 is superior to Method 2, and Method 2 is superior to Method 1.

[0221] Figure 12C This is a comparison diagram of the impedance of three anti-pad design methods when routing high-speed differential signal lines on the third layer.

[0222] Figure 12C The horizontal axis represents time, and the vertical axis represents impedance. The smaller the impedance change, the better the effect. Based on the comparison of Method 1, Method 2, and Method 3, it can be seen that Method 3 has the smallest impedance change, followed by Method 2, while Method 1 has the largest impedance change. Therefore, Method 3 is better than Method 2, and Method 2 is better than Method 1.

[0223] Based on the above Figure 12A , Figure 12B as well as Figure 12C As can be seen from the data, regardless of insertion loss, return loss, or impedance matching, method three performs best, method two second best, and method one performs worst.

[0224] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the present invention. Clearly, those skilled in the art can make various alterations and modifications to the present invention without departing from its spirit and scope. Thus, if such modifications and modifications fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include such modifications and modifications.

Claims

1. A packaging substrate, characterized in that, include: Multiple wiring layers are stacked sequentially in the vertical direction of the packaging substrate; The wiring structure that transmits high-speed differential signals from the chip carried by the packaging substrate to the solder balls of the packaging substrate; The routing structure includes: a pair of vias disposed between two adjacent routing layers for transmitting the high-speed differential signal between the two adjacent routing layers; Anti-pads are provided around pairs of vias on each routing layer; wherein the anti-pads electrically isolate the pairs of vias from the routing layer in which they are located, and the parameters and / or structure of the anti-pads of each routing layer are optimized to adjust the via impedance of each routing layer.

2. The packaging substrate according to claim 1, characterized in that, The plurality of trace layers include a first trace layer, a second trace layer, a third trace layer, a fourth trace layer, a fifth trace layer, a sixth trace layer, a seventh trace layer, and an eighth trace layer arranged from top to bottom, wherein the eighth trace layer is connected to the solder ball; A via connecting the first routing layer and the second routing layer is a first via, a via connecting the second routing layer and the third routing layer is a second via, and a via connecting the third routing layer and the fourth routing layer is a third via; The via connecting the fourth routing layer and the fifth routing layer is the fourth via; The via connecting the fifth and sixth routing layers is the fifth via, the via connecting the sixth and seventh routing layers is the sixth via, and the via connecting the seventh and eighth routing layers is the seventh via.

3. The packaging substrate according to claim 2, characterized in that, The target routing layer is the first routing layer. High-speed differential signals from the chip are transmitted along high-speed differential signal lines laid on the surface of the first routing layer to a pair of first vias, and then sequentially through a pair of first vias, a pair of second vias, a pair of third vias, a pair of fourth vias, a pair of fifth vias, a pair of sixth vias, and a pair of seventh vias to the eighth routing layer, so as to reach the solder ball.

4. The packaging substrate according to claim 3, characterized in that, The anti-pad provided in the second trace layer is an irregular anti-pad. The anti-pad area corresponding to the irregular anti-pad includes a first target area. The first target area is covered with metal and is rectangular, and is located at a position directly below the horizontal trace area of ​​the first trace layer.

5. The packaging substrate according to claim 3 or 4, characterized in that, The anti-pad of the fourth trace layer is an irregularly shaped anti-pad. The anti-pad area corresponding to the irregularly shaped anti-pad includes two second target areas positioned opposite each other relative to the anti-pad centerline. The second target areas are covered with metal and are trapezoidal, with their upper edges close to the anti-pad centerline and their lower edges far from the anti-pad centerline; and / or The anti-pad of the fifth trace layer is an irregular anti-pad. The anti-pad area corresponding to the irregular anti-pad includes two third target areas set opposite to the anti-pad center line. The third target areas are covered with metal, are trapezoidal, and have their upper side close to the anti-pad center line and their lower side far away from the anti-pad center line.

6. The packaging substrate according to claim 5, characterized in that, The anti-pad width of the anti-pad corresponding to the first trace layer is 320um, and the center-to-center distance between the anti-pad holes is 650um. The second trace layer corresponds to the same anti-pad width and anti-pad double hole center distance as the first trace layer; The anti-pad of the third trace layer has a center-to-center distance of 650µm and a width of 690µm. The anti-pad width and anti-pad center distance of the fourth trace layer are the same as those of the third trace layer. The upper edge of the second target area is 187um and the center distance of the upper edge from the center point of the anti-pad is 170um. The fifth routing layer has the same antipad parameters and antipad structure as the fourth routing layer; The anti-pad width of the anti-pad corresponding to the sixth trace layer is 700um, and the center distance between the two anti-pad holes is 650um. The antipad width and antipad center distance of the antipads of the seventh and eighth routing layers are the same as those of the sixth routing layer.

7. The packaging substrate according to claim 2, characterized in that, The target routing layer is the third routing layer. A pair of high-speed differential signal lines are arranged on the surface of the third routing layer along the horizontal direction of the packaging substrate. The pair of high-speed differential signal lines transmit the high-speed differential signal from the chip to the pair of third vias. The high-speed differential signal transmitted to the paired third via is transmitted sequentially through the paired fourth via, the paired fifth via, the paired sixth via, and the paired seventh via to the eighth trace layer, so as to reach the solder ball.

8. The packaging substrate according to claim 7, characterized in that, The anti-pad of the fourth trace layer is an irregular anti-pad. The anti-pad area corresponding to the irregular anti-pad includes a fourth target area. The fourth target area is covered with metal and is rectangular, and is located at a position directly below the horizontal trace area of ​​the third trace layer.

9. The packaging substrate according to claim 7 or 8, characterized in that, The anti-pad of the second routing layer is an irregularly shaped anti-pad. The anti-pad area corresponding to the irregularly shaped anti-pad includes a fifth target area and a sixth target area. The fifth target area and the sixth target area are positioned opposite each other on both sides of the anti-pad center line. The fifth target area is covered with metal and is rectangular, while the sixth target area is covered with metal and is trapezoidal. The fifth target area is positioned directly above the horizontal routing area of ​​the third routing layer. The upper edge of the trapezoid corresponding to the sixth target area is close to the anti-pad center line. The anti-pad of the third trace layer is an irregular anti-pad. The anti-pad area corresponding to the irregular anti-pad includes a seventh target area. The seventh target area is arranged on both sides of the anti-pad center line opposite to the horizontal trace on the surface of the third trace layer. The seventh target area is covered with metal and is trapezoidal. The upper edge of the trapezoid corresponding to the seventh target area is close to the anti-pad center line. The anti-pad of the fourth trace layer is an irregularly shaped anti-pad. The anti-pad area corresponding to the irregularly shaped anti-pad includes two eighth target areas positioned opposite each other relative to the anti-pad centerline. The eighth target areas are covered with metal and are trapezoidal, with their upper edges close to the anti-pad centerline and their lower edges far from the anti-pad centerline; and / or The anti-pad of the fifth trace layer is an irregular anti-pad. The anti-pad area corresponding to the irregular anti-pad includes two ninth target areas set opposite to the anti-pad center line. The ninth target area is covered with metal and is trapezoidal, with its upper side close to the anti-pad center line and its lower side far away from the anti-pad center line.

10. The packaging substrate according to claim 9, characterized in that, The anti-pad width of the anti-pad corresponding to the third trace layer is 680um, and the center distance between the two anti-pad holes is 650um. The second trace layer and the third trace layer have the same anti-pad width and anti-pad double hole center distance; The anti-pad of the fourth trace layer has a center-to-center distance of 650µm and a width of 640µm. The upper edge of the trapezoid of the eighth target area is 245µm and the center of the upper edge is 102µm away from the center point of the anti-pad. The fifth routing layer has the same antipad parameters and antipad structure as the fourth routing layer; The parameters of the anti-solder pads of the sixth routing layer are the same as those of the fourth routing layer; The parameters of the anti-solder pads of the seventh and eighth routing layers are the same as those of the fourth routing layer.

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