Inductive array and integrated circuit comprising the same
By using an inductor array design and a centrally symmetrical longitudinal coil structure with multi-layer metal and dielectric layers connected by vias, the problems of low quality factor and high integration complexity in traditional inductor design are solved. This achieves flexible configuration of inductance value and electromagnetic balance, reduces cost, and improves the flexibility of integrated circuits.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BEIJING YANDONG MICROELECTRONICS
- Filing Date
- 2025-07-04
- Publication Date
- 2026-07-24
AI Technical Summary
Traditional inductor design suffers from problems such as low quality factor, large chip area, and high cost. Furthermore, vertical inductors have low versatility in integrated applications, leading to increased complexity and cost in integrated circuit design.
The design employs an inductor array, which is connected by vias in multiple metal and dielectric layers to form a centrally symmetrical longitudinal coil structure. The sub-inductors are arranged in an array to form an inductor unit, enabling flexible configuration of inductance values and electromagnetic balance.
It improves the versatility of inductor arrays and the flexibility of integrated circuits, reduces chip fabrication costs, optimizes electromagnetic field distribution and heat dissipation performance, and reduces interference between inductor units.
Smart Images
Figure CN224556141U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of microelectronic integrated circuit technology, and more specifically, to an inductor array and an integrated circuit comprising the same. Background Technology
[0002] High Q-factor (quality factor) on-chip integrated inductors are indispensable components in microwave circuits and monolithic integrated radio frequency circuits, and are crucial for achieving high-efficiency circuits. However, traditional inductor designs are limited by factors such as substrate loss, metal loss, and the mutual cancellation of magnetic flux between inductor spirals, resulting in a low quality factor.
[0003] Traditional integrated circuit manufacturing processes face numerous challenges in fabricating inductors, including the difficulty in achieving high-Q inductors and the need for large chip areas. Therefore, circuit designs typically avoid using inductors, opting instead for easier-to-manufacture alternatives such as transistors. For essential inductors, they are often discrete components separate from the integrated circuit and electrically connected via specific pins. While this approach solves integration challenges, it increases system complexity and cost, and also hinders miniaturization. To address this, related technologies utilize multi-metal layer processes, connecting different metal layers through vias to form vertical interconnects, which are then wound into a vertical coil, thus constructing a vertical inductor structure.
[0004] Currently, vertical inductors have limited versatility and their integrated applications remain restricted. For example, the presence of vertical inductors in integrated circuit design hinders redesign and increases costs. Utility Model Content
[0005] To address the technical shortcomings of existing vertical inductor integration applications, embodiments of this application provide an inductor array, including multiple sub-inductors arranged in an array; each sub-inductor includes multiple metal layers stacked along the thickness direction of a substrate, with adjacent metal layers separated by dielectric layers and connected by vias penetrating the dielectric layers to form a coil around the central axis of the sub-inductor;
[0006] The array of the multiple sub-inductors is centrally symmetrical; all sub-inductors in the inductor array are configured such that: the central axes of the sub-inductors in the same row are parallel to each other; the central axes of the sub-inductors in adjacent rows are orthogonal to each other; and two adjacent sub-inductors in the same column are located in two separate rows.
[0007] At least some of the sub-inductors in the inductor array form a plurality of inductor units; each of the plurality of inductor units includes a plurality of sub-inductors connected in series.
[0008] Optionally, each of the plurality of inductor units is configured such that the sub-inductors in the same inductor unit are arranged in a centrally symmetrical manner.
[0009] Optionally, the inductor array further includes a magnetic core array; the magnetic core array includes a plurality of magnetic cores arranged in a centrally symmetrical manner;
[0010] Furthermore, the sub-inductor is located at the boundary of the magnetic core.
[0011] Optionally, adjacent magnetic cores have a spacing.
[0012] Optionally, any two inductor units among the plurality of inductor units may be connected in parallel or in series.
[0013] Optionally, the input / output ports of the inductor unit are located on the periphery of the inductor array.
[0014] Optionally, the inductance values of the plurality of sub-inductors are equal.
[0015] Optionally, the inductance values of any two inductor units among the plurality of inductor units are not equal.
[0016] Optionally, in the plurality of inductor units, at least two sub-inductors in at least one inductor unit are configured to share a magnetic circuit.
[0017] This application also provides an integrated circuit including a vertical inductor array as described in any of the above embodiments.
[0018] The inductor array and integrated circuit containing it provided in this application arrange multiple vertical sub-inductors in a centrally symmetrical array. Furthermore, all sub-inductors in the inductor array are configured such that: the central axes of sub-inductors in the same row are parallel to each other; the central axes of sub-inductors in adjacent rows are orthogonal to each other; and two adjacent sub-inductors in the same column are located in two separate rows. This layout ensures the electromagnetic balance of the entire inductor array. Embodiments of this application use at least some sub-inductors in the inductor array to form at least two inductor units, each inductor unit including multiple sub-inductors connected in series. This allows for flexible configuration of the inductance values of the inductor units, thereby improving the versatility of the inductor array and facilitating redesigns in the integrated circuit layout design process. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.
[0020] Figure 1 A three-dimensional view of the sub-inductor provided in an embodiment of this application is shown;
[0021] Figure 2 This illustration shows a three-dimensional view of two sub-inductors connected in series, as provided in an embodiment of this application.
[0022] Figure 3 This illustration shows a top view of an inductor array provided in an embodiment of this application. Figure 1 ;
[0023] Figure 4 This illustration shows a top view of an inductor array provided in an embodiment of this application. Figure 2 ;
[0024] Figure 5 This illustration shows a top view of an inductor array provided in an embodiment of this application. Figure 3 ;
[0025] Figure 6 This illustration shows a top view of an inductor array provided in an embodiment of this application. Figure 4 ;
[0026] Figure 7 This illustration shows a top view of an inductor array provided in an embodiment of this application. Figure 5 ;
[0027] Figure 8 This illustration shows a top view of an inductor array provided in an embodiment of this application. Figure 6 .
[0028] Some of the attached labels in the figure are as follows:
[0029] 00 - Magnetic core; 1 - Sub-inductor; 101 - Metal layer; 102 - Via. Detailed Implementation
[0030] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are illustrated in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0031] It should be noted that when a component is considered to be "connected" to another component, it can be directly connected to and integrated with the other component, or there may be an intervening component present. The terms "mounted," "one end," "the other end," and similar expressions used herein are for illustrative purposes only. Furthermore, in the description of this application, "multiple" means two or more, or at least two.
[0032] Traditional planar inductor structures suffer from low inductance per unit area due to their small coil spacing and cross-sectional area. Therefore, when a larger inductance is required, planar inductor arrays either occupy a large chip area or require external connection to the die, hindering chip integration. In contrast, vertical inductor arrays can provide a larger inductance per unit area, significantly saving chip area, improving chip integration density, and substantially reducing manufacturing costs. However, the inductance per unit area of a single vertical inductor structure is limited and fixed due to constraints in metal wire type, number of metal wire layers, coil spacing, and coil cross-sectional area. Furthermore, the structure of vertical inductors dictates that they can only be fabricated on a substrate using semiconductor processing techniques. This necessitates designing a new vertical inductor every time the inductance in the integrated circuit needs to be changed. For example, for the same circuit with different inductance specifications, a new vertical inductor needs to be designed for each specification, requiring re-fabrication, which significantly increases the design and manufacturing costs of integrated circuits.
[0033] In view of this, this application provides an inductor array. Figure 1 A three-dimensional view of a single sub-inductor in an inductor array provided in an embodiment of this application is shown. Figure 1 As shown, a single sub-inductor includes multiple metal layers 101 stacked along the thickness direction of the substrate. Adjacent metal layers 101 are separated by dielectric layers. The adjacent metal layers 101 are connected by vias 102 that penetrate the dielectric layers to form a longitudinal coil around the central axis a. Figure 2 A schematic diagram of a structure in which two sub-inductors (11, 12) are connected in series via trace 14 is shown. Of course, trace 14 is also a metal layer, but it is only used here to distinguish between the metal layer used to form the vertical inductor and the metal layer used to connect the two sub-inductors.
[0034] Figures 3 to 8 The following figures show top views of the inductor arrays provided in embodiments of this application. For ease of explanation, in the following description, the horizontal axis will be referred to as a "row" and the vertical axis as a "column".
[0035] See Figures 1 to 6 The inductor array provided in this application embodiment includes multiple sub-inductors arranged in an array, and the arrangement of the multiple sub-inductors is centrally symmetrical. See also... Figures 3 to 5 The inductor array provided in this application embodiment is configured such that the central axes of the sub-inductors in the same row are parallel to each other, for example... Figure 3 The central axes of the sub-inductors M8, M1, and M6 in the first row are parallel. Figure 5 In the first row, the central axes of sub-inductors M12 and M10 are parallel; the central axes of sub-inductors in adjacent rows are orthogonal to each other, for example... Figure 3 The central axes of the sub-inductor M8 in the first row and the sub-inductor M3 in the second row are orthogonal to each other. Figure 5 The central axes of the sub-inductor M12 in the first row and the sub-inductor M8 in the second row are orthogonal to each other; and, two adjacent sub-inductors in the same column are located in two separate rows, for example... Figure 3 The sub-inductors M8 and M5 in the first column are located in the first and third rows, respectively. Figure 5 The sub-inductors M1 and M2 in the third column are located in the second and fourth rows, respectively. Furthermore, at least some of the sub-inductors in the inductor array form at least two inductor units, and each inductor unit includes multiple sub-inductors connected in series.
[0036] The arrangement of sub-inductors in the inductor array shown in the embodiments of this application ensures the electromagnetic balance of the entire inductor array. Furthermore, the orthogonal central axes of the sub-inductors in adjacent rows and the location of adjacent sub-inductors in the same column within two spaced-out rows reduce interference between sub-inductors in adjacent rows / columns. In the inductor array provided in the embodiments of this application, at least some sub-inductors form independent inductor units, each inductor unit including at least two sub-inductors connected in series. This allows for the formation of inductors with different inductance values through series and / or parallel connections of inductor units, enabling flexible configuration of the sub-inductor connection method according to the required inductance value, thus improving the versatility of the inductor array.
[0037] It should be noted that in some optional embodiments, such as Figure 3 As shown, all sub-inductors in the inductor array participate in the composition of the inductor unit. Figure 3 Eight sub-inductors in the array form four inductor units. In some optional embodiments, some sub-inductors in the inductor array do not participate in the formation of the inductor units. For example, as shown... Figure 3 In this array, M1 and M2, and M3 and M4 each form two inductor units, while at least one pair of M5 and M6, and M7 and M8 does not constitute an inductor unit. This preserves redundant sub-inductors in the inductor array for future design modifications. Furthermore, the redundant sub-inductors balance the electromagnetic field, reducing electromagnetic imbalances caused by asymmetry in the position and number of sub-inductors.
[0038] Because a single sub-inductor occupies a small area, its placement on the substrate is highly flexible. This allows for the independent arrangement of sub-inductors within the inductor array, based on design requirements and chip layout. Multiple sub-inductors can then be connected in series to form an inductor unit. Furthermore, where area permits, more sub-inductors than required can be used. This allows for adjustments to the inductance value during subsequent modifications to the integrated circuit layout, thereby reducing tape-out costs.
[0039] According to the embodiments of this application, such as Figures 3 to 6As shown, each of the multiple inductor units is configured such that the sub-inductors within the same inductor unit are centrally symmetrical. For example, Figure 3 Neutron inductors M1 and M2, M3 and M4, M5 and M6, and M7 and M8 are all centrally symmetrical in pairs. For example, Figure 5 Neutron inductors M9 and M10, and M11 and M12, are centrally symmetrical in pairs. In the inductor array provided in this embodiment, by connecting the centrally symmetrical sub-inductors in series to form inductor units, the mutual inductance between the formed inductor units is eliminated, achieving a decoupled integration effect. This avoids mutual interference between the integrated inductor units, allowing each inductor unit to operate independently.
[0040] According to the embodiments of this application, the inductor array provided in this application can be a cored inductor array or a coreless inductor array. Figure 4 The inductor array shown is a coreless inductor array, including sub-inductors arranged in the array. For example... Figure 3 and Figures 5-8 The inductor array shown also includes a magnetic core array. This magnetic core array comprises multiple centrally symmetrically arranged magnetic cores 00, with sub-inductors positioned at the boundaries of the magnetic cores 00. For example, the magnetic cores can be divided into multiple segments along the central axis of the sub-inductors, each segment corresponding to a sub-inductor, constructing a matrix topology composed of simple magnetic cores, thereby enabling control over the magnetic field distribution and reluctance path. Replacing the traditional integrated structure with a modular, scalable, distributed magnetic core layout optimizes the heat dissipation path through the spatial distribution of the magnetic core array, reducing local temperature rise and losses in the inductor array. Furthermore, decoupling integration between inductors is achieved through magnetic core assembly and circuit decoupling (such as cross-interconnection compensation), allowing each inductor to operate independently without interference. Ultimately, this provides a highly flexible, low-cost, scalable solution to improve system integration and energy efficiency, offering an efficient decoupling integration path for high-density, low-loss circuits. Moreover, compared to traditional integrated magnetic core inductors, the equivalent segmentation method and magnetic decoupling technology provided in this application embodiment are low-cost and simple to design.
[0041] Specifically, the magnetic core array in the inductor array should be divided into at least four blocks, meaning the minimum magnetic core array is a 2×2 array. This achieves the simplest equivalent division of the magnetic core. Conversely, if the magnetic core array is a 1×2 or 2×1 array, the magnetic field balance of the inductor array cannot be guaranteed.
[0042] In some embodiments, the magnetic core 00 has a shape including square, regular octagonal, or toroidal. Sufficient physical spacing is maintained between adjacent magnetic cores 00 to reduce magnetic flux overlap between them. Figure 3 , Figures 5-8 As shown, multiple magnetic cores are arranged symmetrically. This arrangement requires a balanced magnetic field distribution to reduce the mutual influence between the multiple magnetic cores. In the embodiments of this application, as... Figure 3 , Figures 5-8 The magnetic cores shown are all square, and their principles and arrangement requirements are as described above. This application does not limit the shape of the magnetic core 00. For regular octagonal or toroidal magnetic cores 00, the inductance principle and arrangement requirements are the same as for square magnetic cores, and will not be elaborated here.
[0043] For example, such as Figure 3 As shown, each inductor unit includes two sub-inductors. For example, as shown... Figure 7 and Figure 8 As shown, some inductor units include three sub-inductors, while others include two sub-inductors. For example... Figure 7 In the inductor array shown, sub-inductors M1, M2, and M19 form an inductor unit; sub-inductors M6, M7, and M20 form an inductor unit; sub-inductors M3, M4, and M13 form an inductor unit; and sub-inductors M9, M11, and M15 form an inductor unit. Each of these inductor units includes three sub-inductors, and the remaining inductor units include two sub-inductors. Figure 3 As shown, the two sub-inductors in any inductor unit are symmetrical about the geometric center of the inductor array on the substrate surface.
[0044] The inductor array provided in this application comprises multiple sub-inductors connected in series. The inductance value can be flexibly set by controlling at least one of the following: the type of metal wire, the number of metal wire layers, the coil spacing, and the coil cross-sectional area of each sub-inductor. Assuming the inductance value of the inductor array provided in this application is L, and the inductance values of the multiple inductor units are L1, L2…L… n , n≥2. For example, L1 to L n The multiple inductance values in the circuit are equal. For example, L1 to L... n All inductance values are equal. For example, L1 to L... n All inductance values are not equal. For example, any two inductor units from a plurality of inductor units are connected in parallel. Also for example, any two inductor units from a plurality of inductor units are connected in series.
[0045] Example 1
[0046] Figure 2 A three-dimensional view of two longitudinal inductors connected in series is shown. For ease of distinction and explanation, these two longitudinal inductors are referred to as the first sub-inductor 11 and the second sub-inductor 12, respectively. Both the first sub-inductor 11 and the second sub-inductor 12 have two connection terminals. One connection terminal of the first sub-inductor 11 is electrically connected to one connection terminal of the second sub-inductor 12 via a trace 14. The other connection terminal 13 of the first sub-inductor 11 and the other connection terminal 15 of the second sub-inductor 12 serve as the input / output ports of the series inductor.
[0047] The series connection of inductors depends on the properties of the inductors (whether there is mutual inductance) and the requirements of the target circuit, and can be divided into two categories. The first category is the series connection of ordinary inductors (without mutual inductance). The magnetic fields of ordinary inductors are independent and there is no mutual inductance coupling. When connected in series, they are simply added together, and any two ends are directly connected (without considering the same-name ends). Taking two sub-inductors in series as an example, the total inductance L = L1 + L2. The other category is the series connection of coupled inductors (with mutual inductance). When the two inductors are on the same magnetic core or have magnetic field coupling, the same-name ends must be considered, and there are two connection methods: one is forward series connection (same-name ends connected to opposite-name ends). Taking two sub-inductors in series as an example, the total inductance L = L1 + L2 + 2M (M is the mutual inductance between the two sub-inductors). The magnetic flux generated by the two inductors is in the same direction, the magnetic fields are superimposed, and the inductance increases. The other is reverse series connection (same-name ends connected to same-name ends). Taking two sub-inductors in series as an example, the total inductance L = L1 + L2 - 2M (M is the mutual inductance between the two sub-inductors). The magnetic flux generated by the two inductors is in opposite directions, partially canceling each other out and reducing the inductance. When selecting the series connection method, if an increase in inductance is needed (such as in a filter circuit), choose forward series connection; if a decrease in inductance is needed or saturation should be avoided (such as in high-frequency applications), choose reverse series connection. Forward series connection can improve energy storage capacity, while reverse series connection can be used to suppress high-frequency noise.
[0048] According to some alternative implementations, the two inductors can be connected in parallel. If two ordinary inductors (without mutual inductance) are connected in parallel, the two inductors are independent, and the total inductance L = (L1*L2) / (L1+L2). If two coupled inductors (with mutual inductance) are connected in parallel, there are two connection methods: one is that the terminals with the same name are connected, in which case the magnetic fields of the two coupled inductors reinforce each other, and the total inductance L = (L1*L2-M) / (L1+L2 ... 2 ) / (L1+L2-2M). Another configuration is where the terminals of opposite names are connected; in this case, the magnetic fields of the two coupled inductors cancel each other out, and the total inductance L = (L1*L2-M) / (L1+L2-2M). 2 ) / (L1+L2+2M).
[0049] Example 2
[0050] Figure 3In the inductor array shown, the first sub-inductor M1 and the second sub-inductor M2 are connected in series to form inductor unit L1; the connection terminal a of the first sub-inductor M1 and the connection terminal b of the second sub-inductor M2 are configured as the input / output ports of inductor unit L1. The third sub-inductor M3 and the fourth sub-inductor M4 are connected in series to form inductor unit L2; the connection terminal c of the third sub-inductor M3 and the connection terminal d of the fourth sub-inductor M4 are configured as the input / output ports of inductor L2. Inductor units L1 and L2 are arranged in a cross-shaped array. When the first sub-inductor M1, the second sub-inductor M2, the third sub-inductor M3, and the fourth sub-inductor M4 are of the same type, and the connection method of the first sub-inductor M1 and the second sub-inductor M2 is the same as that of the third sub-inductor M3 and the fourth sub-inductor M4, the operation of the first sub-inductor M1 and the second sub-inductor M2 does not affect the operation of the third sub-inductor M3 and the fourth sub-inductor M4, and the inductor unit L1 and the inductor unit L2 can be decoupled and integrated. To fully utilize the magnetic circuit, inductor integration can also be continued by completely canceling the coupling effect between the sub-inductors. This is understandable. Figure 3 In any inductor unit, the two sub-inductors can be connected in series in either the forward direction or in the reverse direction.
[0051] like Figure 3 As shown, by setting the fifth sub-inductor M5, the sixth sub-inductor M6, the seventh sub-inductor M7, and the eighth sub-inductor M8, the magnetic circuits of the first sub-inductor M1, the second sub-inductor M2, the third sub-inductor M3, and the fourth sub-inductor M4 are fully utilized. The fifth sub-inductor M5 and the sixth sub-inductor M6 are connected in series to form inductor unit L3, and the connection terminal e of the fifth sub-inductor M5 and the connection terminal f of the sixth sub-inductor M6 are configured as the input / output ports of inductor unit L3. The seventh sub-inductor M7 and the eighth sub-inductor M8 are connected in series to form inductor unit L4, and the connection terminal g of the seventh sub-inductor M7 and the connection terminal h of the eighth sub-inductor M8 are configured as the input / output ports of inductor unit L4.
[0052] like Figure 3 The layout and connection method of the inductor array shown ensures that the input / output ports of each inductor unit are located on the periphery of the inductor array, which facilitates the integration of the inductor array with other electronic components. In practice, this is not a limitation; the connections between terminals a to h can be configured according to design requirements to allow different inductance values to be connected to the integrated circuit, thereby achieving flexible configuration of inductance values and reducing tape-out costs.
[0053] Example 3
[0054] Figure 4 The inductor array shown is a coreless inductor array. Figure 4In the circuit, the first sub-inductor M1 and the second sub-inductor M2 are connected in series to form inductor unit L1; the connection terminal a of the first sub-inductor M1 and the connection terminal b of the second sub-inductor M2 are configured as the input / output ports of inductor unit L1. The third sub-inductor M3 and the fourth sub-inductor M4 are connected in series to form inductor unit L2; the connection terminal c of the third sub-inductor M3 and the connection terminal d of the fourth sub-inductor M4 are configured as the input / output ports of inductor L2. The fifth sub-inductor M5 and the sixth sub-inductor M6 are connected in series to form inductor unit L3; the connection terminal e of the fifth sub-inductor M5 and the connection terminal f of the sixth sub-inductor M6 are configured as the input / output ports of inductor unit L3. The seventh sub-inductor M7 and the eighth sub-inductor M8 are connected in series to form inductor unit L4; the connection terminal g of the seventh sub-inductor M7 and the connection terminal h of the eighth sub-inductor M8 are configured as the input / output ports of inductor unit L4. The ninth sub-inductor M9 and the tenth sub-inductor M10 are connected in series to form inductor unit L5. The connection terminal i of the ninth sub-inductor M9 and the connection terminal j of the tenth sub-inductor M10 are configured as the input / output ports of inductor unit L5. The eleventh sub-inductor M11 and the twelfth sub-inductor M12 are connected in series to form inductor unit L6. The connection terminal k of the eleventh sub-inductor M11 and the connection terminal l of the twelfth sub-inductor M12 are configured as the input / output ports of inductor unit L6.
[0055] Example 4
[0056] like Figure 5 As shown, in the inductor array provided in Embodiment 4, the arrangement and connection of the sub-inductors are the same as those in the inductor array provided in Embodiment 3. The difference is that the inductor array provided in Embodiment 4 contains a magnetic core.
[0057] Example 5
[0058] Figure 6In the inductor array shown, the magnetic core is divided into a 2×3 array. The first sub-inductor M1 and the second sub-inductor M2 are connected in series to form inductor unit L1. Terminal a of the first sub-inductor M1 and terminal b of the second sub-inductor M2 are configured as input / output ports of inductor unit L1. The third sub-inductor M3, the fourth sub-inductor M4, and the thirteenth sub-inductor M13 are connected in series to form inductor unit L2. Terminal c of the third sub-inductor M3 and terminal d of the thirteenth sub-inductor M13 are configured as input / output ports of inductor unit L2. The fifth sub-inductor M5 and the sixteenth sub-inductor M16 are connected in series to form inductor unit L3. Terminal e of the fifth sub-inductor M5 and terminal f of the sixteenth sub-inductor M16 are configured as input / output ports of inductor unit L3. The sixth sub-inductor M6 and the seventh sub-inductor M7 are connected in series to form inductor unit L4. Terminal m of the sixth sub-inductor M6 and terminal n of the seventh sub-inductor M7 are configured as input / output ports of inductor unit L4. The eighth sub-inductor M8 and the seventeenth sub-inductor M17 are connected in series to form inductor unit L5. The connection terminal h of the eighth sub-inductor M8 and the connection terminal g of the seventeenth sub-inductor M17 are set as the input / output port of inductor unit L5. The ninth sub-inductor M9 and the fourteenth sub-inductor M14 are connected in series to form inductor unit L6. The connection terminal i of the ninth sub-inductor M9 and the connection terminal j of the fourteenth sub-inductor M14 are set as the input / output port of inductor unit L6. The tenth sub-inductor M10 and the eleventh sub-inductor M11 are connected in series to form inductor unit L7. The connection terminal p of the tenth sub-inductor M10 and the connection terminal o of the eleventh sub-inductor M11 are set as the input / output port of inductor unit L7. The twelfth sub-inductor M12 and the fifteenth sub-inductor M15 are connected in series to form inductor unit L8. The connection terminal l of the twelfth sub-inductor M12 and the connection terminal k of the fifteenth sub-inductor M15 are set as the input / output port of inductor unit L8.
[0059] Example 6
[0060] like Figure 7The inductor array shown includes a 3×3 magnetic core array. The first sub-inductor M1, the second sub-inductor M2, and the nineteenth sub-inductor M19 are connected in series to form inductor unit L1. Terminal a of the first sub-inductor M1 and terminal b of the nineteenth sub-inductor M19 are configured as input / output ports of inductor unit L1. The third sub-inductor M3, the fourth sub-inductor M4, and the thirteenth sub-inductor M13 are connected in series to form inductor unit L2. Terminal c of the third sub-inductor M3 and terminal d of the thirteenth sub-inductor M13 are configured as input / output ports of inductor unit L2. The fifth sub-inductor M5 and the seventeenth sub-inductor M17 are connected in series to form inductor unit L3. Terminal q of the fifth sub-inductor M5 and terminal r of the seventeenth sub-inductor M17 are configured as input / output ports of inductor unit L3. The sixth sub-inductor M6, the seventh sub-inductor M7, and the twentieth sub-inductor M20 are connected in series to form inductor unit L4. Terminal m of the sixth sub-inductor M6 and terminal n of the twentieth sub-inductor M20 are configured as input / output ports of inductor unit L4. The eighth sub-inductor M8 and the twenty-first sub-inductor M21 are connected in series to form inductor unit L5. Terminal h of the eighth sub-inductor M8 and terminal g of the twenty-first sub-inductor M21 are configured as input / output ports of inductor unit L5. The ninth sub-inductor M9, the eleventh sub-inductor M11, and the fifteenth sub-inductor M15 are connected in series to form inductor unit L6. Terminal s of the ninth sub-inductor M9 and terminal t of the fifteenth sub-inductor M15 are configured as input / output ports of inductor unit L6. The tenth sub-inductor M10 and the twenty-third sub-inductor M23 are connected in series to form inductor unit L7. Terminal p of the tenth sub-inductor M10 and terminal o of the twenty-third sub-inductor M23 are configured as input / output ports of inductor unit L7. The twelfth sub-inductor M12 and the twenty-fourth sub-inductor M24 are connected in series to form inductor unit L8. Terminal l of the twelfth sub-inductor M12 and terminal k of the twenty-fourth sub-inductor M24 are configured as input / output ports of inductor unit L8. The fourteenth sub-inductor M14 and the twenty-second sub-inductor M22 are connected in series to form inductor unit L9. Terminal j of the fourteenth sub-inductor M14 and terminal i of the twenty-second sub-inductor M22 are configured as input / output ports of inductor unit L9. The sixteenth sub-inductor M16 and the eighteenth sub-inductor M18 are connected in series to form inductor unit L... 10 The connection terminal f of the sixteenth sub-inductor M16 and the connection terminal e of the eighteenth sub-inductor M18 are configured as inductor unit L. 10 Input / output ports.
[0061] Example 7
[0062] Figure 8 The inductor array shown comprises a 3×3 array of magnetic cores. See also Figure 8Inductor unit L1 is formed by connecting the first sub-inductor M1, the second sub-inductor M2, and the nineteenth sub-inductor M19 in series. Terminal a of the first sub-inductor M1 and terminal b of the nineteenth sub-inductor M19 are configured as the input / output ports of inductor unit L1. Inductor unit L2 is formed by connecting the third sub-inductor M3, the fourth sub-inductor M4, and the thirteenth sub-inductor M13 in series. Terminal c of the third sub-inductor M3 and terminal d of the thirteenth sub-inductor M13 are configured as the input / output ports of inductor unit L2. Inductor unit L3 is formed by connecting the fifth sub-inductor M5 and the seventeenth sub-inductor M17 in series. Terminal q of the fifth sub-inductor M5 and terminal r of the seventeenth sub-inductor M17 are configured as the input / output ports of inductor unit L3. The sixth sub-inductor M6, the seventh sub-inductor M7, and the twentieth sub-inductor M20 are connected in series to form inductor unit L4. Terminal m of the sixth sub-inductor M6 and terminal n of the twentieth sub-inductor M20 are configured as input / output ports of inductor unit L4. The ninth sub-inductor M9, the eleventh sub-inductor M11, and the fifteenth sub-inductor M15 are connected in series to form inductor unit L5. Terminal s of the ninth sub-inductor M9 and terminal t of the fifteenth sub-inductor M15 are configured as input / output ports of inductor unit L5. The tenth sub-inductor M10 and the thirteenth sub-inductor M23 are connected in series to form inductor unit L6. Terminal p of the tenth sub-inductor M10 and terminal o of the thirteenth sub-inductor M23 are configured as input / output ports of inductor unit L6.
[0063] The eighth sub-inductor M8, the twenty-first sub-inductor M21, the twelfth sub-inductor M12, the twenty-fourth sub-inductor M24, the fourteenth sub-inductor M14, the twenty-second sub-inductor M22, the sixteenth sub-inductor M16, and the eighteenth sub-inductor M18 do not form an inductor unit. They are used as redundant components for later modification and adjustment of inductance values.
[0064] Compared to Figure 7 , Figure 8 In the inductor array, some sub-inductors form 6 inductor units. The sub-inductors that do not participate in the formation of the inductor units are located in pairs at centrally symmetrical positions, which plays a role in balancing the electromagnetic field.
[0065] Secondly, this application also provides an integrated circuit including a vertical inductor array as described in any of the above embodiments.
[0066] In summary, the inductor array and integrated circuit containing it provided in this application arrange the vertical sub-inductors in a centrally symmetrical array. Furthermore, all sub-inductors in the inductor array are configured such that: the central axes of the sub-inductors in the same row are parallel to each other; the central axes of the sub-inductors in adjacent rows are orthogonal to each other; and two adjacent sub-inductors in the same column are located in two separate rows. This layout achieves effective integration of the sub-inductors and ensures the electromagnetic balance of the entire inductor array. The embodiments of this application use at least some of the sub-inductors in the inductor array to form multiple inductor units, each inductor unit including at least two sub-inductors connected in series. Flexible configuration of the inductance value is achieved through the series and / or parallel connection of the inductor units, improving the versatility of the inductor array and facilitating subsequent design modifications.
[0067] This application embodiment further restricts each inductor unit to have at least two sub-inductors connected in series, and the sub-inductors in the same inductor unit are arranged in a centrally symmetrical manner, thereby achieving decoupling between inductor units and avoiding mutual interference between them. Simultaneously, it allows for the simultaneous increase or decrease of sub-inductors at centrally symmetrical positions, forming cross-interconnection compensation and achieving the effect of decoupling integration.
[0068] The inductor array provided in this application may further include array-divided magnetic cores, with sub-inductors positioned at the boundaries of each divided magnetic core, achieving equivalent core division and maintaining magnetic field balance within the inductor array. Multiple sub-inductors are connected in series to form an inductor unit, and the unconnected ends of two sub-inductors are configured as input / output ports of the inductor unit. Arranging multiple inductor units to form an inductor array allows for flexible arrangement of the array's shape and the number of inductors according to design requirements and integrated circuit layout, facilitating inductor array integration. Furthermore, flexible combination of inductor units can be achieved through port configuration within the inductor array, enabling flexible adjustment of inductance values and reducing the manufacturing cost of integrated circuits containing this inductor array.
[0069] The above description is merely a specific implementation of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be included within the protection scope of the embodiments of this application. Therefore, the protection scope of the embodiments of this application should be determined by the protection scope of the claims.
Claims
1. An inductor array, characterized in that, It includes multiple sub-inductors arranged in an array; each sub-inductor includes multiple metal layers stacked along the thickness direction of the substrate, with adjacent metal layers separated by dielectric layers and connected by vias penetrating the dielectric layers to form a coil around the central axis of the sub-inductor; The array of the multiple sub-inductors is centrally symmetrical; all sub-inductors in the inductor array are configured such that: the central axes of the sub-inductors in the same row are parallel to each other; the central axes of the sub-inductors in adjacent rows are orthogonal to each other; and two adjacent sub-inductors in the same column are located in two separate rows. At least some of the sub-inductors in the inductor array form a plurality of inductor units; each of the plurality of inductor units includes a plurality of sub-inductors connected in series.
2. The inductor array according to claim 1, characterized in that, Each of the plurality of inductor units is configured such that the sub-inductors in the same inductor unit are arranged in a centrally symmetrical manner.
3. The inductor array according to claim 2, characterized in that, The inductor array further includes a magnetic core array; the magnetic core array includes multiple magnetic cores arranged in a centrally symmetrical manner. Furthermore, the sub-inductor is located at the boundary of the magnetic core.
4. The inductor array according to claim 3, characterized in that, The adjacent magnetic cores have a spacing.
5. The inductor array according to any one of claims 1 to 4, characterized in that, Any two inductor units among the plurality of inductor units are connected in parallel or in series.
6. The inductor array according to any one of claims 1 to 4, characterized in that, The input / output ports of the inductor unit are located on the periphery of the inductor array.
7. The inductor array according to any one of claims 1 to 4, characterized in that, The inductance values of the plurality of sub-inductors are equal.
8. The inductor array according to any one of claims 1 to 4, characterized in that, The inductance values of any two inductor units among the plurality of inductor units are not equal.
9. The inductor array according to claim 1, characterized in that, In the plurality of inductor units, at least two sub-inductors in at least one inductor unit are configured to share a magnetic circuit.
10. An integrated circuit, characterized in that, Including the inductor array as described in any one of claims 1 to 9.