Solar cell and solar cell sheet without a front grid

Abstract

The application relates to the technical field of photovoltaic solar cells, and discloses a main-grid-free solar cell and a solar cell, which comprise a semiconductor sheet and a plurality of secondary grid lines, the semiconductor sheet has a first surface; the plurality of secondary grid lines are arranged on the first surface and are arranged along a first direction, the secondary grid lines are parallel to each other, at least one auxiliary grid line is arranged on each secondary grid line, the auxiliary grid line intersects with the corresponding secondary grid line and is in contact with the corresponding secondary grid line at the intersection, each auxiliary grid line is arranged on the first surface, and in the first direction, the auxiliary grid lines arranged on the two adjacent secondary grid lines are arranged in a staggered mode. In the application, the auxiliary grid lines arranged in the staggered mode along the first direction can collect the current in the blank area between the secondary grid lines, and the increase of carrier recombination in a local area due to the excessively long distance from the secondary grid lines can be avoided, so that the power of the main-grid-free solar cell is affected.

Description

Technical Field

[0001] This application relates to the field of photovoltaic solar cell technology, and in particular to a gridless solar cell and solar cell. Background Technology

[0002] A solar cell is a device that converts light energy into electrical energy. Generally, the electrodes of a solar cell consist of thinner sub-grid lines and thicker main grid lines. The sub-grid lines mainly collect the current from the silicon wafer, while the main grid lines mainly collect the current from the sub-grid lines. Finally, the current is collected onto the solder strips that are welded to the main grid lines, thus completing the current collection.

[0003] In existing technologies, both the main grid lines and sub-grid lines of solar cells are made of silver, which consumes a significant amount of silver. Currently, the cost of silver paste accounts for a large proportion of the non-silicon cost of the cell. To save on silver paste costs, a gridless solar cell has been proposed, which eliminates the main grid lines.

[0004] However, removing the main grid lines of a solar cell increases the blank area between the sub-grid lines, resulting in poorer current collection efficiency and affecting the power output of the solar cell. Utility Model Content

[0005] This application discloses a gridless solar cell that can collect current in the blank area between the sub-grid lines by using auxiliary grid lines staggered along a first direction. This avoids the increase in carrier recombination in local areas due to excessive distance from the sub-grid lines, which would affect the power of the gridless solar cell. Moreover, this staggered arrangement can make full use of the auxiliary grid lines, allowing the auxiliary grid lines to cover more areas with fewer lines, further reducing the amount of silver paste used while collecting current more effectively and improving the power of the solar cell.

[0006] To achieve the above objectives, according to a first aspect of this application, a gridless solar cell is provided, comprising: a semiconductor wafer having a first surface;

[0007] Multiple sub-gate lines are disposed on the first surface and arranged along a first direction. The sub-gate lines are parallel to each other. Each sub-gate line is provided with at least one auxiliary gate line, which intersects with the corresponding sub-gate line and makes contact and conduction at the intersection. Each auxiliary gate line is disposed on the first surface. In the first direction, the auxiliary gate lines disposed on two adjacent sub-gate lines are staggered.

[0008] As an optional implementation, the width of each of the auxiliary gate lines is less than or equal to the width of the sub-gate line. The width of the auxiliary gate lines does not need to be too large; it can be equal to or less than the width of the sub-gate lines to minimize the amount of silver paste used and reduce production costs.

[0009] As an optional implementation, the width of the sub-grid line is 7μm to 9μm, and the width of the auxiliary grid line is 7μm to 9μm. This structure, which uses the auxiliary grid line to assist the sub-grid line in collecting current, ensures effective current collection and high power output while requiring less silver paste, thus saving significant silver paste costs and reducing the production cost of solar cells.

[0010] As an optional implementation, the auxiliary gate lines intersecting the same sub-gate line are parallel to each other and evenly distributed on the sub-gate line. This allows the auxiliary gate lines to collect the current around the corresponding intersecting sub-gate lines more evenly, improving the current collection effect.

[0011] As an optional implementation, each of the auxiliary gate lines is perpendicular to the sub-gate lines, and the spacing between two adjacent auxiliary gate lines on each sub-gate line is the same.

[0012] As an optional implementation, the intersection of each of the auxiliary gate lines and the sub-gate lines is located at the midpoint of the auxiliary gate line along its length direction, the length of each of the auxiliary gate lines is the same, and the spacing between adjacent sub-gate lines is the same as the length of the auxiliary gate line.

[0013] As an optional implementation, the gridless solar cell further includes:

[0014] Multiple sets of pads are spaced apart along the extension direction of the sub-gate line. Each set contains multiple pads, and the multiple pads in each set are spaced apart along a direction perpendicular to the sub-gate line. All pads are located on the sub-gate line, and a portion of the pads are located at the intersection of the sub-gate line and the auxiliary gate line.

[0015] As an optional implementation, the length of the pad along the first direction is less than its length along the second direction;

[0016] The second direction is perpendicular to the first direction.

[0017] As an alternative implementation, the length of the pad along the first direction gradually decreases from its center to both sides.

[0018] According to an embodiment of the second aspect of this application, a solar cell is provided, comprising:

[0019] The aforementioned gridless solar cell.

[0020] Compared with the prior art, the beneficial effects of this application are:

[0021] The gridless solar cell provided in this application can collect current in the blank areas between sub-grid lines through auxiliary grid lines. This allows current to flow more effectively from various regions of the semiconductor wafer to the sub-grid lines, preventing increased carrier recombination in local areas due to excessive distance from the sub-grid lines, thereby improving the power of the gridless solar cell. Furthermore, in this application, the auxiliary grid lines on adjacent sub-grid lines are staggered in the first direction. This staggered layout allows for more efficient use of the auxiliary grid lines, further expanding the current collection coverage without significantly increasing the number of auxiliary grid lines. This prevents excessive current concentration or leakage in the areas between adjacent sub-grid lines, thereby improving the overall current collection efficiency of the solar cell. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the structure of the gridless solar cell disclosed in the embodiments of this application;

[0024] Figure 2 This is a schematic diagram of the structure of the pads disclosed in the embodiments of this application.

[0025] Explanation of reference numerals in the attached figures:

[0026] 100 - Semiconductor wafer; 11 - First surface; 200 - Sub-gate line; 21 - Auxiliary gate line; 300 - Pad; a - First direction; b - Second direction; d1 - Length of pad along the first direction; d2 - Length of pad along the second direction. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] In this application, the terms "upper," "lower," "top," "bottom," "inner," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0029] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0030] Furthermore, the terms "set up," "equipped with," and "connected" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0031] Furthermore, the terms "first," "second," etc., are primarily used to distinguish different devices, elements, or components (which may be the same or different in specific type and construction), and are not intended to indicate or imply the relative importance or quantity of the indicated devices, elements, or components. Unless otherwise stated, "a plurality of" means two or more.

[0032] A solar cell, also known as a solar cell or photovoltaic cell, is a semiconductor device that directly converts sunlight into electrical energy. It utilizes the photovoltaic effect to achieve energy conversion and is the core component of solar power generation. Its working principle is based on the photovoltaic effect of semiconductor materials. When sunlight shines on the surface of a solar cell, the energy of the photons excites electrons in the semiconductor material, causing them to jump from the valence band to the conduction band, thus generating electron-hole pairs. These electrons and holes separate under the influence of a built-in electric field; electrons move towards the negative electrode of the cell, and holes move towards the positive electrode, thereby creating a potential difference across the two ends of the cell and generating a current.

[0033] The core material of a solar cell is the solar cell wafer. The wafer is made from silicon wafers through a series of processes, transforming them into a power-generating material. The current generated by the silicon wafer is conducted through silver grid lines printed on it. These silver grid lines are generally called the electrodes of the solar cell. Typically, the electrodes of a solar cell consist of thinner sub-grid lines and thicker main grid lines. The sub-grid lines are primarily responsible for collecting the current from the silicon wafer, while the main grid lines are primarily responsible for collecting the current from the sub-grid lines. The semiconductor wafer, as the foundation of the solar cell, is usually made of silicon and is classified as either P-type or N-type semiconductors. When sunlight shines on the semiconductor wafer, photon energy excites electron-hole pairs, generating photogenerated charge carriers. These photogenerated charge carriers separate under the influence of a built-in electric field, with electrons and holes collected by the N-type and P-type semiconductors, respectively. The sub-grid lines collect these charge carriers, while the main grid lines collect and transmit the current from each sub-grid line.

[0034] A grid-less solar cell has been proposed in the prior art, which eliminates the main grid lines. By eliminating the relatively thick main grid lines, a significant amount of silver paste can be saved, thereby greatly reducing the manufacturing cost of the solar cell. Therefore, grid-less solar cells have become a trend in solar cells and have a very broad application prospect.

[0035] However, removing the main grid lines of a solar cell increases the blank area between the sub-grid lines, which leads to a decrease in the current collection efficiency of the solar cell and affects its power output.

[0036] Based on this, this application embodiment also provides a gridless solar cell, which can collect current in the blank area between the sub-grid lines by means of auxiliary grid lines staggered along the first direction. This can avoid the increase of carrier recombination in local areas due to excessive distance from the sub-grid lines, which would affect the power of the gridless solar cell. Moreover, this staggered arrangement can make full use of the auxiliary grid lines, allowing the auxiliary grid lines to cover more areas with fewer lines, further reducing the amount of silver paste used while collecting current more effectively and improving the power of the solar cell.

[0037] The technical solution of this application will be further described below with reference to the embodiments and accompanying drawings.

[0038] Please see Figure 1 , Figure 1This is a schematic diagram of the structure of a gridless solar cell disclosed in an embodiment of this application. The embodiment of this application discloses a gridless solar cell, comprising: a semiconductor wafer 100 and multiple sub-gate lines 200. The semiconductor wafer 100 has a first surface 11; the multiple sub-gate lines 200 are all disposed on the first surface 11 and arranged along a first direction a, with each sub-gate line 200 parallel to the others. Each sub-gate line 200 is provided with at least one auxiliary gate line 21, which intersects with the corresponding sub-gate line 200 and makes contact and conduction at the intersection. Each auxiliary gate line 21 is disposed on the first surface 11, and in the first direction a, the auxiliary gate lines 21 disposed on adjacent sub-gate lines 200 are staggered.

[0039] Specifically, both the sub-grid line 200 and the auxiliary grid line 21 can be grid lines formed by silver paste. The width of the sub-grid line 200 can be 7μm to 9μm, and the width of the auxiliary grid line 21 can be 7μm to 9μm. The width of the auxiliary grid line 21 can be less than or equal to that of the sub-grid line 200. This allows the auxiliary grid line 21 to collect as much current as possible in the blank area between the sub-grid lines 200 and 201, while minimizing the amount of silver paste used and reducing the production cost of solar cells.

[0040] Multiple sub-gate lines 200 are provided. These sub-gate lines 200 are parallel to each other and are all disposed on the first surface 11 of the semiconductor chip 100, which can collect and transmit the current on the first surface 11 of the semiconductor chip 100.

[0041] One or more auxiliary grid lines 21 can be provided on each sub-grid line 200. These auxiliary grid lines 21 intersect with the corresponding sub-grid line 200. Intersection means that the auxiliary grid line 21 and the corresponding sub-grid line 200 have only one intersection point. The auxiliary grid line 21 and the sub-grid line 200 can make contact and conduct at the intersection point, so that the auxiliary grid line 21 can be electrically connected to the sub-grid line 200. In this way, the collected current can be transferred to the auxiliary grid line 21, which is equivalent to enabling the auxiliary grid line 21 to collect current from more blank areas.

[0042] The auxiliary grid lines 21 on two adjacent sub-grid lines 200 are also staggered, as can be seen from the following: Figure 1As shown, in the first direction a, the auxiliary gate lines 21 on two adjacent sub-gate lines 200 are not on the same straight line. That is, in the projection on the first direction a, the first auxiliary gate line 21 on the second sub-gate line 200 along the second direction b is located between the first and second auxiliary gate lines 21 on the first sub-gate line 200 along the second direction b, and the second auxiliary gate line 21 on the second sub-gate line 200 along the second direction b is located between the second and third auxiliary gate lines 21 on the first sub-gate line 200 along the second direction b, and so on, according to the above rules. This staggered arrangement of auxiliary gate lines 21 can collect the current generated on the first surface 11 of the semiconductor wafer 100 more uniformly, making up for the problem of poor current collection effect that may be caused by the absence of a main gate. Moreover, this staggered arrangement is equivalent to expanding the coverage of current collection, which can collect the current of more areas with fewer auxiliary gate lines 21, making full use of the auxiliary gate lines 21, without having to add too many auxiliary gate lines 21 for current collection, thereby further reducing costs.

[0043] According to the embodiments of the present invention, the gridless solar cell can collect current in the blank areas between the sub-grid lines 200 through auxiliary grid lines 21, so that the current can flow more effectively from various regions of the semiconductor wafer 100 to the sub-grid lines 200. This avoids the increase of carrier recombination in local areas due to excessive distance from the sub-grid lines 200, thereby improving the current and power of the gridless solar cell. Moreover, in the first direction a, the auxiliary grid lines 21 on two adjacent sub-grid lines 200 are staggered. This staggered layout can make fuller use of the auxiliary grid lines 21, and without significantly increasing the number of auxiliary grid lines 21, the coverage of current collection can be further expanded, avoiding excessive concentration or leakage of current in the areas between adjacent sub-grid lines 200, thereby improving the current collection efficiency of the entire solar cell.

[0044] Combination Figure 1 In some embodiments, the width of each auxiliary gate line 21 is less than or equal to the width of the sub-gate line 200.

[0045] Specifically, the auxiliary grid line 21 is mainly responsible for collecting current from the auxiliary sub-grid line 200. By collecting the current between the sub-grid lines 200, it can prevent the increase of carrier recombination in local areas due to excessive distance from the grid line, which would affect the power of the solar cell. Therefore, the width of the auxiliary grid line 21 does not need to be too large, and can be equal to or smaller than the width of the sub-grid line 200, in order to minimize the amount of silver paste used and reduce production costs.

[0046] Combination Figure 1In some embodiments, the width of the sub-gate line 200 is 7μm to 9μm, and the width of the auxiliary gate line 21 is 7μm to 9μm.

[0047] Specifically, the width of the sub-grid line 200 is 7μm to 9μm, and the width of the auxiliary grid line 21 is 7μm to 9μm. Compared with the existing technology's thicker main grid line and sub-grid line 200 combination structure, the structure proposed in this application uses the sub-grid line 200 to collect and transmit current, and the auxiliary grid line 21 to assist the sub-grid line 200 in collecting current. While ensuring the current collection effect and power output, it requires less silver paste, which can save a lot of silver paste cost, thereby reducing the production cost of solar cells.

[0048] In some embodiments, the auxiliary gate lines 21 that intersect the same sub-gate line 200 are parallel to each other and are evenly distributed on the sub-gate line 200.

[0049] Specifically, a plurality of auxiliary gate lines 21 can be provided on a sub-gate line 200. These auxiliary gate lines 21 can be parallel to each other and evenly distributed on the sub-gate line 200. Along the second direction b, that is, along the extension direction of the sub-gate line 200, the spacing between each auxiliary gate line 21 is the same, and they can fill the sub-gate line 200, so that the auxiliary gate lines 21 can collect the current around the entire sub-gate line 200, that is, the rectangular area centered on the sub-gate line 200. This allows the auxiliary gate lines 21 to collect the current around the sub-gate lines 200 that they intersect more evenly, improving the current collection effect.

[0050] Combination Figure 1 In some embodiments, each auxiliary gate line 21 is perpendicular to the sub-gate line 200, and the spacing between two adjacent auxiliary gate lines 21 on each sub-gate line 200 is the same.

[0051] Specifically, the sub-gate lines 200 are parallel to each other, and the auxiliary gate lines 21 are perpendicular to the sub-gate lines 200, so that the auxiliary gate lines 21 and sub-gate lines 200 generally form a grid-like structure, which can more uniformly cover the entire first surface 11 of the semiconductor wafer 100. Moreover, the spacing between two adjacent auxiliary gate lines 21 located on adjacent sub-gate lines 200 is the same, which can uniformly cover the entire first surface 11, thereby effectively collecting current in various blank areas and improving the power of the solar cell.

[0052] Combination Figure 1 In some embodiments, the intersection of each auxiliary gate line 21 and the sub-gate line 200 is located at the midpoint of the auxiliary gate line 21 along its length direction. The lengths of each auxiliary gate line 21 are the same, and the spacing between adjacent sub-gate lines 200 is the same as the length of the auxiliary gate line 21.

[0053] Specifically, all auxiliary gate lines 21 have the same length, which facilitates their production. The intersection points of each auxiliary gate line 21 with the corresponding sub-gate line 200 are all located at the midpoint of the auxiliary gate line 21 along its length. This ensures that the auxiliary gate line 21 extends the same distance on both sides of the sub-gate line 200 along the first direction a, allowing the auxiliary gate line 21 to collect the current on both sides of the sub-gate line 200 along the first direction a more evenly.

[0054] Furthermore, by setting the length of the auxiliary grid line 21 to be equal to the spacing between adjacent sub-grid lines 200, and ensuring that the intersection points of each auxiliary grid line 21 with the corresponding intersecting sub-grid line 200 are all located at the midpoint of the auxiliary grid line 21 along its length, the area between adjacent sub-grid lines 200 can be covered by the half-auxiliary grid line 21 that intersects and extends from the first sub-grid line 200 and the half-auxiliary grid line 21 that intersects and extends from the second sub-grid line 200. This allows the auxiliary grid line 21 to completely cover the blank area between the two sub-grid lines 200 along the first direction a. However, these two half-auxiliary grid lines 21 will be staggered and not connected to each other. The auxiliary grid line 21 can more evenly and comprehensively cover the blank area between adjacent sub-grid lines 200, making full use of the auxiliary grid line 21 to cover more areas, improving the current collection effect of the auxiliary grid line 21, and enabling the auxiliary grid line 21 to absorb the current between adjacent sub-grid lines 200 more evenly and comprehensively, thereby improving the power of the solar cell.

[0055] Combination Figure 1 and Figure 2 , Figure 2 This is a schematic diagram of the structure of the pads disclosed in an embodiment of this application. In some embodiments, the gridless solar cell further includes: multiple sets of pads 300, which are spaced apart along the extension direction of the sub-grid line 200. Each set of pads 300 contains multiple pads, and the multiple pads 300 in each set are spaced apart along a direction perpendicular to the sub-grid line 200. All pads 300 are located on the sub-grid line 200, and a portion of the pads 300 are located at the intersection of the sub-grid line 200 and the auxiliary grid line 21.

[0056] Specifically, in a gridless solar cell, after the main grid is eliminated, solder ribbons can be directly welded to the sub-grid lines 200. However, this welding method reduces the welding strength. The gridless solar cell proposed in this embodiment also has multiple sets of solder pads 300, each set containing multiple pads 300. These pads 300 are arranged in an array, with each set spaced apart along a first direction a, and multiple sets spaced apart along the extension direction of the sub-grid lines 200. Solder ribbons extend along the first direction a and are spaced apart along the extension direction of the sub-grid lines 200. The number of solder ribbons is the same as the number of sets of solder pads 300. Each solder ribbon corresponds to a set of solder pads 300. The solder pads 300 increase the welding strength between the solder ribbons and the sub-grid lines 200, reducing problems such as incomplete soldering and over-soldering during the welding process, improving welding quality, and thus enhancing the reliability of the solar cell.

[0057] Furthermore, all pads 300 are located on the sub-gate lines 200, and some pads 300 are positioned at the intersections of the sub-gate lines 200 and the auxiliary gate lines 21. That is, because the auxiliary gate lines 21 on adjacent sub-gate lines 200 are staggered in the first direction a, and the pads 300 are arranged in an array, some pads 300 can be located at the intersections of the sub-gate lines 200 and the auxiliary gate lines 21. In other words, combining... Figure 1 As shown, in each group of pads 300, the first pad 300 can be directly placed on the sub-gate line 200, the second pad 300 is placed at the intersection of the sub-gate line 200 and the auxiliary gate line 21, then the third is placed on the sub-gate line 200, and the fourth is placed at the intersection of the sub-gate line 200 and the auxiliary gate line 21, and so on in a cyclical manner. This allows as many pads 300 as possible to be placed at the intersection of the sub-gate line 200 and the auxiliary gate line 21, further connecting and fixing the sub-gate line 200 and the auxiliary gate line 21 through the pads 300, thus improving the connection strength between the sub-gate line 200 and the auxiliary gate line 21. Furthermore, the current path is from the auxiliary gate line 21 to the sub-gate line 200, then to the pads 300, and finally to the solder ribbon. The auxiliary gate line 21 with pads 300 can also transfer current to the solder ribbon more quickly, further improving the power output of the solar cell.

[0058] Combination Figure 2 In some embodiments, the length d1 of the pad 300 along the first direction a is less than its length d2 along the second direction b;

[0059] Wherein, the second direction b is perpendicular to the first direction a.

[0060] Specifically, in combination Figure 2Since the solder strips extend along the first direction a and are then spaced apart along the second direction b, misalignment may occur during soldering. In this embodiment, the length d1 of the pad 300 along the first direction a is shorter than its length d2 along the second direction b. That is, the length d2 of the pad 300 along the second direction b is longer, which increases the coverage area of ​​the pad 300 along the second direction b, ensuring proper contact between the solder strips and the pad 300. Simultaneously, the shorter length d1 along the first direction a in this embodiment minimizes the coverage area of ​​the pad 300 along the first direction a, reducing the light-shielding area of ​​the pad 300 on the first surface 11 of the semiconductor wafer 100, reducing the impact on the current collected on the first surface 11, and improving the power of the solar cell.

[0061] Combination Figure 2 In some embodiments, the length d1 of the pad 300 along the first direction a gradually decreases from the middle to both sides.

[0062] Specifically, since the solder ribbon is designed to prevent misalignment during welding, the central portion of the pad 300 has the highest utilization rate. The wider central portion of the pad 300 allows for better welding with the solder ribbon, while the gradually narrowing sides reduce the coverage area of ​​the pad 300, decrease its shading area, and minimize its impact on the current collected on the first surface 11, thus improving the solar cell's power. Its length along the second direction b does not need to be changed, allowing it to still cover the solder ribbon that may have some misalignment along the second direction b.

[0063] The pad 300 can specifically be an octagon. Through the octagonal structural design, it can have a certain length in the first direction 'a', while minimizing its length in the second direction 'b'. Figure 2 The octagonal structure shown has a hypotenuse that can further reduce the coverage area of ​​the pad 300 without affecting the length of the pad 300 in the second direction b. This can reduce the light-shielding area of ​​the pad 300 on the first surface 11 of the semiconductor wafer 100, reduce the impact on the current collected on the first surface 11, and improve the power of the solar cell.

[0064] In actual production, the pad 300 can be a long rectangular pad 300 with its strip-like extension direction being the second direction b. Then, the four corners are chamfered to further reduce the light-shielding area of ​​the pad 300.

[0065] Please see 1 and Figure 2 This application discloses a solar cell, including the aforementioned gridless solar cell.

[0066] Specifically, the solar cell constructed using the gridless solar cell proposed in this application embodiment can not only significantly reduce the amount of silver paste used and reduce production costs by eliminating the main grid, but also improve the current collection capability of the sub-grid line 200 through the auxiliary grid line 21. The auxiliary grid line 21 proposed in this application embodiment can, through reasonable layout, use fewer grid lines to more uniformly and comprehensively cover the blank area between the sub-grid lines 200, so that the current can flow more effectively from all areas of the semiconductor wafer 100 to the sub-grid line 200, avoiding the increase of carrier recombination in local areas due to excessive distance from the sub-grid line 200, thereby improving the current and power of the solar cell. Furthermore, through the design of the solder pad 300, the welding strength between the solder strip and the semiconductor wafer 100 can be increased, reducing problems such as cold solder joints and over-soldering during the welding process, improving welding quality, and thus enhancing the reliability of the solar cell.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A gridless solar cell, characterized in that, include: A semiconductor wafer (100) having a first surface (11); Multiple sub-gate lines (200) are disposed on the first surface (11) and arranged along the first direction (a). The sub-gate lines (200) are parallel to each other. Each sub-gate line (200) is provided with at least one auxiliary gate line (21). The auxiliary gate line (21) intersects with the corresponding sub-gate line (200) and makes contact and conduction at the intersection. Each auxiliary gate line (21) is disposed on the first surface (11). In the first direction (a), the auxiliary gate lines (21) disposed on two adjacent sub-gate lines (200) are staggered.

2. The gridless solar cell according to claim 1, characterized in that, The width of each of the auxiliary gate lines (21) is less than or equal to the width of the sub-gate line (200).

3. The gridless solar cell according to claim 2, characterized in that, The width of the sub-gate line (200) is 7μm to 9μm, and the width of the auxiliary gate line (21) is 7μm to 9μm.

4. The gridless solar cell according to claim 1, characterized in that, Each of the auxiliary grid lines (21) intersecting the same sub-grid line (200) is parallel to each other and is evenly distributed on the sub-grid line (200).

5. The gridless solar cell according to claim 4, characterized in that, Each of the auxiliary gate lines (21) is perpendicular to the sub-gate lines (200), and the spacing between any two adjacent auxiliary gate lines (21) on each sub-gate line (200) is the same.

6. The gridless solar cell according to claim 5, characterized in that, The positions where each of the auxiliary gate lines (21) intersects with the sub-gate lines (200) are all located at the midpoint of the auxiliary gate line (21) along its length direction. Each of the auxiliary gate lines (21) has the same length, and the spacing between adjacent sub-gate lines (200) is the same as the length of the auxiliary gate line (21).

7. The gridless solar cell according to any one of claims 1-6, characterized in that, The gridless solar cell also includes: Multiple sets of pads (300) are spaced apart along the extension direction of the sub-gate line (200). Each set of pads (300) contains multiple pads. The multiple pads (300) in each set are spaced apart along a direction perpendicular to the sub-gate line (200). All pads (300) are located on the sub-gate line (200), and a portion of the pads (300) are located at the intersection of the sub-gate line (200) and the auxiliary gate line (21).

8. The gridless solar cell according to claim 7, characterized in that, The length (d1) of the pad (300) along the first direction (a) is less than its length (d2) along the second direction (b); Wherein, the second direction (b) is perpendicular to the first direction (a).

9. The gridless solar cell according to claim 8, characterized in that, The length (d1) of the pad (300) along the first direction (a) gradually decreases from the middle to both sides.

10. A solar cell, characterized in that, include: The gridless solar cell as described in any one of claims 1-9.

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