Chip package structure

Abstract

The application discloses a chip packaging structure and belongs to the technical field of semiconductors. The chip packaging structure comprises a first re-wiring structure, a first chip, a heat conduction layer and a heat conduction column. The first re-wiring structure comprises at least one conductive circuit. The first chip is located on the first re-wiring structure and connected with the conductive circuit. The heat conduction layer is located on the first chip and in contact with the first chip. The heat conduction column is located on the side of the first chip and in contact with the heat conduction layer. The at least one conductive circuit comprises a first conductive circuit located at the bottom of the heat conduction column, and the heat conduction column is connected with the first conductive circuit. The application can improve the heat dissipation efficiency of the chip.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a chip packaging structure. Background Technology

[0002] As product performance demands increase, overheating issues with certain chips in some products are becoming more severe. Related technologies involve directly covering the chip with a packaging layer, but this layer is made of resin, which has poor thermal conductivity and cannot effectively dissipate the chip's heat. Utility Model Content

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a chip packaging structure that can improve the heat dissipation efficiency of the chip.

[0004] In a first aspect, this application provides a chip packaging structure, including:

[0005] The first rewiring structure includes at least one conductive line;

[0006] A first chip is located on the first redistribution structure and is connected to the conductive line;

[0007] A thermally conductive layer is located on the first chip and is in contact with the first chip;

[0008] A heat-conducting pillar is located on the periphery of the first chip and is in contact with the heat-conducting layer;

[0009] The at least one conductive line includes a first conductive line located at the bottom of the heat-conducting column, and the heat-conducting column is connected to the first conductive line.

[0010] According to the chip packaging structure of this application, by providing a heat-conducting layer in contact with the first chip and providing heat-conducting pillars in contact with the heat-conducting layer on the periphery of the first chip, and connecting the heat-conducting pillars to the first conductive line at the bottom, the heat of the first chip is quickly dissipated through the heat-conducting path formed by the heat-conducting layer, the heat-conducting pillars and the first conductive line. The heat-conducting path is short, which effectively improves the heat dissipation efficiency of the chip. The first conductive line in the first rewiring structure is used for heat conduction, which avoids increasing the circuit complexity in the first rewiring structure.

[0011] According to one embodiment of this application, the first rewiring structure further includes a heat-conducting line connected between the heat-conducting pillar and the first conductive line, and the heat-conducting line corresponds to the position of the heat-conducting pillar.

[0012] According to one embodiment of this application, the first rewiring structure further includes a plurality of connection structures, through which the plurality of conductive lines are connected;

[0013] The first rewiring structure further includes multiple heat-conducting structures. The heat-conducting lines are respectively connected to the heat-conducting pillars and the first conductive lines, and the positions of the heat-conducting structures correspond to those of the heat-conducting pillars.

[0014] The lateral dimension of the heat-conducting structure is larger than the lateral dimension of the connecting structure.

[0015] According to one embodiment of this application, the first rewiring structure further includes a plurality of connection structures, through which the plurality of conductive lines are connected;

[0016] The at least one conductive line includes a plurality of first conductive lines stacked at the bottom of the heat-conducting column, and the plurality of connection structures include a first connection structure connected between adjacent first conductive lines, and the first connection structure corresponds to the position of the heat-conducting column.

[0017] The lateral dimension of the first connection structure is larger than the lateral dimension of the other connection structures.

[0018] According to one embodiment of this application, the thermally conductive layer includes a thermally conductive pattern.

[0019] According to one embodiment of this application, the chip packaging structure further includes a plurality of bumps located between the first chip and the first rewiring structure, wherein the first chip is connected to a plurality of conductive lines through the plurality of bumps respectively;

[0020] The first chip has a heat source area on the side near the first redistribution structure, the plurality of bumps includes a target bump located in the heat source area, and the at least one conductive line further includes a second conductive line located at the bottom of the target bump and connected to the target bump.

[0021] The lateral dimension of the target protrusion is larger than the lateral dimension of the other protrusions.

[0022] According to one embodiment of this application, the first rewiring structure further includes a plurality of connection structures, through which the plurality of conductive lines are connected;

[0023] The at least one conductive line includes a plurality of second conductive lines stacked on the bottom of the target bump, and the plurality of connection structures include a second connection structure connected between adjacent second conductive lines, and the second connection structure corresponds to the position of the target bump;

[0024] The lateral dimension of the second connection structure is larger than the lateral dimension of the other connection structures.

[0025] According to one embodiment of this application, the chip packaging structure further includes:

[0026] A second rewiring structure covers the heat-conducting layer;

[0027] The second chip is located on the second redistribution structure and is connected to the second redistribution structure;

[0028] Conductive pillars are located on the periphery of the first chip and are connected to the conductive lines in the second rewiring structure and the first rewiring structure, respectively.

[0029] The lateral dimension of the heat-conducting column is larger than the lateral dimension of the conductive column.

[0030] According to one embodiment of this application, the heat-conducting pillar is located on the side of the conductive pillar close to the first chip.

[0031] According to one embodiment of this application, the thermally conductive layer includes a metal layer; and / or,

[0032] The heat-conducting pillar comprises a metal pillar.

[0033] The above-described one or more technical solutions in the embodiments of this application have at least one of the following technical effects:

[0034] By setting a heat-conducting layer on the first chip that contacts the first chip, and setting heat-conducting pillars on the periphery of the first chip that contact the heat-conducting layer, and connecting the heat-conducting pillars to the first conductive line at the bottom, the heat of the first chip is quickly dissipated through the heat-conducting path formed by the heat-conducting layer, the heat-conducting pillars, and the first conductive line. The heat-conducting path is short, which effectively improves the heat dissipation efficiency of the chip. The first conductive line in the first rewiring structure is used for heat conduction, which avoids increasing the circuit complexity in the first rewiring structure.

[0035] Furthermore, by increasing the lateral dimensions of the heat-conducting pillars, heat-conducting structures, the first connection structure, and / or the second connection structure, the heat conduction channels are widened, thereby further improving the heat extraction efficiency of the chip.

[0036] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0037] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0038] Figure 1 This is a schematic diagram of the chip packaging structure provided in the embodiments of this application;

[0039] Figure 2 This is one of the schematic diagrams of the thermal conductive layer in the chip packaging structure provided in the embodiments of this application;

[0040] Figure 3 This is the second schematic diagram of the thermal conductive layer in the chip packaging structure provided in this application embodiment. Detailed Implementation

[0041] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0042] The chip packaging structure provided in the embodiments of this application is described below with reference to the accompanying drawings.

[0043] Figure 1 This is a schematic diagram of the chip packaging structure provided in an embodiment of this application.

[0044] like Figure 1 As shown, the chip packaging structure provided in this application embodiment includes a first redistribution structure 1, a first chip 2, a thermal conductive layer 3, and a thermal conductive pillar 4.

[0045] The first rewiring structure 1 includes at least one conductive line 11. When the first rewiring structure 1 includes multiple conductive lines 11, the multiple conductive lines 11 can be disposed in the same layer or located in different film layers. For example, the first rewiring structure 1 may include at least one circuit layer, each circuit layer including at least one conductive line 11. When the first rewiring structure 1 includes multiple circuit layers, the multiple circuit layers are stacked, and the conductive lines 11 in adjacent circuit layers are connected, such that the stacked circuit layers are sequentially connected. The material of the conductive line 11 may include metals, such as copper.

[0046] The first chip 2 is located on the first redistribution structure 1 and is connected to the conductive line 11. For example, the first chip 2 can be connected to the conductive line 11 in the top layer of a plurality of stacked circuit layers. Other devices can be connected to the first chip 2 through the conductive line 11 in the first redistribution structure 1.

[0047] The number of first chips 2 can be one or more. When the chip package structure includes multiple first chips 2, the multiple first chips 2 are respectively located on the first redistribution structure 1 and respectively connected to the first redistribution structure 1. For example, each circuit layer includes multiple conductive lines 11, and the multiple first chips 2 are respectively connected to the multiple conductive lines 11 in the top circuit layer of the multiple stacked circuit layers.

[0048] The thermally conductive layer 3 is located on the first chip 2 and is in contact with the first chip 2, that is, the thermally conductive layer 3 is in contact with the surface of the first chip 2 facing away from the first redistribution structure 1. The thermally conductive layer 3 can be made of a material with good thermal conductivity. In some embodiments, the thermally conductive layer 3 may include a metal layer, that is, the material of the thermally conductive layer 3 may include a metal, such as copper. The thermal conductivity of the thermally conductive layer 3 (such as metal) is much higher than that of the encapsulation layer (such as resin) in related technologies.

[0049] In the case where the chip packaging structure includes multiple first chips 2, a thermal conductive layer 3 can be provided on each first chip 2, or a thermal conductive layer 2 can be provided on some of the first chips 2 (such as a heat source chip).

[0050] The heat-conducting pillar 4 is located on the periphery of the first chip 2 and is in contact with the heat-conducting layer 3. The heat-conducting pillar 4 is situated between the heat-conducting layer 3 and the first redistribution structure 1, and can be positioned close to the first chip 2. The top of the heat-conducting pillar 4 (i.e., the side of the heat-conducting pillar 4 closest to the heat-conducting layer 3) can extend longitudinally into the heat-conducting layer 3, so that the surface of the heat-conducting pillar 4 closest to the heat-conducting layer 3 is in contact with the heat-conducting layer 3. The heat-conducting pillar 4 can be made of a material with good thermal conductivity. In some embodiments, the heat-conducting pillar 4 may include a metal pillar, i.e., the material of the heat-conducting pillar 4 may include a metal, such as copper.

[0051] The number of heat-conducting pillars 4 can be one or more. In the case where the chip package structure includes multiple heat-conducting pillars 4, the multiple heat-conducting pillars 4 can be arranged around the periphery of the first chip 2, and each heat-conducting pillar 4 is in contact with the heat-conducting layer 3.

[0052] At least one conductive line 11 includes a first conductive line 11a. The first conductive line 11a is located at the bottom of the heat-conducting pillar 4, and the orthographic projection of the heat-conducting pillar 4 on the first redistribution structure 1 at least partially overlaps with the first conductive line 11a. The heat-conducting pillar 4 is connected to the first conductive line 11a. The bottom of the heat-conducting pillar 4 (i.e., the side of the heat-conducting pillar 4 near the first redistribution structure 1) can extend longitudinally to the first redistribution structure 1, so that the side of the heat-conducting pillar 4 near the first redistribution structure 1 is connected to the first conductive line 11a. The first conductive line 11a can transmit signals and conduct heat.

[0053] The heat-conducting layer 3, the heat-conducting pillar 4, and the first conductive line 11a constitute the heat conduction path of the first chip 2. When the first chip 2 has a heat source on the side facing away from the first redistribution structure 1, the heat from the first chip 2 can be quickly conducted to the heat-conducting layer 3, and then rapidly dissipated through the heat-conducting layer 3, the heat-conducting pillar 4, and the first conductive line 11a, effectively improving the heat dissipation efficiency of the first chip 2 and ensuring that the temperature of the first chip 2 remains within its optimal operating range. Furthermore, the heat-conducting pillar 4 extends longitudinally, contacting the top heat-generating layer 3 and connecting to the bottom first conductive line 11a, minimizing the heat conduction path and further improving the heat dissipation efficiency of the first chip 2. Moreover, the first conductive line 11a, as part of the heat conduction path, utilizes the first conductive line 11a in the first redistribution structure 1 for heat conduction, avoiding increasing the circuit complexity in the first redistribution structure 1, and the arrangement of the heat conduction path has almost no impact on the overall volume of the structure.

[0054] In some embodiments, the heat-conducting pillar 4 is in contact with the first conductive line 11a. The top layer of the stacked circuit layers has a conductive line located at the bottom of the heat-conducting pillar 4, that is, the top layer includes the first conductive line 11a, and the bottom of the heat-conducting pillar 4 extends longitudinally to the top layer and is in direct contact with the first conductive line 11a.

[0055] The heat-conducting layer 3, the heat-conducting pillar 4, and the first conductive line 11a constitute the heat conduction path of the first chip 2. The heat of the first chip 2 is rapidly dissipated through the heat-conducting layer 3, the heat-conducting pillar 4, and the first conductive line 11a.

[0056] In some embodiments, the first rewiring structure 1 further includes a heat-conducting line 12 connected between the heat-conducting pillar 4 and the first conductive line 11a, and the heat-conducting line 12 corresponds to the position of the heat-conducting pillar 4. The heat-conducting line 12 can be made of a material with good thermal conductivity. In some embodiments, the material of the heat-conducting line 12 may include a metal, such as copper.

[0057] The top n layers of the N stacked circuit layers do not have conductive lines located at the bottom of the heat-conducting pillar 4; that is, none of the top n layers include the first conductive line 11a, while the (n+1)th top layer includes the first conductive line 11a, where 1 ≤ n < N. Heat-conducting lines 12 are respectively disposed in the top n layers, and the heat-conducting lines 12 are located between the heat-conducting pillar 4 and the first conductive line 11a, meaning the positions of the heat-conducting lines 12 and the heat-conducting pillar 4 correspond. The orthographic projection of the heat-conducting pillar 4 on the first rewiring structure 1 at least partially overlaps with the heat-conducting lines 12.

[0058] The heat-conducting pillar 4 is connected to the heat-conducting line 12, and the heat-conducting lines 12 of different layers are connected. The heat-conducting line 12 is connected to the first conductive line 11a, so that the heat-conducting layer 3, the heat-conducting pillar 4, the heat-conducting line 12, and the first conductive line 11a constitute the heat conduction path of the first chip 2. The heat of the first chip 2 is quickly dissipated through the heat-conducting layer 3, the heat-conducting pillar 4, the heat-conducting line 12, and the first conductive line 11a.

[0059] In this embodiment, when the heat-conducting pillar 4 and the first conductive line 11a cannot be directly connected, a heat-conducting line 12 is provided between the heat-conducting pillar 4 and the first conductive line 11a, so that the heat-conducting pillar 4 is connected to the first conductive line 11a through the heat-conducting line 12, so as to shorten the heat conduction path as much as possible and improve the heat dissipation efficiency of the first chip 2.

[0060] In some embodiments, such as Figure 1 As shown, the first rewiring structure 1 further includes multiple connection structures 13, through which multiple conductive lines 11 are connected. When the first rewiring structure 1 includes multiple stacked circuit layers, it also includes multiple insulating dielectric layers 14, with an insulating dielectric layer 14 between any two adjacent circuit layers. The connection structure 13 penetrates the insulating dielectric layer 14, and the conductive lines 11 in any two adjacent circuit layers are connected through the connection structure 13, so that the conductive lines 11 in the stacked circuit layers are sequentially connected. The connection structure 13 can be made of a material with good thermal conductivity. In some embodiments, the material of the connection structure 13 may include metal, such as copper.

[0061] The first rewiring structure 1 also includes multiple heat-conducting structures 15, with heat-conducting structures 15 connecting the heat-conducting line 12 to the heat-conducting pillar 4 and the first conductive line 11a, respectively. An insulating dielectric layer 14 is provided between the heat-conducting line 12 and the heat-conducting pillar 4, and the insulating dielectric layer 14 has heat-conducting structures 15 penetrating through it, allowing the heat-conducting line 12 to be connected to the heat-conducting pillar 4 through the heat-conducting structures 15. Similarly, an insulating dielectric layer 14 is provided between the heat-conducting line 12 and the first conductive line 11a, and the insulating dielectric layer 14 has heat-conducting structures 15 penetrating through it, allowing the heat-conducting line 12 to be connected to the first conductive line 11a through the heat-conducting structures 15.

[0062] When heat-conducting lines 12 are respectively arranged in the top n (n>1) layers of circuitry, the n layers of heat-conducting lines 12 are stacked, and an insulating dielectric layer 14 is provided between any two adjacent layers of heat-conducting lines 12. The insulating dielectric layer 14 has a heat-conducting structure 15 that penetrates the insulating dielectric layer 14, so that any two adjacent layers of heat-conducting lines 12 are connected through the heat-conducting structure 15. The heat-conducting pillar 4 is connected to the top layer of heat-conducting lines 12 through the heat-conducting structure 15, and the bottom layer of heat-conducting lines 12 is connected to the first conductive line 11a through the heat-conducting structure 15.

[0063] The thermally conductive structure 15 is positioned corresponding to the thermally conductive pillar 4, that is, the orthogonal projection of the thermally conductive pillar 4 on the first rewiring structure 1 at least partially overlaps with the thermally conductive structure 15, so that the thermally conductive pillar 4, the thermally conductive line 12, the thermally conductive structure 15 and the first conductive line 11a form a longitudinally extending thermally conductive channel, thereby shortening the thermal conduction path of the first chip 2 as much as possible and improving the heat dissipation efficiency of the first chip 2.

[0064] The lateral dimension of the heat-conducting structure 15 is larger than that of the connecting structure 13. This lateral dimension may include area, length, and / or diameter. When both the heat-conducting structure 15 and the connecting structure 13 have circular cross-sections, the lateral dimension can be the diameter, meaning the diameter of the heat-conducting structure 15 is larger than the diameter of the connecting structure 13. It should be noted that the diameter of the heat-conducting structure 15 can be increased as much as possible within its manufacturing process limits.

[0065] This embodiment increases the lateral dimension of the heat-conducting structure 15 to widen the heat-conducting channel formed by the heat-conducting structure 15, thereby further improving the heat dissipation efficiency of the first chip 2.

[0066] In some embodiments, the first rerouting structure 1 further includes a plurality of connection structures 13, through which a plurality of conductive lines 11 are connected. When the first rerouting structure 1 includes a plurality of stacked circuit layers, conductive lines 11 in any two adjacent circuit layers are connected through the connection structures 13, so that the conductive lines 11 in the stacked circuit layers are connected sequentially.

[0067] At least one conductive line 11 includes a plurality of first conductive lines 11a stacked at the bottom of the heat-conducting pillar 4. A plurality of connection structures 13 include a first connection structure 13a connecting adjacent first conductive lines 11a.

[0068] The bottom m layers of the N stacked circuit layers each have conductive lines located at the bottom of the heat-conducting pillars 4, meaning that each bottom m layer includes a first conductive line 11a, where 1 < m ≤ N. The first conductive lines 11a in the bottom m layers are stacked, and any two adjacent layers of first conductive lines 11a are connected by a first connecting structure 13a, so that the first conductive lines 11a in the bottom m layers are connected sequentially.

[0069] When m = N, the first conductive line 11a of the top layer can be in direct contact with the heat-conducting pillar 4, or the first conductive line 11a of the top layer can be connected to the heat-conducting pillar 4 through the heat-conducting structure 15. When 1 < m < N, the first conductive line 11a of the top layer can be connected to the heat-conducting line 12 through the heat-conducting structure 15.

[0070] The first connection structure 13a corresponds to the position of the heat-conducting pillar 4. That is, the orthographic projection of the heat-conducting pillar 4 on the first rewiring structure 1 overlaps at least partially with the first connection structure 13a, so that the heat-conducting pillar 4, the first connection structure 13a and the first conductive line 11a form a longitudinal heat-conducting channel, thereby shortening the heat conduction path of the first chip 2 as much as possible and improving the heat dissipation efficiency of the first chip 2.

[0071] The lateral dimension of the first connecting structure 13a is larger than the lateral dimensions of the other connecting structures 13. When the cross-section of the connecting structure 13 is circular, the lateral dimension can be the diameter, meaning the diameter of the first connecting structure 13a is larger than the diameter of the other connecting structures 13. It should be noted that the diameter of the first connecting structure 13a can be increased as much as possible within its manufacturing process.

[0072] When the first rewiring structure 1 also includes a heat-conducting structure 15, the diameter of the heat-conducting structure 15 is larger than the diameter of the other connection structures 13 besides the first connection structure 13a. The size relationship between the heat-conducting structure 15 and the second connection structure 13b is not specifically limited, that is, the diameter of the heat-conducting structure 15 can be greater than, less than or equal to the diameter of the first connection structure 13a.

[0073] This embodiment increases the lateral dimension of the first connection structure 13a to widen the heat conduction channel formed by the first connection structure 13a, thereby further improving the heat dissipation efficiency of the first chip 2.

[0074] In some embodiments, the thermally conductive layer 3 includes a thermally conductive pattern, i.e., the thermally conductive layer 3 has a hollow area, in order to reduce the amount of material (such as metal) used in the thermally conductive layer 3 and reduce the amount of thermal expansion and contraction of the metal, thereby reducing the stress impact on the product.

[0075] In some embodiments, such as Figure 2 As shown, the thermal conductive pattern in the thermal conductive layer 3 is in the form of a grid. The thermal conductive pattern in the thermal conductive layer 3 may include multiple grids uniformly distributed on the first chip 2 to uniformly conduct heat to the first chip 2.

[0076] In some embodiments, such as Figure 3 As shown, the first chip 2 has a first heat source region 21 on the side near the heat-conducting layer 3. The heat-conducting pattern in the heat-conducting layer 3 is arranged in a radiating pattern with the first heat source region 21 as the center. For example, the heat-conducting pattern includes multiple heat-conducting strips, one end of which is connected to the first heat source region 21, and the other end of which extends in a direction away from the first heat source region 21. This embodiment can effectively conduct heat to localized hot spots of the first chip 2.

[0077] It should be noted that the heat conduction pattern in the heat conduction layer 3 can also take other shapes depending on the size and location of the heat source area, and no specific limitation is made here.

[0078] In some embodiments, the chip package structure further includes a plurality of bumps 5 located between the first chip 2 and the first redistribution structure 1, wherein the first chip 2 is connected to a plurality of conductive lines 11 through the plurality of bumps 5. The top layer of the stacked circuit layers may include a plurality of conductive lines 11, and the first chip 2 is correspondingly connected to the plurality of conductive lines 11 in the top layer through the plurality of bumps 5. The material of the bumps may include metal, such as copper.

[0079] The first chip 2 has a heat source region (i.e., a second heat source region) on the side near the first redistribution structure 1, and the plurality of bumps 5 include a target bump 5a located in the second heat source region. In the case where the second heat source region has a plurality of bumps 5, at least one bump 5 in the second heat source region is a target bump 5a.

[0080] At least one conductive line 11 further includes a second conductive line 11b, which is located at the bottom of the target bump 5a. The orthographic projection of the target bump 5a onto the first redistribution structure 1 at least partially overlaps with the second conductive line 11b. The second conductive line 11b is connected to the target bump 5a. A pad is provided at the bottom of the target bump 5a, and the target bump 5a is connected to the second conductive line 11b through the pad. The second conductive line 11b can transmit signals and conduct heat.

[0081] The target bump 5a and the second conductive line 11b constitute another heat conduction path for the first chip 2. When the first chip 2 has a heat source (i.e., the second heat source region 22) on the side near the first redistribution structure 1, the heat from the second heat source region 22 can be quickly conducted to the target bump 5a and then rapidly discharged via the second conductive line 11b, effectively improving the heat dissipation efficiency of the first chip 2. Furthermore, the second conductive line 11b is located at the bottom of the target bump 5a, forming a vertical heat conduction channel between the target bump 5a and the second conductive line 11b, minimizing the heat conduction path and further improving the heat dissipation efficiency of the first chip 2.

[0082] The lateral dimension of the target bump 5a is larger than that of the other bumps 5. When the cross-section of the bump 5 is circular, the lateral dimension can be the diameter, meaning the diameter of the target bump 5a is larger than the diameter of the other bumps 5. It should be noted that the diameter of the target bump 5a can be as large as possible within its manufacturing process limits.

[0083] This embodiment increases the lateral dimension of the target bump 5a to widen the heat conduction channel formed by the target bump 5a, thereby further improving the heat dissipation efficiency of the first chip 2.

[0084] In some embodiments, the first rerouting structure 1 further includes a plurality of connection structures 13, through which a plurality of conductive lines 11 are connected. When the first rerouting structure 1 includes a plurality of stacked circuit layers, conductive lines 11 in any two adjacent circuit layers are connected through the connection structures 13, so that the conductive lines 11 in the stacked circuit layers are connected sequentially.

[0085] At least one conductive line 11 includes a plurality of second conductive lines 11b stacked on the bottom of the target bump 5a. A plurality of connection structures 13 include a second connection structure 13b connecting adjacent second conductive lines 11b.

[0086] Each of the N stacked circuit layers has a conductive line located at the bottom of the target bump 5a, meaning each circuit layer includes a second conductive line 11b. The second conductive lines 11b in the N circuit layers are stacked, and any two adjacent layers of second conductive lines 11b are connected by a second connection structure 13b, thus sequentially connecting the second conductive lines 11b in the N circuit layers. The top layer of second conductive line 11b is connected to the target bump 5a.

[0087] The second connection structure 13b corresponds to the position of the target bump 5a, that is, the orthographic projection of the target bump 5a on the first redistribution structure 1 overlaps at least partially with the second connection structure 13b, so that the target bump 5a, the second connection structure 13b and the second conductive line 11b form a longitudinal heat conduction channel, thereby shortening the heat conduction path of the first chip 2 as much as possible and improving the heat dissipation efficiency of the first chip 2.

[0088] The lateral dimension of the second connecting structure 13b is larger than the lateral dimensions of the other connecting structures 13. When the cross-section of the connecting structure 13 is circular, the lateral dimension can be the diameter, meaning the diameter of the second connecting structure 13b is larger than the diameter of the other connecting structures 13. It should be noted that the diameter of the second connecting structure 13b can be increased as much as possible within its manufacturing process.

[0089] When the first rewiring structure 1 also includes a first connection structure 13a, the diameter of the second connection structure 13b is larger than the diameter of the other connection structures 13 besides the first connection structure 13a and the second connection structure 13b. The size relationship between the first connection structure 13a and the second connection structure 13b is not specifically limited, that is, the diameter of the second connection structure 13b can be greater than, less than or equal to the diameter of the first connection structure 13a.

[0090] This embodiment increases the lateral dimension of the second connection structure 13b to widen the heat conduction channel formed by the second connection structure 13b, thereby further improving the heat dissipation efficiency of the first chip 2.

[0091] In some embodiments, the chip packaging structure further includes a first packaging layer 91, which covers the first redistribution structure 1 and is disposed around the first chip 2 and the heat-conducting pillar 4. The material of the first packaging layer 91 may include resin.

[0092] In some embodiments, the chip package structure further includes a second redistribution structure 6, a second chip 7, and conductive pillars 8.

[0093] The second rewiring structure 6 covers the thermally conductive layer 3. The second rewiring structure 6 may include alternately stacked insulating layers 61 and circuit layers, each circuit layer including at least one circuit 62. Circuits 62 in adjacent circuit layers are connected by a connection structure penetrating the insulating layer 61. The bottom insulating layer 61 in the second rewiring structure 6 covers the thermally conductive layer 3 and the first encapsulation layer 91. In cases where the thermally conductive layer 3 is not disposed on a portion of the first chip 2, the bottom insulating layer 61 in the second rewiring structure 6 also covers a portion of the first chip 2.

[0094] The second chip 7 is located on and connected to the second redistribution structure 6. The second chip 7 is connected to the line 62 in the top layer of the second redistribution structure 6. There can be one or more second chips 7. When the chip package structure includes multiple second chips 7, the multiple second chips 7 are respectively located on the second redistribution structure 6 and respectively connected to the line 62 in the second redistribution structure 6.

[0095] The conductive post 8 is located around the first chip 7 and is connected to the conductive lines 11 in the second redistribution structure 6 and the first redistribution structure 1, respectively. The conductive post 8 extends longitudinally, with its top connected to the line 62 in the bottom layer of the second redistribution structure 6 and its bottom connected to the conductive line 11 in the top layer of the first redistribution structure 1. The first encapsulation layer 91 is also disposed around the conductive post 8.

[0096] Conductive pillars 8 and heat-conducting pillars 4 are spaced apart. The lateral dimension of heat-conducting pillar 4 is larger than that of conductive pillar 8. When both conductive pillar 8 and heat-conducting pillar 4 have circular cross-sections, the lateral dimension can be the diameter, meaning the diameter of heat-conducting pillar 4 is larger than the diameter of conductive pillar 8. It should be noted that the diameter of heat-conducting pillar 4 can be as large as possible within its manufacturing process range.

[0097] This embodiment increases the lateral dimension of the heat-conducting pillar 4 to widen the heat-conducting channel formed by the heat-conducting pillar 4, thereby further improving the heat dissipation efficiency of the first chip 2.

[0098] It should be noted that when the second chip 7 has a heat source, the heat conduction path of the second chip 7 can also be formed by setting a heat conduction layer, heat conduction pillars and target bumps at the second chip 7, so as to quickly conduct the heat of the second chip 7.

[0099] In some embodiments, the heat-conducting pillar 4 is located on the side of the conductive pillar 8 closer to the first chip 2. Both the heat-conducting pillar 4 and the conductive pillar 8 are located on the periphery of the first chip 2. The heat-conducting pillar 4 can be positioned closer to the first chip 2 to shorten the heat conduction path of the first chip 2 as much as possible and improve the heat dissipation efficiency of the first chip 2.

[0100] In some embodiments, the chip packaging structure further includes a second packaging layer 92, which covers the second chip 7 and the second redistribution structure 6. The material of the second packaging layer 92 may include resin.

[0101] It should be noted that the chip package structure may also include other redistribution structures and chips, without further limitations. For example, the chip package structure may also include a third redistribution structure and a third chip. The third redistribution structure is located on the second package layer 92 and connected to the second redistribution structure 6, and the third chip is located on the third redistribution structure and connected to the third redistribution structure.

[0102] In summary, according to the chip packaging structure provided in this application embodiment, by providing a heat-conducting layer 3 in contact with the first chip 2, and providing heat-conducting pillars 4 in contact with the heat-conducting layer 3 on the periphery of the first chip 2, and connecting the heat-conducting pillars 4 to the first conductive line 11a at the bottom, the heat of the first chip 2 is quickly dissipated through the heat-conducting path formed by the heat-conducting layer 3, the heat-conducting pillars 4, and the first conductive line 11a. The heat-conducting path is short, effectively improving the heat dissipation efficiency of the chip. Moreover, by utilizing the first conductive line 11a in the first rewiring structure 1 for heat conduction, the circuit complexity in the first rewiring structure 1 is avoided. Furthermore, by increasing the lateral dimensions of the heat-conducting pillars 4, the heat-conducting structure 15, the first connection structure 13a, and / or the second connection structure 13b, the heat conduction channel is widened, further improving the heat dissipation efficiency of the chip.

[0103] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more.

[0104] In the description of this application, "multiple" means two or more.

[0105] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0106] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A chip packaging structure, characterized in that, include: The first rewiring structure includes at least one conductive line; A first chip is located on the first redistribution structure and is connected to the conductive line; A thermally conductive layer is located on the first chip and is in contact with the first chip; A heat-conducting pillar is located on the periphery of the first chip and is in contact with the heat-conducting layer; The at least one conductive line includes a first conductive line located at the bottom of the heat-conducting column, and the heat-conducting column is connected to the first conductive line.

2. The chip packaging structure according to claim 1, characterized in that, The first rewiring structure further includes a heat-conducting line connected between the heat-conducting pillar and the first conductive line, and the heat-conducting line corresponds to the position of the heat-conducting pillar.

3. The chip packaging structure according to claim 2, characterized in that, The first rewiring structure further includes multiple connection structures, through which the multiple conductive lines are connected; The first rewiring structure further includes multiple heat-conducting structures. The heat-conducting lines are respectively connected to the heat-conducting pillars and the first conductive lines, and the positions of the heat-conducting structures correspond to those of the heat-conducting pillars. The lateral dimension of the heat-conducting structure is larger than the lateral dimension of the connecting structure.

4. The chip packaging structure according to claim 1, characterized in that, The first rewiring structure further includes multiple connection structures, through which the multiple conductive lines are connected; The at least one conductive line includes a plurality of first conductive lines stacked at the bottom of the heat-conducting column, and the plurality of connection structures include a first connection structure connected between adjacent first conductive lines, and the first connection structure corresponds to the position of the heat-conducting column. The lateral dimension of the first connection structure is larger than the lateral dimension of the other connection structures.

5. The chip packaging structure according to claim 1, characterized in that, The thermally conductive layer includes a thermally conductive pattern.

6. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure further includes a plurality of bumps located between the first chip and the first rewiring structure, wherein the first chip is connected to a plurality of conductive lines through the plurality of bumps; The first chip has a heat source area on the side near the first redistribution structure, the plurality of bumps includes a target bump located in the heat source area, and the at least one conductive line further includes a second conductive line located at the bottom of the target bump and connected to the target bump. The lateral dimension of the target protrusion is larger than the lateral dimension of the other protrusions.

7. The chip packaging structure according to claim 6, characterized in that, The first rewiring structure further includes multiple connection structures, through which the multiple conductive lines are connected; The at least one conductive line includes a plurality of second conductive lines stacked on the bottom of the target bump, and the plurality of connection structures include a second connection structure connected between adjacent second conductive lines, and the second connection structure corresponds to the position of the target bump; The lateral dimension of the second connection structure is larger than the lateral dimension of the other connection structures.

8. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure also includes: A second rewiring structure covers the heat-conducting layer; The second chip is located on the second redistribution structure and is connected to the second redistribution structure; Conductive pillars are located on the periphery of the first chip and are connected to the conductive lines in the second rewiring structure and the first rewiring structure, respectively. The lateral dimension of the heat-conducting column is larger than the lateral dimension of the conductive column.

9. The chip packaging structure according to claim 8, characterized in that, The heat-conducting pillar is located on the side of the conductive pillar closest to the first chip.

10. The chip packaging structure according to any one of claims 1-9, characterized in that, The thermally conductive layer includes a metal layer; and / or, The heat-conducting pillar comprises a metal pillar.

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