Control circuit and control system of an encoder

Abstract

This application discloses a control circuit and control system for an encoder. The control circuit includes: a control module for receiving multiple sets of encoder data and outputting multiple enable signals; multiple transmitting circuits connected to the control module, each transmitting circuit corresponding to one of the enable signals; and multiple signal receiving circuits, each signal receiving circuit connected to both the transmitting circuits and the control module. Each transmitting circuit includes multiple signal transmitting circuits, each signal transmitting circuit corresponding to one of the signal receiving circuits, and each signal receiving circuit connected to the multiple signal transmitting circuits. The signal transmitting circuits output encoder data to their corresponding signal receiving circuits based on the received enable signals. The signal receiving circuits transmit encoder data to the control module, thereby acquiring the encoder data. Through this method, the control module achieves encoder data transmission using a smaller number of input and output pins.

Description

Technical Field

[0001] This application relates to the field of encoder control technology, and in particular to an encoder control circuit and control system. Background Technology

[0002] In motor control systems, encoders are commonly used to detect the angular displacement data of the motor's rotation and convert this data into electrical signals, which are then transmitted to the microcontroller in real time. Upon receiving the electrical signals, the microcontroller adjusts the control commands to the motor, achieving closed-loop feedback control of the motor's position.

[0003] When a single microcontroller needs to transmit data to multiple encoders simultaneously, parallel control is often used for the data transmission lines to achieve this. However, parallel control requires a large number of input and output pins on the microcontroller, thus increasing the cost of replacing the microcontroller with one that has more pins. Utility Model Content

[0004] This application mainly provides a control circuit and control system for an encoder, which solves the problem that parallel control requires a large number of input / output ports of the microcontroller.

[0005] This application provides a control circuit for an encoder, including:

[0006] The control module is used to receive multiple sets of encoder data and output multiple enable signals, wherein the multiple sets of encoder data are configured to correspond to the multiple enable signals;

[0007] Multiple transmitting circuits are connected to the control module, and the multiple transmitting circuits are configured to correspond to the multiple enable signals;

[0008] Multiple signal receiving circuits, each of which is connected to multiple transmitting circuits and the control module respectively;

[0009] Each of the transmitting circuits includes multiple signal transmitting circuits, and the multiple signal transmitting circuits are correspondingly configured with multiple signal receiving circuits. Each signal receiving circuit is connected to the multiple signal transmitting circuits. The signal transmitting circuit is used to output the encoder data to the corresponding signal receiving circuit based on the received corresponding enable signal. The signal receiving circuit is used to transmit the encoder data to the control module to realize the acquisition of the encoder data.

[0010] In some embodiments, each of the signal transmitting circuits includes a first common-mode inductor, a first capacitor, a first resistor, a first filter circuit, a second resistor, a second filter circuit, a third resistor, a first chip, and a third filter circuit.

[0011] The input terminal of the third filter circuit is connected to the control module, and the output terminal of the third filter circuit is connected to the enable pin of the first chip. The input pin of the first chip is connected to the encoder. The first differential signal pin of the first chip is connected to one end of the first filter circuit, and the other end of the first filter circuit is connected to the first input terminal of the first common-mode inductor. The second differential signal pin of the first chip is connected to one end of the second filter circuit, and the other end of the second filter circuit is connected to the second input terminal of the first common-mode inductor. One end of the first capacitor is connected between one end of the first filter circuit and the first differential signal pin of the first chip, and the other end of the first capacitor is connected to one end of the second filter circuit. The first resistor is connected between the first capacitor and the second differential signal pin of the first chip; one end of the first resistor is connected between the first capacitor and the first differential signal pin of the first chip, and the other end of the first resistor is connected between the first capacitor and the second differential signal pin of the first chip; one end of the second resistor is connected between the first filter circuit and the first differential signal pin of the first chip, and the other end of the second resistor is connected to the reference power supply; one end of the third resistor is connected between the second filter circuit and the second differential signal pin of the first chip, and the other end of the third resistor is grounded; the first output terminal and the second output terminal of the first common mode inductor are connected to the signal receiving circuit.

[0012] In some embodiments, when the control module controls the enable signal to be high, the first chip is used to receive the enable signal and the encoder data, convert the encoder data into a first differential signal and a second differential signal, and output the first differential signal through the first differential signal pin and the second differential signal through the second differential signal pin.

[0013] In some embodiments, the signal transmitting circuit further includes a first dual-channel bidirectional electrostatic transistor, a first end of which is connected between one end of the first resistor and a first differential signal pin of the first chip, a second end of which is connected between the other end of the first resistor and a second differential signal pin of the first chip, and a third end of which is grounded.

[0014] In some embodiments, the first filter circuit includes a second capacitor and a fourth resistor. One end of the fourth resistor is connected to a first differential signal pin of the first chip, and the other end of the fourth resistor is connected to a first input terminal of the first common-mode inductor. One end of the second capacitor is connected between one end of the fourth resistor and the first differential signal pin of the first chip, and the other end of the second capacitor is grounded.

[0015] The second filter circuit includes a third capacitor and a fifth resistor. One end of the fifth resistor is connected to the second differential signal pin of the first chip, and the other end of the fifth resistor is connected to the second input terminal of the first common-mode inductor. One end of the third capacitor is connected between one end of the fifth resistor and the second differential signal pin of the first chip, and the other end of the third capacitor is connected to the other end of the third resistor.

[0016] The third filter circuit includes a fourth capacitor, a sixth resistor, and a seventh resistor. One end of the sixth resistor is connected to the control module, and the other end of the sixth resistor is connected to the enable pin of the first chip. One end of the fourth capacitor is connected between the other end of the sixth resistor and the enable pin of the first chip, and the other end of the fourth capacitor is grounded. One end of the seventh resistor is connected between the other end of the sixth resistor and one end of the fourth capacitor, and the other end of the seventh resistor is connected to the other end of the fourth capacitor.

[0017] In some embodiments, the signal receiving circuit includes a second common-mode inductor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, and a second chip.

[0018] The first input terminal of the second common-mode inductor is connected to the first output terminal of the first common-mode inductor, the second input terminal of the second common-mode inductor is connected to the second output terminal of the first common-mode inductor, the first output terminal of the second common-mode inductor is connected to the first differential signal pin of the second chip through the ninth resistor, the second output terminal of the second common-mode inductor is connected to the second differential signal pin of the second chip through the eighth resistor, and the output pin of the second chip is connected to the control module.

[0019] One end of the seventh capacitor is connected between the eighth resistor and the second differential signal pin of the second chip, and the other end of the seventh capacitor is connected between the ninth resistor and the first differential signal pin of the second chip; one end of the twelfth resistor is connected between one end of the seventh capacitor and the second differential signal pin of the second chip, and the other end of the twelfth resistor is connected between the other end of the seventh capacitor and the first differential signal pin of the second chip; one end of the tenth resistor is connected between one end of the seventh capacitor and the second differential signal pin of the second chip, and the other end of the tenth resistor is grounded; one end of the eleventh resistor is connected between the other end of the seventh capacitor and the first differential signal pin of the second chip, and the other end of the eleventh resistor is connected to the reference power supply; one end of the fifth capacitor is connected between one end of the eighth resistor and one end of the tenth resistor, and the other end of the fifth capacitor is connected to the other end of the tenth resistor; one end of the sixth capacitor is connected between the ninth resistor and the eleventh resistor, and the other end of the sixth capacitor is grounded.

[0020] In some embodiments, the second chip is used to receive the first differential signal and the second differential signal through the second common-mode inductor and the seventh capacitor, convert the first differential signal and the second differential signal into encoder data, and output them to the control module.

[0021] In some embodiments, the signal receiving circuit further includes a second dual-channel bidirectional electrostatic transistor, the first end of which is connected between one end of the twelfth resistor and the second differential signal pin of the second chip, the second end of which is connected between the other end of the twelfth resistor and the first differential signal pin of the second chip, and the third end of which is grounded.

[0022] In some embodiments, when the control module controls an enable signal to be high, the corresponding transmitting circuit is used to control the corresponding plurality of signal transmitting circuits to start working based on the enable signal, and to send the encoder data to the corresponding signal receiving circuit.

[0023] This application also provides a control system, including the encoder control circuit as described above.

[0024] The beneficial effects of this application are as follows: This application forms a matrix control method by connecting the control module with multiple transmitting circuits and multiple receiving circuits, with each transmitting circuit including multiple signal transmitting circuits and each receiving circuit connected to multiple signal transmitting circuits; compared with the parallel control method, this application uses matrix control to achieve encoder data transmission with fewer input and output pins, thereby reducing the cost of replacing the control module with more pins. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0026] Figure 1 This is a circuit diagram of one embodiment of the encoder control circuit provided in this application;

[0027] Figure 2 This is a circuit diagram of one embodiment of the signal transmission circuit provided in this application;

[0028] Figure 3 This is a circuit diagram of one embodiment of the signal receiving circuit provided in this application. Detailed Implementation

[0029] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0031] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly indicating the number, specific order, or primary and secondary relationship of the indicated technical features.

[0032] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0033] Please see Figure 1 As shown, Figure 1 This is a circuit diagram of one embodiment of the encoder control circuit provided in this application. The control circuit 100 of this embodiment includes a control module 10, multiple transmitting circuits 20, and multiple signal receiving circuits 30.

[0034] The control module 10 is used to receive multiple sets of encoder data and output multiple enable signals, with the multiple sets of encoder data and multiple enable signals being set accordingly.

[0035] The control module 10 includes, but is not limited to, a microcontroller, a digital signal processor, or a field-programmable gate array.

[0036] Multiple transmitting circuits 20 are connected to the control module 10, and each transmitting circuit 20 is configured with a corresponding enable signal. Each signal receiving circuit 30 is connected to both the multiple transmitting circuits 20 and the control module 10.

[0037] In some embodiments, the plurality of transmitting circuits 20 include a plurality of encoders, that is, the plurality of transmitting circuits 20 include a plurality of sets of encoder data.

[0038] like Figure 1 As shown, the control module 10 outputs three enable signals to three transmitting circuits 20, and each of the three transmitting circuits 20 is connected to three signal receiving circuits 30. The three sets of encoder data from the three transmitting circuits 20 are transmitted to the control module 10 through the three signal receiving circuits 30. The three sets of encoder data correspond one-to-one with the three enable signals, and the three transmitting circuits 20 correspond one-to-one with the three enable signals.

[0039] Each transmitting circuit 20 includes multiple signal transmitting circuits 21, which are correspondingly configured with multiple signal receiving circuits 30. Each signal receiving circuit 30 is connected to multiple signal transmitting circuits 21. The signal transmitting circuit 21 is used to output encoder data to the corresponding signal receiving circuit 30 based on the received corresponding enable signal. The signal receiving circuit 30 is used to transmit encoder data to the control module 10 to realize the acquisition of encoder data.

[0040] In some embodiments, each signal transmitting circuit includes encoder data, and each signal receiving circuit 30 is connected to one of the multiple transmitting circuits 20, i.e., each signal receiving circuit 30 is connected to the multiple signal transmitting circuits 21.

[0041] The control module 10, the transmitting circuit 20, and the signal receiving circuit 30 are connected based on an RS485 bus; the signal transmitting circuit 21 includes, but is not limited to, the RS485 transmitting chipset inside the encoder, and the signal receiving circuit 30 includes, but is not limited to, the RS485 receiving chipset.

[0042] like Figure 1 As shown, each of the three transmitting circuits 20 includes three signal transmitting circuits 21. Each signal receiving circuit 30 is connected to one of the three transmitting circuits 21, that is, each signal receiving circuit 30 is connected to three signal transmitting circuits 21. At this time, the signal transmitting circuits 21 and the signal receiving circuits 30 form a matrix control method.

[0043] In this embodiment, the control module 10 is connected to multiple transmitting circuits 20 and multiple signal receiving circuits 30, and each transmitting circuit 20 includes multiple signal transmitting circuits 21, and each signal receiving circuit 30 is connected to multiple signal transmitting circuits 21, forming a matrix control method. Compared with the parallel control method, this embodiment uses matrix control to transmit encoder data with fewer input and output pins, thereby reducing the cost of replacing the control module 10 with more pins.

[0044] In practical applications, encoders are typically connected to the circuit board containing the microcontroller using conductive wires for electrical signal connection and data transmission. The longer the conductive wire, the more encoder channels can be connected, but the larger the parasitic parameters related to the circuit on the parallel data transmission bus become, such as parasitic capacitance, inductance, and resistance. These parasitic parameters affect the normal waveform of the electrical signal, thus impacting the stability of data transmission.

[0045] This embodiment uses matrix control, which reduces the use of input and output pins of the control module 10 and improves the stability of data transmission.

[0046] According to some embodiments of this application, when the control module 10 controls an enable signal to be high, the corresponding transmitting circuit 20 is used to control the corresponding multiple signal transmitting circuits 21 to start working based on the enable signal, and to send encoder data to the corresponding signal receiving circuit 30.

[0047] In some embodiments, when the control module 10 controls one enable signal to be high and the other enable signals to be low, the transmitting circuit 20 that receives the high-level enable signal controls multiple internal signal transmitting circuits 21 to start working and sends encoder data to the corresponding signal receiving circuit 30.

[0048] like Figure 1 As shown, the control module 10 controls the left-side transmitting circuit 20 to receive a high-level enable signal, while the other two enable signals are low-level. Based on the high-level enable signal, the three signal transmitting circuits 21 are controlled to start working and send the encoder data to the corresponding signal receiving circuits 30 respectively. At this time, all three signal receiving circuits receive a set of encoder data, and the three signal receiving circuits respectively transmit the corresponding encoder data to the control module 10.

[0049] In other embodiments, when the control module 10 controls one enable signal to be low and the other enable signals to be high, the transmitting circuit 20 that receives the low-level enable signal controls multiple internal signal transmitting circuits 21 to start working and sends encoder data to the corresponding signal receiving circuit 30.

[0050] According to some embodiments of this application, see Figure 2 As shown, Figure 2 This is a circuit diagram of an embodiment of the signal transmission circuit provided in this application. In this embodiment, each signal transmission circuit 21 includes a first common-mode inductor L1, a first capacitor C1, a first resistor R1, a first filter circuit 211, a second resistor R2, a second filter circuit 212, a third resistor R3, a first chip U1, and a third filter circuit 213.

[0051] The input terminal of the third filter circuit 213 is connected to the control module 10, and the output terminal of the third filter circuit 213 is connected to the enable pin DE of the first chip U1. The input pin D1 of the first chip U1 is connected to the encoder (not shown). The first differential signal pin A of the first chip U1 is connected to one end of the first filter circuit 211, and the other end of the first filter circuit 211 is connected to the first input terminal of the first common-mode inductor L1. The second differential signal pin B of the first chip U1 is connected to one end of the second filter circuit 212, and the other end of the second filter circuit 212 is connected to the second input terminal of the first common-mode inductor L1. One end of the first capacitor C1 is connected between one end of the first filter circuit 211 and the first differential signal pin A of the first chip U1, and the other end of the first capacitor C1 is connected between one end of the second filter circuit 212 and the second differential signal pin B of the first chip U1.

[0052] One end of the first resistor R1 is connected between one end of the first capacitor C1 and the first differential signal pin A of the first chip U1, and the other end of the first resistor R1 is connected between the other end of the first capacitor C1 and the second differential signal pin B of the first chip U1; one end of the second resistor R2 is connected between one end of the first filter circuit 211 and the first differential signal pin A of the first chip U1, and the other end of the second resistor R2 is connected to the reference power supply (+5V); one end of the third resistor R3 is connected between the second filter circuit 212 and the second differential signal pin B of the first chip U1, and the other end of the third resistor R3 is grounded; the first output terminal and the second output terminal of the first common mode inductor L1 are connected to the signal receiving circuit 30.

[0053] Among them, the first chip U1 includes, but is not limited to, an RS485 transceiver chip.

[0054] According to some embodiments of this application, when the control module 10 controls the enable signal to be high, the first chip U1 is used to receive the enable signal and encoder data, convert the encoder data into a first differential signal and a second differential signal, and output the first differential signal through the first differential signal pin A and the second differential signal through the second differential signal pin B.

[0055] like Figure 2 As shown, after the enable pin DE of the first chip U1 receives a high-level enable signal, it converts the encoder data received by the input pin D1 into a first differential signal and a second differential signal, and outputs the first differential signal and the second differential signal to the signal receiving circuit 30 through the first differential signal pin A and the second differential signal pin B, the first filter circuit 211 and the second filter circuit 212, and the first common-mode inductor L1, respectively.

[0056] The first common-mode inductor L1 and the first capacitor C1 are used to filter out common-mode interference; the first filter circuit 211 is used to filter out differential-mode interference on the first differential signal; the second filter circuit 212 is used to filter out differential-mode interference on the second differential signal; and the third filter circuit 213 is used to filter out differential-mode interference on the enable signal. The first resistor R1 is an RS485 bus matching resistor.

[0057] Since one end of the third resistor R3 is connected to the second differential signal and the other end of the third resistor R3 is connected to the electrical ground, one end of the second resistor R2 is connected to the first differential signal and the other end of the second resistor R2 is connected to the reference power supply (+5V), the voltage difference between the first differential signal and the second differential signal is kept constant at +5V under the default state, so as to avoid voltage instability at the nodes of the RS485 bus when it is not working.

[0058] In practical applications, encoders are typically connected to the circuit board containing the microcontroller using conductive wires for electrical signal connection and data transmission. The longer the conductive wire, the greater the electromagnetic interference it experiences in space. When multiple encoders are connected simultaneously, the interference from these multiple conductive wires accumulates at the common connection point, affecting the stability of data transmission and potentially damaging digital components on the circuit board. Using shielded conductive wires to address this interference problem would incur significant cost.

[0059] This embodiment strengthens the anti-interference design of the signal transmission circuit 21 by setting up the first common-mode inductor L1, the first chip U1, the first filter circuit 211, the second filter circuit 212, and the third filter circuit 213, solving the electromagnetic field interference problem caused by long and multiple conductive wires, and improving the stability of data transmission.

[0060] According to some embodiments of this application, the signal transmitting circuit 21 further includes a first dual-channel bidirectional electrostatic transistor D3. The first end of the first dual-channel bidirectional electrostatic transistor D3 is connected between one end of the first resistor R1 and the first differential signal pin A of the first chip U1. The second end of the first dual-channel bidirectional electrostatic transistor D3 is connected between the other end of the first resistor R1 and the second differential signal pin B of the first chip U1. The third end of the first dual-channel bidirectional electrostatic transistor D3 is grounded.

[0061] In some embodiments, the first dual-channel bidirectional electrostatic tube D3 includes two bidirectional electrostatic tubes connected in series, and the connection point of the two bidirectional electrostatic tubes is grounded.

[0062] This embodiment solves the problem of electrostatic damage to the first chip U1 caused by the injection of static electricity from the first differential signal and the second differential signal through the setting of the first dual-channel bidirectional electrostatic tube D3.

[0063] According to some embodiments of this application, the first filter circuit 211 includes a second capacitor C2 and a fourth resistor R4. One end of the fourth resistor R4 is connected to the first differential signal pin A of the first chip U1, and the other end of the fourth resistor R4 is connected to the first input terminal of the first common mode inductor L1. One end of the second capacitor C2 is connected between one end of the fourth resistor R4 and the first differential signal pin A of the first chip U1, and the other end of the second capacitor C2 is grounded.

[0064] The second capacitor C2 and the fourth resistor R4 form a low-pass filter, which can effectively filter out differential-mode interference on the first differential signal.

[0065] The second filter circuit 212 includes a third capacitor C3 and a fifth resistor R5. One end of the fifth resistor R5 is connected to the second differential signal pin B of the first chip U1, and the other end of the fifth resistor R5 is connected to the second input terminal of the first common mode inductor L1. One end of the third capacitor C3 is connected between one end of the fifth resistor R5 and the second differential signal pin B of the first chip U1, and the other end of the third capacitor C3 is connected to the other end of the third resistor R3.

[0066] The third capacitor C3 and the fifth resistor R5 form a low-pass filter, which can effectively filter out differential-mode interference on the second differential signal.

[0067] The third filter circuit 213 includes a fourth capacitor C4, a sixth resistor R6, and a seventh resistor R7. One end of the sixth resistor R6 is connected to the control module 10, and the other end of the sixth resistor R6 is connected to the enable pin DE of the first chip U1. One end of the fourth capacitor C4 is connected between the other end of the sixth resistor R6 and the enable pin DE of the first chip U1, and the other end of the fourth capacitor C4 is grounded. One end of the seventh resistor R7 is connected between the other end of the sixth resistor R6 and one end of the fourth capacitor C4, and the other end of the seventh resistor R7 is connected to the other end of the fourth capacitor C4.

[0068] The fourth capacitor C4 and the sixth resistor R6 form a low-pass filter, which can effectively filter out differential-mode interference on the enable signal.

[0069] According to some embodiments of this application, see Figure 3 As shown, Figure 3 This is a circuit diagram of an embodiment of the signal receiving circuit provided in this application. In this embodiment, the signal receiving circuit 30 includes a second common-mode inductor L2, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and a second chip U2.

[0070] The first input terminal of the second common-mode inductor L2 is connected to the first output terminal of the first common-mode inductor L1. The second input terminal of the second common-mode inductor L2 is connected to the second output terminal of the first common-mode inductor L1. The first output terminal of the second common-mode inductor L2 is connected to the first differential signal pin A of the second chip U2 through the ninth resistor R9. The second output terminal of the second common-mode inductor L2 is connected to the second differential signal pin B of the second chip U2 through the eighth resistor R8. The output pin RO of the second chip U2 is connected to the control module 10.

[0071] One end of the seventh capacitor C7 is connected between the eighth resistor R8 and the second differential signal pin B of the second chip U2, and the other end of the seventh capacitor C7 is connected between the ninth resistor R9 and the first differential signal pin A of the second chip U2. One end of the twelfth resistor R12 is connected between one end of the seventh capacitor C7 and the second differential signal pin B of the second chip U2, and the other end of the twelfth resistor R12 is connected between the other end of the seventh capacitor C7 and the first differential signal pin A of the second chip U2.

[0072] One end of the tenth resistor R10 is connected between one end of the seventh capacitor C7 and the second differential signal pin B of the second chip U2, and the other end of the tenth resistor R10 is grounded. One end of the eleventh resistor R11 is connected between the other end of the seventh capacitor C7 and the first differential signal pin A of the second chip U2, and the other end of the eleventh resistor R11 is connected to the reference power supply (+5V). One end of the fifth capacitor C5 is connected between the eighth resistor R8 and one end of the tenth resistor R10, and the other end of the fifth capacitor C5 is connected to the other end of the tenth resistor R10. One end of the sixth capacitor C6 is connected between the ninth resistor R9 and the eleventh resistor R11, and the other end of the sixth capacitor C6 is grounded.

[0073] The second chip U2 includes, but is not limited to, an RS485 transceiver chip.

[0074] Compared to the signal transmitting circuit 21, the signal receiving circuit 30 in this embodiment lacks the differential mode interference filtering on the enable signal; the differential mode interference filtering and common mode interference filtering on the first differential signal and the second differential signal in the signal receiving circuit 30 are the same as those in the signal transmitting circuit 21, and will not be described again here.

[0075] According to some embodiments of this application, the second chip U2 is used to receive the first differential signal and the second differential signal through the second common-mode inductor L2 and the seventh capacitor C7, convert the first differential signal and the second differential signal into encoder data, and output them to the control module 10.

[0076] like Figure 3 As shown, the first differential signal pin A and the second differential signal pin B of the second chip U2 receive the first differential signal and the second differential signal respectively. After the second chip U2 converts the first differential signal and the second differential signal into corresponding encoder data, it transmits them to the control module 10 through the output pin RO.

[0077] According to some embodiments of this application, the signal receiving circuit 30 further includes a second dual-channel bidirectional electrostatic transistor D2. The first end of the second dual-channel bidirectional electrostatic transistor D2 is connected between one end of the twelfth resistor R12 and the second differential signal pin B of the second chip U2. The second end of the second dual-channel bidirectional electrostatic transistor D2 is connected between the other end of the twelfth resistor R12 and the first differential signal pin A of the second chip U2. The third end of the second dual-channel bidirectional electrostatic transistor D2 is grounded.

[0078] In some embodiments, the second dual-channel bidirectional electrostatic tube D2 includes two bidirectional electrostatic tubes connected in series, and the connection point of the two bidirectional electrostatic tubes is grounded.

[0079] This embodiment solves the problem of electrostatic damage to the second chip U2 caused by the injection of static electricity from the first differential signal and the second differential signal through the setting of the second dual-channel bidirectional electrostatic tube D2.

[0080] Another embodiment of this application provides a control system, including the control circuit 100 of the above embodiment. The control system includes, but is not limited to, a mechanical equipment control system, such as a robot control system.

[0081] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A control circuit of an encoder, characterized by, include: The control module is used to receive multiple sets of encoder data and output multiple enable signals, wherein the multiple sets of encoder data are configured to correspond to the multiple enable signals; Multiple transmitting circuits are connected to the control module, and the multiple transmitting circuits are configured to correspond to the multiple enable signals; Multiple signal receiving circuits, each of which is connected to multiple transmitting circuits and the control module respectively; Each of the transmitting circuits includes multiple signal transmitting circuits, and the multiple signal transmitting circuits are correspondingly configured with multiple signal receiving circuits. Each signal receiving circuit is connected to the multiple signal transmitting circuits. The signal transmitting circuit is used to output the encoder data to the corresponding signal receiving circuit based on the received corresponding enable signal. The signal receiving circuit is used to transmit the encoder data to the control module to realize the acquisition of the encoder data.

2. The control circuit of claim 1, wherein, Each of the signal transmitting circuits includes a first common-mode inductor, a first capacitor, a first resistor, a first filter circuit, a second resistor, a second filter circuit, a third resistor, a first chip, and a third filter circuit; The input terminal of the third filter circuit is connected to the control module, and the output terminal of the third filter circuit is connected to the enable pin of the first chip. The input pin of the first chip is connected to the encoder. The first differential signal pin of the first chip is connected to one end of the first filter circuit, and the other end of the first filter circuit is connected to the first input terminal of the first common-mode inductor. The second differential signal pin of the first chip is connected to one end of the second filter circuit, and the other end of the second filter circuit is connected to the second input terminal of the first common-mode inductor. One end of the first capacitor is connected between one end of the first filter circuit and the first differential signal pin of the first chip, and the other end of the first capacitor is connected to one end of the second filter circuit. The first resistor is connected between the first capacitor and the second differential signal pin of the first chip; one end of the first resistor is connected between the first capacitor and the first differential signal pin of the first chip, and the other end of the first resistor is connected between the first capacitor and the second differential signal pin of the first chip; one end of the second resistor is connected between the first filter circuit and the first differential signal pin of the first chip, and the other end of the second resistor is connected to the reference power supply; one end of the third resistor is connected between the second filter circuit and the second differential signal pin of the first chip, and the other end of the third resistor is grounded; the first output terminal and the second output terminal of the first common mode inductor are connected to the signal receiving circuit.

3. The control circuit of claim 2, wherein, When the control module controls the enable signal to be high, the first chip is used to receive the enable signal and the encoder data, convert the encoder data into a first differential signal and a second differential signal, and output the first differential signal through the first differential signal pin and the second differential signal through the second differential signal pin.

4. The control circuit according to claim 2, characterized in that, The signal transmitting circuit further includes a first dual-channel bidirectional electrostatic transistor. The first end of the first dual-channel bidirectional electrostatic transistor is connected between one end of the first resistor and the first differential signal pin of the first chip. The second end of the first dual-channel bidirectional electrostatic transistor is connected between the other end of the first resistor and the second differential signal pin of the first chip. The third end of the first dual-channel bidirectional electrostatic transistor is grounded.

5. The control circuit according to claim 2, characterized in that, The first filter circuit includes a second capacitor and a fourth resistor. One end of the fourth resistor is connected to the first differential signal pin of the first chip, and the other end of the fourth resistor is connected to the first input terminal of the first common-mode inductor. One end of the second capacitor is connected between one end of the fourth resistor and the first differential signal pin of the first chip, and the other end of the second capacitor is grounded. The second filter circuit includes a third capacitor and a fifth resistor. One end of the fifth resistor is connected to the second differential signal pin of the first chip, and the other end of the fifth resistor is connected to the second input terminal of the first common-mode inductor. One end of the third capacitor is connected between one end of the fifth resistor and the second differential signal pin of the first chip, and the other end of the third capacitor is connected to the other end of the third resistor. The third filter circuit includes a fourth capacitor, a sixth resistor, and a seventh resistor. One end of the sixth resistor is connected to the control module, and the other end of the sixth resistor is connected to the enable pin of the first chip. One end of the fourth capacitor is connected between the other end of the sixth resistor and the enable pin of the first chip, and the other end of the fourth capacitor is grounded. One end of the seventh resistor is connected between the other end of the sixth resistor and one end of the fourth capacitor, and the other end of the seventh resistor is connected to the other end of the fourth capacitor.

6. The control circuit according to claim 3, characterized in that, The signal receiving circuit includes a second common-mode inductor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, and a second chip; The first input terminal of the second common-mode inductor is connected to the first output terminal of the first common-mode inductor, the second input terminal of the second common-mode inductor is connected to the second output terminal of the first common-mode inductor, the first output terminal of the second common-mode inductor is connected to the first differential signal pin of the second chip through the ninth resistor, the second output terminal of the second common-mode inductor is connected to the second differential signal pin of the second chip through the eighth resistor, and the output pin of the second chip is connected to the control module. One end of the seventh capacitor is connected between the eighth resistor and the second differential signal pin of the second chip, and the other end of the seventh capacitor is connected between the ninth resistor and the first differential signal pin of the second chip; one end of the twelfth resistor is connected between one end of the seventh capacitor and the second differential signal pin of the second chip, and the other end of the twelfth resistor is connected between the other end of the seventh capacitor and the first differential signal pin of the second chip; one end of the tenth resistor is connected between one end of the seventh capacitor and the second differential signal pin of the second chip, and the other end of the tenth resistor is grounded; one end of the eleventh resistor is connected between the other end of the seventh capacitor and the first differential signal pin of the second chip, and the other end of the eleventh resistor is connected to the reference power supply; one end of the fifth capacitor is connected between one end of the eighth resistor and one end of the tenth resistor, and the other end of the fifth capacitor is connected to the other end of the tenth resistor; one end of the sixth capacitor is connected between the ninth resistor and the eleventh resistor, and the other end of the sixth capacitor is grounded.

7. The control circuit of claim 6, wherein, The second chip is used to receive the first differential signal and the second differential signal through the second common-mode inductor and the seventh capacitor, convert the first differential signal and the second differential signal into encoder data, and output them to the control module.

8. The control circuit of claim 6, wherein, The signal receiving circuit further includes a second dual-channel bidirectional electrostatic transistor. The first end of the second dual-channel bidirectional electrostatic transistor is connected between one end of the twelfth resistor and the second differential signal pin of the second chip. The second end of the second dual-channel bidirectional electrostatic transistor is connected between the other end of the twelfth resistor and the first differential signal pin of the second chip. The third end of the second dual-channel bidirectional electrostatic transistor is grounded.

9. The control circuit according to claim 1, characterized in that, When the control module controls an enable signal to be high, the corresponding transmitting circuit controls the corresponding plurality of signal transmitting circuits to start working based on the enable signal, and transmits the encoder data to the corresponding signal receiving circuit.

10. A control system characterized by, Includes the control circuit as described in any one of claims 1-9.

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