Non-polarity anti-reverse connection automatic identification circuit

Abstract

The application discloses a non-polarity anti-reverse connection automatic identification circuit, which comprises a switching main power module, a voltage detection comparison module and a driving module; the input end of the switching main power module is connected with a power supply; the control end of the switching main power module is connected with the signal output end of the driving module; the input end of the voltage detection comparison module is connected with the power supply; the output end of the voltage detection comparison module is connected with the input end of the driving module; when the switching main power module and the input end of the switching main power module are both connected with the power supply, the switching main power module is configured to input a reference voltage to the driving module; the output end of the voltage detection comparison module outputs a high level or a low level to the input end of the driving module; and the driving module outputs a control signal to the switching main power module. The technical effect of automatic identification and adaptive output of the power supply input end is realized, and the working efficiency and reliability are improved.

Description

Technical Field

[0001] This application relates to the field of reverse connection protection circuit technology, and in particular to a non-polarity reverse connection protection automatic identification circuit. Background Technology

[0002] In power supply applications, the input terminal usually needs to have reverse connection protection functions to prevent damage to the internal circuitry due to operational errors that could cause the power supply polarity to be reversed.

[0003] Traditional reverse polarity protection solutions, such as series power diodes or MOSFETs with simple control logic, have significant limitations: First, their function is singular, allowing current to flow only when connected in the forward direction, and completely blocking current when reversed, causing the power supply to malfunction. Second, when input line reverse connection occurs, the user must manually disconnect the power supply and readjust the wiring polarity to restore normal operation. This manual intervention process is not only time-consuming and laborious, increasing the user's operational burden and workload, but may also be difficult to implement or pose safety hazards in remote or sealed equipment. Furthermore, traditional diode solutions suffer from large forward voltage drop, high power consumption, and significant efficiency loss. Therefore, there is an urgent need for a reverse polarity protection solution that can automatically identify input polarity, achieve adaptive forward and reverse polarity without user intervention, and possess high efficiency and high reliability. Utility Model Content

[0004] This application provides a non-polarity reverse connection protection automatic identification circuit, which solves the problems of limited functionality, manual switching required for reverse connection, and low efficiency of existing reverse connection protection circuits. It achieves the technical effects of non-polarity automatic identification and adaptive output at the power input terminal, thereby improving working efficiency and reliability.

[0005] This utility model embodiment provides a non-polarity reverse connection protection automatic identification circuit, including a main power switching module, a voltage detection and comparison module, and a drive module. The input terminal of the main power switching module is connected to a power supply, and the control terminal of the main power switching module is connected to the signal output terminal of the drive module. The input terminal of the voltage detection and comparison module is connected to the power supply, and the output terminal of the voltage detection and comparison module is connected to the input terminal of the drive module. When both the main power switching module and its input terminal are connected to the power supply, the main power switching module is configured to input a reference voltage to the drive module, the output terminal of the voltage detection and comparison module outputs a high level or a low level to the input terminal of the drive module, and the drive module outputs a control signal to the main power switching module.

[0006] In one possible implementation, the main power switching module includes PMOS transistors Q1, Q2, Q3, and Q4, resistors R1, R2, R3, and R4, and capacitor C1; resistor R1 is connected between the source and gate of PMOS transistor Q1, and the drain of PMOS transistor Q1 is connected to the drain of NMOS transistor Q4; resistor R2 is connected between the source and gate of PMOS transistor Q2, and the drain of PMOS transistor Q2 is connected to the drain of NMOS transistor Q3; the source of PMOS transistor Q1 is connected to the source of PMOS transistor Q2; the NMOS transistor Q4... A resistor R3 is connected between the source of S-MOSFET Q3 and the gate of NMOS MOSFET Q3; a resistor R4 is connected between the source of NMOS MOSFET Q4 and the gate of NMOS MOSFET Q4; the sources of NMOS MOSFET Q3 and NMOS MOSFET Q4 are connected, and both the sources of NMOS MOSFET Q3 and NMOS MOSFET Q4 are grounded; the V1N1 terminal of the power supply is connected between PMOS MOSFET Q1 and NMOS MOSFET Q4, and the V1N2 terminal of the power supply is connected between PMOS MOSFET Q2 and NMOS MOSFET Q3; one end of capacitor C1 is connected between PMOS MOSFET Q1 and PMOS MOSFET Q2, and the other end of capacitor C1 is grounded.

[0007] In one possible implementation, the main power switching module further includes a Zener diode IC5, a resistor R5, and a capacitor C2; the anode of the Zener diode IC5 is grounded, the cathode of the Zener diode IC5 is connected to one end of the resistor R5, and the other end of the resistor R5 is connected between the PMOS transistors Q1 and Q2; one end of the capacitor C2 is grounded, and the other end of the capacitor C2 is connected between the Zener diode IC5 and the resistor R5.

[0008] In one possible implementation, the voltage detection and comparison module includes an operational amplifier IC6, resistors R12, R13, and R16, and a capacitor C4; one end of resistor R12 is connected to the V1N1 terminal of the power supply, and the other end of resistor R12 is connected to the non-inverting input terminal of the operational amplifier IC6; one end of resistor R13 is connected to the V1N2 terminal of the power supply, and the other end of resistor R13 is connected to the inverting input terminal of the operational amplifier IC6; the output terminal of the operational amplifier IC6 is connected to the input terminal of the drive module; one end of resistor R16 is connected between resistor R13 and the inverting input terminal of the operational amplifier IC6, and the other end of resistor R16 is grounded; one end of capacitor C4 is connected between resistor R13 and the inverting input terminal of the operational amplifier IC6, and the other end of capacitor C4 is grounded.

[0009] In one possible implementation, the voltage detection and comparison module further includes a resistor R10 and a diode VD1; the resistor R10 and the diode VD1 are connected in series between the positive input terminal of the operational amplifier IC6 and the output terminal of the operational amplifier IC6.

[0010] In one possible implementation, the voltage detection and comparison module includes a resistor R11 and a capacitor C3; one end of the capacitor C3 is connected between the resistor R12 and the operational amplifier IC6, and the other end of the capacitor C3 is grounded; the resistor R11 is connected in parallel across the two ends of the capacitor C3.

[0011] In one possible implementation, the driving module includes operational amplifier IC1, operational amplifier IC2, operational amplifier IC3, operational amplifier IC4, resistors R6, R8, R14, and R18; the non-inverting input of operational amplifier IC1 is connected between the Zener diode IC5 and the resistor R5, the inverting input of operational amplifier IC1 is connected to the output of operational amplifier IC6, and the output of operational amplifier IC1 is connected to the gate of PMOS transistor Q1; the non-inverting input of operational amplifier IC2 is connected to the output of operational amplifier IC6, the inverting input of operational amplifier IC2 is connected between the Zener diode IC5 and the resistor R5, and the output of operational amplifier IC2 is connected to the gate of PMOS transistor Q2; the non-inverting input of operational amplifier IC3 is connected to the output of operational amplifier IC6, and the inverting input of operational amplifier IC3 is connected to the... The Zener diode IC5 and the resistor R5 are connected together; the output terminal of the operational amplifier IC3 is connected to the gate of the NMOS transistor Q3; the non-inverting input terminal of the operational amplifier IC4 is connected between the Zener diode IC5 and the resistor R5; the inverting input terminal of the operational amplifier IC4 is connected to the output terminal of the operational amplifier IC6; the output terminal of the operational amplifier IC4 is connected to the gate of the NMOS transistor Q4; the resistor R6 is also connected between the non-inverting input terminal and the output terminal of the operational amplifier IC1; the resistor R14 is also connected between the non-inverting input terminal and the output terminal of the operational amplifier IC2; the resistor R8 is also connected between the non-inverting input terminal and the output terminal of the operational amplifier IC3; and the resistor R18 is also connected between the non-inverting input terminal and the output terminal of the operational amplifier IC4.

[0012] In a possible implementation, the driving module further includes a resistor R7, a resistor R9, a resistor R15, and a resistor R19; a resistor R7 is further connected between the output terminal of the operational amplifier IC1 and the gate of the PMOS transistor Q1; a resistor R15 is further connected between the output terminal of the operational amplifier IC2 and the gate of the PMOS transistor Q2; a resistor R9 is further connected between the output terminal of the operational amplifier IC3 and the gate of the NMOS transistor Q3; a resistor R19 is further connected between the output terminal of the operational amplifier IC4 and the gate of the NMOS transistor Q4.

[0013] One or more technical solutions provided by this application have at least the following technical effects: In the embodiment of the present utility model, a non-polarity reverse connection prevention and automatic recognition circuit is adopted, which includes a switch main power module, a voltage detection and comparison module, and a driving module; the switch main power module includes a PMOS transistor Q1, a PMOS transistor Q2, an NMOS transistor Q3, and an NMOS transistor Q4; whether the power supply is connected correctly or reversely, the states of the PMOS transistor Q1, the PMOS transistor Q2, the NMOS transistor Q3, and the NMOS transistor Q4 can be automatically adjusted through the driving module, and the driving module judges the state of the power supply being connected correctly or reversely through the voltage detection and comparison module. Therefore, this application can automatically detect the polarity relationship of the input power supply. Whether the power supply is connected correctly, that is, VIN1 > VIN2, or the power supply is connected reversely, that is, VIN < VIN2, the conduction states of the internal MOS transistors can be automatically adjusted through the circuit of this application, so as to ensure that the output terminal of the power supply always maintains the correct polarity, without any manual switching operation by the user, greatly simplifying the user operation, reducing the usage difficulty and workload. It solves the problems of the single function of the reverse connection prevention circuit in the prior art, manual switching required during reverse connection, and low efficiency, realizes the technical effects of non-polarity automatic recognition and adaptive output at the power input end, and improves the work efficiency and reliability. Description of the Drawings

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for describing the embodiments of the present utility model will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0015] [[ID=?]] Figure 1 is the circuit diagram of the switch main power module provided by the embodiment of this application; Figure 2 is the circuit diagram of the voltage detection and comparison module and the driving module provided by the embodiment of this application. Detailed Embodiments

[0016] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of the present utility model. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present utility model.

[0017] In the description of the embodiments of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing the embodiments of this utility model and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. The terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. In addition, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this utility model can be understood according to the specific circumstances.

[0018] A non-polarity reverse connection protection automatic identification circuit, such as Figure 1-2 As shown, the system includes a main power switching module, a voltage detection and comparison module, and a drive module. The input terminal of the main power switching module is connected to the power supply, and the control terminal of the main power switching module is connected to the signal output terminal of the drive module. The input terminal of the voltage detection and comparison module is connected to the power supply, and the output terminal of the voltage detection and comparison module is connected to the input terminal of the drive module. When both the main power switching module and its input terminal are connected to the power supply, the main power switching module is configured to input a reference voltage to the drive module, the output terminal of the voltage detection and comparison module outputs a high or low level to the input terminal of the drive module, and the drive module outputs a control signal to the main power switching module.

[0019] In the embodiments of this application, such as Figure 1-2As shown, the main power switching module includes PMOS transistors Q1, Q2, Q3, and Q4, resistors R1, R2, R3, and R4, and capacitor C1. Resistor R1 connects the source and gate of PMOS transistor Q1, and the drain of PMOS transistor Q1 is connected to the drain of NMOS transistor Q4. Resistor R2 connects the source and gate of PMOS transistor Q2, and the drain of PMOS transistor Q2 is connected to the drain of NMOS transistor Q3. The source of PMOS transistor Q1 is connected to the source of PMOS transistor Q2. A resistor R3 is connected between the source of S-MOSFET Q3 and the gate of NMOS MOSFET Q3; a resistor R4 is connected between the source of NMOS MOSFET Q4 and the gate of NMOS MOSFET Q4; the sources of NMOS MOSFET Q3 and NMOS MOSFET Q4 are connected, and both the sources of NMOS MOSFET Q3 and NMOS MOSFET Q4 are grounded; the V1N1 terminal of the power supply is connected between PMOS MOSFET Q1 and NMOS MOSFET Q4, and the V1N2 terminal of the power supply is connected between PMOS MOSFET Q2 and NMOS MOSFET Q3; one end of capacitor C1 is connected between PMOS MOSFET Q1 and PMOS MOSFET Q2, and the other end of capacitor C1 is grounded.

[0020] In the embodiments of this application, such as Figure 1-2 As shown, the main power switching module also includes a Zener diode IC5, a resistor R5, and a capacitor C2; the anode of the Zener diode IC5 is grounded, the cathode of the Zener diode IC5 is connected to one end of the resistor R5, and the other end of the resistor R5 is connected between PMOS transistors Q1 and Q2; one end of the capacitor C2 is grounded, and the other end of the capacitor C2 is connected between the Zener diode IC5 and the resistor R5.

[0021] In the embodiments of this application, such as Figure 1-2 As shown, the voltage detection and comparison module includes operational amplifier IC6, resistors R12, R13, R16 and capacitor C4; one end of resistor R12 is connected to the V1N1 terminal of the power supply, and the other end of resistor R12 is connected to the non-inverting input terminal of operational amplifier IC6. One end of resistor R13 is connected to the V1N2 terminal of the power supply, and the other end of resistor R13 is connected to the inverting input terminal of op-amp IC6; the output terminal of op-amp IC6 is connected to the input terminal of the driver module; one end of resistor R16 is connected between resistor R13 and the inverting input terminal of op-amp IC6, and the other end of resistor R16 is grounded; one end of capacitor C4 is connected between resistor R13 and the inverting input terminal of op-amp IC6, and the other end of capacitor C4 is grounded.

[0022] In the embodiments of this application, such as Figure 1-2As shown, the voltage detection and comparison module also includes a resistor R10 and a diode VD1; the resistor R10 and the diode VD1 are connected in series between the positive input terminal and the output terminal of the operational amplifier IC6.

[0023] For example, R10 and VD1 in the circuit perform a one-way adjustable hysteresis comparison to adjust the hysteresis voltage and prevent logic errors when the circuit is restarted after a power failure.

[0024] In the embodiments of this application, such as Figure 1-2 As shown, the voltage detection and comparison module includes a resistor R11 and a capacitor C3; one end of the capacitor C3 is connected between the resistor R12 and the operational amplifier IC6, and the other end of the capacitor C3 is grounded; the resistor R11 is connected in parallel across the two ends of the capacitor C3.

[0025] For example, resistors R11 and R12, and R13 and R16 in the circuit are input voltage divider resistors, which reduce the input voltage division ratio and protect the input terminal of op-amp IC6. Capacitors C3 and C4 serve as filters and delays, delaying the driving of circuit drivers G1, G2, G3, and G4. This ensures that the body diodes of transistors Q1, Q2, Q3, and Q4 conduct first, and then drive the MOSFETs to turn on, reducing circuit losses and significantly improving the safety and reliability of the circuit.

[0026] In the embodiments of this application, such as Figure 1-2 As shown, the driving module includes operational amplifier IC1, operational amplifier IC2, operational amplifier IC3, operational amplifier IC4, resistors R6, R8, R14, and R18. The non-inverting input of operational amplifier IC1 is connected between Zener diode IC5 and resistor R5; the inverting input of operational amplifier IC1 is connected to the output of operational amplifier IC6; and the output of operational amplifier IC1 is connected to the gate of PMOS transistor Q1. The non-inverting input of operational amplifier IC2 is connected to the output of operational amplifier IC6; the inverting input of operational amplifier IC2 is connected between Zener diode IC5 and resistor R5; and the output of operational amplifier IC2 is connected to the gate of PMOS transistor Q2. The non-inverting input of operational amplifier IC3 is connected to the output of operational amplifier IC6; and the inverting input of operational amplifier IC3 is connected to... Between Zener diode IC5 and resistor R5, the output of operational amplifier IC3 is connected to the gate of NMOS transistor Q3; the non-inverting input of operational amplifier IC4 is connected between Zener diode IC5 and resistor R5, the inverting input of operational amplifier IC4 is connected to the output of operational amplifier IC6, and the output of operational amplifier IC4 is connected to the gate of NMOS transistor Q4; resistor R6 is also connected between the non-inverting input and output of operational amplifier IC1; resistor R14 is also connected between the non-inverting input and output of operational amplifier IC2; resistor R8 is also connected between the non-inverting input and output of operational amplifier IC3; and resistor R18 is also connected between the non-inverting input and output of operational amplifier IC4.

[0027] In the embodiments of this application, such as Figure 1-2 As shown, the driving module also includes resistors R7, R9, R15, and R19; resistor R7 is also connected between the output terminal of operational amplifier IC1 and the gate of PMOS transistor Q1; resistor R15 is also connected between the output terminal of operational amplifier IC2 and the gate of PMOS transistor Q2; resistor R9 is also connected between the output terminal of operational amplifier IC3 and the gate of NMOS transistor Q3; and resistor R19 is also connected between the output terminal of operational amplifier IC4 and the gate of NMOS transistor Q4.

[0028] For example, resistors R7, R9, R15, and R19 in the circuit are current-limiting voltage divider drive resistors. Together with resistors R1, R2, R3, and R4, they can prevent the gate voltages of Q1, Q2, Q3, and Q4 from becoming too high, and also limit the drive current of operational amplifiers IC1, IC2, IC3, and IC4, thereby preventing damage to power devices.

[0029] For example, when power inputs VIN1 and VIN2 are connected (condition VIN1 > VIN2), in the power circuit, the body diodes of PMOS transistor Q1 and NMOS transistor Q3 conduct first (while the body diodes of Q2 and Q4 are cut off), the charging voltage of capacitor C1 rises, and the voltage regulator reference IC5 conducts (R5 is used for current limiting, C2 is used for reference energy storage, providing a stable reference VREF), providing the reference voltage VREF to operational amplifiers IC1, IC2, IC3, and IC4.

[0030] Simultaneously, during this process, operational amplifier IC4 compares the inputs VIN1 and VIN2 (VIN1 > VIN2). At this time, operational amplifier IC6 outputs a high level, which is compared with the reference VREF of the driver module operational amplifiers IC1, IC2, IC3, and IC4. Under this condition (VIN1 > VIN2), IC1 outputs G1 low to drive PMOS transistor Q1 to conduct, and IC3 outputs G3 high to drive NMOS transistor Q3 to conduct. At the same time, IC2 outputs G2 high to drive PMOS transistor Q2 to turn off, and IC4 outputs G4 low to drive NMOS transistor Q4 to turn off. In this way, the circuit reduces the conduction loss of traditional diodes and improves the overall efficiency of the circuit.

[0031] Similarly, when the power input VIN1 < VIN2, the circuit operates in the opposite way. Operational amplifier IC6 outputs a low level, IC1 outputs G1 a high level to turn off PMOS transistor Q1, and IC3 outputs G3 a low level to turn off NMOS transistor Q3. Simultaneously, IC2 outputs G2 a low level to turn on PMOS transistor Q2, and IC4 outputs G4 a high level to turn on NMOS transistor Q4.

[0032] The various embodiments in this specification are described in a progressive manner. For the same or similar parts between the various embodiments, please refer to each other. Each embodiment focuses on describing the differences from other embodiments.

[0033] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of this application.

Claims

1. A non-polarity anti-reverse connection automatic identification circuit, characterized in that, It includes a main power switching module, a voltage detection and comparison module, and a drive module; The input terminal of the main power module is connected to the power supply, and the control terminal of the main power module is connected to the signal output terminal of the drive module. The input terminal of the voltage detection and comparison module is connected to the power supply, and the output terminal of the voltage detection and comparison module is connected to the input terminal of the drive module. When both the main power module and its input terminal are connected to the power supply, the main power module is configured to input a reference voltage to the drive module, the output terminal of the voltage detection and comparison module outputs a high or low level to the input terminal of the drive module, and the drive module outputs a control signal to the main power module.

2. The non-polar anti-reverse automatic identification circuit according to claim 1, characterized in that, The main power switching module includes PMOS transistor Q1, PMOS transistor Q2, NMOS transistor Q3, NMOS transistor Q4, resistors R1, R2, R3, R4, and capacitor C1. The resistor R1 is connected between the source and the gate of the PMOS transistor Q1, and the drain of the PMOS transistor Q1 is connected to the drain of the NMOS transistor Q4. The resistor R2 is connected between the source and the gate of the PMOS transistor Q2, and the drain of the PMOS transistor Q2 is connected to the drain of the NMOS transistor Q3. The source of PMOS transistor Q1 is connected to the source of PMOS transistor Q2; The resistor R3 is connected between the source and the gate of the NMOS transistor Q3. The resistor R4 is connected between the source and the gate of the NMOS transistor Q4. The source of NMOS transistor Q3 is connected to the source of NMOS transistor Q4, and both the source of NMOS transistor Q3 and the source of NMOS transistor Q4 are grounded. The V1N1 terminal of the power supply is connected between the PMOS transistor Q1 and the NMOS transistor Q4, and the V1N2 terminal of the power supply is connected between the PMOS transistor Q2 and the NMOS transistor Q3. One end of capacitor C1 is connected between PMOS transistors Q1 and Q2, and the other end of capacitor C1 is grounded.

3. The non-polar anti-reverse automatic identification circuit according to claim 2, characterized in that, The main power module of the switch also includes a Zener diode IC5, a resistor R5 and a capacitor C2; The anode of the Zener diode IC5 is grounded, the cathode of the Zener diode IC5 is connected to one end of the resistor R5, and the other end of the resistor R5 is connected between the PMOS transistor Q1 and the PMOS transistor Q2. One end of the capacitor C2 is grounded, and the other end of the capacitor C2 is connected between the Zener diode IC5 and the resistor R5.

4. The non-polar anti-reverse automatic identification circuit according to claim 3, characterized in that, The voltage detection and comparison module includes operational amplifier IC6, resistor R12, resistor R13, resistor R16, and capacitor C4; One end of the resistor R12 is connected to the V1N1 terminal of the power supply, and the other end of the resistor R12 is connected to the non-inverting input terminal of the operational amplifier IC6. One end of the resistor R13 is connected to the V1N2 terminal of the power supply, and the other end of the resistor R13 is connected to the inverting input terminal of the operational amplifier IC6. The output terminal of the operational amplifier IC6 is connected to the input terminal of the driver module; One end of resistor R16 is connected between resistor R13 and the inverting input of operational amplifier IC6, and the other end of resistor R16 is grounded. One end of the capacitor C4 is connected between the resistor R13 and the inverting input of the operational amplifier IC6, and the other end of the capacitor C4 is grounded.

5. The non-polar anti-reverse automatic identification circuit according to claim 4, characterized in that, The voltage detection and comparison module also includes a resistor R10 and a diode VD1; The resistor R10 and the diode VD1 are connected in series between the positive input terminal and the output terminal of the operational amplifier IC6.

6. The non-polar anti-reverse automatic identification circuit according to claim 4, characterized in that, The voltage detection and comparison module includes a resistor R11 and a capacitor C3; One end of capacitor C3 is connected between resistor R12 and operational amplifier IC6, and the other end of capacitor C3 is grounded; The resistor R11 is connected in parallel across the capacitor C3.

7. The non-polar anti-reverse automatic identification circuit according to claim 4, characterized in that, The driving module includes operational amplifier IC1, operational amplifier IC2, operational amplifier IC3, operational amplifier IC4, resistor R6, resistor R8, resistor R14 and resistor R18; The non-inverting input terminal of the operational amplifier IC1 is connected between the Zener diode IC5 and the resistor R5, the inverting input terminal of the operational amplifier IC1 is connected to the output terminal of the operational amplifier IC6, and the output terminal of the operational amplifier IC1 is connected to the gate of the PMOS transistor Q1. The non-inverting input terminal of the operational amplifier IC2 is connected to the output terminal of the operational amplifier IC6, the inverting input terminal of the operational amplifier IC2 is connected between the Zener diode IC5 and the resistor R5, and the output terminal of the operational amplifier IC2 is connected to the gate of the PMOS transistor Q2. The non-inverting input terminal of the operational amplifier IC3 is connected to the output terminal of the operational amplifier IC6, the inverting input terminal of the operational amplifier IC3 is connected between the Zener diode IC5 and the resistor R5, and the output terminal of the operational amplifier IC3 is connected to the gate of the NMOS transistor Q3. The non-inverting input terminal of the operational amplifier IC4 is connected between the Zener diode IC5 and the resistor R5, the inverting input terminal of the operational amplifier IC4 is connected to the output terminal of the operational amplifier IC6, and the output terminal of the operational amplifier IC4 is connected to the gate of the NMOS transistor Q4. The resistor R6 is also connected between the non-inverting input terminal and the output terminal of the operational amplifier IC1; The resistor R14 is also connected between the non-inverting input terminal and the output terminal of the operational amplifier IC2; The resistor R8 is also connected between the non-inverting input terminal and the output terminal of the operational amplifier IC3; The resistor R18 is also connected between the non-inverting input terminal and the output terminal of the operational amplifier IC4.

8. The non-polar anti-reverse automatic identification circuit according to claim 7, characterized in that, The drive module also includes resistors R7, R9, R15, and R19; A resistor R7 is also connected between the output terminal of the operational amplifier IC1 and the gate of the PMOS transistor Q1. The output end of the operational amplifier IC2 and the gate of the PMOS tube Q2 are further connected with a resistor R15; The output end of the operational amplifier IC3 and the gate of the NMOS tube Q3 are further connected with a resistor R9; The output end of the operational amplifier IC4 and the gate of the NMOS tube Q4 are further connected with a resistor R19.

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