A bridgeless totem-pole PFC lightning protection circuit

Abstract

This utility model relates to a bridgeless totem pole PFC lightning protection circuit, comprising a bridge switching transistor module located between the L and N lines, a rectifier bridge BD1 connected to the N line, and a Hall effect chip connected between the bridge switching transistor module and the N line. The bridge switching transistor module includes two slow-acting transistors and two fast-acting transistors, driven by a control chip. The Hall effect chip samples the current flowing through the fast and slow transistors, processes it through an operational amplifier, and sends the sample to the control chip. Simultaneously, the rectifier bridge BD1, connected to a current transformer, also samples the current and sends it to the control chip. Thus, through two different current detection circuits, the drive signals of the slow and fast transistors are controlled separately. When lightning strikes the internal circuit, the circuit can quickly respond and stop the drive of the corresponding power transistor, reliably protecting the power transistors. The circuit is simple in structure, easy to operate, and provides good lightning protection, making it widely applicable in switching power supply devices.

Description

Technical Field

[0001] This utility model relates to the field of lightning protection circuit technology, specifically to a bridgeless totem pole PFC lightning protection circuit. Background Technology

[0002] In recent years, improving the efficiency and power density of switching power supplies has been a pursuit of the power electronics industry. With continuous technological updates and the development of the semiconductor industry, the efficiency of switching power supplies has increased to over 95%. For a period after reaching 95%, due to the limitations of silicon-based semiconductors, further efficiency improvements were limited. It was only with the advent of third-generation semiconductor devices—silicon carbide and gallium nitride—that new high efficiency was achieved. Bridgeless totem-pole power supply (PFC) has become increasingly widely used in recent years, standing out for its high efficiency and simple circuit design. Combining silicon carbide with bridgeless totem-pole technology further enhances efficiency. However, silicon carbide devices are much less shock-resistant than traditional MOSFETs, revealing their vulnerability when facing lightning strikes. Utility Model Content

[0003] In view of this, a bridgeless totem pole PFC protection circuit with simple and effective circuit structure, fast and sensitive response, high reliability and protection of MOSFET is provided for lightning strike protection.

[0004] A bridgeless totem pole PFC lightning protection circuit is connected between the L line and the N line of the AC input terminal. The bridgeless totem pole PFC lightning protection circuit includes a bridge switch module disposed between the L line and the N line, a rectifier bridge BD1 connected to the N line, and a Hall chip connected between the bridge switch module and the N line.

[0005] The bridge switching module includes a first slow MOS transistor Q1 and a second slow MOS transistor Q51 connected to the L line, and a first fast MOS transistor TR1 and a second fast MOS transistor TR11 connected to the negative input pin IN- of the Hall chip U23.

[0006] The positive input pin IN+ of the Hall chip U23 is connected to the N line. The Hall chip U23 has a voltage reference pin VREF and a superimposed voltage signal pin VOUT. The voltage reference pin VREF and the superimposed voltage signal pin VOUT are respectively connected to the operational amplifier unit. The processed voltage signal is output by the operational amplifier unit to the control chip. When the control chip determines that the voltage signal exceeds a first predetermined threshold, it outputs a drive signal to disconnect the first MOS fast transistor TR1 and the second MOS fast transistor TR11.

[0007] The midpoint of the rectifier bridge BD1 is connected to the N line. The positive DC output of the rectifier bridge BD1 is connected to the first current transformer TR2, which is connected to the positive terminal of the output capacitor C23. The negative DC output of the rectifier bridge BD1 is connected to the second current transformer TR3, which is connected to the negative terminal of the output capacitor C23. The positive and negative terminals of the output capacitor C23 are simultaneously connected to the bridge switching transistor module.

[0008] The first current transformer TR2 and the second current transformer TR3 sample the induced current and convert it into a voltage sampling signal, which is then sent to the event processing pin of the control chip. When the voltage sampling signal exceeds a second predetermined threshold, the control chip stops sending the drive signals of the first MOS slow transistor Q1 and the second MOS slow transistor Q51.

[0009] Furthermore, the L-line is connected to the drain of the first slow MOS transistor Q1 and the source of the second slow MOS transistor Q51 after the fuse. The drain of the second slow MOS transistor Q51, the drain of the second fast MOS transistor TR11, and the positive terminal of the output capacitor C23 are connected together. The source of the first slow MOS transistor Q1, the source of the first fast MOS transistor TR1, and the negative terminal of the output capacitor C23 are connected together. The drain of the first fast MOS transistor TR1 and the source of the second fast MOS transistor TR11 are connected together. The gates of each switching transistor are connected to the control chip.

[0010] Furthermore, the negative input pin IN- of the Hall chip U23 is connected to the drain of the first MOS fast transistor TR1 and the source of the second MOS fast transistor TR11 via an energy storage inductor L9.

[0011] Furthermore, the two AC input pins of the rectifier bridge BD1 are connected to the N line and the positive input pin IN+ of the Hall chip U23; the L line is connected to a fuse and then to a filter capacitor Cx2, which is connected in parallel between the L line and the N line.

[0012] Further, the operational amplifier unit includes a first operational amplifier U17-A and a second operational amplifier U17-B; the non-inverting input of the first operational amplifier U17-A is connected to the voltage reference pin VREF of the Hall chip U23, and the inverting input is connected to the superimposed voltage signal pin VOUT of the Hall chip U23; the non-inverting input of the second operational amplifier U17-B is connected to the superimposed voltage signal pin VOUT of the Hall chip U23, and the inverting input is connected to the voltage reference pin VREF of the Hall chip U23; the outputs of the first operational amplifier U17-A and the second operational amplifier U17-B are connected in parallel to an overpower protection pin IA_OPP of the control chip; the parallel connection of the outputs of the first operational amplifier U17-A and the second operational amplifier U17-B forms the processed voltage signal and is transmitted to the control chip.

[0013] Furthermore, the voltage reference pin VREF of the Hall chip U23 outputs the reference voltage signal PFC-VREF of the Hall chip U23, and the superimposed voltage signal pin VOUT of the Hall chip U23 outputs a Hall sampling signal PFC-S formed by superimposing the reference voltage signal PFC-VREF after being proportionally converted internally by the Hall chip U23. The reference voltage signal PFC-VREF and the Hall sampling signal PFC-S are respectively sent to the non-inverting input terminal and the inverting input terminal of the second operational amplifier U17-B after passing through current limiting resistors R1 and R2, respectively. At the same time, a first-order four-phase current is connected in parallel between the reference voltage signal PFC-VREF and the Hall sampling signal PFC-S before they are connected to the second operational amplifier U17-B. Capacitor C114; the reference voltage signal PFC-VREF and the Hall sampling signal PFC-S are respectively sent to the non-inverting input terminal and the inverting input terminal of the first operational amplifier U17-B after passing through another current limiting resistor R3 and R7, respectively. The output signal of the first operational amplifier U17-A and the output signal of the second operational amplifier U17-B are respectively divided by resistors R248 and R122, and a voltage signal is formed at the midpoint and sent to the control chip. The inverting input terminal of the first operational amplifier U17-A is shorted to the output terminal of the first operational amplifier U17-A through the first-four resistor R114, and the inverting input terminal of the second operational amplifier U17-B is shorted to the output terminal of the second operational amplifier U17-B through the first-two resistor R112.

[0014] Further, the first current transformer TR2 includes a first primary current transformer coil TR2-B and a first secondary current transformer coil TR2-A; the second current transformer TR3 includes a second primary current transformer coil TR3-B and a second secondary current transformer coil TR3-A; the two ends of the first primary current transformer coil TR2-B are respectively connected to the positive DC output of the rectifier bridge BD1 and the positive terminal of the output capacitor C23; the two ends of the second primary current transformer coil TR3-B are respectively connected to the negative DC output of the rectifier bridge BD1 and the negative terminal of the output capacitor C23; the first secondary current transformer coil TR2-A and the second secondary current transformer coil TR3-A are respectively rectified by diodes and then connected to a sampling resistor to obtain the voltage sampling signal.

[0015] Furthermore, each of the mutual inductance secondary coils TR2-A or TR3-A is connected to two switching diodes at its two ends. The cathodes of the two switching diodes are connected together and then connected to the output terminal LLC_IP via a current-limiting resistor. The output terminal LLC_IP is connected to the event processing pin of the control chip. The anodes of the two switching diodes are connected together and then grounded, and connected to the power supply terminal SMCU_3.3V via another switching diode. The sampling resistor is connected in parallel between the common cathode connection point and the common anode connection point of the two switching diodes, and an RC filter circuit is connected in parallel. The RC filter circuit includes a filter capacitor and a filter resistor connected in parallel. The first anode of the other switching diode is connected to the common anode connection point, the second cathode is connected to the power supply terminal SMCU_3.3V, and the common terminal is connected to the output terminal LLC_IP.

[0016] Furthermore, the two current-limiting resistors R1 and R2 have the same resistance value, the two current-limiting resistors R3 and R7 have the same resistance value, the two resistors R248 and R122 have the same resistance value, and the first four resistors R114 and the first two resistors R112 have the same resistance value.

[0017] Furthermore, the positive input pin IN+ and negative input pin IN- of the Hall chip U23 are bidirectional, and can respectively collect positive current or negative current; the first MOS fast transistor TR1 and the second MOS fast transistor TR11 are silicon carbide fast transistors or gallium nitride fast transistors, respectively.

[0018] In the above-mentioned bridgeless totem pole PFC lightning protection circuit, two different current or voltage detection circuits, namely Hall effect chip and current transformer, control the drive signals of MOS slow transistor and MOS fast transistor respectively. When lightning energy impacts the internal circuit, it can quickly respond and stop the drive of the corresponding power transistor, thereby reliably protecting the MOS slow transistor and MOS fast transistor. The overall circuit structure is simple, low cost, easy to operate with microcontroller control, convenient to use, and has good lightning protection effect. It can be widely used in switching power supply devices. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the main circuit principle of a bridgeless totem pole PFC lightning protection circuit provided in this embodiment of the utility model.

[0020] Figure 2 This is a schematic diagram of the operational amplifier circuit in a bridgeless totem pole PFC lightning protection circuit provided in this embodiment of the utility model.

[0021] Figure 3 This is a schematic diagram of the secondary circuit principle of the first current transformer in a bridgeless totem pole PFC lightning protection circuit provided in this embodiment of the present invention.

[0022] Figure 4 This is a schematic diagram of the secondary circuit principle of the second current transformer in a bridgeless totem pole PFC lightning protection circuit provided in this embodiment of the present invention. Detailed Implementation

[0023] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative effort are within the protection scope of the present utility model.

[0024] Please see Figures 1 to 4 This illustration shows a bridgeless totem pole PFC lightning protection circuit and its sub-circuit structure provided by an embodiment of the present invention. The protection circuit is connected between the L line and the N line of the AC input terminal, for example, between the positive and negative terminals of the AC circuit output. The bridgeless totem pole PFC lightning protection circuit includes a bridge switching transistor module disposed between the L line and the N line, a rectifier bridge BD1 connected to the N line, and a Hall effect chip connected between the bridge switching transistor module and the N line.

[0025] The bridge switching module includes a first slow MOS transistor Q1 and a second slow MOS transistor Q51 connected to the L line, and a first fast MOS transistor TR1 and a second fast MOS transistor TR11 connected to the negative input pin IN- of the Hall chip U23.

[0026] The positive input pin IN+ of the Hall chip U23 is connected to the N line. The Hall chip U23 has a voltage reference pin VREF and a superimposed voltage signal pin VOUT. The voltage reference pin VREF and the superimposed voltage signal pin VOUT are respectively connected to the operational amplifier unit. The processed voltage signal is output by the operational amplifier unit to the control chip. When the control chip determines that the voltage signal exceeds the first predetermined threshold, it outputs a drive signal to disconnect the first MOS fast transistor TR1 and the second MOS fast transistor TR11.

[0027] The midpoint of the rectifier bridge BD1 is connected to the neutral (N) line. The positive DC output of rectifier bridge BD1 is connected to the first current transformer TR2, which is connected to the positive terminal of output capacitor C23. The negative DC output of rectifier bridge BD1 is connected to the second current transformer TR3, which is connected to the negative terminal of output capacitor C23. Both the positive and negative terminals of output capacitor C23 are connected to the bridge switching transistor module. Output capacitor C23 is an electrolytic capacitor.

[0028] The first current transformer TR2 and the second current transformer TR3 sample the induced current and convert it into a voltage sampling signal, which is then sent to the event processing pin of the control chip. When the voltage sampling signal exceeds a second predetermined threshold, the control chip stops sending the drive signals of the first MOS slow transistor Q1 and the second MOS slow transistor Q51.

[0029] like Figure 1 As shown, specifically, the L line is connected to the fuse F2 and then to the drain of the first slow MOS transistor Q1 and the source of the second slow MOS transistor Q51. The drains of the second slow MOS transistor Q51 and the second fast MOS transistor TR11, as well as the positive terminal of the output capacitor C23, are connected together. The sources of the first slow MOS transistor Q1 and the first fast MOS transistor TR1, as well as the negative terminal of the output capacitor C23, are connected together. The drains of the first fast MOS transistor TR1 and the source of the second fast MOS transistor TR11 are connected together. The gates of each switching transistor are connected to the control chip. The control chip is a microcontroller, for example, an STM32F334 series microcontroller (MCU). Furthermore, the negative input pin IN- of the Hall chip U23 is connected to the drain of the first fast MOS transistor TR1 and the source of the second fast MOS transistor TR11 via an energy storage inductor L9. The Hall chip U23 is a current detection Hall chip. The Hall chip U23 detects the current passing through the slow tube, the fast tube and the N line, and processes it into a voltage signal by the operational amplifier and sends it to the control chip.

[0030] Furthermore, the two AC input pins of the rectifier bridge BD1 (i.e., pins 2 and 3 of the rectifier bridge BD1 in the figure) are connected to the N line and the positive input pin IN+ of the Hall chip U23. The L line is connected to a filter capacitor Cx2 after the fuse F2, and the filter capacitor Cx2 is connected in parallel between the L line and the N line.

[0031] like Figure 2 As shown, the operational amplifier unit further includes a first operational amplifier U17-A and a second operational amplifier U17-B. The non-inverting input (pin 3) of the first operational amplifier U17-A is connected to the voltage reference pin VREF of the Hall chip U23, and the inverting input (pin 3) is connected to the superimposed voltage signal pin VOUT of the Hall chip U23. The non-inverting input (pin 5) of the second operational amplifier U17-B is connected to the superimposed voltage signal pin VOUT of the Hall chip U23, and the inverting input (pin 6) is connected to the voltage reference pin VREF of the Hall chip U23. The outputs of the first operational amplifier U17-A and the second operational amplifier U17-B are connected in parallel to an overpower protection pin IA_OPP of the control chip. The parallel connection of the outputs of the first operational amplifier U17-A and the second operational amplifier U17-B forms the processed voltage signal and is transmitted to the control chip, i.e., to the overpower protection pin IA_OPP of the control chip. In addition, a capacitor C110 is grounded at the transmission front end to protect the signal and stabilize the output.

[0032] Specifically, the voltage reference pin VREF of the Hall chip U23 outputs the reference voltage signal PFC-VREF of the Hall chip U23. The superimposed voltage signal pin VOUT of the Hall chip U23 outputs a Hall sampling signal PFC-S, which is formed by superimposing the reference voltage signal PFC-VREF after being proportionally converted internally by the Hall chip U23. For example, if the reference voltage is set to 1.65V, the superimposed signal will form a voltage signal PFC-S around 1.65V. The reference voltage signal PFC-VREF and the Hall sampling signal PFC-S are respectively sent to the non-inverting input terminal and the inverting input terminal of the second operational amplifier U17-B after passing through current limiting resistors R1 and R2. At the same time, a first-four capacitor C114 is connected in parallel before the reference voltage signal PFC-VREF and the Hall sampling signal PFC-S are connected to the second operational amplifier U17-B. The reference voltage signal PFC-VREF and the Hall sampling signal PFC-S are respectively sent to the non-inverting input terminal and the inverting input terminal of the first operational amplifier U17-B after passing through another current limiting resistor R3 and R7. The output signal of the first operational amplifier U17-A and the output signal of the second operational amplifier U17-B are respectively divided by resistors R248 and R122, and a voltage signal is formed at the midpoint and sent to the control chip. The inverting input terminal of the first operational amplifier U17-A is shorted to the output terminal of the first operational amplifier U17-A through a first-four resistor R114, and the inverting input terminal of the second operational amplifier U17-B is shorted to the output terminal of the second operational amplifier U17-B through a first-two resistor R112. Preferably, the two current-limiting resistors R1 and R2 have the same resistance value, the two current-limiting resistors R3 and R7 have the same resistance value, the two resistors R248 and R122 have the same resistance value, and the first-four resistor R114 and the first-two resistor R112 have the same resistance value.

[0033] Further, the first current transformer TR2 includes a first primary current transformer coil TR2-B and a first secondary current transformer coil TR2-A; the second current transformer TR3 includes a second primary current transformer coil TR3-B and a second secondary current transformer coil TR3-A; the two ends of the first primary current transformer coil TR2-B are respectively connected to the positive DC output of the rectifier bridge BD1 and the positive terminal of the output capacitor C23; the two ends of the second primary current transformer coil TR3-B are respectively connected to the negative DC output of the rectifier bridge BD1 and the negative terminal of the output capacitor C23; the first secondary current transformer coil TR2-A and the second secondary current transformer coil TR3-A are respectively rectified by diodes and then connected to a sampling resistor to obtain the voltage sampling signal.

[0034] like Figure 1 and Figure 3 , Figure 4As shown, each of the mutual inductance secondary coils TR2-A or TR3-A has two switching diodes connected to its two ends respectively. The cathodes of the two switching diodes are connected together and then connected to the output terminal LLC_IP via a current-limiting resistor. The output terminal LLC_IP is connected to the event processing pin of the control chip. The anodes of the two switching diodes are connected together and then grounded, and connected to the power supply terminal SMCU_3.3V via another switching diode. The sampling resistor is connected in parallel between the common cathode connection point and the common anode connection point of the two switching diodes, and an RC filter circuit is connected in parallel. The RC filter circuit includes a filter capacitor and a filter resistor connected in parallel. The first anode of the other switching diode is connected to the common anode connection point, the second cathode is connected to the power supply terminal SMCU_3.3V, and the common terminal is connected to the output terminal LLC_IP.

[0035] Specifically, such as Figure 3 The diagram shows the circuit structure of the first mutual inductance secondary coil TR2-A. The cathodes (pin 2) of two switching diodes D2 and D3 are connected together and then connected to the output terminal LLC_IP via a current-limiting resistor R9. The anodes (pin 1) of two switching diodes D2 and D3 are connected together and then grounded. Two switching diodes D2 and D3 are also connected to the power supply terminal SMCU_3.3V via another switching diode D1. The sampling resistors are two resistors connected in parallel, namely the tenth sampling resistor R10 and the eleventh sampling resistor R11, connected in parallel between the common cathode connection point and the common anode connection point of the two switching diodes D2 and D3, and also connected in parallel between the common cathode connection point and the common anode connection point. The RC filter circuit includes a parallel filter capacitor C2 and a filter resistor R8. The first anode (pin 1) of the other switching diode D1 is connected to the common anode connection point, the second cathode (pin 2) is connected to the power supply terminal SMCU_3.3V, and the common terminal (pin 3) is connected to the output terminal LLC_IP.

[0036] like Figure 4The circuit structure of the second mutual inductor secondary coil TR2-B is shown. It is basically the same as the circuit structure of the first mutual inductor secondary coil TR2-A, only the labeling is different. Specifically, the cathodes (pin 2) of the two switching diodes D8 and D13 are connected together and then connected to the current-limiting resistor R25 to serve as the output terminal LLC_IP. The anodes (pin 1) of the two switching diodes D8 and D13 are connected together and then grounded; the two switching diodes D8 and D13 are also connected to the power supply terminal SMCU_3.3V via another switching diode D53. The sampling resistor consists of two resistors in parallel, namely sampling resistor R222 and sampling resistor R111, connected in parallel between the common cathode connection point and the common anode connection point of the two switching diodes D8 and D13, and also between the common cathode connection point and the common anode connection point. An RC filter circuit is also connected in parallel between the common cathode connection point and the common anode connection point. The RC filter circuit includes a filter capacitor C120 and a filter resistor R129 connected in parallel. The first anode (pin 1) of the other switching diode D53 is connected to the common anode connection point, the second cathode (pin 2) is connected to the power supply terminal SMCU_3.3V, and the common terminal (pin 3) is connected to the output terminal LLC_IP.

[0037] Furthermore, the positive input pin IN+ and negative input pin IN- of the Hall chip U23 are bidirectional, and can respectively collect positive current or negative current; the first MOS fast transistor TR1 and the second MOS fast transistor TR11 are silicon carbide fast transistors or gallium nitride fast transistors, respectively.

[0038] The working principle of the bridgeless totem pole PFC lightning protection in this implementation is briefly described below:

[0039] Please see Figure 1 When the voltage of line L is greater than that of line N, if the second slow MOSFET Q51 and the second fast MOSFET TR11 are turned on, the current flows from line L to fuse F2 to the second slow MOSFET Q51 to the second fast MOSFET TR11, then through the energy storage inductor L9 and the current detection Hall chip U23 back to line N. At this time, the energy storage inductor L9 is in a charging state. In this state, if there is a lightning strike energy with a positive voltage, that is, a lightning strike energy with a voltage of line L greater than that of line N, a short-term large current will impact the power transistor through the above loop. The forward withstand current of the body diode of the second slow MOSFET Q51 is very large. After the current detection Hall chip U23 detects the large current, it transmits the Hall sampling signal PFC-S to the control chip. When the threshold set by the chip is exceeded, the control chip stops sending the drive signal of the second fast MOSFET TR11, the loop is cut off, and the current flowing through the second fast MOSFET TR11 is limited. Therefore, the power transistor can withstand the impact of lightning energy.

[0040] In this state, if a lightning strike with negative voltage enters the circuit (i.e., the voltage of the L line is less than the voltage of the N line), the power transistor will switch due to input commutation. However, the second MOSFET Q51 will not have time to turn off. A large current will flow from the N line to the rectifier bridge BD1, then to the primary side of the first transformer TR2, then through the second MOSFET Q51, and finally through the fuse F2 back to the L line. At this time, the body diode of the second MOSFET Q51 will withstand a reverse surge current. The current flowing through the first transformer TR2 will be transferred to the secondary side. The current signal on the secondary side is converted into a voltage signal by the sampling resistor and sent to the control chip. If the current exceeds the threshold set by the chip, the drive signal of the second MOSFET Q51 will be stopped. In other words, the current loop will be cut off, the power transistor will be protected, and it can withstand the lightning strike energy surge.

[0041] Please see Figure 1 When the voltage on line L is greater than that on line N, if the second slow MOSFET Q51 and the first fast MOSFET TR1 are turned on, the current flows from line L to fuse F2, then to the second slow MOSFET Q51, then to output capacitor C23, then back to the first fast MOSFET TR1, then through energy storage inductor L9 and current detection Hall chip U23 back to line N. At this time, energy storage inductor L9 is in a discharging state. In this state, if there is positive lightning energy injected into the circuit, that is, the lightning energy of line L being greater than that of line N, the current will have two directions. The first is to impact the power transistor through the above loop. The forward withstand current of the body diode of the second slow MOSFET Q51 is very large, while the current flowing through the current detection Hall chip U23 is... The current is transmitted to the control chip through the Hall sampling signal PFC-S. After reaching the threshold set by the chip, the control chip stops sending the drive signal of the first MOS fast transistor TR1. At this time, the current flows through the body diode of the power fast transistor. The second current flow is through the L line to the second MOS slow transistor Q51, to the output capacitor C23, to the second current transformer TR3, to the rectifier bridge BD1, and back to the N line. The impedance of the second current loop is small. The rectifier bridge BD1 bears most of the current for the body diode of the first MOS fast transistor TR1, so that the current flowing through the first MOS fast transistor TR1 is within its tolerance range. At the same time, the forward current of the diode is strong and resistant to current surge. Therefore, the power transistors can withstand the energy surge of lightning strikes.

[0042] In this state, if a lightning strike with negative voltage enters the circuit (i.e., the voltage of the L line is less than the voltage of the N line), the power transistor will switch due to input commutation. However, the second MOSFET Q51 cannot turn off in time. At this time, the current flows from the N line through the rectifier bridge BD1, then through the first transformer TR2 and the second MOSFET Q51, and the fuse F2 back to the L line. At this time, the body diode of the second MOSFET Q51 is subjected to reverse surge current. When the large current flows through the primary side of the first transformer TR2, the current measured on the secondary side is converted into a voltage signal by the sampling resistor and sent to the control chip. After reaching the threshold voltage set by the chip, the chip stops sending the drive signal of the second MOSFET Q51. This current loop is cut off, and the power transistor is protected.

[0043] Please see Figure 1 When the L-line voltage is less than the N-line voltage, if the first slow MOSFET Q1 and the first fast MOSFET TR1 are turned on, the current flows from the N-line to the current detection Hall chip U23, then to the energy storage inductor L9, then through the first fast MOSFET TR1 and the first slow MOSFET Q1, then through the fuse F2 back to the L-line. At this time, the energy storage inductor L9 is in a charging state. In this state, if a lightning strike with positive voltage is injected into the circuit, that is, if the L-line voltage is greater than the N-line voltage, the power slow MOSFET should switch direction, but it is too late. The MOSFET Q1 is not yet turned off. The current flows from the L line through the fuse F2 to the first MOSFET Q1, then to the rectifier bridge BD1, and back to the N line. The body diode of the first MOSFET Q1 will be subjected to a large reverse surge current. After the transformer TR3 detects the brief large current, it is transmitted to the secondary side. The current signal on the secondary side is converted into a voltage signal by the sampling resistor and sent to the control chip. After reaching the threshold set by the chip, the chip stops sending the drive signal of the first MOSFET Q1, the current loop is cut off, and the power MOSFET is protected.

[0044] In this state, if a lightning strike with negative voltage enters the circuit (i.e., the voltage of the L line is less than that of the N line), the current flows from the N line to the current detection Hall chip U23, then to the energy storage inductor L9, then through the first fast MOSFET TR1 and the first slow MOSFET Q1, and finally through the fuse F2 back to the L line. At this time, the energy storage inductor L9 is in a charging state. The body diode of the first slow MOSFET Q1 has strong forward withstand capability, while the body diode of the first fast MOSFET TR1 has weak reverse withstand capability. Therefore, after the current flows through the current detection Hall chip U23, the chip sends the Hall sampling signal PFC-S to the control chip. After reaching the threshold set by the control chip, the control chip stops sending the drive signal of the first fast MOSFET TR1. At this time, the current loop is cut off, and the first fast MOSFET TR1 is protected.

[0045] Please see Figure 1When the voltage of line L is less than that of line N, if the first slow MOSFET Q1 and the second fast MOSFET TR11 are turned on, the current flows from line N to the current detection Hall chip U23, then to the energy storage inductor L9, then through the second fast MOSFET TR11 to the output electrolytic capacitor C23, and then back to line L through the first slow MOSFET Q1 and fuse F2. The energy storage inductor L9 is in a discharging state. In this state, if a positive voltage lightning strike energy is injected into the circuit (i.e., the voltage of line L is greater than the voltage of line N), the power slow MOSFET should normally commutate, but it is too late. That is, the first MOS transistor Q1 is not yet turned off. The current flows from the L line through the fuse F2 to the first MOS transistor Q1, then to the rectifier bridge BD1, and back to the N line. The body diode of the first MOS transistor Q1 will be subjected to a large reverse impact current. After the second current transformer TR3 detects the brief large current, it is transmitted to the secondary side. The current signal on the secondary side is converted into a voltage signal through the sampling resistor and sent to the control chip. After reaching the threshold set by the control chip, the control chip stops sending the drive signal of the first MOS transistor Q1. The current loop is cut off, and the power transistor is protected.

[0046] In this state, if a lightning strike with negative voltage enters the circuit (i.e., the voltage of the L line is less than the voltage of the N line), there are two possible current flows. The first is from the N line to the current detection Hall chip U23, then to the energy storage inductor L9, then to the second fast MOSFET TR11, then to the output capacitor C23, and finally back to the L line through the first slow MOSFET Q1 and the fuse F2. The current flows through the current detection Hall chip U23, which transmits the Hall sampling signal PFC-S to the control chip. Once the threshold set by the control chip is reached, the control chip stops sending the drive signal for the second fast MOSFET TR11, and the current flows through its body diode. The second possible current flow is from the N line to the rectifier bridge BD1, then to the first transformer TR2, then to the output capacitor C23, and finally back to the L line through the first slow MOSFET Q1 and the fuse F2. This circuit has a lower impedance and a larger current flow, resulting in a smaller current flowing through the body diode of the second fast MOSFET TR11, allowing the power transistor to withstand the impact of the lightning strike energy.

[0047] Therefore, it can be seen that in the above-mentioned bridgeless totem pole PFC lightning protection circuit, the drive signals of the MOS slow transistor and MOS fast transistor are controlled by two different current or voltage detection circuits through Hall chip and current transformer respectively. When lightning energy impacts the internal circuit, it can quickly respond and stop the drive of the corresponding power transistor, thereby reliably protecting the MOS slow transistor and MOS fast transistor. The overall circuit structure is simple, low cost, easy to operate with single-chip microcomputer control, convenient to use, and has good lightning protection effect. It can be widely used in switching power supply devices.

[0048] It should be noted that this utility model is not limited to the above-described embodiments. Based on the inventive spirit of this utility model, those skilled in the art can make other changes, and these changes made based on the inventive spirit of this utility model should be included within the scope of protection claimed by this utility model.

Claims

1. A bridgeless totem-pole PFC lightning protection circuit, which is connected between an L line of an AC input end and an N line of the AC input end, characterized in that, The bridgeless totem pole PFC lightning protection circuit includes a bridge switch module located between the L line and the N line, a rectifier bridge BD1 connected to the N line, and a Hall chip connected between the bridge switch module and the N line. The bridge switching module includes a first slow MOS transistor Q1 and a second slow MOS transistor Q51 connected to the L line, and a first fast MOS transistor TR1 and a second fast MOS transistor TR11 connected to the negative input pin IN- of the Hall chip U23. The positive input pin IN+ of the Hall chip U23 is connected to the N line. The Hall chip U23 has a voltage reference pin VREF and a superimposed voltage signal pin VOUT. The voltage reference pin VREF and the superimposed voltage signal pin VOUT are respectively connected to the operational amplifier unit. The processed voltage signal is output by the operational amplifier unit to the control chip. When the control chip determines that the voltage signal exceeds a first predetermined threshold, it outputs a drive signal to disconnect the first MOS fast transistor TR1 and the second MOS fast transistor TR11. The midpoint of the rectifier bridge BD1 is connected to the N line. The positive DC output of the rectifier bridge BD1 is connected to the first current transformer TR2, which is connected to the positive terminal of the output capacitor C23. The negative DC output of the rectifier bridge BD1 is connected to the second current transformer TR3, which is connected to the negative terminal of the output capacitor C23. The positive and negative terminals of the output capacitor C23 are simultaneously connected to the bridge switching transistor module. The first current transformer TR2 and the second current transformer TR3 sample the induced current and convert it into a voltage sampling signal, which is then sent to the event processing pin of the control chip. When the voltage sampling signal exceeds a second predetermined threshold, the control chip stops sending the drive signals of the first MOS slow transistor Q1 and the second MOS slow transistor Q51.

2. The bridgeless totem-pole PFC lightning surge protection circuit of claim 1, wherein, The L-line is connected to the fuse and then to the drain of the first slow MOS transistor Q1 and the source of the second slow MOS transistor Q51. The drain of the second slow MOS transistor Q51, the drain of the second fast MOS transistor TR11, and the positive terminal of the output capacitor C23 are connected together. The source of the first slow MOS transistor Q1, the source of the first fast MOS transistor TR1, and the negative terminal of the output capacitor C23 are connected together. The drain of the first fast MOS transistor TR1 and the source of the second fast MOS transistor TR11 are connected together. The gates of each switching transistor are connected to the control chip.

3. The bridgeless totem-pole PFC lightning surge protection circuit of claim 1, wherein, The negative input pin IN- of the Hall chip U23 is connected to the drain of the first fast MOS transistor TR1 and the source of the second fast MOS transistor TR11 via an energy storage inductor L9.

4. The bridgeless totem-pole PFC lightning surge protection circuit of claim 1, wherein, The two AC input pins of the rectifier bridge BD1 are connected to the N line and the positive input pin IN+ of the Hall chip U23; the L line is connected to a fuse and then to a filter capacitor Cx2, which is connected in parallel between the L line and the N line.

5. The bridgeless totem-pole PFC lightning surge protection circuit of claim 1, wherein, The operational amplifier unit includes a first operational amplifier U17-A and a second operational amplifier U17-B. The non-inverting input of the first operational amplifier U17-A is connected to the voltage reference pin VREF of the Hall chip U23, and the inverting input is connected to the superimposed voltage signal pin VOUT of the Hall chip U23. The non-inverting input of the second operational amplifier U17-B is connected to the superimposed voltage signal pin VOUT of the Hall chip U23, and the inverting input is connected to the voltage reference pin VREF of the Hall chip U23. The outputs of the first operational amplifier U17-A and the second operational amplifier U17-B are connected in parallel to an overpower protection pin IA_OPP of the control chip. The parallel connection of the outputs of the first operational amplifier U17-A and the second operational amplifier U17-B forms the processed voltage signal and is transmitted to the control chip.

6. The bridgeless totem-pole PFC lightning surge protection circuit of claim 5, wherein, The voltage reference pin VREF of the Hall chip U23 outputs the reference voltage signal PFC-VREF of the Hall chip U23. The superimposed voltage signal pin VOUT of the Hall chip U23 outputs a Hall sampling signal PFC-S formed by superimposing the reference voltage signal PFC-VREF after being proportionally converted internally by the Hall chip U23. The reference voltage signal PFC-VREF and the Hall sampling signal PFC-S are respectively sent to the non-inverting input terminal and the inverting input terminal of the second operational amplifier U17-B after passing through current limiting resistors R1 and R2, respectively. At the same time, a first-four capacitor C1 is connected in parallel before the reference voltage signal PFC-VREF and the Hall sampling signal PFC-S are connected to the second operational amplifier U17-B. 14; The reference voltage signal PFC-VREF and the Hall sampling signal PFC-S are respectively sent to the non-inverting input terminal and the inverting input terminal of the first operational amplifier U17-B after passing through another current limiting resistor R3 and R7. The output signal of the first operational amplifier U17-A and the output signal of the second operational amplifier U17-B are respectively divided by resistors R248 and R122, and a voltage signal is formed at the midpoint and sent to the control chip. The inverting input terminal of the first operational amplifier U17-A is shorted to the output terminal of the first operational amplifier U17-A through the first-four resistor R114, and the inverting input terminal of the second operational amplifier U17-B is shorted to the output terminal of the second operational amplifier U17-B through the first-two resistor R112.

7. The bridgeless totem-pole PFC lightning surge protection circuit of claim 1, wherein, The first current transformer TR2 includes a first primary current transformer coil TR2-B and a first secondary current transformer coil TR2-A; the second current transformer TR3 includes a second primary current transformer coil TR3-B and a second secondary current transformer coil TR3-A; the two ends of the first primary current transformer coil TR2-B are respectively connected to the positive DC output of the rectifier bridge BD1 and the positive terminal of the output capacitor C23; the two ends of the second primary current transformer coil TR3-B are respectively connected to the negative DC output of the rectifier bridge BD1 and the negative terminal of the output capacitor C23; the first secondary current transformer coil TR2-A and the second secondary current transformer coil TR3-A are respectively rectified by diodes and then connected to a sampling resistor to obtain the voltage sampling signal.

8. The bridgeless totem-pole PFC lightning surge protection circuit of claim 7, wherein, Each of the mutual inductance secondary coils TR2-A or TR3-A has two switching diodes connected to its two ends respectively. The cathodes of the two switching diodes are connected together and then connected to the output terminal LLC_IP via a current-limiting resistor. The output terminal LLC_IP is connected to the event processing pin of the control chip. The anodes of the two switching diodes are connected together and then grounded, and connected to the power supply terminal SMCU_3.3V via another switching diode. The sampling resistor is connected in parallel between the common cathode connection point and the common anode connection point of the two switching diodes, and an RC filter circuit is connected in parallel. The RC filter circuit includes a filter capacitor and a filter resistor connected in parallel. The first anode of the other switching diode is connected to the common anode connection point, the second cathode is connected to the power supply terminal SMCU_3.3V, and the common terminal is connected to the output terminal LLC_IP.

9. The bridgeless totem-pole PFC lightning surge protection circuit of claim 6, wherein, The two current-limiting resistors R1 and R2 have the same resistance value, the two current-limiting resistors R3 and R7 have the same resistance value, the two resistors R248 and R122 have the same resistance value, and the first four resistors R114 and the first two resistors R112 have the same resistance value.

10. The bridgeless totem-pole PFC lightning surge protection circuit of claim 1, wherein, The positive input pin IN+ and negative input pin IN- of the Hall chip U23 are bidirectional, and can collect positive current or negative current respectively; the first MOS fast transistor TR1 and the second MOS fast transistor TR11 are silicon carbide fast transistors or gallium nitride fast transistors respectively.

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