semiconductor element

Abstract

A semiconductor element is provided. The semiconductor element includes a first organic light emitting diode (OLED) unit and a second OLED unit. The first OLED unit includes a first reflective pedestal, a first electroluminescent structure on the first reflective pedestal, and a first optical resonance structure between the first electroluminescent structure and the first reflective pedestal. The second OLED unit includes a second reflective pedestal, a second electroluminescent structure above the second reflective pedestal, and a second optical resonance structure between the second electroluminescent structure and the second reflective pedestal, wherein an elevation of the first reflective pedestal is different from an elevation of the second reflective pedestal.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Semiconductor components are used in many electronic devices, such as mobile phones, notebook computers, desktop computers, tablet computers, watches, gaming systems, and a variety of other industrial, commercial, and consumer electronics. A semiconductor component typically consists of a semiconductor portion and wiring portions formed within that semiconductor portion. Utility Model Content

[0003] This disclosure provides a semiconductor device comprising a first organic light-emitting diode (OLED) unit and a second OLED unit. The first OLED unit includes a first reflective substrate, a first electroluminescent structure on the first reflective substrate, and a first optical resonant structure between the first electroluminescent structure and the first reflective substrate. The second OLED unit includes a second reflective substrate, a second electroluminescent structure above the second reflective substrate, and a second optical resonant structure between the second electroluminescent structure and the second reflective substrate, wherein the elevation of the first reflective substrate is different from the elevation of the second reflective substrate.

[0004] This disclosure provides a semiconductor device comprising a first organic light-emitting diode (OLED) unit and a second OLED unit. The first OLED unit includes a first reflective substrate, a first optical resonant structure, and a first electroluminescent structure. The first electroluminescent structure is located above the first optical resonant structure. The second OLED unit includes a second reflective substrate, a second optical resonant structure, and a second electroluminescent structure. The second electroluminescent structure is located above the second optical resonant structure. The elevations of the first and second reflective substrates are different, and the first and second electroluminescent structures are coplanar.

[0005] This disclosure provides a semiconductor device including a first organic light-emitting diode (OLED) unit and a second OLED unit. The first OLED unit includes a first reflective substrate and a first electroluminescent structure. The first electroluminescent structure is located above the first reflective substrate. The second OLED unit includes a second reflective substrate and a second electroluminescent structure. The second electroluminescent structure is located above the second reflective substrate. The elevations of the first and second reflective substrates are different, and the distance between the first reflective substrate and the first electroluminescent structure is different from the distance between the second reflective substrate and the second electroluminescent structure. Attached Figure Description

[0006] When with attachment Figure 1For the best understanding of all aspects of this disclosure, please refer to the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of discussion.

[0007] Figure 1 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0008] Figure 2 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0009] Figure 3 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0010] Figure 4 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0011] Figure 5 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0012] Figure 6 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0013] Figure 7 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0014] Figure 8 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0015] Figure 9 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0016] Figure 10 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0017] Figure 11 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0018] Figure 12 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0019] Figure 13 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0020] Figure 14To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0021] Figure 15 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0022] Figure 16 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0023] Figure 17 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0024] Figure 18 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0025] Figure 19 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0026] Figure 20 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0027] Figure 21 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0028] Figure 22 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0029] Figure 23 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0030] Figure 24A To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0031] Figure 24B To illustrate a top view of a semiconductor device in the manufacturing stage according to certain embodiments;

[0032] Figure 24C To illustrate a top view of a semiconductor device in the manufacturing stage according to certain embodiments;

[0033] Figure 24D To illustrate a top view of a semiconductor device in the manufacturing stage according to certain embodiments;

[0034] Figure 25A To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0035] Figure 25BTo illustrate a top view of a semiconductor device in the manufacturing stage according to certain embodiments;

[0036] Figure 25C To illustrate a top view of a semiconductor device in the manufacturing stage according to certain embodiments;

[0037] Figure 25D To illustrate a top view of a semiconductor device in the manufacturing stage according to certain embodiments;

[0038] Figure 26 To illustrate a cross-sectional view of a semiconductor device during the manufacturing process according to certain embodiments;

[0039] Figure 27 To illustrate a cross-sectional view of a semiconductor device according to certain embodiments.

[0040] [Symbol Explanation]

[0041] 100: Semiconductor components

[0042] 102: Component Layer

[0043] 104: Interconnection Layer

[0044] 106: First etch stop layer

[0045] 108: First dielectric layer

[0046] 110, 1104, 112: Thickness

[0047] 120: First organic light-emitting diode driving circuit

[0048] 122: Second Organic Light Emitting Diode Driver Circuit

[0049] 124: Third Organic Light Emitting Diode Driver Circuit

[0050] 130: First interconnect element

[0051] 132: Second interconnect element

[0052] 134: Third interconnect element

[0053] 202: First photoresist

[0054] 302: First patterned photoresist

[0055] 304, 306: Opening

[0056] 308, 310, 408, 410: Partial

[0057] 504: First trench

[0058] 506: Second trench

[0059] 508, 510: Top surface

[0060] 702: Floor

[0061] 704: Thickness

[0062] 802: First Floor

[0063] 902: First filling structure

[0064] 904: Second filling structure

[0065] 906: First conductive structure

[0066] 908: Second conductive structure

[0067] 1002: Second etch stop layer

[0068] 1004: Thickness

[0069] 1102: Second dielectric layer

[0070] 1106, 1108: Partial

[0071] 1206: Third trench

[0072] 1210, 1212, 1214: Top surface

[0073] 1220: Second patterned photoresist

[0074] 1302: Floor

[0075] 1304: Thickness

[0076] 1402: Second Floor

[0077] 1502: Third filling structure

[0078] 1506: Third conductive structure

[0079] 1602: Third Etching Stop Layer

[0080] 1604, 1704: Thickness

[0081] 1702: Third dielectric layer; 1706, 1708, 1710, 1712, 1714, 1716, 1718, 1720, 1722, 1724, 1726, 1728: Partial; 1802: Fourth trench.

[0082] 1804: Fifth trench

[0083] 1806: Sixth trench

[0084] 1808, 1810, 1812, 1814, 1816, 1818: Exposed surfaces

[0085] 1820: Third Patterned Photoresist

[0086] 1822, 1824, 1826: Exposed surfaces

[0087] 1830, 1832, 1834: Depth

[0088] 1902: Reflective layer

[0089] 1904: Thickness

[0090] 2002: Optical Resonance Layer

[0091] 2102: First Structure

[0092] 2104: Second Structure

[0093] 2106: Third Structure

[0094] 2108, 2110, 2112: Partial

[0095] 2202: First optical resonance structure

[0096] 2204: Second optical resonance structure

[0097] 2206: Third optical resonance structure

[0098] 2302: Electroluminescent layer

[0099] 2402: First electroluminescent structure

[0100] 2404: Second electroluminescent structure

[0101] 2406: Third electroluminescent structure

[0102] 2408, 2410, 2412: Top surface

[0103] 2414: First Reflection Structure

[0104] 2414a: First reflector base

[0105] 2414b: First reflecting wall

[0106] 2414c: Second reflector

[0107] 2416: Second Reflection Structure

[0108] 2416a: Second reflector base

[0109] 2416b: Third reflector

[0110] 2416c: Fourth reflector

[0111] 2418: Third Reflection Structure

[0112] 2418a: Third reflector base

[0113] 2418b: Fifth Reflector

[0114] 2418c: Sixth reflector

[0115] 2424: First Organic Light Emitting Diode Unit

[0116] 2426: Second Organic Light Emitting Diode Unit

[0117] 2428: Third organic light-emitting diode unit; 2430, 2530, 2532, 2534, 2536, 2538, 2540, 2542, 2544, 2546, 2548, 2550, 2552: Thickness; 2602: Color filter layer.

[0118] 2604: First color filter

[0119] 2606: Second color filter

[0120] 2608: Third color filter

[0121] 2702: First Current

[0122] 2704: Second Current

[0123] 2706: Third Current

[0124] 2708: The First Light Path

[0125] 2710: Second Optical Path

[0126] 2712: The Third Optical Path

[0127] 2718: First emitted light

[0128] 2720: Second emitted light

[0129] 2722: Third emitted light

[0130] AA: Line

[0131] B1, B2, B3, B4, B5, B6: Barrier Structures

[0132] D1, D2, D3, D7: Distance

[0133] D4: Width

[0134] D5: Length

[0135] M1, M2, M3, M4, M5, M6: Mirror structure

[0136] S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24: Sidewall

[0137] TB1: Trench substrate

[0138] TB2: Trench substrate

[0139] TB3: Trench substrate

[0140] y1, y2, y3, y4: Elevation Detailed Implementation

[0141] The following disclosure provides several different implementations, or embodiments, for carrying out the various features of this disclosure. Specific embodiments of components and arrangements are described below to simplify the content of this disclosure. Of course, these are merely embodiments and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include implementations where the first and second features are in direct contact, or implementations where additional features may be formed between the first and second features, such that the first and second features do not need to be in direct contact. Furthermore, reference numerals or letters may be repeated in various embodiments of this disclosure. This repetition is for brevity and does not in itself represent a relationship between the various implementations or configurations discussed.

[0142] Furthermore, for ease of description, this disclosure may use spatially relative terms such as "below," "below," "lower part," "above," "upper part," etc., to describe the relationship of one element or feature to other elements or features, as shown in the accompanying drawings. Spatially relative terms include not only the directions shown in the drawings but also the different orientations of the element during use or operation. This device may be used in other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0143] The term "cover" and / or similar terms can be used to describe an element or feature that overlaps vertically with another element or feature and is at a higher elevation than the other element or feature. For example, if the elevation of a first element is higher than that of a second element, and at least a portion of the first element is perpendicularly coincident with at least a portion of the second element, then the first element covers the second element.

[0144] The term "bottom" and / or similar terms can be used to describe an element or feature that coincides vertically with another element or feature but is at a lower elevation than the other element or feature. For example, if the elevation of a first element is lower than that of a second element, and at least a portion of the first element is vertically aligned with at least a portion of the second element, then the first element is below the second element.

[0145] The term "above" can be used to describe an element or feature that is at a higher elevation than another element or feature. For example, if the first element is at a higher elevation than the second element, then the first element is above the second element.

[0146] The term "below" can be used to describe an element or feature that is at a lower elevation than another element or feature. For example, if the elevation of the first element is lower than that of the second element, then the first element is below the second element.

[0147] The semiconductor device includes a first organic light-emitting diode (OLED) unit and a second OLED unit. The first OLED unit includes a first reflective substrate, a first electroluminescent structure above the first reflective substrate, and a first optical resonant structure between the first electroluminescent structure and the first reflective substrate. The second OLED unit includes a second reflective substrate, a second electroluminescent structure covering the second reflective substrate, and a second optical resonant structure between the second electroluminescent structure and the second reflective substrate. In some embodiments, the first OLED unit is configured to emit light of a first color, and the second OLED unit is configured to emit light of a second color different from the first color. In some embodiments, the elevation of the first reflective substrate is different from the elevation of the second reflective substrate. In some embodiments, the first electroluminescent structure and the second electroluminescent structure are coplanar.

[0148] Figure 1 To Figure 26 To illustrate the semiconductor device 100 at various stages of manufacturing according to some embodiments. Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24A , Figure 25A , Figure 26 and Figure 27 A cross-sectional view of semiconductor device 100 is shown. Figures 24B to 24D To illustrate the top view of semiconductor element 100 under various conditions. Figure 24A The view shown is along Figure 24B Line AA in the middle Figure 24C Line AA or Figure 24D A cross-sectional view of semiconductor device 100 taken by line AA. Figures 25B to 25D Top view of semiconductor element 100 under various conditions. Figure 25A The view shown is along Figure 25B Line AA in the middle Figure 25C Line AA or Figure 25D The cross-sectional view of semiconductor device 100 taken by line AA in the figure.

[0149] In some embodiments, the semiconductor element 100 includes a display panel, such as an OLED display panel. In some embodiments, the display panel includes an OLED cell array. Other structures and / or configurations of the semiconductor element 100 and / or the display panel are within the scope of this disclosure.

[0150] Figure 1To illustrate a semiconductor device 100 according to some embodiments. In some embodiments, the semiconductor device 100 includes at least one of a device layer 102, an interconnect layer 104, a first etch stop layer 106, or a first dielectric layer 108. In some embodiments, the device layer 102 includes a substrate. In some embodiments, the device layer 102 includes at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a wafer formed from a wafer. In some embodiments, the device layer 102 includes at least one of silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonide, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or other suitable materials. The device layer 102 includes single-crystal silicon, having <100> Crystalline silicon with crystal orientation, <110> Crystalline silicon with crystal orientation, <111> At least one of crystalline silicon or other suitable materials with a crystalline orientation. Other structures and / or configurations of the element layer 102 are within the scope of this disclosure. In some embodiments, the element layer 102 includes dopants having a conductivity type, such as n-type or p-type. In some embodiments, the element layer 102 is formed by at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), spin, growth, or other suitable techniques.

[0151] In some embodiments, element layer 102 includes a front-end process (FEOL) layer of semiconductor element 100. In some embodiments, OLED-cell driving elements are disposed in element layer 102. In some embodiments, the OLED-cell driving elements include at least one of a first organic light-emitting diode (OLED) driving circuit 120, a second OLED driving circuit 122, or a third OLED driving circuit 124. In some embodiments, the first OLED driving circuit 120 includes at least one of (i) one or more first transistors, (ii) one or more first capacitors, (iii) one or more first resistors, or (iv) one or more other suitable elements. In some embodiments, the second OLED driving circuit 122 includes at least one of (i) one or more second transistors, (ii) one or more second capacitors, (iii) one or more second resistors, or (iv) one or more other suitable elements. In some embodiments, the third organic light-emitting diode driving circuit 124 includes at least one of (i) one or more third transistors, (ii) one or more third capacitors, (iii) one or more third resistors, or (iv) one or more other suitable elements.

[0152] Interconnect layer 104 is formed over element layer 102 by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin, growth, or other suitable techniques. In some embodiments, interconnect layer 104 comprises a back-to-offline (BEOL) layer of semiconductor element 100. In some embodiments, interconnect layer 104 comprises at least one of undoped silicate glass (USG), silicon nitride, phosphosilicate glass (PSG), fluorosilicate glass (FSG), dielectric material, low-k dielectric material, very low-k dielectric material, black diamond, or other suitable materials. The term "low-k dielectric material" as used herein refers to a material with a dielectric constant k less than about 3.9. As used in this disclosure, the term "very low-k dielectric material" refers to a material with a dielectric constant k less than about 2.5. In some embodiments, interconnect elements are disposed in interconnect layer 104. In some embodiments, the interconnect element includes one or more conductive structures, such as vias, wiring, contacts, metal lines, etc., which provide interconnection between at least one of various doping features of the semiconductor element 100, OLED cells, circuits, inputs / outputs, etc. In some embodiments, the interconnect element includes at least one of a first interconnect element 130, a second interconnect element 132, or a third interconnect element 134. In some embodiments, at least one of the first interconnect element 130, the second interconnect element 132, or the third interconnect element 134 includes one or more metals or other suitable materials. In some embodiments, at least one of the first interconnect element 130, the second interconnect element 132, or the third interconnect element 134 includes copper (Cu).

[0153] The first etch stop layer 106 is formed over the interconnect layer 104 by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin, growth, or other suitable techniques. The first etch stop layer 106 comprises at least one of the following: (i) covering the interconnect layer 104; (ii) directly contacting the top surface of the interconnect layer 104; or (iii) indirectly contacting the top surface of the interconnect layer 104. The first etch stop layer 106 comprises at least one of the following: (i) covering at least one of the first interconnect element 130, the second interconnect element 132, or the third interconnect element 134; (ii) directly contacting the top surface of at least one of the first interconnect element 130, the second interconnect element 132, or the third interconnect element 134; or (iii) indirectly contacting the top surface of at least one of the first interconnect element 130, the second interconnect element 132, or the third interconnect element 134. In some embodiments, the first etch stop layer 106 comprises at least one of silicon nitride (SiN), silicon carbide (SiC), or other suitable materials. The thickness 110 of the first etch stop layer 106 is between about 10 angstroms and about 500,000 angstroms. Other values ​​for the thickness 110 are also within the scope of this disclosure.

[0154] The first dielectric layer 108 is formed over the first etch stop layer 106 by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin, growth, or other suitable techniques. The first dielectric layer 108 is at least one of: (i) covering the first etch stop layer 106; (ii) directly contacting the top surface of the first etch stop layer 106; or (iii) indirectly contacting the top surface of the first etch stop layer 106. In some embodiments, the first dielectric layer 108 includes an intermetallic dielectric (IMD) layer. In some embodiments, the first dielectric layer 108 comprises at least one of undoped silicate glass (USG), silicon nitride, phosphosilicate glass (PSG), fluorosilicate glass (FSG), a dielectric material, a low-k dielectric material, an extremely low-k dielectric material, or other suitable materials. The thickness 112 of the first dielectric layer 108 is between about 100 angstroms and about 500,000 angstroms. Other values ​​for thickness 112 are also within the scope of this disclosure.

[0155] Figure 2To illustrate a first photoresist 202 formed over a first dielectric layer 108 according to some embodiments. The first photoresist 202 at least covers the first dielectric layer 108, is in direct contact with the top surface of the first dielectric layer 108, or is in indirect contact with the top surface of the first dielectric layer 108. The first photoresist 202 is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin, growth, or other suitable techniques.

[0156] In some embodiments, the first photoresist 202 comprises a photosensitive material, wherein the properties of the first photoresist 202 (e.g., solubility) are affected by light. The first photoresist 202 is either a negative photoresist or a positive photoresist. With a negative photoresist, when illuminated by a light source, the areas of the negative photoresist become insoluble, and therefore, in a subsequent development stage, applying a solvent to the negative photoresist removes the unilluminated areas of the negative photoresist. Thus, the pattern formed in the negative photoresist is a negative defined by the opaque areas of the template (e.g., a mask) between the light source and the negative photoresist. With a positive photoresist, the illuminated areas of the positive photoresist become soluble and are removed during development using a solvent. Thus, the pattern formed in the positive photoresist is a positive image of the opaque areas of the template (e.g., a mask) between the light source and the positive photoresist.

[0157] Figure 3 To illustrate a first patterned photoresist 302 formed from a first photoresist 202 according to some embodiments. In some embodiments, the first patterned photoresist 302 defines openings 304 and 306 exposing portions 308 and 310 of the first dielectric layer 108. Although two openings are depicted in the first patterned photoresist 302, it is conceivable to have any number of openings in the first patterned photoresist 302.

[0158] Figures 4 to 5 To illustrate, a first patterned photoresist 302 is used to form a first set of trenches according to some embodiments. In some embodiments, a first etching process is performed to remove a portion of at least one of a first dielectric layer 108 or a first etch stop layer 106 to form the first set of trenches. In some embodiments, the first set of trenches includes a first trench 504 and a second trench 506 (e.g., Figure 5 (As shown). Although the figure shows two trenches in the first group of trenches, it is still possible to consider opening any number of trenches in the first group of trenches.

[0159] In some embodiments, a first etching process is performed to form a first set of trenches, wherein openings in the first patterned photoresist 302 allow one or more etchants applied in the first etching process to remove portions of at least one of the first dielectric layer 108 or the first etch stop layer 106, while the first patterned photoresist 302 protects or shields portions of the first dielectric layer 108 covered by the first patterned photoresist 302 to form the first set of trenches. In some embodiments, the first etching process includes a first multi-stage etching process comprising a first etching stage and a second etching stage. In some embodiments, the second etching stage is performed after the first etching stage. In some embodiments, the first etching stage includes at least one of a dry etching process, a wet etching process, an anisotropic etching process, an isotropic etching process, or other suitable etching processes. The first etching stage uses one or more first etching chemicals, including plasma, fluorine, hydrogen fluoride (HF), diluted HF, sulfur hexafluoride (SF6), and chlorinated compounds such as hydrogen chloride (HC). l2 The first etching chemical may be at least one of hydrogen sulfide (H2S), tetrafluoromethane (CF4), or other suitable materials. The second etching stage uses one or more second etching chemicals, including at least one of plasma, fluorine, HF, diluted HF, SF6, chlorine compounds such as HCl2, H2S, CF4, or other suitable materials. One or more first etching chemicals may be the same as or different from one or more second etching chemicals. In some embodiments, the second etching stage includes at least one of dry etching, wet etching, anisotropic etching, isotropic etching, or other suitable etching processes.

[0160] Figure 4 To illustrate a first etching stage of a first etching process implemented using a first patterned photoresist 302 according to some embodiments. In some embodiments, the first etching stage includes removing portions 308 and 310 of the first dielectric layer 108 (e.g., using one or more first etch chemicals). Figure 3 As shown), the openings in the first patterned photoresist 302 allow one or more first etch chemicals to remove portions 308 and 310 of the first dielectric layer 108, while the first patterned photoresist 302 protects or shields portions of the first dielectric layer 108 covered by the first patterned photoresist 302. In some embodiments, the first etch stage or at least one of the first etch chemicals has etch selectivity, such that the first etch stage removes and / or etches away portions 308 and 310 of the first dielectric layer 108, while removing and / or etching little or no first etch stop layer 106.

[0161] Figure 5To illustrate a second etching stage of a first etching process implemented using a first patterned photoresist 302 according to some embodiments. In some embodiments, the second etching stage includes removing portions 408 and 410 of the first etch stop layer 106 (e.g., using one or more second etch chemicals). Figure 4 As shown), the openings in the first patterned photoresist 302 allow one or more second etch chemicals to remove portions 408 and 410 of the first etch stop layer 106, while the first patterned photoresist 302 protects or shields portions of the first dielectric layer 108 and / or the first etch stop layer 106 covered by the first patterned photoresist 302. In some embodiments, the second etch stage or at least one of one or more second etch chemicals has etch selectivity, such that the second etch stage removes and / or etches away portions 408 and 410 of the first etch stop layer 106, while removing and / or etching away one or more other layers and / or elements or semiconductor elements 100, such as at least one of interconnect layer 104, first interconnect element 130, second interconnect element 132, or third interconnect element 134. In some embodiments, using a first etch stop layer 106 to perform a first multi-stage etch process to form a first set of trenches can provide at least one of the following: (i) improved control and accuracy in forming the first set of trenches; or (ii) reduced unwanted etching and / or damage to layers and / or elements of semiconductor device 100, such as at least one of interconnect layer 104, first interconnect element 130, second interconnect element 132, or third interconnect element 134. In some embodiments, the first trench 504 exposes the top surface 508 of the second interconnect element 132. In some embodiments, the second trench 506 exposes the top surface 510 of the third interconnect element 134.

[0162] Figure 6 To illustrate the removal of the first patterned photoresist 302 according to some embodiments. In some embodiments, the first patterned photoresist 302 is removed after the first set of trenches is formed. The first patterned photoresist 302 is removed by performing a cleaning process to wash away the first patterned photoresist 302, stripping the first patterned photoresist 302, etching the first patterned photoresist 302, chemical mechanical planarization (CMP), or at least one of other suitable techniques.

[0163] Figure 7To illustrate layer 702 formed over and / or in a first set of trenches according to some embodiments. Layer 702 is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin, growth, or other suitable techniques. Layer 702 includes at least (i) covering the first dielectric layer 108, (ii) being in direct contact with the top surface of the first dielectric layer 108, or (iii) being indirect contact with the top surface of the first dielectric layer 108. Layer 702 has at least one of the following: (i) covering at least one of the second interconnect element 132 or the third interconnect element 134, (ii) being in direct contact with at least one of the top surface 508 of the second interconnect element 132 or the top surface 510 of the third interconnect element 134, or (iii) being indirect contact with at least one of the top surface 508 of the second interconnect element 132 or the top surface 510 of the third interconnect element 134. In some embodiments, layer 702 comprises at least one of tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), aluminum copper (AlCu), aluminum silicon copper (AlSiCu), titanium nitride (TiN), tantalum nitride (TaN), or other suitable materials. The thickness 704 of layer 702 is between about 100 angstroms and about 600,000 angstroms. Other values ​​for the thickness 704 are also within the scope of this disclosure.

[0164] Figure 8 To illustrate a first layer 802 formed over layer 702 according to some embodiments. The first layer 802 is formed via at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin, growth, or other suitable techniques. The first layer 802 comprises at least one of: (i) a cover layer 702; (ii) direct contact with the top surface of layer 702; or (iii) indirect contact with the top surface of layer 702. In some embodiments, the first layer 802 comprises at least one of an oxide semiconductor material (e.g., silicon oxide), a metal, undoped silicate glass (USG), or other suitable materials. In some embodiments, the metal of the first layer 802 comprises at least one of a ferrous metal, aluminum, copper, tungsten, aluminum copper (e.g., aluminum copper with an aluminum content greater than about 99% and a copper content less than about 1%), or one or more other suitable metals.

[0165] Figure 9 To illustrate the removal of at least one of layer 702 or first layer 802 according to some embodiments ( Figure 8As shown, at least one of (i) a first conductive structure 906 comprising a first portion of layer 702, (ii) a second conductive structure 908 comprising a second portion of layer 702, (iii) a first filling structure 902 comprising a first portion of first layer 802, or (iv) a second filling structure 904 comprising a second portion of first layer 802 is formed. In some embodiments, at least a portion of layer 702 or first layer 802 is removed by at least one of chemical mechanical planarization (CMP), etching, cleaning processes, stripping, or other suitable techniques.

[0166] Figure 10 To illustrate a second etch stop layer 1002 formed over a first dielectric layer 108 according to some embodiments. The second etch stop layer 1002 is formed via at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin, growth, or other suitable techniques. The second etch stop layer 1002 includes at least one of the following: (i) covering the first dielectric layer 108; (ii) directly contacting the top surface of the first dielectric layer 108; or (iii) indirectly contacting the top surface of the first dielectric layer 108. The second etch stop layer 1002 has at least one of the following characteristics: (i) covering at least one of the first conductive structure 906, the second conductive structure 908, the first fill structure 902, or the second fill structure 904; (ii) directly contacting at least one of the top surfaces of the first conductive structure 906 and the second conductive structure 908; or (iii) indirectly contacting at least one of the top surfaces of the first conductive structure 906, the second conductive structure 908, the first fill structure 902, or the second fill structure 904. In some embodiments, the second etch stop layer 1002 comprises at least one of silicon nitride (SiN), silicon carbide (SiC), or other suitable materials. The thickness 1004 of the second etch stop layer 1002 is between about 10 angstroms and about 500,000 angstroms. Other values ​​for the thickness 1004 are also within the scope of this disclosure.

[0167] Figure 11To illustrate a second dielectric layer 1102 formed over a second etch stop layer 1002 according to some embodiments. The second dielectric layer 1102 is formed via at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin, growth, or other suitable techniques. The second dielectric layer 1102 has at least one of the following characteristics: (i) covering the second etch stop layer 1002; (ii) directly contacting the top surface of the second etch stop layer 1002; or (iii) indirectly contacting the top surface of the second etch stop layer 1002. In some embodiments, the second dielectric layer 1102 comprises an IMD layer. In some embodiments, the second dielectric layer 1102 comprises at least one of undoped silicate glass (USG), silicon nitride, phosphosilicate glass (PSG), fluorosilicate glass (FSG), a dielectric material, a low-k dielectric material, an extremely low-k dielectric material, or other suitable materials. The thickness 1104 of the second dielectric layer 1102 is between about 100 angstroms and about 500,000 angstroms. Other values ​​for the thickness 1104 are within the scope of this disclosure.

[0168] Figure 12 To illustrate, a third trench 1206 is formed in at least one of a second dielectric layer 1102 or a second etch stop layer 1002 according to some embodiments. In some embodiments, a second photoresist (not shown) is used to form the third trench 1206. The second photoresist is formed above the second dielectric layer 1102. The second photoresist at least covers the second dielectric layer 1102, is in direct contact with the top surface of the second dielectric layer 1102, or is in indirect contact with the top surface of the second dielectric layer 1102. The second photoresist is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin, growth, or other suitable techniques. In some embodiments, the second photoresist is patterned to form a second patterned photoresist 1220 (e.g., Figure 12(As shown). In some embodiments, the second patterned photoresist 1220 is used to form the third trench 1206, for example using one or more techniques, etching chemicals, etc. provided herein for using the first patterned photoresist 302 to form the first set of trenches. In some embodiments, a second multi-stage etching process is performed to form the third trench 1206, for example using one or more techniques, etching chemicals, etc. provided herein for performing a first multi-stage etching process to form the first set of trenches. In some embodiments, performing a second multi-stage etching process to form the third trench 1206 using the second etch stop layer 1002 includes at least one of the following: (i) performing a third etch stage of the second multi-stage etching process using one or more third etch chemicals (e.g., one or more second etch chemicals), (ii) performing a fourth etch stage of the second multi-stage etching process using one or more fourth etch chemicals (e.g., one or more second etch chemicals) to remove a portion 1106 of the second etch stop layer 1002 (e.g., ...). Figure 11 (as shown), or (iii) using one or more fourth etch chemicals (e.g., one or more second etch chemicals) to perform the fourth etch stage of the second multi-stage etch process to remove portion 1108 of the second etch stop layer 1002 (as shown). Figure 11 (As shown). In some embodiments, performing a second multi-stage etching process using the second etch stop layer 1002 to form the third trench 1206 provides at least one of the following: (i) improved control and accuracy in forming the third trench 1206, or (ii) reduced unwanted etching and / or damage to layers and / or elements of the semiconductor element 100 (e.g., at least one of the second conductive structure 908 or the second fill structure 904). In some embodiments, the third trench 1206 exposes at least one of the top surface 1210 of the second conductive structure 908, the top surface 1214 of the second conductive structure 908, or the top surface 1212 of the second fill structure 904. In some embodiments, the second patterned photoresist 1220 is removed after the third trench 1206 is formed. The second patterned photoresist 1220 is removed by performing at least one of a cleaning procedure to wash away the second patterned photoresist 1220, stripping the second patterned photoresist 1220, etching the second patterned photoresist 1220, chemical mechanical planarization (CMP), or other suitable techniques.

[0169] Figure 13To illustrate layer 1302 formed over second dielectric layer 1102 and / or in third trench 1206 according to some embodiments. Layer 1302 is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin, growth, or other suitable techniques. Layer 1302 has at least one of the following characteristics: (i) covering second dielectric layer 1102; (ii) in direct contact with the top surface of second dielectric layer 1102; or (iii) indirect contact with the top surface of second dielectric layer 1102. The layer 1302 has at least one of the following characteristics: (i) covering at least one of the second conductive structure 908 or the second filling structure 904; (ii) being in direct contact with at least one of the top surface 1210, the top surface 1214 of the second conductive structure 908 or the top surface 1212 of the second filling structure 904, or (iii) being in indirect contact with at least one of the top surface 1210, the top surface 1214 of the second conductive structure 908 or the top surface 1212 of the second filling structure 904. In some embodiments, the layer 1302 comprises at least one of tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), aluminum-copper (AlCu), aluminum-silicon-copper (AlSiCu), titanium nitride (TiN), tantalum nitride (TaN), or other suitable materials. The thickness 1304 of layer 1302 is between about 100 angstroms and about 600,000 angstroms. Other values ​​for the thickness 1304 are within the scope of this disclosure.

[0170] Figure 14 To illustrate a second layer 1402 formed over layer 1302 according to some embodiments. The second layer 1402 is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin, growth, or other suitable techniques. The second layer 1402 is at least one of: (i) a cover layer 1302; (ii) in direct contact with the top surface of layer 1302; or (iii) in indirect contact with the top surface of layer 1302. In some embodiments, the second layer 1402 comprises at least one of an oxide semiconductor material (e.g., silicon oxide), a metal, undoped silicate glass (USG), or other suitable materials. In some embodiments, the metal of the second layer 1402 includes at least one of ferrous metals, aluminum, copper, tungsten, aluminum copper (e.g., aluminum copper with an aluminum content greater than about 99% and a copper content less than about 1%), or one or more other suitable metals.

[0171] Figure 15For illustration purposes, according to some embodiments, at least one portion of layer 1302 or second layer 1402 is removed. Figure 14 As shown in the diagram, at least one of (i) a third conductive structure 1506 comprising a portion of layer 1302, or (ii) a third filling structure 1502 comprising a portion of second layer 1402 is formed. In some embodiments, at least a portion of layer 1302 or second layer 1402 is removed by at least one of chemical mechanical planarization (CMP), etching, washing processes, stripping, or other suitable techniques.

[0172] Figure 16 To illustrate a third etch stop layer 1602 formed over a second dielectric layer 1102 according to some embodiments. The third etch stop layer 1602 is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin, growth, or other suitable techniques. The third etch stop layer 1602 includes at least one of the following: (i) covering the second dielectric layer 1102; (ii) directly contacting the top surface of the second dielectric layer 1102; or (iii) indirectly contacting the top surface of the second dielectric layer 1102. The third etch stop layer 1602 has at least one of the following characteristics: (i) covering at least one of the third conductive structure 1506 or the third fill structure 1502; (ii) in direct contact with at least one of the top surface of the third conductive structure 1506 or the top surface of the third fill structure 1502; or (iii) indirect contact with at least one of the top surface of the third conductive structure 1506 or the top surface of the third fill structure 1502. In some embodiments, the third etch stop layer 1602 comprises at least one of silicon nitride (SiN), silicon carbide (SiC), or other suitable materials. The thickness 1604 of the third etch stop layer 1602 is between about 10 angstroms and about 500,000 angstroms. Other values ​​for the thickness 1604 are within the scope of this disclosure.

[0173] Figure 17To illustrate a third dielectric layer 1702 formed over a third etch stop layer 1602 according to some embodiments. The third dielectric layer 1702 is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. The third dielectric layer 1702 includes at least one of: (i) covering the third etch stop layer 1602; (ii) being in direct contact with the top surface of the third etch stop layer 1602; or (iii) being in indirect contact with the top surface of the third etch stop layer 1602. In some embodiments, the third dielectric layer 1702 includes an IMD layer. In some embodiments, the third dielectric layer 1702 includes at least one of undoped silicate glass (USG), silicon nitride, phosphosilicate glass (PSG), fluorosilicate glass (FSG), a dielectric material, a low-k dielectric material, an extremely low-k dielectric material, or other suitable materials. The thickness 1704 of the third dielectric layer 1702 is between about 100 angstroms and about 500,000 angstroms. Other values ​​for the thickness 1704 are within the scope of this disclosure. The first ratio of the thickness 1704 of the third dielectric layer 1702 to the thickness 1104 of the second dielectric layer 1102 is between about 1:1 and about 5000:1. Other values ​​for the first ratio are within the scope of this disclosure.

[0174] Figure 18 This illustration depicts a second set of trenches formed in at least one of a third dielectric layer 1702 or a third etch stop layer 1602 according to some embodiments. In some embodiments, the second set of trenches includes at least one of a fourth trench 1802, a fifth trench 1804, or a sixth trench 1806. Even though three trenches of the second set of trenches are depicted, any number of trenches in the second set of trenches can be considered.

[0175] In some embodiments, a third photoresist (not shown) is used to form the second set of trenches. The third photoresist is formed over the third dielectric layer 1702. The third photoresist at least covers the third dielectric layer 1702, is in direct contact with the top surface of the third dielectric layer 1702, or is in indirect contact with the top surface of the third dielectric layer 1702. The third photoresist is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin, growth, or other suitable techniques. In some embodiments, the third photoresist is patterned to form a third patterned photoresist 1820. In some embodiments, the third patterned photoresist 1820 is used to form the second set of trenches, for example using one or more techniques, etching chemicals, etc., provided herein for forming the first set of trenches using the first patterned photoresist 302. In some embodiments, a third multi-stage etching process is performed to form the second set of trenches, for example, using one or more techniques, etching chemicals, etc., provided by this disclosure for performing a first multi-stage etching process to form the first set of trenches. In some embodiments, performing a third multi-stage etching process to form the second set of trenches includes at least one of the following: (i) performing a fifth etching stage of the third multi-stage etching process using one or more fifth etching chemicals (e.g., part 1706 (e.g.)). Figure 17 (i) at least one of the following: portion 1708 or portion 1710 of the third dielectric layer 1702; (ii) portion 1712 of the sixth etch stage of the third multi-stage etch process performed using one or more sixth etch chemicals (e.g., one or more second etch chemicals). Figure 17 (iii) at least one of the following: portion 1714 or portion 1716 of the third etch stop layer 1602; (iii) portion 1718 of the seventh etch stage of the third multi-stage etch process performed using one or more seventh etch chemicals (e.g., one or more first etch chemicals). Figure 17 (iv) performing the eighth etch stage of the third multi-stage etch process (as shown) or at least one of the portions 1720 of the second dielectric layer 1102, using one or more eighth etch chemicals (e.g., one or more second etch chemicals). Figure 17 (v) at least one of the portions 1722 or 1724 of the second etch stop layer 1002 (as shown), and (v) the ninth etch portion 1726 of the third multi-stage etching process is performed using one or more ninth etch chemicals (e.g., one or more first etch chemicals). Figure 17(vi) A portion of the first dielectric layer 108 (as shown) or (vi) the tenth etch stage of a third multi-stage etch process is performed using one or more tenth etch chemicals (e.g., one or more second etch chemicals) to remove a portion 1728 of the first etch stop layer 106 (as shown). Figure 17 (As shown). In some embodiments, performing a third multi-stage etching process using a third etch stop layer 1602 to form the second set of trenches can provide at least one of the following: (i) improved control and accuracy in forming the second set of trenches, or (ii) reduced unwanted etching and / or damage to layers and / or elements of the semiconductor element 100, such as at least one of the first interconnect element 130, the first conductive structure 906, the first fill structure 902, the third conductive structure 1506, or the third fill structure 1502. In some embodiments, the third patterned photoresist 1820 is removed after the second set of trenches is formed. The third patterned photoresist 1820 is removed by performing a cleaning procedure to wash away the third patterned photoresist 1820, stripping the third patterned photoresist 1820, etching the third patterned photoresist 1820, chemical mechanical planarization (CMP), or other suitable techniques.

[0176] In some embodiments, the fourth trench 1802 is defined by at least one of the following: the sidewall S1 of the first etch stop layer 106, the sidewall S2 of the first dielectric layer 108, the sidewall S3 of the second etch stop layer 1002, the sidewall S4 of the second dielectric layer 1102, the sidewall S5 of the third etch stop layer 1602, the sidewall S6 of the third dielectric layer 1702, the sidewall S7 of the first etch stop layer 106, the sidewall S8 of the first dielectric layer 108, the sidewall S9 of the second etch stop layer 1002, the sidewall S10 of the second dielectric layer 1102, the sidewall S11 of the third etch stop layer 1602, the sidewall S12 of the third dielectric layer 1702, or the trench substrate TB1. In some embodiments, the trench substrate TB1 of the fourth trench 1802 includes at least one of the exposed surface 1808 of the interconnect layer 104, the exposed surface 1810 of the first interconnect element 130, or the exposed surface 1812 of the interconnect layer 104. In some embodiments, at least one of the sidewalls S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, or S12 is tapered. In some embodiments, at least one of the sidewalls S1, S2, S3, S4, S5, or S6 is tapered to have a negative slope, and at least one of the sidewalls S7, S8, S9, S10, S11, or S12 is tapered to have a positive slope.

[0177] In some embodiments, the fifth trench 1804 is defined by at least one of the sidewalls S13 of the second etch stop layer 1002, the sidewalls S14 of the second dielectric layer 1102, the sidewalls S15 of the third etch stop layer 1602, the sidewalls S16 of the third dielectric layer 1702, the sidewalls S17 of the second etch stop layer 1002, the sidewalls S18 of the second dielectric layer 1102, the sidewalls S19 of the third etch stop layer 1602, the sidewalls S20 of the third dielectric layer 1702, or the trench substrate TB2. In some embodiments, the trench substrate TB2 of the fifth trench 1804 includes at least one of the exposed surface 1814 of the first conductive structure 906, the exposed surface 1816 of the first filling structure 902, or the exposed surface 1818 of the first conductive structure 906. In some embodiments, at least one of sidewalls S13, S14, S15, S16, S17, S18, S19, or S20 is tapered. In some embodiments, at least one of sidewalls S13, S14, S15, or S16 is tapered to have a negative slope, and at least one of sidewalls S17, S18, S19, or S20 is tapered to have a positive slope.

[0178] In some embodiments, the sixth trench 1806 is defined by at least one of the sidewalls S21, S22, S23, S24 of the third etch stop layer 1602, or the trench substrate TB3. In some embodiments, the trench substrate TB3 of the sixth trench 1806 includes at least one of the exposed surfaces 1822, 1824, or 1826 of the third conductive structure 1506. In some embodiments, at least one of the sidewalls S21, S22, S23, or S24 is tapered. In some embodiments, at least one of the sidewalls S21 or S22 is tapered to have a negative slope, and at least one of the sidewalls S23 or S24 is tapered to have a positive slope.

[0179] In some embodiments, the elevation of the trench base TB1 of the fourth trench 1802 is different from (e.g., lower than) at least one of the elevations of the trench base TB2 of the fifth trench 1804 or the trench base TB3 of the sixth trench 1806. In some embodiments, the elevation of the trench base TB2 of the fifth trench 1804 is different from (e.g., lower than) the elevation of the trench base TB3 of the sixth trench 1806.

[0180] The second ratio of the depth 1830 of the fourth trench 1802 to the depth 1832 of the fifth trench 1804 is between about 1.5:1 and about 27,000:1. The third ratio of the depth 1830 of the fourth trench 1802 to the depth 1834 of the sixth trench 1806 is between about 3:1 and about 27,000:1. The fourth ratio of the depth 1832 of the fifth trench 1804 to the depth 1834 of the sixth trench 1806 is between about 2:1 and about 18,000:1. Other values ​​of the second, third, and fourth ratios are within the scope of this disclosure.

[0181] Figure 19 To illustrate a reflective layer 1902 formed over a second dielectric layer 1102 and / or in a third trench 1206 according to some embodiments. The reflective layer 1902 is formed from at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. The reflective layer 1902 has at least one of the following: (i) it is connected to the trench substrate TB1 of the fourth trench 1802 (e.g., ...). Figure 18 (as shown), the trench base TB2 of the fifth trench 1804, the trench base TB3 of the sixth trench 1806, the sidewalls S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23 or S24 are aligned, (ii) with at least one of the trench base TB1 of the fourth trench 1802 (as shown). Figure 18 At least one of the following is in direct contact: the trench base TB2 of the fifth trench 1804, the trench base TB3 of the sixth trench 1806 of the fourth trench 1802, the sidewall S1, sidewall S2, sidewall S3, sidewall S4, sidewall S5, sidewall S6, sidewall S7, sidewall S8, sidewall S9, sidewall S10, sidewall S11, the sidewall S12, sidewall S13, sidewall S14, sidewall S15, sidewall S16, sidewall S17, sidewall S18, sidewall S19, sidewall S20, sidewall S21, sidewall S22, sidewall S23 or sidewall S24, or (iii) with the trench base TB1 of the fourth trench 1802 (as shown). Figure 18At least one of the following (shown) indirect contact, the trench base TB2 of the fifth trench 1804, the trench base TB3 of the sixth trench 1806 of the fourth trench 1802, the sidewall S1, sidewall S2, sidewall S3, sidewall S4, sidewall S5, sidewall S6, sidewall S7, sidewall S8, the sidewall S9, sidewall S10, sidewall S11, sidewall S12, sidewall S13, sidewall S14, sidewall S15, sidewall S16, sidewall S17, sidewall S18, sidewall S19, sidewall S20, sidewall S21, sidewall S22, sidewall S23 or sidewall S24. In some embodiments, the reflective layer 1902 comprises at least one of tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), aluminum copper (AlCu), aluminum silicon copper (AlSiCu), titanium nitride (TiN), tantalum nitride (TaN), or other suitable materials. The thickness 1904 of the reflective layer 1902 is between about 100 angstroms and about 600,000 angstroms. Other values ​​for the thickness 1904 are within the scope of this disclosure.

[0182] Figure 20 To illustrate an optical resonant layer 2002 formed over a reflective layer 1902 according to some embodiments. The optical resonant layer 2002 is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin, growth, or other suitable techniques. The optical resonant layer 2002 includes at least one of: (i) covering the reflective layer 1902; (ii) being in direct contact with the reflective layer 1902; or (iii) being in indirect contact with the reflective layer 1902. In some embodiments, the optical resonant layer 2002 includes at least one of oxide semiconductor materials (e.g., silicon oxide), nitride semiconductor materials (e.g., silicon nitride), undoped silicate glass (USG), phosphosilicate glass (PSG), fluorosilicate glass (FSG), low-k dielectric materials, very low-k dielectric materials, black diamond, or other suitable materials. In some embodiments, the optical resonant layer 2002 comprises a transparent material.

[0183] Figure 21 To illustrate, according to some embodiments, at least one of the reflective layer 1902 or the optical resonant layer 2002 is removed ( Figure 20 As shown, at least one of (i) a first structure 2102 including a first portion of the optical resonant layer 2002, (ii) a second structure 2104 including a second portion of the optical resonant layer 2002, or (iii) a third structure 2106 including a third portion of the optical resonant layer 2002 is formed. In some embodiments, at least one portion of the reflective layer 1902 or the optical resonant layer 2002 is removed by at least one of chemical mechanical planarization (CMP), etching, cleaning processes, stripping, or other suitable techniques.

[0184] Figure 22 To illustrate the removal of portions 2108, 2110, and 2112 (e.g., from the first structure 2102, the second structure 2104, and the third structure 2106) Figure 21 As shown), to form a set of optical resonant structures, the set of optical resonant structures includes at least one of the first optical resonant structures 2202 that are a part of the first structure 2102, (ii) a second optical resonant structure 2204 that is a part of the second structure 2104, or (iii) at least one of the third optical resonant structures 2206 that is a part of the third structure 2106. Even though three optical resonant structures of the optical resonant structure set are depicted, any number of optical resonant structures of the optical resonant structure set can be considered. In some embodiments, portions 2108, 2110, and 2112 are removed by a wet etch solution immersion process, wherein the semiconductor element 100 is immersed in an etch solution containing one or more etch chemicals, such as at least one of HF, diluted HF, or other suitable materials. In some embodiments, the reflective layer 1902 acts as a protective shield to mitigate unwanted etching and / or damage to one or more portions of the semiconductor element 100 (e.g., one or more portions of the third dielectric layer 1702) during the wet etch solution immersion process. Other techniques for removing portions 2108, 2110, and 2112 fall within the scope of this disclosure, such as lithography, chemical mechanical planarization (CMP), cleaning processes, stripping, or at least one of other suitable techniques.

[0185] Figure 23 This illustration depicts an electroluminescent layer 2302 formed over a set of optical resonant structures according to some embodiments. The electroluminescent layer 2302 is formed from at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. The electroluminescent layer 2302 has at least one of the following characteristics: (i) covering one, part, or all of the optical resonant structures in the set; (ii) in direct contact with one, part, or all of the optical resonant structures in the set; or (iii) indirect contact with one, part, or all of the optical resonant structures in the set. In some embodiments, the electroluminescent layer 2302 comprises an organic compound capable of emitting light in response to an electric current. Other materials for the electroluminescent layer 2302 are within the scope of this disclosure.

[0186] Figures 24A to 24DTo illustrate, according to some embodiments, the electroluminescent layer 2302 is patterned to form a set of electroluminescent structures, the set of electroluminescent structures including at least one of the following: (ii) a first electroluminescent structure 2402 comprising a first portion of the electroluminescent layer 2302, (iii) a second electroluminescent structure 2404 comprising a second portion of the electroluminescent layer 2302, or (iii) a third electroluminescent structure 2406 comprising a third portion of the electroluminescent layer 2302. Even though three electroluminescent structures of the set of electroluminescent structures are depicted, any number of electroluminescent structures of the set of electroluminescent structures is considered. The thickness 2430 of each electroluminescent structure, one, part, or all of the electroluminescent structures in the set of electroluminescent structures (e.g., Figure 24A and Figure 25A (As shown) The thickness ranges from about 10 angstroms to about 500,000 angstroms. Other values ​​for the thickness of 2430 are within the range disclosed herein.

[0187] In some embodiments, the electroluminescent layer 2302 is patterned via a planarization process including at least one of CMP or other suitable techniques to form the set of electroluminescent structures. In some embodiments, the planarization process includes removing one or more top portions of at least one of the electroluminescent layer 2302 or the reflective layer 1902. In some embodiments, the planarization process is performed such that portions or all of the top surfaces 2408, 2410, and / or 2412 (of the first electroluminescent structure 2402, the second electroluminescent structure 2404, and / or the third electroluminescent structure 2406) are coplanar with each other. In some embodiments, according to some implementations, the planarization process forms a set of reflective structures including at least one of (ii) a first reflective structure 2414 comprising a first portion of the reflective layer 1902, (iii) a second reflective structure 2416 comprising a second portion of the reflective layer 1902, or (iv) a third reflective structure 2418 comprising a third portion of the reflective layer 1902. Even though only three reflective structures in a reflective structure group are depicted, any number of reflective structures in the reflective structure group are considered. Other processes and / or techniques for forming electroluminescent and / or reflective structure groups are within the scope of this disclosure.

[0188] In some embodiments, the first reflective structure 2414 includes at least one of the following: (i) a first reflective base 2414a (in...) Figure 24A (i) shown in the outline of a broken line), (ii) the first reflective wall 2414b (in Figure 24A (shown in the outline of the broken dotted line), or the second reflective wall 2414c (in Figure 24A (i) The outline of the first optical resonant structure 2202 is shown in the middle. (ii) The first reflective wall 2414b is aligned with the first side of the first optical resonant structure 2202. Figure 24A(shown in the middle with a broken dashed outline), or the second reflective wall 2414c aligned with the second side of the first optical resonance structure 2202 .... Figure 24A (shown in dashed outline). In some embodiments, at least one of the first reflective base 2414a, the first reflective wall 2414b, or the second reflective wall 2414c is at least (i) aligned with the first optical resonant structure 2202, (ii) in direct contact with the first optical resonant structure 2202, or (iii) indirectly in contact with the first optical resonant structure 2202.

[0189] In some embodiments, the second reflective structure 2416 includes at least one of the following: (i) a second reflective base 2416a (in Figure 24A (i) The second reflective base 2416a is located below the second optical resonant structure 2204; (ii) The third reflective wall 2416b (in the outline shown by dashes) Figure 24A (shown as a dashed outline in the image), the third reflective wall 2416b is aligned with the first side of the second optical resonant structure 2204, or the fourth reflective wall 2416c is aligned with the second side of the second optical resonant structure 2204 (in...). Figure 24A (shown in the outline with punctuated lines), aligned with the first side of the second optical resonant structure 2204. In some embodiments, at least one of the second reflective base 2416a, the third reflective wall 2416b, or the fourth reflective wall 2416c is at least (i) aligned with the second optical resonant structure 2204, (ii) in direct contact with the second optical resonant structure 2204, or (iii) indirectly in contact with the second optical resonant structure 2204.

[0190] In some embodiments, the third reflective structure 2418 includes at least one of the following: (i) a third reflective base 2418a (in Figure 24A (i) shown in the outline of a broken line), which is located at the bottom layer of the third optical resonance structure 2206; (ii) the fifth reflective wall 2418b (in Figure 24A (shown in the outline of a broken line), which is aligned with the first side of the third optical resonant structure 2206, or the sixth reflective wall 2418c (in Figure 24A (i) The fifth reflective wall 2418b, which is aligned with the second side of the third optical resonant structure 2206 (shown in the outline of a broken line), is aligned with the first side of the third optical resonant structure 2206. Figure 24A (shown in the middle with a broken dashed outline), or the sixth reflective wall 2418c aligned with the second side of the third optical resonance structure 2206 (shown in the middle with a broken dashed outline), Figure 24A(shown in dashed outline). In some embodiments, at least one of the third reflective base 2418a, the fifth reflective wall 2418b, or the sixth reflective wall 2418c is at least (i) aligned with the third optical resonant structure 2206, (ii) in direct contact with the third optical resonant structure 2206, or (iii) indirectly in contact with the third optical resonant structure 2206.

[0191] In some implementations, some or all of the electroluminescent structures in the set of electroluminescent structures are coplanar, such that a plane (e.g., composed of...) Figure 24A The single plane formed by the horizontal line x1 shown in the diagram passes through some or all of the electroluminescent structures and / or intersects with some or all of the electroluminescent structures. In some embodiments, the electroluminescent structures of this group of electroluminescent structures have different elevations (e.g., slightly different elevations) and the group of electroluminescent structures are coplanar, such that the plane passes through and / or intersects with the electroluminescent structures of this group of electroluminescent structures (even if the top and / or bottom surfaces of the electroluminescent structures may not be coplanar).

[0192] In some embodiments, the semiconductor element 100 includes a group of organic light-emitting diode (OLED) units, which include at least one of a first OLED unit 2424, a second OLED unit 2426, or a third OLED unit 2428. Although three OLED units in a group of OLED units are described, any number of OLED units in a group of OLED units is contemplated. In some embodiments, the first OLED unit 2424 includes at least one of (i) a first reflective structure 2414, (ii) a first electroluminescent structure 2402, or (iii) a first optical resonant structure 2202 between a first reflective base 2414a of the first reflective structure 2414 and the first electroluminescent structure 2402. In some embodiments, the second OLED unit 2426 includes at least one of (i) a second reflective structure 2416, (ii) a second electroluminescent structure 2404, or (iii) a second optical resonant structure 2204 between a second reflective base 2416a of the second reflective structure 2416 and the second electroluminescent structure 2404. In some embodiments, the third organic light-emitting diode unit 2428 includes at least one of (i) a third reflective structure 2418, (ii) a third electroluminescent structure 2406, or (iii) a third optical resonant structure 2206 between the third reflective base 2418a of the third reflective structure 2418 and the third electroluminescent structure 2406.

[0193] Figure 24BA top view of a semiconductor element 100 according to a first embodiment of some implementations is shown. In the first embodiment, at least one of (i) the electroluminescent structures of the electroluminescent structure set has a circular shape, or (ii) the reflective structures of the reflective structure set has a circular shape. Figure 24C A top view of a semiconductor element 100 according to a second embodiment is shown. In the second embodiment, (i) the electroluminescent structure of the set of electroluminescent structures has a rectangular shape, or (ii) the reflective structure of the set of reflective structures has at least one of a rectangular shape. Figure 24D A top view is provided to illustrate a semiconductor element 100 according to a third embodiment of certain implementations. In the third embodiment, (i) the electroluminescent structures of the set of electroluminescent structures have a triangular shape, or (ii) the reflective structures of the set of reflective structures have at least one of a triangular shape. Other shapes of the set of electroluminescent structures and / or the set of reflective structures besides those shown and / or described herein are also within the scope of this disclosure.

[0194] Figures 25A to 25D To illustrate a semiconductor element 100 in a scheme comprising a set of reflective structures according to some embodiments, including a multilayer structure. In some embodiments, a first reflective structure 2414 includes a mirror structure M1 and a blocking structure B1, wherein the mirror structure M1 separates the blocking structure B1 from at least one of a first optical resonant structure 2202 or a first electroluminescent structure 2402. Thus, according to some embodiments, (i) a first reflective base 2414a includes a portion of the blocking structure B1 and a portion of the mirror structure M1, (ii) a first reflective wall 2414b includes a portion of the blocking structure B1 and a portion of the mirror structure M1, and (iii) a second reflective wall 2414c includes a portion of the blocking structure B1 and a portion of the mirror structure M1. In some embodiments, the thickness 2530 of the mirror structure M1 is greater than the thickness 2532 of the blocking structure B1. The thickness 2530 is between about 100 angstroms and about 500,000 angstroms. The thickness 2532 is between about 10 angstroms and about 100,000 angstroms. Other values ​​for thicknesses 2530 and 2532 are within the scope of this disclosure.

[0195] In some embodiments, the second reflective structure 2416 includes a mirror structure M2 and a blocking structure B2, wherein the mirror structure M2 separates the blocking structure B2 from at least one of the second optical resonant structure 2204 or the second electroluminescent structure 2404. Therefore, according to some embodiments, (i) the second reflective base 2416a includes a portion of the blocking structure B2 and a portion of the mirror structure M2, (ii) the third reflective wall 2416b includes a portion of the blocking structure B2 and a portion of the mirror structure M2, and (iii) the fourth reflective wall 2416c includes a portion of the blocking structure B2 and a portion of the mirror structure M2. In some embodiments, the thickness 2534 of the mirror structure M2 is greater than the thickness 2536 of the blocking structure B2. The thickness 2534 is between about 100 angstroms and about 500,000 angstroms. The thickness 2536 is between about 10 angstroms and about 100,000 angstroms. Other values ​​for thicknesses 2534 and 2536 are within the scope of this disclosure.

[0196] In some embodiments, the third reflective structure 2418 includes a mirror structure M3 and a blocking structure B3, wherein the mirror structure M3 separates the blocking structure B3 from at least one of the third optical resonant structure 2206 or the third electroluminescent structure 2406. Therefore, according to some embodiments, (i) the third reflective base 2418a includes a portion of the blocking structure B3 and a portion of the mirror structure M3, (ii) the fifth reflective wall 2418b includes a portion of the blocking structure B3 and a portion of the mirror structure M3, and (iii) the sixth reflective wall 2418c includes a portion of the blocking structure B3 and a portion of the mirror structure M3. In some embodiments, the thickness 2538 of the mirror structure M2 is greater than the thickness 2540 of the blocking structure B2. The thickness 2538 is between about 100 angstroms and about 500,000 angstroms. The thickness 2540 is between about 10 angstroms and about 100,000 angstroms. Other values ​​for thicknesses 2538 and 2540 are within the scope of this disclosure.

[0197] In some embodiments, the reflective layer 1902 (e.g. Figure 19 (As shown) includes at least one of a first barrier layer or a first mirror layer. In some embodiments, forming the reflective layer 1902 includes (i) forming a first barrier layer and (ii) forming a first mirror layer over the first barrier layer. At least one of the first barrier layer or the first mirror layer is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. In some embodiments, barrier structures B1, B2, and B3 include respective portions of the first barrier layer. In some embodiments, mirror structures M1, M2, and M3 include respective portions of the first mirror layer.

[0198] The first mirror layer differs from the first barrier layer, for example, by having a different material composition, thus defining an interface between the first mirror layer and the first barrier layer. In some embodiments, the first mirror layer does not have a different material composition from the first barrier layer. However, since the first mirror layer and the first barrier layer are separate and non-equivalent layers, an interface is defined between the first mirror layer and the first barrier layer. In some embodiments, the first mirror layer has a higher reflectivity for visible light (e.g., light with wavelengths between about 350 nm and about 780 nm) than the first barrier layer has for visible light. In some embodiments, the first mirror layer has a reflectivity for visible light of at least about 80%. In some embodiments, the first mirror layer comprises a metal alloy, and the first barrier layer comprises a metal alloy. In some embodiments, the first mirror layer (and the mirror structures M1, M2, and M3 formed from the first mirror layer) comprises at least one of tungsten (W), copper (Cu), aluminum (Al), aluminum-copper (AlCu), aluminum-silicon-copper (AlSiCu), or other suitable materials. In some embodiments, the first barrier layer (and the barrier structures B1, B2, and B3 formed by the first barrier layer) comprises at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable materials. In some embodiments, the first barrier layer provides a reflective layer 1902 (and / or a first mirror layer) and sidewalls S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, and / or S24 (e.g., ...). Figure 18 (As shown) Improved adhesion. In some embodiments, the first barrier layer comprises an adhesive material.

[0199] In some embodiments, the carbon concentration per unit volume in the first mirror layer differs from the carbon concentration per unit volume in the first barrier layer. In some embodiments, the copper concentration per unit volume in the first mirror layer differs from the copper concentration per unit volume in the first barrier layer. In some embodiments, the aluminum concentration per unit volume in the first mirror layer differs from the aluminum concentration per unit volume in the first barrier layer. In some embodiments, the silicon concentration per unit volume in the first mirror layer differs from the silicon concentration per unit volume in the first barrier layer.

[0200] In some embodiments, the first conductive structure 906 includes a mirror structure M4 and a barrier structure B4. In some embodiments, the second conductive structure 908 includes a mirror structure M5 and a barrier structure B5. In some embodiments, layer 702 (e.g. Figure 7 (As shown) includes at least one of a second barrier layer or a second mirror layer. In some embodiments, forming layer 702 includes (i) forming a second barrier layer and (ii) forming a second mirror layer over the second barrier layer. At least one of the second barrier layer or the second mirror layer is formed via at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin, growth, or other suitable techniques. In some embodiments, barrier structures B4 and B5 each comprise a portion of the second barrier layer. In some embodiments, mirror structures M4 and M5 each comprise a portion of the second mirror layer. In some embodiments, the thickness 2542 of mirror structure M4 is greater than the thickness 2544 of barrier structure B4. Thickness 2542 is between about 100 angstroms and about 500,000 angstroms. Thickness 2544 is between about 10 angstroms and about 100,000 angstroms. In some embodiments, the thickness 2546 of the mirror structure M5 is greater than the thickness 2548 of the barrier structure B5. Thickness 2546 is between about 100 angstroms and about 500,000 angstroms. Thickness 2548 is between about 10 angstroms and about 100,000 angstroms. Other values ​​for thicknesses 2542, 2544, 2546, and 2548 are within the scope of this disclosure.

[0201] The second mirror layer differs from the second barrier layer, for example, by having a different material composition, thus defining an interface between the second mirror layer and the second barrier layer. In some embodiments, the second mirror layer does not have a different material composition from the second barrier layer. However, since the second mirror layer and the second barrier layer are separate and asymmetrical layers, an interface is defined between the second mirror layer and the second barrier layer. In some embodiments, the second mirror layer has a higher reflectivity to visible light than the second barrier layer. In some embodiments, the second mirror layer has a reflectivity to visible light of at least about 80%. In some embodiments, the second mirror layer comprises a metal alloy, and the second barrier layer comprises a metal alloy. In some embodiments, the second mirror layer (and the mirror structures M4 and M5 formed by the second mirror layer) comprises at least one of tungsten (W), copper (Cu), aluminum (Al), aluminum-copper (AlCu), aluminum-silicon-copper (AlSiCu), or other suitable materials. In some embodiments, the second barrier layer (and the barrier structures B4 and B5 formed by the second barrier layer) comprises at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable materials. In some embodiments, the second barrier layer comprises an adhesive material.

[0202] In some embodiments, the carbon concentration per unit volume in the second mirror layer differs from the carbon concentration per unit volume in the second barrier layer. In some embodiments, the copper concentration per unit volume in the second mirror layer differs from the copper concentration per unit volume in the second barrier layer. In some embodiments, the aluminum concentration per unit volume in the second mirror layer differs from the aluminum concentration per unit volume in the second barrier layer. In some embodiments, the silicon concentration per unit volume in the second mirror layer differs from the silicon concentration per unit volume in the second barrier layer.

[0203] In some embodiments, the third conductive structure 1506 includes a mirror structure M6 and a barrier structure B6. In some embodiments, layer 1302 (e.g. Figure 13The third barrier layer (as shown) includes at least one of a third barrier layer or a third mirror layer. In some embodiments, forming layer 1302 includes (i) forming a third barrier layer and (ii) forming a third mirror layer over the third barrier layer. At least one of the third barrier layer or the third mirror layer is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin, growth, or other suitable techniques. In some embodiments, the barrier structure B6 includes a portion of the third barrier layer. In some embodiments, the mirror structure M6 includes a portion of the third mirror layer. In some embodiments, the thickness 2550 of the mirror structure M6 is greater than the thickness 2552 of the barrier structure B6. The thickness 2550 is between about 100 angstroms and about 500,000 angstroms. The thickness 2552 is between about 10 angstroms and about 100,000 angstroms. Other values ​​for thickness 2550 and thickness 2552 are within the scope of this disclosure.

[0204] The third mirror layer differs from the third barrier layer, for example, by having a different material composition, thus defining an interface between the third mirror layer and the third barrier layer. In some embodiments, the third mirror layer does not have a different material composition from the third barrier layer. However, since the third mirror layer and the third barrier layer are separate and non-equivalent layers, an interface is defined between them. In some embodiments, the reflectivity of the third mirror layer to visible light is greater than that of the third barrier layer to visible light. In some embodiments, the reflectivity of the third mirror layer to visible light is at least about 80%. In some embodiments, the third reflective mirror layer comprises a metal alloy, and the third barrier layer comprises a metal alloy. In some embodiments, the third mirror layer (and the mirror structure M6 formed by the third mirror layer) comprises at least one of tungsten (W), copper (Cu), aluminum (Al), aluminum-copper (AlCu), aluminum-silicon-copper (AlSiCu), or other suitable materials. In some embodiments, the third barrier layer (and the barrier structure B6 formed by the third barrier layer) comprises at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable materials. In some embodiments, the third barrier layer comprises an adhesive material.

[0205] In some embodiments, the carbon concentration per unit volume in the third mirror layer differs from the carbon concentration per unit volume in the third barrier layer. In some embodiments, the copper concentration per unit volume in the third mirror layer differs from the copper concentration per unit volume in the third barrier layer. In some embodiments, the aluminum concentration per unit volume in the third mirror layer differs from the aluminum concentration per unit volume in the third barrier layer. In some embodiments, the silicon concentration per unit volume in the third mirror layer differs from the silicon concentration per unit volume in the third barrier layer.

[0206] Figure 25B For illustrating a top view of semiconductor element 100, in which, according to some embodiments, (i) the electroluminescent structures of the electroluminescent structure assembly have a circular shape, or (ii) the reflective structures of the reflective structure assembly have a circular shape, at least one of these is provided. Figure 25C To illustrate a top view of the semiconductor element 100, in which, according to some embodiments, (i) the electroluminescent structure of the set of electroluminescent structures has a rectangular shape, or (ii) the reflective structure of the set of reflective structures has at least one of a rectangular shape. Figure 25D For illustration of a top view of semiconductor element 100, in which, according to some embodiments, (i) the electroluminescent structures of the group of electroluminescent structures have a triangular shape, or (ii) the reflective structures of the group of reflective structures have at least one of the triangular shapes. Other shapes of the group of electroluminescent structures and / or the group of reflective structures besides those shown and / or described herein are also within the scope of this disclosure.

[0207] Figure 26 A color filter layer 2602 is shown formed over the set of electroluminescent structures and / or the set of reflective structures according to some embodiments. The color filter layer 2602 is formed via at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. In some embodiments, the color filter layer 2602 includes a set of color filters comprising at least one of a first color filter 2604 covering the first electroluminescent structure 2402, a second color filter 2606 covering the second electroluminescent structure 2404, or a third color filter 2608 covering the third electroluminescent structure 2406. Although a color filter with three sets of color filters is described, any number of sets of color filters is contemplated.

[0208] Figure 27To illustrate various aspects of the operation of a semiconductor element 100 according to some embodiments. In some embodiments, a first interconnect element 130 is configured to establish a first electrical connection between a first organic light-emitting diode (OLED) cell 2424 and a first OLED driving circuit 120. In some embodiments, the first OLED driving circuit 120 drives the first OLED cell 2424 via the first electrical connection. In some embodiments, the first OLED driving circuit 120 supplies a first current 2702 to a first electroluminescent structure 2402 via a first electrical connection. In some embodiments, the first current 2702 flows through at least one of the first interconnect element 130 or the first reflective structure 2414 (e.g., at least one of the mirror structure M1 or the blocking structure B1) to the first electroluminescent structure 2402. In some embodiments, the first electroluminescent structure 2402 is configured to emit first light, such as white light, in response to the first current 2702. In some embodiments, the first electroluminescent structure 2402 emits the first light toward a first optical resonant structure 2202. In some embodiments, the first optical resonant structure 2202 includes at least one of a first transparent material (e.g., an oxide semiconductor material (e.g., silicon oxide), a nitride semiconductor material (e.g., silicon nitride), undoped silicate glass (USG), phosphosilicate glass (PSG), fluorosilicate glass (FSG), a low-k dielectric material, an ultra-low-k dielectric material, black diamond, or other suitable material) to establish a first optical path 2708 between the first reflective substrate 2414a and the first electroluminescent structure 2402. In some embodiments, the first transparent material is transparent to visible light. In some embodiments, the first light moves along the first optical path 2708. In some embodiments, at least some of the first light emitted from the first electroluminescent structure 2402 moves toward the first reflective substrate 2414a and is reflected back by the first reflective substrate 2414a toward at least one of the first electroluminescent structure 2402 or the first color filter 2604. At least a portion of the first light (e.g., light reflected by the first reflective base 2414a) passes through at least one of the first electroluminescent structure 2402 or the first color filter 2604 to generate first emitted light 2718 emitted by the semiconductor element 100.

[0209] In some embodiments, the first organic light-emitting diode unit 2424 is associated with a first color. In some embodiments, the distance D1 between the first reflective substrate 2414a and the first electroluminescent structure 2402 (e.g., ...) is... Figure 24A(As shown) Based on a first color. In some embodiments, the first optical resonant structure 2202 is configured to provide a first interference to the first light (e.g., traveling along the first optical path 2708) to process the first light to generate a second light or (ii) extract the second light from the first light. In some embodiments, the second light contains light having the first color. In some embodiments, the amount of light having the first color in the second light is greater than the amount of light having the first color in the first light, for example, at least in part due to the first interference provided by the first optical resonant structure 2202 to the first light. In some embodiments, the second light passes through a first color filter 2604. In some embodiments, the first color filter 2604 filters out the second light to generate a first emitted light 2718. In some embodiments, the first color filter 2604 filters wavelengths outside the wavelength range associated with the first color from the second light to generate the first emitted light 2718. In some embodiments, the amount of the first interference depends on a distance D1, and the distance D1 is controlled such that at least one of the first light, the second light, or the first emitted light 2718 has one or more desired colors (e.g., the first color). In some implementations, the first color is red or another suitable color.

[0210] In some embodiments, the second interconnect element 132 is configured to establish a second electrical connection between the second organic light-emitting diode (OLED) unit 2426 and the second OLED driving circuit 122. In some embodiments, the second OLED driving circuit 122 drives the second OLED unit 2426 via the second electrical connection. In some embodiments, the second OLED driving circuit 122 supplies a second current 2704 to the second electroluminescent structure 2404 via the second electrical connection. In some embodiments, the second current 2704 flows through at least one of the second interconnect element 132, the first conductive structure 906 (e.g., at least one of a mirror structure M4 or a blocking structure B4), or the second reflective structure 2416 (e.g., at least one of a mirror structure M2 or a blocking structure B2). In some embodiments, the second current 2704 flows through a conductive material of the first filling structure 902. Embodiments in which the first filling structure 902 comprises a non-conductive or low-conductivity material are conceivable. In some embodiments, the second electroluminescent structure 2404 is configured to emit a third light, such as white light, to the second current 2704. In some embodiments, the second electroluminescent structure 2404 emits third light toward the second optical resonant structure 2204. In some embodiments, the second optical resonant structure 2204 comprises at least one of a second transparent material (e.g., an oxide semiconductor material (e.g., silicon oxide), a nitride semiconductor material (e.g., silicon nitride), undoped silicate glass (USG), phosphosilicate glass (PSG), fluorosilicate glass (FSG), a low-k dielectric material, an extremely low-k dielectric material, black diamond, or other suitable materials) to establish a second optical path 2710 between the second reflective substrate 2416a and the second electroluminescent structure 2404. In some embodiments, the second transparent material is transparent to visible light. In some embodiments, the third light moves along the second optical path 2710. In some embodiments, at least some of the third light emitted from the second electroluminescent structure 2404 moves toward the second reflective substrate 2416a and is reflected back by the second reflective substrate 2416a toward at least one of the second electroluminescent structure 2404 or the second color filter 2606. At least a portion of the third light (e.g., light reflected by the second reflective base 2416a) passes through at least one of the second electroluminescent structure 2404 or the second color filter 2606 to generate a second emitted light 2720 emitted by the semiconductor element 100.

[0211] In some embodiments, the second organic light-emitting diode unit 2426 is associated with a second color. In some embodiments, the distance D2 between the second reflective substrate 2416a and the second electroluminescent structure 2404 (e.g., ...) Figure 24A(As shown) Based on the second color. In some embodiments, the distance D2 is less than the distance D1 associated with the first organic light-emitting diode unit 2424 (e.g., Figure 24A (As shown). In some embodiments, the second optical resonant structure 2204 is configured to provide a second interference to the third light (e.g., traveling along the second optical path 2710) to (i) process the third light to generate a fourth light or (ii) extract at least one of the fourth lights from the third light. In some embodiments, the fourth light comprises light having a second color. In some embodiments, the amount of light having the second color in the fourth light is greater than the amount of light having the second color in the third light, for example, at least in part due to the second interference provided by the second optical resonant structure 2204 to the third light. In some embodiments, the fourth light passes through a second color filter 2606. In some embodiments, the second color filter 2606 filters out the fourth light to generate a second emitted light 2720. In some embodiments, the second color filter 2606 filters wavelengths outside the wavelength range associated with the second color from the fourth light to generate the second emitted light 2720. In some embodiments, the amount of the second interference depends on a distance D2, and the distance D2 is controlled such that at least one of the third light, the fourth light, or the second emitted light 2720 has one or more desired colors (e.g., the second color). In some implementations, the second color is green or another suitable color.

[0212] In some embodiments, the third interconnect element 134 is configured to establish a third electrical connection between the third organic light-emitting diode (OLED) unit 2428 and the third OLED driving circuit 124. In some embodiments, the third OLED driving circuit 124 drives the third OLED unit 2428 via the third electrical connection. In some embodiments, the third OLED driving circuit 124 supplies a third current 2706 to the third electroluminescent structure 2406 via a third electrical connection. In some embodiments, the third current 2706 flows through at least one of the third interconnect element 134, the second conductive structure 908 (e.g., at least one of a mirror structure M5 or a blocking structure B5), the third conductive structure 1506 (e.g., at least one of a mirror structure M6 or a blocking structure B6), or the third reflective structure 2418 (e.g., at least one of a mirror structure M3 or a blocking structure B3). In some embodiments, the third current 2706 flows through at least one of the conductive material of the second filling structure 904 or the conductive material of the third filling structure 1502. In some embodiments, at least one of the second filling structures 904 comprises a non-conductive or low-conductive material, or the third filling structure 1502 comprises a non-conductive or low-conductive material. In some embodiments, the third electroluminescent structure 2406 is configured to emit a fifth light, such as white light, in response to a third current 2706. In some embodiments, the third electroluminescent structure 2406 emits the fifth light toward the third optical resonant structure 2206. In some embodiments, the third optical resonant structure 2206 comprises at least one of a third transparent material (e.g., an oxide semiconductor material (e.g., silicon oxide), a nitride semiconductor material (e.g., silicon nitride), undoped silicate glass (USG), phosphosilicate glass (PSG), fluorosilicate glass (FSG), a low-k dielectric material, an extremely low-k dielectric material, black diamond, or other suitable material) to establish a third optical path 2712 between the third reflective substrate 2418a and the third electroluminescent structure 2406. In some embodiments, the third transparent material is transparent to visible light. In some embodiments, the fifth light moves along the third optical path 2712. In some embodiments, at least some of the fifth light emitted from the third electroluminescent structure 2406 moves toward the third reflective base 2418a and is reflected back by the third reflective base 2418a toward at least one of the third electroluminescent structure 2406 or the third color filter 2608. At least a portion of the fifth light (e.g., reflected by the third reflective base 2418a) passes through at least one of the third electroluminescent structure 2406 or the third color filter 2608 to generate third emitted light 2722 emitted by the semiconductor element 100.

[0213] In some embodiments, the third organic light-emitting diode unit 2428 is associated with a third color. In some embodiments, the distance D3 between the third reflective substrate 2418a and the third electroluminescent structure 2406 (e.g., ...) is... Figure 24A (As shown) Based on a third color. In some embodiments, the distance D3 is less than (i) the distance D1 associated with the first organic light-emitting diode unit 2424 (e.g. Figure 24A (as shown) or (ii) the distance D2 associated with the second organic light-emitting diode unit 2426 (e.g. Figure 24A At least one of the following (shown). In some embodiments, the third optical resonant structure 2206 is configured to provide a third interference to the fifth light (e.g., traveling along the third optical path 2712) to (i) process the fifth light to generate a sixth light or (ii) extract at least one of the sixth lights from the fifth light. In some embodiments, the sixth light contains light having a third color. In some embodiments, the amount of light having a third color in the sixth light is greater than the amount of light having a third color in the fifth light, for example, at least in part due to the third interference provided to the fifth light by the third optical resonant structure 2206. In some embodiments, the sixth light passes through a third color filter 2608. In some embodiments, the third color filter 2608 filters out the sixth light to generate a third emitted light 2722. In some embodiments, the third color filter 2608 filters wavelengths outside the wavelength range associated with the third color from the sixth light to generate the third emitted light 2722. In some embodiments, the amount of the third interference depends on the distance D3, and the distance D3 is controlled such that at least one of the fifth, sixth, or third emitted light 2722 has one or more desired colors (e.g., the third color). In some embodiments, the third color is blue or another suitable color.

[0214] In some embodiments, the semiconductor element 100 includes a near-eye display (NED), such as an organic light-emitting diode near-eye display panel. In some embodiments, the distance D7 between the semiconductor element 100 and the user's eyes (e.g., ...) Figure 27 (As shown) less than a first threshold distance associated with near-eye display technology. In some embodiments, the semiconductor element 100 is part of a wearable device (e.g., headphones) worn by a user, such that the semiconductor element 100 is positioned toward the user's eyes. In some embodiments, the semiconductor element 100 provides at least one of immersive experiences, extended reality experiences, mixed reality experiences, etc.

[0215] In some embodiments, the elevation y1 of the first reflective base 2414a is different from (e.g., lower than) the elevation y2 of the second reflective base 2416a. In some embodiments, the elevation difference between the first reflective base 2414a and the second reflective base 2416a is less than the elevation difference between the first electroluminescent structure 2402 (e.g., elevation y4) and the second electroluminescent structure 2404 (e.g., elevation y4). In some embodiments, the elevation y2 of the second reflective base 2416a is different from (e.g., lower than) the elevation y3 of the third reflective base 2418a. In some embodiments, the elevation difference between the elevation y2 of the second reflective base 2416a and the elevation y3 of the third reflective base 2418a is less than the elevation difference between the elevation of the second electroluminescent structure 2404 (e.g., elevation y4) and the elevation of the third electroluminescent structure 2406 (e.g., elevation y4).

[0216] In some embodiments, the first pixel of the semiconductor element 100 includes at least one of a first organic light-emitting diode (OLED) unit 2424 (e.g., a red sub-pixel), a second OLED unit 2426 (e.g., a green sub-pixel), or a third OLED unit 2428 (e.g., a blue sub-pixel). In some embodiments, the semiconductor element 100 includes a plurality of pixels arranged in a pixel array. In some embodiments, some or all of each of the plurality of pixels includes one or more OLED units, said OLED units including OLED units configured to emit light having a first color (e.g., red), OLED units configured to emit light having a second color (e.g., green), or OLED units configured to emit light having a third color (e.g., blue), wherein the one or more OLED units are formed using one or more techniques provided herein for forming the first OLED unit 2424, the second OLED unit 2426, and / or the third OLED unit 2428. The pixel width D4 of the first pixel (e.g., ...) Figures 24A to 24D and Figures 25A to 25D (As shown) is between approximately 10 micrometers and approximately 100 micrometers, for example, approximately 50 micrometers. The pixel length D5 of the first pixel (as shown) Figures 24B to 24D and Figures 25B to 25D (As shown) values ​​range from approximately 10 micrometers to approximately 100 micrometers, for example, approximately 50 micrometers. Other values ​​for pixel width D4 and pixel length D5 are within the scope of this disclosure.

[0217] In some embodiments, the semiconductor element 100 includes a first set of organic light-emitting diode (OLED) units associated with a first color. In some embodiments, the first set of OLED units includes a first OLED unit 2424. In some embodiments, each of the first set of OLED units is configured to emit light having a first color (e.g., red). In some embodiments, the reflective bases (e.g., a first reflective base 2414a) of some or all of the OLED units in the first set of OLED units are coplanar.

[0218] In some embodiments, the semiconductor element 100 includes a second group of organic light-emitting diode (OLED) units associated with a second color. In some embodiments, the second group of OLED units includes a second OLED unit 2426. In some embodiments, each of the second group of OLED units is configured to emit light having a second color (e.g., green). In some embodiments, the reflective bases (e.g., the second reflective base 2416a) of some or all of the OLED units in the second group are coplanar.

[0219] In some embodiments, semiconductor element 100 includes a third organic light-emitting diode (OLED) unit associated with a third color. In some embodiments, the third group of OLED units includes a third OLED unit 2428. In some embodiments, each of the third group of OLED units is configured to emit light having a third color (e.g., blue). In some embodiments, the reflective bases (e.g., third reflective base 2418a) of some or all of the OLED units in the third group are coplanar.

[0220] In some embodiments, the benefits provided by this disclosure include, but are not limited to, at least one of the following: (i) improved uniformity of the thickness of the electroluminescent structure; (ii) increased uniformity of light emitted by the organic light-emitting diode units and / or primitives of the semiconductor element 100; (iii) increased predictability of the display performance of the semiconductor element 100; and (iv) faster semiconductor element manufacturing speed. In some embodiments, at least part of the advantages are due to at least one of: (i) patterning and / or performing a planarization process on the electroluminescent layer 2302 to produce the set of electroluminescent structures; and (ii) the coplanarity of the electroluminescent structures of the set of electroluminescent structures.

[0221] In some embodiments, a semiconductor device is provided. The semiconductor device includes a first organic light-emitting diode (OLED) unit and a second OLED unit. The first OLED unit includes a first reflective substrate, a first electroluminescent structure above the first reflective substrate, and a first optical resonant structure between the first electroluminescent structure and the first reflective substrate. The second OLED unit includes a second reflective substrate, a second electroluminescent structure above the second reflective substrate, and a second optical resonant structure between the second electroluminescent structure and the second reflective substrate, wherein the elevation of the first reflective substrate is different from the elevation of the second reflective substrate.

[0222] In some embodiments, the difference between the elevation of the first reflective base and the elevation of the second reflective base is less than the difference between the elevation of the first electroluminescent structure and the elevation of the second electroluminescent structure.

[0223] In some embodiments, the semiconductor element further includes a first interconnect element and a second interconnect element. The first interconnect element is configured to establish an electrical connection between a first organic light-emitting diode unit and at least one of a first transistor or a first capacitor. The second interconnect element is configured to establish an electrical connection between a second organic light-emitting diode unit and at least one of a second transistor or a second capacitor.

[0224] In some embodiments, the distance between the first reflective base and the first electroluminescent structure is greater than the distance between the second reflective base and the second electroluminescent structure.

[0225] In some embodiments, a first organic light-emitting diode (OLED) unit is configured to generate light having a first color. A second OLED unit is configured to generate light having a second color different from the first color.

[0226] In some embodiments, the distance between the first reflective substrate and the first electroluminescent structure is based on a first color. The distance between the second reflective substrate and the second electroluminescent structure is based on a second color.

[0227] In some embodiments, the semiconductor element further includes a third organic light-emitting diode (OLED) unit. The third OLED unit includes a third reflective substrate, a third electroluminescent structure, and a third optical resonant structure. The third electroluminescent structure is located above the third reflective substrate. The third optical resonant structure is located between the third electroluminescent structure and the third reflective substrate, wherein the elevation of the third reflective substrate differs from the elevations of the first and second reflective substrates.

[0228] In some implementations, at least one of them is: the first color corresponds to red, the second color corresponds to green, or the third color corresponds to blue.

[0229] In some implementations, the distance between the third reflective substrate and the third electroluminescent structure is based on a third color.

[0230] In some embodiments, the first optical resonant structure includes a first transparent material to establish a first optical path between the first reflective substrate and the first electroluminescent structure. The second optical resonant structure includes a second transparent material to establish a second optical path between the second reflective substrate and the second electroluminescent structure.

[0231] In some embodiments, a method for forming a semiconductor device is provided. The method includes forming one or more dielectric layers over an interconnect layer. The method includes forming a first trench and a second trench in the one or more dielectric layers. The method includes forming a first reflective base for an organic light-emitting diode (OLED) cell in the first trench. The method includes forming a second reflective base for an OLED cell in the second trench. The elevation of the first reflective base is different from the elevation of the second reflective base.

[0232] In some embodiments, forming the first trench and the second trench includes forming the first trench and the second trench such that the elevation of the first base of the first trench is different from the elevation of the second base of the second trench.

[0233] In some embodiments, a first optical resonant structure of a first organic light-emitting diode (OLED) unit is formed in a first trench above a first reflective substrate. A second optical resonant structure of a second OLED unit is formed in a second trench above a second reflective substrate.

[0234] In some embodiments, the method includes forming an electroluminescent layer over one or more dielectric layers and patterning the electroluminescent layer to: form a first electroluminescent structure with a first organic light-emitting diode unit over a first optical resonant structure and a second electroluminescent structure with a second organic light-emitting diode unit over a second optical resonant structure.

[0235] In some embodiments, patterning the electroluminescent layer includes patterning the electroluminescent layer such that the first electroluminescent structure and the second electroluminescent structure are coplanar.

[0236] In some embodiments, forming a first trench includes forming a first trench over a first interconnect element in the interconnect layer, wherein the first interconnect element is configured to establish an electrical connection between a first organic light-emitting diode cell and at least one of a first transistor or a first capacitor. Forming a second trench includes forming a second trench over a second interconnect element in the interconnect layer, wherein the second interconnect element is configured to establish an electrical connection between a second organic light-emitting diode cell and at least one of a second transistor or a second capacitor.

[0237] In some embodiments, patterning the electroluminescent layer includes: forming a first electroluminescent structure at a first distance from a first reflective substrate, wherein the first distance is based on a first color associated with a first organic light-emitting diode unit; and forming a second electroluminescent structure at a second distance from a second reflective substrate, wherein the second distance is based on a second color associated with a second organic light-emitting diode unit.

[0238] In some embodiments, a third reflective base is included, which forms a third trench in one or more dielectric layers and a third organic light-emitting diode unit in the third trench, wherein the elevation of the second reflective base is different from the elevation of the third reflective base.

[0239] In some embodiments, a semiconductor device is provided. The semiconductor device includes a first organic light-emitting diode (OLED) unit configured to generate light having a first color and a second OLED unit configured to generate light having a second color different from the first color. The first OLED unit includes a first optical resonant structure and a first electroluminescent structure above the first optical resonant structure. The second OLED unit includes a second optical resonant structure and a second electroluminescent structure above the second optical resonant structure. The first electroluminescent structure and the second electroluminescent structure are coplanar.

[0240] In some embodiments, the first organic light-emitting diode (OLED) unit includes a first reflective base. The second OLED unit includes a second reflective base. The elevation of the first reflective base is different from the elevation of the second reflective base.

[0241] In some embodiments, a semiconductor device is provided. The semiconductor device includes a first organic light-emitting diode (OLED) unit and a second OLED unit. The first OLED unit includes a first reflective substrate, a first optical resonant structure, and a first electroluminescent structure. The first electroluminescent structure is located above the first optical resonant structure. The second OLED unit includes a second reflective substrate, a second optical resonant structure, and a second electroluminescent structure. The second electroluminescent structure is located above the second optical resonant structure. The elevations of the first and second reflective substrates are different, and the first and second electroluminescent structures are coplanar.

[0242] In some embodiments, the distance between the first reflective base and the first electroluminescent structure is different from the distance between the second reflective base and the second electroluminescent structure.

[0243] In some embodiments, a semiconductor device is provided. The semiconductor device includes a first organic light-emitting diode (OLED) unit and a second OLED unit. The first OLED unit includes a first reflective substrate and a first electroluminescent structure. The first electroluminescent structure is located above the first reflective substrate. The second OLED unit includes a second reflective substrate and a second electroluminescent structure. The second electroluminescent structure is located above the second reflective substrate. The elevation of the first reflective substrate is different from the elevation of the second reflective substrate, and the distance between the first reflective substrate and the first electroluminescent structure is different from the distance between the second reflective substrate and the second electroluminescent structure.

[0244] In some embodiments, the semiconductor element further includes a third organic light-emitting diode (OLED) unit. The third OLED unit includes a third reflective substrate and a third electroluminescent structure. The third electroluminescent structure is located above the third reflective substrate. The elevation of the third reflective substrate differs from the elevations of the first and second reflective substrates.

[0245] In some embodiments, the distance between the third reflective base and the third electroluminescent structure is different from the distance between the first reflective base and the first electroluminescent structure and the distance between the second reflective base and the second electroluminescent structure.

[0246] Although the subject matter has been described in language specific to structural features or methodological behavior, it should be understood that the subject matter of the appended patent claims is not necessarily limited to the specific features or behaviors described above. Rather, the specific features and behaviors described above are disclosed as embodiments that implement at least a portion of the patent claims.

[0247] This disclosure provides various operations for each implementation. The order in which some or all of the operations are described should not be construed as implying that these operations are necessarily dependent on the order. Alternative orderings will be understood to have the benefits of this description. Furthermore, it is understood that not all operations are necessarily present in all the implementations provided in this disclosure. Moreover, it is understood that not all operations are necessary in some implementations.

[0248] It is understood that the layers, features, elements, etc., described in this disclosure have specific dimensions relative to each other, such as structural dimensions or orientations, for example, for the purpose of simplification and ease of understanding, and in some embodiments, the same actual dimensions may differ significantly from the dimensions described in this disclosure. Furthermore, various techniques exist for forming the layers, regions, features, elements, etc., mentioned in this disclosure, such as at least one etching technique, planarization technique, implantation technique, doping technique, spin-dipation technique, sputtering technique, growth technique, or deposition technique, such as chemical vapor deposition (CVD).

[0249] Furthermore, the terms "exemplary" and / or similar terms used herein are intended to refer to embodiments, examples, illustrations, etc., and are not necessarily advantageous. As used in this application, "or" means inclusive "or" rather than exclusive "or". Furthermore, the word "a" as used in this application and the appended claims is generally interpreted as "one or more" unless otherwise stated or clearly indicated from the context as referring to the singular form. Additionally, within the scope of use of "comprising," "having," or variations thereof, such terms are intended to indicate inclusion in a manner similar to the term "comprising". Furthermore, unless otherwise stated, "first," "second," or similar terms do not refer to temporal, spatial, or sequential aspects. Rather, such terms are used only for identifiers, names, etc., of features, elements, items, etc. For example, a first element and a second element typically correspond to element A and element B, or two different or two identical elements, or the same element.

[0250] Furthermore, although this disclosure has been shown and described with respect to one or more implementations, equivalent changes and modifications will occur to those skilled in the art based on their reading and understanding of this specification and drawings. This disclosure includes all such modifications and variations and is limited only to the scope of the following patent claims. In particular, regarding the various functions performed by the foregoing elements (e.g., elements, resources, etc.), unless otherwise stated, the vocabulary used to describe such elements is intended to correspond to any element performing the specified function of said element (e.g., functionally equivalent elements), even if structurally not equivalent to the disclosed structure. Moreover, although a particular feature of this disclosure may be disclosed only in one of several implementations, that feature may be combined with one or more other features of other implementations, as that feature may be necessary and advantageous for any given or particular application.

Claims

1. A semiconductor element characterized by comprising: Include: A first organic light-emitting diode unit, comprising: First reflecting base; A first electroluminescent structure, above the first reflective base; and A first optical resonant structure is located between the first electroluminescent structure and the first reflective base; as well as A second organic light-emitting diode unit, comprising: A second reflector base; A second electroluminescent structure, above the second reflective base; and A second optical resonant structure is provided between the second electroluminescent structure and the second reflective base, wherein an elevation of the first reflective base is different from an elevation of the second reflective base.

2. The semiconductor device according to claim 1, wherein in: The difference between the elevation of the first reflective base and the elevation of the second reflective base is less than the difference between the elevation of the first electroluminescent structure and the elevation of the second electroluminescent structure.

3. The semiconductor device according to claim 1, wherein Further includes: A first interconnecting element, electrically connected between the first organic light-emitting diode unit and at least one of a first transistor or a first capacitor; and A second interconnecting element is electrically connected between the second organic light-emitting diode unit and at least one of a second transistor or a second capacitor.

4. The semiconductor device according to claim 1, wherein in: The distance between the first reflective base and the first electroluminescent structure is greater than the distance between the second reflective base and the second electroluminescent structure.

5. The semiconductor device according to claim 1, wherein Further includes: A third organic light-emitting diode unit, comprising: A third reflector base; A third electroluminescent structure, above the third reflective base; and A third optical resonance structure is provided between the third electroluminescent structure and the third reflective base, wherein an elevation of the third reflective base is different from the elevation of the first reflective base and the elevation of the second reflective base.

6. A semiconductor element characterized by comprising: Include: A first organic light-emitting diode unit, comprising: First reflecting base; A first optical resonance structure; and A first electroluminescent structure, above the first optical resonant structure; and A second organic light-emitting diode unit, comprising: A second reflector base; A second optical resonance structure; and A second electroluminescent structure is located above the second optical resonant structure, wherein an elevation of the first reflective base is different from an elevation of the second reflective base, and the first electroluminescent structure and the second electroluminescent structure are coplanar.

7. The semiconductor device according to claim 6, wherein The distance between the first reflective base and the first electroluminescent structure is different from the distance between the second reflective base and the second electroluminescent structure.

8. A semiconductor element characterized by comprising: Include: A first organic light-emitting diode unit, comprising: A first reflecting base; and A first electroluminescent structure, above the first reflective base; and A second organic light-emitting diode unit, comprising: A second reflector base; and A second electroluminescent structure is located above the second reflective base, wherein an elevation of the first reflective base is different from an elevation of the second reflective base, and a distance between the first reflective base and the first electroluminescent structure is different from a distance between the second reflective base and the second electroluminescent structure.

9. The semiconductor device according to claim 8, wherein Further includes: A third organic light-emitting diode unit, comprising: A third reflector base; and A third electroluminescent structure is located above the third reflective base, wherein an elevation of the third reflective base is different from the elevation of the first reflective base and the elevation of the second reflective base.

10. The semiconductor device according to claim 9, wherein The distance between the third reflective base and the third electroluminescent structure is different from the distance between the first reflective base and the first electroluminescent structure and the distance between the second reflective base and the second electroluminescent structure.

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