A QFN frame structure

Abstract

The QFN frame structure of the utility model discloses includes pad, chip operation area and pin array. The edge of pad is periodic concave-convex structure. Chip operation area is located in the central region of pad, and the shape of chip operation area is square, and the length of the side length of chip operation area is greater than 3.0mm. Pin array is set up in the outer edge of pad. The QFN frame structure of the application can solve the miniaturization demand problem, through the periodic concave-convex structure of the edge of pad, not only can reduce stress concentration, alleviate delamination risk, simultaneously, under the premise of not increasing the size of package, increase the operation space of chip, this means that in the same space, can handle larger chip, greatly improve the operation efficiency, save time and resources.

Description

Technical Field

[0001] This utility model relates to the field of electronic packaging technology, specifically to a QFN frame structure. Background Technology

[0002] In the field of microelectromechanical systems (MEMS) technology, semiconductor packaging technology plays an indispensable role. MEMS technology integrates micro-mechanical devices and electronic circuits onto a single chip. This highly integrated design has enabled the widespread application of MEMS devices in sensors, actuators, and other micro-mechanical systems. Semiconductor packaging technology also plays a crucial role in precision engineering. Precision engineering involves high-precision manufacturing and assembly technologies, including micron and nanometer-level manufacturing processes. With continuous technological advancements, electronic devices are evolving towards smaller, lighter, thinner, and smarter designs, demanding that semiconductor packaging technology achieve even higher precision chip packaging.

[0003] However, frame delamination is a common problem in semiconductor packaging, severely impacting packaging quality and reliability. Frame delamination refers to the separation of the adhesive layer between the package frame and the chip or substrate. This separation can be caused by various factors, including mismatches in the thermal expansion coefficients of the packaging materials, mechanical stress during the packaging process, and changes in humidity and temperature in the packaging environment. These factors work together to lead to delamination. This phenomenon not only affects packaging reliability, making the package structure more susceptible to loosening and cracking under external forces, temperature changes, or humidity influences, but can also lead to a decline in chip performance. For example, in high-frequency circuits, frame delamination can cause signal instability, increase signal attenuation and distortion, and affect the signal quality and transmission distance of communication equipment. In high-power chips, frame delamination can lead to poor heat dissipation, causing excessively high chip temperatures, which in turn affects chip performance and lifespan, and may even lead to complete chip failure, resulting in significant economic losses. Therefore, solving the frame delamination problem is crucial for improving semiconductor packaging quality and reliability. Meanwhile, the current market demand for Saw-type QFN frame packages shows a clear trend towards miniaturization. Taking the QFN frame structure as an example, its package size requirements have gradually shrunk from the traditional large size to 5mm×5mm or even smaller. However, current technologies cannot simultaneously prevent delamination and increase the chip's operating space. This makes ensuring package reliability while meeting the demand for large chip size during miniaturization a pressing problem that needs to be solved. Utility Model Content

[0004] In view of the problems existing in the prior art described above, this application provides a QFN frame structure that can prevent frame layering while increasing the chip operating space.

[0005] To achieve the above and other related objectives, this utility model provides a QFN frame structure, comprising:

[0006] The pads have a periodic uneven structure at their edges;

[0007] The chip working area is located in the center of the pads. The chip working area is square in shape, and the side length of the chip working area is greater than 3.0mm.

[0008] A pin array is arranged around the outer edge of the pad.

[0009] Optionally, the periodic protrusion structure is located on the wire bonding area of ​​the pad.

[0010] Optionally, the side length of the chip working area is between 3.1mm and 3.3mm.

[0011] Optionally, the QFN framework structure also includes a chip, which is located in the chip operating area.

[0012] Optionally, the periodic protrusion structure includes alternating protrusions and grooves.

[0013] Optionally, the protrusions of the periodic protrusion structure are trapezoidal protrusions.

[0014] Optionally, the upper bottom width of the periodic protrusion structure is between 0.20mm and 0.30mm, the lower bottom width is between 0.25mm and 0.35mm, and the height is between 0.10mm and 0.20mm.

[0015] Optionally, the bumps and grooves are evenly distributed around the perimeter of the chip working area.

[0016] Optionally, the shortest distance between the chip working area and the wire bonding area on the pad is between 0.2mm and 0.35mm.

[0017] Optionally, the periodic protrusion structure is a wave-shaped structure.

[0018] As described above, the QFN frame structure provided by this utility model has at least the following beneficial technical effects:

[0019] The QFN frame structure of this invention includes pads, a chip working area, and a pin array. The edges of the pads have a periodic concave-convex structure. The chip working area is located in the central region of the pads, and is square in shape with a side length greater than 3mm. This size design ensures sufficient space for chip installation and operation, while also accommodating chip requirements of different sizes. The pin array is arranged around the outer edge of the pads. It is used to realize the electrical connection between the chip and external circuits. This surrounding pin design improves packaging flexibility and connection efficiency.

[0020] The QFN framework structure proposed in this application effectively solves the miniaturization challenge. In modern electronic devices, as device size continues to shrink, the requirements for chip package dimensions are becoming increasingly stringent. This application achieves package optimization within a limited space by designing the pad edges as a periodic bump-and-recess structure. This periodic bump-and-recess structure not only mitigates delamination risks and improves package reliability and stability but also increases the chip's working space. This means that larger chips can be processed within the same space, significantly improving operational efficiency and saving time and resources. This is of great significance for improving production efficiency and reducing production costs, and also provides strong support for the miniaturization and high performance of electronic devices. Attached Figure Description

[0021] Figure 1 The diagram shown is a structural schematic of a QFN frame structure provided in an embodiment of this utility model.

[0022] Figure 2 The diagram shown is a structural schematic of a QFN frame structure provided in another embodiment of this utility model.

[0023] Figure 3 The diagram shown is a structural schematic of the QFN frame structure provided in another embodiment of this utility model.

[0024] Figure Labels

[0025] 1. Pad; 11. Chip working area; 12. Wire bonding area; 2. Periodic bump structure; 21. Bump; 22. Groove; 3. Pin array; 31. Pin; 4. Chip. Detailed Implementation

[0026] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model.

[0027] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this utility model. Although the illustrations only show components related to this utility model and are not drawn according to the actual number, shape and size of the components, the shape, quantity, positional relationship and proportion of each component can be arbitrarily changed under the premise of realizing the technical solution of this utility model, and the layout of the components may also be more complex.

[0028] This embodiment provides a QFN framework structure, referencing... Figures 1 to 3 It includes pad 1, chip work area 11 and pin array 3.

[0029] The edge of the pad 2 has a periodic raised / lowered structure 2. Optionally, the periodic raised / lowered structure 2 includes alternating protrusions 21 and grooves 22. The protrusions 21 and grooves 22 are evenly distributed around the perimeter of the chip working area 11. During the packaging process, the molding compound flows into the grooves 22, significantly increasing the contact area between the molding compound and the pad 2, thereby greatly reducing the probability of delamination between the pad 2 and the molding compound. In addition, by changing the shape of the edge of the pad 2, stress is dispersed among multiple small protrusions 21 and grooves 22, thereby reducing stress concentration and mitigating the risk of delamination. This periodic raised / lowered structure 2 design effectively improves the reliability and stability of the package. Compared with the traditional slot design, it can more effectively reduce stress concentration and mitigate the risk of delamination. The traditional slot design improves delamination by hollowing out the surface of the pad, but its space limitations are obvious in scenarios with small frame sizes and large chip sizes. The design of the periodic bump structure 2 breaks through this limitation. While achieving the anti-delamination effect, it can adapt to larger chip sizes. Through this design of the periodic bump structure 2, the reliability and stability of the package are effectively improved.

[0030] Optionally, refer to Figure 1The periodic raised and recessed structure 2 has 211 trapezoidal raised protrusions. The upper base width of the trapezoidal raised protrusion is between 0.20mm and 0.30mm, the lower base width is between 0.25mm and 0.35mm, and the height is between 0.10mm and 0.20mm. The spacing between adjacent raised protrusions 21 is between 0.30mm and 0.50mm. This size design is optimized so that the molding compound can better fill the groove 22 during the encapsulation process, while the raised protrusions 21 can also provide sufficient support to prevent excessive flow of the molding compound. In an optional embodiment of this example, the upper base width of the trapezoidal raised protrusion is 0.25mm, the lower base width is 0.30mm, and the height is 0.15mm. The spacing between adjacent raised protrusions 21 is 0.40mm. By designing the edge of the pad 1 as a periodic raised and recessed structure 2, stress concentration can be effectively reduced. Stress concentration is an important factor leading to the failure of the encapsulation structure, especially in miniaturized packaging, where this problem is more prominent. By reducing stress concentration, the reliability and lifespan of the package can be significantly improved. Simultaneously, compared to traditional slot designs, this design increases the maximum usable chip size with the same pad size. For example, with a 5.0mm × 5.0mm frame size, the maximum usable chip size with a traditional slot design is 3.0mm × 3.0mm, while with the periodic bump structure design, the maximum usable chip size can reach 3.2mm × 3.2mm. The chip size to package size ratio also increases from 77% to 82%, allowing for the processing of larger chips within the same space, greatly improving operational efficiency and saving time and resources. This design also demonstrates excellent adaptability in actual packaging processes. Due to the regularity and uniformity of the periodic bump structure, both the injection of molding compound and the subsequent curing process can proceed smoothly during packaging. This design not only improves packaging reliability but also increases production efficiency. The regularity and uniformity of the periodic bump structure ensures uniform distribution of molding compound during injection, reducing the formation of bubbles and voids, thereby improving packaging quality. During the curing process, this design also ensures uniform curing of the molding compound, further improving the stability and reliability of the encapsulation. The design of the periodic concave-convex structure 2 is not only technically innovative, but also has wide applicability and significant advantages in practical applications.

[0031] The periodic bump structure 2 offers design flexibility, allowing for various shapes to suit different packaging needs and process requirements. (Refer to...) Figure 3The periodic bump and recess structure 2 can also be designed as a wave-like structure. A wave-like structure is characterized by continuous peaks and troughs at its edges. This design creates a series of undulations at the edges of the pad 2, resembling a wave shape. The bumps and recesses of the wave-like structure can be smooth curves. This design helps guide material flow during molding compound injection, reducing material buildup at the edges, thereby improving the uniformity and reliability of the package. Simultaneously, the continuity of the wave-like structure also helps disperse stress, reducing stress concentration points and further improving the stability of the package structure. Additionally, refer to... Figure 2 The protrusions 21 of the periodic bump structure 2 can also be designed as rectangular protrusions. Rectangular protrusions are characterized by right angles at their edges, forming a series of regular rectangular protrusions. This design is relatively easy to implement during manufacturing because it does not require complex mold processing. Rectangular protrusions can provide a larger contact area, helping to enhance the adhesion between the pads 2 and the molding compound, thereby reducing the risk of delamination. Furthermore, the regular arrangement of the rectangular protrusions also helps to maintain a uniform distribution of material during the encapsulation process, ensuring that the molding compound can fully fill each groove, improving the overall quality of the encapsulation. These different designs of the periodic bump structure 2 can be selected and optimized according to specific encapsulation requirements and process conditions. Their common goal is to improve encapsulation reliability, reduce stress concentration, adapt to the needs of miniaturized encapsulation, and ensure uniform distribution of the molding compound during the encapsulation process, thereby improving the overall performance and quality of the encapsulation. Besides wavy and rectangular protrusion structures, the periodic bump structure 2 can also adopt various other shape designs, as long as it achieves the effect of preventing delamination; the specific shape of the periodic bump structure 2 is not limited. With these flexible design options, the QFN frame structure can better meet the market's demand for high performance, high reliability, and miniaturized packaging.

[0032] Reference Figure 1 The periodic bump structure 2 is located on the wire bonding area 12 of the pad 1. This ensures that the wire bonding process can proceed smoothly during packaging. The wire bonding area 12 is a critical area for the connection between the chip 4 and external circuitry, and the periodic bump structure 2 of the pad 2 is located precisely in this area, providing a stable platform for wire bonding. This design not only ensures the reliability of the electrical connection but also improves the overall quality of the package.

[0033] Reference Figure 1The chip working area 11 is located in the central region of pad 1 and is the core part of the entire QFN frame structure. The chip working area 11 is square in shape, with a side length greater than 3mm. Further, the side length of the chip working area 11 is between 3.1mm and 3.3mm. This size design ensures that the chip working area 11 can accommodate chips 4 of different sizes while maintaining sufficient space for the layout of other packaged components, improving the flexibility of the entire QFN frame structure. Taking a 5.0mm × 5.0mm package size as an example, the traditional slot design results in a working size of only 3.0mm × 3.0mm for the chip 4, while the size of the chip working area 11 in this design breaks through this limitation. In an optional embodiment, the working size of chip 4 is 3.2mm × 3.2mm, which significantly increases the working size compared to the maximum chip working size of 3.0mm × 3.0mm under the traditional slot design. This results in a higher chip size to package size ratio from 77% to 82% within the same 3.9mm × 3.9mm pad 1, allowing for the assembly of a larger chip 4 within a limited package space and improving space utilization. Chip 4 is fixed to the chip working area 11 using a high-precision mounting process, ensuring good contact and electrical connection between chip 4 and the chip working area 11, providing a solid foundation for stable chip operation. In an optional embodiment of this example, the side length of the chip working area 11 is 3.2mm. Furthermore, the shortest distance d between the chip working area 11 and the wire bonding area 12 on the pad 1 is also a key design parameter. The shortest distance d between the chip working area 11 and the wire bonding area 12 on the pad 1 is between 0.2mm and 0.35mm. In an optional embodiment of this example, the shortest distance d between the chip working area 11 and the wire bonding area 12 on the pad 1 is 0.279 mm. This distance is set to take into account the requirements of the wire bonding process and the stability of the packaging structure, ensuring that the wire bonding process can be carried out smoothly during the packaging process, while avoiding the risk of short circuits caused by excessive distance, thus improving the reliability and safety of the packaging.

[0034] Reference Figure 1Pin array 3 is arranged around the outer edge of pad 2. Connection to external circuits is achieved through pins 31. The design of pin 31 is a crucial part of the entire package structure. Pin 31 design must not only meet electrical performance requirements but also possess sufficient mechanical strength to ensure stable electrical connections in high-density packaging. In terms of electrical performance, pin 31 design must ensure low-resistance and low-inductance connections, which are essential for high-frequency and high-speed signal transmission. Regarding mechanical strength, pin 31 design must consider various mechanical stresses during the packaging process, including soldering stress, thermal expansion stress, and mechanical shock. In different application scenarios, the layout and size of pin 31 can be adjusted according to specific packaging requirements. For example, in some high-density packaging applications, the pin spacing of pin 31 may be smaller to accommodate a more compact package structure. In applications with high heat dissipation requirements, the pin 31 design may consider increasing the heat dissipation area to improve the package's heat dissipation performance.

[0035] Reference Figures 1 to 3 The QFN frame structure of this application, by designing the pad edges as a periodic concave-convex structure 2, allows stress to be evenly distributed among multiple small protrusions 21 and grooves 22, thereby significantly reducing the risk of stress concentration. It also allows the molding compound to better fill the grooves 22 during injection, while the protrusions 21 provide sufficient support to prevent excessive flow of the molding compound. This significantly improves the adhesion between the pad 1 and the molding compound, thereby greatly reducing the possibility of delamination. Furthermore, by optimizing the shape of the pad 2 edges, the QFN frame structure of this application effectively increases the working space for the chip 4 without increasing the package size. This means that a larger chip 4 can be processed within the same space, thereby greatly improving operating efficiency and saving time and resources.

[0036] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit the scope of this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model.

Claims

1. A QFN frame structure, characterized in that, include: The pads have a periodic concave-convex structure at their edges; The chip working area is located in the center of the pads. The chip working area is square in shape, and the side length of the chip working area is greater than 3.0 mm. A pin array is arranged around the outer edge of the pad.

2. The QFN frame structure according to claim 1, characterized in that, The periodic protrusion structure is located on the bonding area of ​​the pad.

3. The QFN frame structure according to claim 1, characterized in that, The side length of the chip working area is between 3.1mm and 3.3mm.

4. The QFN frame structure according to claim 1, characterized in that, Also includes: A chip is disposed in the chip operating area.

5. The QFN frame structure according to claim 1, characterized in that, The periodic protrusion structure includes alternating protrusions and grooves.

6. The QFN frame structure according to claim 5, characterized in that, The protrusions of the periodic protrusion structure are trapezoidal protrusions.

7. The QFN frame structure according to claim 6, characterized in that, The upper base width of the periodic protrusion structure is between 0.20mm and 0.30mm, the lower base width is between 0.25mm and 0.35mm, and the height is between 0.10mm and 0.20mm.

8. The QFN frame structure according to claim 7, characterized in that, The protrusions and grooves are evenly distributed around the perimeter of the chip working area.

9. The QFN frame structure according to claim 1, characterized in that, The shortest distance between the chip working area and the wire bonding area on the pad is between 0.2mm and 0.35mm.

10. The QFN frame structure according to claim 1, characterized in that, The periodic protrusion structure is a wave-shaped structure.

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