A saturated voltage reducing triode
Patent Information
- Application Number
- CN202521833868.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-27
- Publication Date
- 2026-08-18
- Estimated Expiration
- 2035-08-27
AI Technical Summary
以上方式虽然可以提高三极管功率密度，但是对于三极管，发射极掺杂浓度越大，三极管开启电压越大，因此不同应用场景下的三极管发射极掺杂浓度参数基本已经固化；针对减薄基区厚度，不同应用场景下的三极管，其发射区下方基区厚度参数和掺杂浓度参数基本已经固化；针对增加发射区面积，会减小单位面积下的基区面积，影响三极管的其它电性参数，因此对于传统结构三极管，确定应用场景，其发射区掺杂浓度、基区厚度、发射区面积基本已经固化
本实用新型通过薄基区和厚基区结构设计，在厚基区内形成发射区，薄基区上形成基极电极，相对传统结构减小了发射区两侧基区厚度，减小载流子在发射区两侧基区的复合，增加单位电流密度，同时该创新型结构增大基极电极下方基区和集电区结的面积，薄基区和厚基区的高度差，使厚基区的侧面与集电区接触，增大基区和集电区结的面积，进而增大集电区收集基区中载流子的数量，增大单位面积电流密度，提高功率密度。
Smart Images
Figure CN224653864U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to a transistor for reducing saturation voltage. Background Technology
[0002] In the field of power electronic device technology, transistors are a commonly used semiconductor device, often used in switching circuits and amplifier circuits. As the power density requirements of power electronic device applications become increasingly higher, the development of high power density transistors has always been an industry trend.
[0003] Current density refers to the intensity of current flowing per unit area. In transistors, it typically refers to the amount of current carried per unit area of the collector or emitter. The formula is current density = current / area (units are amperes per square decimeter or amperes per square millimeter). Increasing the current density per unit area means handling a higher current per unit area of the transistor, which directly improves the power density (power handled per unit volume or unit area), which is crucial for optimizing transistor performance. Its significance is mainly reflected in the following aspects: 1. Improve current gain and amplification efficiency: Increasing current density allows the transistor to collect more charge carriers (such as electrons or holes) in the same area, thereby enhancing current gain (β value), improving amplification performance, and making signal processing more efficient.
[0004] 2. Reduce collector resistance and power consumption: Higher current density reduces the internal resistance of the collector, reduces voltage drop and conduction loss caused by resistance, and allows more power supply voltage to be effectively used for amplification, improving overall energy efficiency.
[0005] Currently, the main technologies for increasing the power density of transistors are achieved through the following core methods: 1. Increase the doping concentration in the emitter region to improve the emitter injection efficiency and increase the power density of the transistor; 2. Reduce the thickness of the base region to decrease carrier recombination in the base region and increase the power density of the transistor; 3. Increase the emitter area, thereby improving the emitter injection efficiency and increasing the power density of the transistor; While the above methods can improve the power density of transistors, for transistors, a higher emitter doping concentration leads to a higher turn-on voltage. Therefore, the emitter doping concentration parameters for different application scenarios are essentially fixed. Similarly, for reducing the base thickness, the base thickness and doping concentration parameters below the emitter region are also essentially fixed for different application scenarios. Increasing the emitter area reduces the base area per unit area, affecting other electrical parameters of the transistor. Therefore, for traditional transistor structures, the emitter doping concentration, base thickness, and emitter area are essentially fixed for a given application scenario. Therefore, how to improve transistor power density using a new transistor structure is a crucial technical problem that needs to be solved in this case. Utility Model Content
[0006] To address the above problems, this invention provides a transistor that increases the current density per unit area while improving power density and reducing the base-collector saturation voltage under the same device area.
[0007] The technical solution of this utility model is: A transistor for reducing saturation voltage and its fabrication method, comprising the following steps: Step S100: Prepare a first heavily doped thin base region in the epitaxial wafer, and prepare a first heavily doped thick base region in the first heavily doped thin base region. Step S200: Prepare a second doped emitter region within the first doped thick base region; Step S300: Prepare a first isolation layer on the epitaxial wafer, and open windows at the first heavily doped thin base region and the first heavily doped thick base region to prepare the base electrode; In step S400, a window is opened in the second doped emitter region to prepare the emitter electrode; Step S500: Prepare a collector electrode on the back side of the epitaxial wafer.
[0008] Specifically, step S100 includes: Step S110: Using photolithography, a mask is used to protect the outer region of the first heavily doped thin base region; the first heavily doped thin base region is formed by diffusion or ion implantation. Step S120: Using photolithography, a mask is used to protect the outer region of the first heavily doped thick base region; the first heavily doped thick base region is formed by diffusion or ion implantation.
[0009] Specifically, in step S100, the first heavily doped thick base region is formed within the first heavily doped thin base region using a self-aligned process.
[0010] Specifically, step S200 includes: Step S210: Using photolithography, a mask is used to protect the outer region of the second doped emitter region; the second doped emitter region is formed by diffusion or ion implantation.
[0011] Specifically, step S300 includes: Step S310: The first isolation layer is prepared by chemical vapor deposition, and the outer area of the base electrode is protected by photolithography using a mask and etched to open the window. Step S320: Use a stripping or etching process to prepare the base electrode at the window opening.
[0012] Specifically, step S400 includes: Step S410: Using photolithography, a mask is used to protect the outer area of the emitter electrode, and an etching process is used to open a window. Step S420: Use a stripping or etching process to prepare an emitter electrode at the window opening.
[0013] Specifically, step S500 includes: Step S510: Thin the epitaxial wafer using a thinning process, and fabricate a collector electrode on the back side of the epitaxial wafer using a sputtering or deposition process.
[0014] A transistor for reducing saturation voltage includes a collector electrode, an epitaxial wafer, and a first isolation layer arranged sequentially from bottom to top. The epitaxial wafer is provided with: The first doped thick base region extends downward from the top surface of the epitaxial wafer; The first heavily doped thin base region is provided in several parts, which extend downward from the top surface of the epitaxial wafer and are connected to the first heavily doped thick base region; the depth (Z direction) of the first heavily doped thin base region is less than the depth of the first heavily doped thick base region. The second doped emitter region is provided in several parts, which extend downward from the top surface of the first doped thick base region and are spaced apart from the bottom of the first doped thick base region. A first isolation layer is deposited on the top surface of the epitaxial wafer; The base electrode has several electrodes that extend downward from the top surface of the first isolation layer and are connected to the second heavily doped emitter region, forming a good ohmic contact with the second heavily doped emitter region. The emitter electrode is provided in several parts, which are respectively located between the adjacent base electrodes. It extends downward from the top surface of the first isolation layer and its bottom is connected to the first heavily doped thin base region or the first heavily doped thick base region, forming a good ohmic contact with the first heavily doped thin base region and the first heavily doped thick base region.
[0015] Specifically, the thickness of the first heavily doped thick base region is greater than that of the first heavily doped thin base region.
[0016] Specifically, the first heavily doped thick base region and the first heavily doped thin base region are connected.
[0017] The beneficial effects of this utility model are: This invention utilizes a thin-base and thick-base structure design, forming an emitter region within the thick-base region and a base electrode on the thin-base region. Compared to traditional structures, this reduces the thickness of the base regions on both sides of the emitter region, decreasing carrier recombination and increasing the unit current density. Simultaneously, this innovative structure increases the area of the base region and collector region junction below the base electrode. The height difference between the thin and thick-base regions allows the side of the thick-base region to contact the collector region, further increasing the area of the base region and collector region junction. This, in turn, increases the number of carriers collected in the base region by the collector region, increasing the unit area current density and improving the power density. Attached Figure Description
[0018] Figure 1 This is a process flow diagram of this utility model; Figure 2 This is a top view schematic diagram of the fabrication of the first-doped thin base region; Figure 3 This is a top view schematic diagram of the fabrication of the first-layer doped thick-base region; Figure 4 This is a top view schematic diagram of the fabrication of the second-doped emitter region; Figure 5 This is a schematic diagram of the fabrication of the second-doped emitter region along the X1 cross section; Figure 6 This is a schematic diagram of the fabrication of the second-doped emitter region along the X2 cross section; Figure 7 This is a top view schematic diagram of the fabrication of the first isolation layer, base electrode, and emitter electrode; Figure 8 This is a schematic diagram of the fabrication of the base electrode and emitter electrode along the X1 cross section; Figure 9 This is a schematic diagram of the fabrication of the base electrode and emitter electrode along the X2 cross section; Figure 10 This is a schematic diagram of the cross-sectional structure of the current collector electrode; In the figure, 1 is the epitaxial wafer, 2 is the first heavily doped thin base region, 3 is the first heavily doped thick base region, 4 is the second heavily doped emitter region, 5 is the first isolation layer, 6 is the base electrode, 7 is the emitter electrode, and 8 is the collector electrode. Detailed Implementation
[0019] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.
[0020] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0021] The following is for reference. Figure 1-10 Describe this utility model; A method for fabricating a transistor with reduced saturation voltage includes the following steps: Step S100: A first heavily doped thin base region 2 is prepared within the epitaxial wafer 1, and a first heavily doped thick base region 3 is prepared within the first heavily doped thin base region 2, as shown in the figure. Figure 2-3 As shown; Step S110: Using photolithography, a mask is used to protect the outer region of the first heavily doped thin base region 2; the first heavily doped thin base region 2 is formed by diffusion or ion implantation. In step S120, the outer region of the first heavily doped thick base region 3 is protected using a photolithography process and a mask; the first heavily doped thick base region 3 is formed by a diffusion process or an ion implantation process.
[0022] Accordingly, the first and second doped regions are either P-regions or N-regions with opposite doping charges. The thickness of epitaxial wafer 1 is 100-2000 μm, the thickness of the first heavily doped thin base region 2 is set to 0.5-20 μm, the thickness of the first heavily doped thick base region 3 is set to 1-50 μm, and the doping concentration range of N-type doping is 1e. 14 .cm -3 -1e 20 .cm -3 The doping concentration range for P-type doping is 1e. 15 .cm -3 -1e 20 .cm -3 The relevant parameter settings are related to the electrical design of the device; In this embodiment, the first doped region is a P-region, the second doped region is an N-region, and the thickness of the epitaxial wafer 1 is 350 μm; the thickness of the first heavily doped thin base region 2 is 1 μm, and the doping concentration is 1e.16 .cm -3 The first doped thick base region 3 has a thickness of 5 μm and a doping concentration of 1e. 16 .cm -3 The first heavily doped thin base region 2 and the first heavily doped thick base region 3 were prepared using ion implantation.
[0023] Step S200: Prepare a second heavily doped emitter region 4 within the first heavily doped thick base region 3, referring to... Figure 4-6 As shown; Step S210: Using photolithography, a mask is used to protect the outer region of the second heavily doped emission region 4; the second heavily doped emission region 4 is formed by diffusion or ion implantation.
[0024] Accordingly, the thickness of the second doped emitter region 4 is set to 0.5-49 μm; In this embodiment, the thickness of the second doped emitter region 4 is set to 3 μm, and the doping concentration is 1e. 19. cm -3 .
[0025] Step S300: A first isolation layer 5 is prepared on the epitaxial wafer 1. Windows are opened at the first heavily doped thin base region 2 and the first heavily doped thick base region 3 to prepare the base electrode 6, as shown in the figure. Figure 7-10 As shown; Step S310: Prepare the first isolation layer 5 by chemical vapor deposition, protect the external area of the base electrode 6 by photolithography using a mask, and open the window by etching. In step S320, the base electrode 6 is prepared at the window using a stripping or etching process.
[0026] Correspondingly, the first isolation layer 5 serves a protective function. It is made of SiO2 or Si3N4 and has a thickness of 10-5000nm. It uses ICP dry etching to create a window. The window extends from the top surface of the first isolation layer 5 downward into the first heavily doped thin base region 2 and the first heavily doped thick base region 3. The base electrode 6 contacts the first heavily doped thin base region 2 and the first heavily doped thick base region 3 to form an ohmic contact. The relevant parameter settings are related to the electrical design of the device. In this embodiment, Si3N4 is used as the first isolation layer 5 with a thickness of 200nm. ICP dry etching is used to create a window with a depth of 200nm. A 200nm thick Ti / Al two-layer metal is prepared as the base electrode 6 using a local heavy doping remetallization process and a lift-off process.
[0027] Step S400: A window is opened in the second heavily doped emitter region 4 to prepare the emitter electrode 7, as per [reference]. Figure 7-10 As shown; Step S410: Using photolithography, a mask is used to protect the external area of the emitter electrode 7, and an etching process is used to open a window. Step S420: Using a stripping or etching process, prepare the emitter electrode 7 at the window opening; Accordingly, ICP dry etching is used to create a window that extends downward from the top of the first isolation layer 7 into the interior of the second heavily doped emitter region 4. The emitter electrode 7 contacts the second heavily doped emitter region 4 to form an ohmic contact. The relevant parameter settings are related to the electrical design of the device. In this embodiment, ICP dry etching is used to create a window with a depth of 200 nm. A 200 nm thick Ti / Al double metal layer is then prepared as the emitter electrode 7 using a lift-off process.
[0028] Step S500: Fabricate collector electrode 8 on the back side of the epitaxial wafer, referring to... Figure 10 As shown.
[0029] Correspondingly, the epitaxial wafer 1 is thinned to the corresponding thickness through a thinning process, and the collector electrode 8 is prepared on the back side of the epitaxial wafer using a deposition process or a sputtering process; In this embodiment, a thinning process is used to reduce the thickness of the 350µm epitaxial wafer 1 to 180µm, and a deposition process is used to prepare a 1µm thick Ti / Al as the collector electrode 8.
[0030] A transistor for reducing saturation voltage includes a collector electrode 8, an epitaxial wafer 1, and a first isolation layer 5 arranged sequentially from bottom to top. The epitaxial wafer 1 is provided with: The first heavily doped thick base region 3 extends downward from the top surface of the epitaxial wafer 1; The first heavily doped thin base region 2 is provided in several parts, which extend downward from the top surface of the epitaxial wafer 1 and are connected to the first heavily doped thick base region 3; the depth (Z direction) of the first heavily doped thin base region 2 is less than the depth of the first heavily doped thick base region 3. The second doped emitter region 4 is provided in several parts, which extend downward from the top surface of the first doped thick base region 3 and are spaced apart from the bottom of the first doped thick base region 3. The first isolation layer 5 is deposited on the top surface of the epitaxial wafer 1; The base electrode 6 is provided with several electrodes that extend downward from the top surface of the first isolation layer 5 and are connected to the second heavily doped emitter region 4, forming a good ohmic contact with the second heavily doped emitter region 4. Emitter electrodes 7 are provided in several forms, each located between adjacent base electrodes 6. They extend downward from the top surface of the first isolation layer 5 and are connected at the bottom to the first heavily doped thin base region 2 or the first heavily doped thick base region 3, forming a good ohmic contact with the first heavily doped thin base region 2 and the first heavily doped thick base region 3.
[0031] The thickness of the first heavily doped thick base region 3 is greater than that of the first heavily doped thin base region 2.
[0032] The first heavily doped thick base region 3 and the first heavily doped thin base region 2 are connected.
[0033] This invention addresses the issue of improving the power density of transistors by providing a transistor with reduced saturation voltage. Through an innovative structure, the area of the junction between the base and collector regions is increased, thereby increasing the number of charge carriers collected in the base region by the collector region. This increases the current density per unit area under the same device area, thus improving the power density by 10%-20% under the same device area.
[0034] Regarding the information disclosed in this case, the following points need to be clarified: The accompanying drawings of the embodiments disclosed in this case only relate to the structures involved in the embodiments disclosed in this case; other structures can be referred to with ordinary designs. Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.
Claims
1. A transistor for reducing saturation voltage, characterized in that, It includes a collector electrode (8), an epitaxial wafer (1) and a first isolation layer (5) arranged sequentially from bottom to top; The epitaxial wafer (1) is provided with: The first heavily doped thick base region (3) extends downward from the top surface of the epitaxial wafer (1); The first heavily doped thin base region (2) is provided in several parts, which extend downward from the top surface of the epitaxial wafer (1) and are connected to the first heavily doped thick base region (3); The second doped emitter region (4) is provided in several parts, which extend downward from the top surface of the first doped thick base region (3); A first isolation layer (5) is deposited on the top surface of the epitaxial wafer (1); The base electrode (6) is provided with several electrodes that extend downward from the top surface of the first isolation layer (5) and are connected to the second heavily doped emission region (4), forming a good ohmic contact with the second heavily doped emission region (4); Emitter electrodes (7) are provided in several places, respectively located between adjacent base electrodes (6), extending downward from the top surface of the first isolation layer (5), and connected at the bottom to the first heavily doped thin base region (2) or the first heavily doped thick base region (3), forming a good ohmic contact with the first heavily doped thin base region (2) and the first heavily doped thick base region (3).
2. A transistor for reducing saturation voltage according to claim 1, characterized in that, The thickness of the first heavily doped thick base region (3) is greater than that of the first heavily doped thin base region (2).
3. A transistor for reducing saturation voltage according to claim 1, characterized in that, The first heavily doped thick base region (3) and the first heavily doped thin base region (2) are connected.
4. A transistor for reducing saturation voltage according to claim 1, characterized in that, The thickness of the epitaxial wafer (1) is 100-2000um.
5. A transistor for reducing saturation voltage according to claim 1, characterized in that, The thickness of the first heavily doped thin base region (2) is 0.5-20 μm.
6. A transistor for reducing saturation voltage according to claim 1, characterized in that, The thickness of the first heavily doped thick base region (3) is 1-50 μm.