Pixel structure, array substrate, display panel and display device

Abstract

Embodiments of the present disclosure provide a pixel structure, an array substrate, a display panel and a display device, and relate to the technical field of display, and are used for improving pixel aperture ratio. The pixel structure comprises a plurality of gate lines, a plurality of signal lines and a plurality of thin film transistors. The plurality of gate lines are arranged along a first direction, and the plurality of gate lines extend along a second direction, wherein the first direction intersects the second direction. The plurality of signal lines are arranged along the second direction, and the plurality of signal lines extend along the first direction. Each of at least two adjacent gate lines of the plurality of gate lines and the signal line are insulatively overlapped to form a plurality of pixel units. The plurality of thin film transistors are arranged between any two of the at least two adjacent gate lines, and one of the thin film transistors is coupled with one of the gate lines and one of the signal lines. The pixel structure is used for driving a display image.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel structure, an array substrate, a display panel, and a display device. Background Technology

[0002] Liquid crystal displays (LCDs) are widely used in various fields due to their low power consumption, small size, light weight, and excellent display quality. The display principle of an LCD is to use the electric field formed by the pixel structure to control the arrangement of liquid crystal molecules, thereby changing the polarization state of light. This, combined with a backlight and color filters, controls the brightness and color of the pixels, thus displaying an image. The pixel structure can also be called a pixel circuit or pixel circuit structure. The quality of the pixel structure design directly affects the display effect of the LCD. Utility Model Content

[0003] The purpose of the embodiments of this disclosure is to provide a pixel structure, array substrate, display panel, and display device for improving pixel aperture ratio.

[0004] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0005] On one hand, a pixel structure is provided, comprising multiple gate lines, multiple signal lines, and multiple thin-film transistors. The multiple gate lines are arranged along a first direction and extend along a second direction, the first direction intersecting the second direction. The multiple signal lines are arranged along the second direction and extend along the first direction. Each pair of adjacent gate lines, at least two insulated from the signal lines, overlaps and forms multiple pixel units. Multiple thin-film transistors are disposed between any two of the adjacent gate lines, each thin-film transistor being coupled to one gate line and one signal line.

[0006] Through the above embodiments, in the pixel structure of the dual-gate design, thin-film transistors are disposed between each group of dual gate lines, and the space occupied by the thin-film transistors and the spacing space that needs to be reserved between adjacent dual gate lines are reused, which effectively improves the space utilization rate of the non-aperture area of ​​the array substrate of the dual-gate design, thereby reducing the occupied area of ​​the non-aperture area, and thus improving the pixel aperture ratio of the pixel structure of the dual-gate design and even the array substrate.

[0007] In some embodiments, each pair of adjacent gate lines is insulated from and overlaps with the signal line to form a plurality of pixel units. A plurality of thin-film transistors are disposed between each pair of adjacent gate lines. The plurality of thin-film transistors disposed between each pair of adjacent gate lines are alternately coupled to the gate lines on both sides along the second direction.

[0008] In some embodiments, the thin-film transistor includes an active layer. The active layer has channels. The channels of the active layers of the plurality of thin-film transistors disposed between each pair of adjacent gate lines are arranged along the second direction.

[0009] In some embodiments, each pair of adjacent gate lines has a first spacing D1, where D1 ≥ 5.5 μm.

[0010] In some embodiments, each set of three adjacent gate lines is insulated from and overlaps with the signal line to form a plurality of pixel units. A plurality of thin-film transistors are disposed between any two of the three adjacent gate lines. The plurality of thin-film transistors disposed between any two of the three adjacent gate lines are alternately coupled to the three gate lines along the second direction.

[0011] In some embodiments, each set of three adjacent gate lines includes a first gate line, a second gate line, and a third gate line arranged along the first direction. The thin-film transistor includes a first transistor and a second transistor, the first transistor being disposed between the first gate line and the second gate line, and the second transistor being disposed between the second gate line and the third gate line. A portion of the structure of the second gate line located on one side of the first transistor has a second spacing D2 with the first gate line, and a portion of the structure of the second gate line located on one side of the second transistor has a third spacing D3 with the first gate line, where D2 > D3. And / or, a portion of the structure of the second gate line located on one side of the first transistor has a fourth spacing D4 with the third gate line, and a portion of the structure of the second gate line located on one side of the second transistor has a fifth spacing D5 with the third gate line, where D4 > D5. <D5。

[0012] In some embodiments, the plurality of signal lines include a first signal line, a second signal line, and a third signal line alternately arranged along the second direction. The plurality of thin-film transistors include a first transistor, a second transistor, and a third transistor alternately arranged along the second direction. The first transistor is coupled to the first signal line and the first gate line, and is located between the first gate line and the second gate line. The second transistor is coupled to the first signal line and the second gate line, and is located between the second gate line and the third gate line. The third transistor is coupled to the third signal line and the third gate line, and is located between the second gate line and the third gate line.

[0013] On the other hand, an array substrate is provided, the array substrate including a substrate and a pixel structure as described in any of the above embodiments, the pixel structure being disposed on one side of the substrate.

[0014] In another aspect, a display panel is provided, comprising a color filter substrate, a liquid crystal, and an array substrate as described in any of the above embodiments, wherein the pixel structure of the array substrate is disposed between a substrate and the color filter substrate. The liquid crystal fills the space between the color filter substrate and the array substrate.

[0015] In another aspect, a display device is provided, comprising a driving circuit board and a display panel as described in any of the preceding embodiments. The driving circuit board is electrically connected to the display panel.

[0016] The array substrate, display panel, and display device described above have the same structure and beneficial technical effects as the pixel structure provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0018] Figure 1 This is an external view of a display device according to some embodiments of the present disclosure;

[0019] Figure 2 This is a stacked structure diagram of a display device according to some embodiments of the present disclosure;

[0020] Figure 3 This is a diagram showing the stacked structure of a display module according to some embodiments of the present disclosure;

[0021] Figure 4 This is a diagram showing the stacked structure of another display module according to some embodiments of the present disclosure;

[0022] Figure 5 This is a diagram showing the stacked structure of a display panel according to some embodiments of the present disclosure;

[0023] Figure 6 This is a wiring diagram of a pixel structure according to some embodiments of the present disclosure;

[0024] Figure 7 This is a wiring diagram of another pixel structure according to some embodiments of the present disclosure;

[0025] Figure 8 This is a wiring diagram of yet another pixel structure according to some embodiments of the present disclosure;

[0026] Figure 9 This is a wiring diagram of yet another pixel structure according to some embodiments of the present disclosure;

[0027] Figure 10 for Figure 8 A cross-sectional view of the pixel structure along the AA' direction in the illustrated embodiment.

[0028] Figure label:

[0029] 1-Display device; 2-Display panel; 3-Driver circuit board; 4-Display driver chip; 5-Flexible circuit board; 6-Display module; 7-Backlight module; 21-Array substrate; 22-Color filter substrate; 23-Liquid crystal; 71-Backlight substrate; 72-Backlight source; 73-First diffusion layer; 74-Light homogenizing layer; 75-Light enhancement layer; 76-Second diffusion layer; 77-Reflective layer; 78-Light guide plate; 211-Substrate; 212-Pixel structure; 221-Filter substrate; 222-Color filter layer; S-Signal line; S1-First Signal line; S2 - Second signal line; S3 - Third signal line; S4 - Fourth signal line; S5 - Fifth signal line; G - Gate line; G1 - First gate line; G2 - Second gate line; G3 - Third gate line; T - Thin film transistor; T1 - First transistor; T2 - Second transistor; T3 - Third transistor; P - Pixel unit; L - Pixel electrode line; T01 - Gate; T02 - Active layer; T03 - Channel; T04 - Source; T05 - Drain; T06 - Insulating layer; X - First direction; Y - Second direction; Z - Third direction. Detailed Implementation

[0030] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0031] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0032] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0033] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0034] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0035] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0036] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0037] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0038] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0039] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0040] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0041] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0042] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0043] In embodiments of this disclosure, some figures illustrate an XYZ coordinate system for representing directions. For example, X can represent a first direction, Y can represent a second direction, and Z can represent a third direction.

[0044] Some embodiments of this disclosure provide a display device. For example... Figure 1As shown, the display device 1 can be any display device that displays either moving (e.g., video) or stationary (e.g., still image) text or images. More specifically, the display device 1 of the contemplated embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of an item), etc.

[0045] The form of the display device and the form of the screen are not restricted. For example Figure 1 As shown, display device 1 can also be a mobile phone terminal. For example, display device 1 can be a flat panel display for a computer.

[0046] For example, the type of display device 1 may include, but is not limited to, a liquid crystal display (LCD).

[0047] In some embodiments, such as Figure 2 As shown, the display device 1 may specifically include a display panel 2 and a driving circuit board 3. The driving circuit board 3 is electrically connected to the display panel 2.

[0048] In some examples, depending on the material classification, the display panel 2 may include, but is not limited to, a low-temperature poly-silicon (LTPS) display panel, an indium gallium zinc oxide (IGZO) display panel, or an amorphous silicon (a-Si) display panel.

[0049] In some other examples, based on the liquid crystal arrangement and driving method, the display panel 2 may include, but is not limited to, in-plane switching (IPS) display panels, vertical alignment (VA) display panels, and twisted nematic (TN) display panels.

[0050] In some examples, the driver circuit board 3 can house the display driver chip 4 and other electronic components. The display driver chip 4, also known as a display driver integrated circuit (DDIC), is mainly used to control parameters such as the light emission, color, and brightness of the pixels of the display panel 2 to achieve correct display of images and videos.

[0051] For example, the display device 1 may specifically include a flexible circuit board 5, and the display panel 2 can be bonded to the driving circuit board 3 through the flexible circuit board 5, thereby realizing the electrical connection between the display panel 2 and the display driving chip 4.

[0052] In some examples, display device 1 includes a display module.

[0053] like Figure 3 and Figure 4 As shown, the display module 6 includes a display panel 2 and a backlight module 7. For example, the display panel 2 is a liquid crystal display panel, and the display module 6 is a liquid crystal display module.

[0054] like Figure 3 As shown, in some examples, the backlight module 7 is a direct-lit backlight module.

[0055] For example, such as Figure 3 As shown, the backlight module 7 includes a backlight substrate 71, a backlight source 72, a first diffusion layer 73, a light-diffusing layer 74, a light-enhancing layer 75, and a second diffusion layer 76, which are sequentially stacked along the vertical light emission direction. For example, the backlight source 72 is a direct-lit backlight source, and the light emission direction of the direct-lit backlight source can be parallel to the vertical light emission direction of the backlight module 7.

[0056] For example, the light-diffusing layer 74 can be one or more layers, and the light-enhancing layer 75 can be one or more layers.

[0057] like Figure 4 As shown, in some other examples, the backlight module 7 is a side-lit backlight module.

[0058] For example, such as Figure 4 As shown, the backlight module 7 includes a reflective layer 77, a light guide plate 78, a first diffusion layer 73, a brightness enhancement layer 75, and a second diffusion layer 76, which are sequentially stacked along the vertical light emission direction. The backlight module 7 also includes a backlight source 72, which is disposed on one side of the light guide plate 78. For example, the backlight source 72 is a side-lit backlight source, and the light emission direction of the side-lit backlight source can intersect with the vertical light emission direction of the backlight module 7. Alternatively, the light emission direction of the side-lit backlight source can be perpendicular to the vertical light emission direction of the backlight module 7.

[0059] For example, the brightening layer 75 can be one or more layers.

[0060] Some embodiments of this disclosure provide a display panel. For example, the display panel is the one described in the above embodiments.

[0061] like Figure 5 As shown, the display panel 2 includes an array substrate 21, a color filter substrate 22, and a liquid crystal 23. For example, the display panel 2 is an LCD display panel.

[0062] like Figure 5 As shown, liquid crystal 23 is filled between array substrate 21 and color filter substrate 22. Exemplarily, array substrate 21 and color filter substrate 22 can be configured to form a liquid crystal cell for accommodating liquid crystal 23.

[0063] For example, in the display module 6, the color filter substrate 22 may be located on the side of the array substrate 21 away from the driving circuit board 3. Alternatively, the color filter substrate 22 may be located on the light-emitting side of the array substrate 21 facing the display panel 2.

[0064] In the display panel 2, the light-emitting side and the backlight side are arranged opposite to each other. The overall direction of the light emitted by the display panel 2 is from the backlight side to the light-emitting side. This direction can also be called the vertical light-emitting direction of the display panel 2.

[0065] like Figure 5 As shown, the display panel 2 is approximately parallel to the first direction X and the second direction Y, the thickness direction of the display panel 2 is approximately parallel to the third direction Z, and the vertical light emission direction of the display panel 2 is parallel to the third direction Z. For example, the first direction X can be parallel to the extension direction of the short side of the display panel 2, and the second direction Y can be parallel to the extension direction of the long side of the display panel 2.

[0066] For example, the color filter substrate 22 includes a filter substrate 221 and a color filter layer 222. The color filter layer 222 may be located on the side of the filter substrate 221 facing the array substrate 21.

[0067] For example, the color filter layer 222 may include multiple color blocking and light-shielding layers disposed in the same layer.

[0068] For example, the color filter layer 222 may include a red color filter, a green color filter, and a blue color filter. The red color filter can be configured to allow red light to pass through, the green color filter can be configured to allow green light to pass through, and the blue color filter can be configured to allow blue light to pass through. The light-shielding layer can be made of an opaque material and is disposed between two adjacent color filters. The light-shielding layer serves to block light and isolate the color filters of different colors.

[0069] Some embodiments of this disclosure provide an array substrate. For example, the array substrate is the array substrate described in the above embodiments.

[0070] like Figure 5As shown, in some embodiments, the array substrate 21 includes a substrate 211 and a pixel structure 212.

[0071] like Figure 5 As shown, the pixel structure 212 is disposed on one side of the substrate 211. For example, the pixel structure 212 may be disposed on the side of the substrate 211 facing the color filter substrate 22.

[0072] For example, pixel structure 212 can be electrically connected to flexible circuit board 5, thereby connecting to display driver chip 4 in sequence through flexible circuit board 5 and driver circuit board 3.

[0073] For example, the display driver chip 4 can transmit signals to the pixel structure 212, and control the arrangement of the liquid crystal 23 by controlling the switches in the pixel structure 212, thereby modulating the light of the display panel 2.

[0074] The initial arrangement of liquid crystals 23 differs depending on the type of display panel 2. For example, in a TN display panel, the liquid crystals are twisted 90° from bottom to top in the absence of an electric field. In a VA display panel, the liquid crystals 23 are arranged perpendicular to the array substrate 21 in the absence of an electric field.

[0075] Some embodiments of this disclosure provide a pixel structure. For example, the pixel structure is the pixel structure in the above embodiments.

[0076] like Figures 6-9 As shown, in some embodiments, pixel structure 212 includes multiple gate lines G, multiple signal lines S, and multiple thin-film transistors T.

[0077] like Figures 6-9 As shown, multiple grid lines G are arranged along a first direction X, and multiple grid lines G extend along a second direction Y. The first direction X and the second direction Y intersect.

[0078] like Figures 6-8 As shown, for example, the gate line G may include a straight line that may extend along the second direction Y.

[0079] like Figure 9 As shown, for example, the gate line G may include a bend line that extends generally along the second direction Y. Alternatively, a portion of the structure of the gate line G may extend along the second direction Y.

[0080] Multiple signal lines S are arranged along the second direction Y, and multiple signal lines S extend along the first direction X.

[0081] like Figure 6 or Figure 7 As shown, for example, the signal line S may include a straight line that extends along a first direction X.

[0082] like Figure 8 or Figure 9 As shown, for example, the signal line S may include a bend that may extend generally along a first direction X.

[0083] like Figures 6-9 As shown, at least two adjacent gate lines G are insulated from and overlap with the signal line S to form multiple pixel units P.

[0084] For example, a pixel unit P can be a sub-pixel. For instance, multiple pixel units P can include red sub-pixels, green sub-pixels, and blue sub-pixels arranged alternately along a first direction X or a second direction Y.

[0085] The red, green, and blue subpixels are configured to correspond to the red, green, and blue color filters in the color filter layer 222, respectively. By controlling whether the subpixels of different colors emit light or the intensity of their light emission, the display panel 2 displays the corresponding image.

[0086] For example, in the array substrate 21, the pixel unit P is located in the pixel aperture region, and the gate line G, signal line S, and thin film transistor T are located in the non-aperture region. The pixel aperture region is the effective light-transmitting area in the pixel region of the array substrate 21. The liquid crystal display panel 2 2 itself does not emit light, and the light source is provided by the backlight module 7. The pixel aperture ratio determines the utilization rate of the backlight light.

[0087] The pixel aperture ratio refers to the ratio of the pixel aperture area to the total area of ​​the pixel region in the pixel region of the array substrate 21. For example, the total area of ​​the pixel region can be equal to the sum of the areas of the pixel aperture area and the non-aperture area.

[0088] For example, each pair of adjacent gate lines G and signal lines S are insulated from each other and overlap to form multiple pixel units P. The shape of each pixel unit P can be rectangular. The two opposite sides of the rectangle can be two gate lines G, and the other two opposite sides of the rectangle can be a signal line S.

[0089] For example, signal line S can be used to transmit data signals, and signal line S can be a data signal line S. For example, signal line S can connect the source of pixel unit P and the source drive signal terminal of display driver chip 4.

[0090] For example, a gate line G can be used to transmit gate signals. Figure 8 As shown, one end of the gate line G can be connected to the gate T01 of the pixel unit P.

[0091] For example, the other end of the gate line G can be connected to the gate drive signal terminal of the display driver chip 4.

[0092] For example, at least a portion of the structure of the signal line S and at least a portion of the structure of the gate line G may be insulated from each other, or in other words, at least a portion of the structure of the signal line S and at least a portion of the structure of the gate line G may be spaced apart. For instance, an insulating layer may be present between at least a portion of the structure of the signal line S and at least a portion of the structure of the gate line G.

[0093] In this embodiment of the disclosure, taking the example of each pair of adjacent gate lines G and signal lines S being insulated and overlapping to form a plurality of pixel units P, each pair of adjacent gate lines G can drive the pixel units P on both sides respectively, and each pair of adjacent columns of pixel units P arranged along the second direction Y can share a signal line S. Thus, half of the signal lines S do not need to transmit data signals, reducing the manufacturing difficulty of the pixel structure 212, and also helping to simplify the structure of the display driver chip 4, reduce the manufacturing cost of the display driver chip 4, and reduce the difficulty of bonding and connecting the array substrate 21 and the display driver chip 4.

[0094] Multiple thin-film transistors T are disposed between any two of each of at least two adjacent gate lines G, and each thin-film transistor T is coupled to one gate line G and one signal line S.

[0095] like Figure 8 As shown, exemplarily, the thin-film transistor T includes an active layer T02 and a gate T01. The active layer T02 includes a channel T03 and a source T04 and a drain T05 located on both sides of the channel T03. For example, the active layer T02 may be located on the side of the gate T01 away from the substrate 211.

[0096] For example, multiple thin-film transistors T or multiple pixel units P can be arranged in an array on one side of the substrate 211.

[0097] In this embodiment, the thin-film transistor T can act as a switch of the array substrate 21. By turning itself on or off, it controls whether the pixel electrode line L of the pixel unit P is energized, thereby changing the electric field that affects the deflection of the liquid crystal 23 and controlling the display image of the display panel 2.

[0098] The inventors discovered that if there are multiple gate lines G between two adjacent rows or columns of pixel units P, these adjacent gate lines G need to have sufficient spacing to reduce or avoid short circuits between them. The larger the spacing between adjacent gate lines G, the larger the area of ​​the non-aperture region of the array substrate 21, the lower the pixel aperture ratio of the array substrate 21, the lower the light transmittance of the display panel 2, and the worse the display effect of the display device 1. Thin-film transistors T, located between the gate lines G and the aperture region, also occupy a large area and affect the pixel aperture ratio. For example, the size of some thin-film transistors T can be close to 45 μm, and correspondingly, the width of the light-shielding matrix at the thin-film transistor can reach 62 μm.

[0099] Through the above embodiments, in the pixel structure 212 designed with dual gate lines G or multiple gate lines G, the thin film transistor T in the pixel structure 212 is disposed between any two of the at least two adjacent gate lines G. The space occupied by the thin film transistor T and the space that needs to be reserved between adjacent gate lines G are reused, which effectively improves the space utilization rate of the non-aperture area of ​​the array substrate 21, thereby reducing the occupied area of ​​the non-aperture area, and thus improving the pixel aperture ratio of the pixel structure 212 and even the array substrate 21, which is conducive to improving the light transmittance of the display panel 2 and improving the display effect of the display device 1.

[0100] like Figure 10 As shown, in some examples, in pixel structure 212, signal line S can have a stacked relationship with gate line G.

[0101] For example, in the array substrate 21, the gate line G may be located on one side of the substrate 211, and the signal line S may be located on the side of the gate line G away from the substrate 211.

[0102] like Figure 10 As shown, for example, pixel structure 212 includes gate line G, insulating layer T06, and signal line S. Insulating layer T06 may be disposed between at least a portion of the structure of signal line S and at least a portion of the structure of gate line G.

[0103] For example Figure 10 As shown, the active layer T02 can be located on the side of the insulating layer T06 away from the gate line G or the gate T01 of the thin-film transistor T.

[0104] For example, different ions can be doped at both ends of the active layer T02 to form semiconductors with different conductivity types, thereby forming the source T04 and drain T05, as well as the channel T03 between the source T04 and drain T05.

[0105] For example, signal line S can be connected to source T04, and pixel motor line L can be connected to drain T05.

[0106] like Figure 8 As shown, in some embodiments, each pair of adjacent gate lines G has a first spacing D1, where D1 ≥ 5.5 μm. This reduces or avoids short circuits between adjacent gate lines G.

[0107] For example, the first spacing D1 may include, but is not limited to, 5.5 μm, 10 μm, 15 μm, 20 μm, and 25 μm.

[0108] like Figure 8 As shown, in the exemplary pixel structure 212 with a dual-gate line G design, the first pitch D1 is ≥ 20 μm. Thus, the gap created by the first pitch accommodates the thin-film transistor T.

[0109] For example, the first spacing D1 may include, but is not limited to, 20μm, 25μm, 30μm, 35μm, and 40μm.

[0110] In some examples, the linewidth of signal line S can be greater than or equal to 3 μm. For example, the linewidth of signal line S can be, but is not limited to, 3 μm, 4 μm, 5 μm, 6 μm, and 7 μm.

[0111] The linewidth of the gate line G can be greater than or equal to 6 μm. For example, the linewidth of the gate line G can be, but is not limited to, 6 μm, 8 μm, 10 μm, 12 μm, and 14 μm.

[0112] like Figure 8 As shown, for example, the channel width W1 of the thin-film transistor T can range from 2μm to 6μm. For instance, the channel width W1 of the thin-film transistor T can include, but is not limited to, 2μm, 3μm, 4μm, 5μm, and 6μm.

[0113] like Figure 10 As shown, by way of example, the width W2 of at least one edge of the gate T01 of the thin-film transistor T extending beyond the edge of the active layer T02 is ≥ 3 μm. For example, the width W2 may include, but is not limited to, 3 μm, 4 μm, 5 μm, 6 μm, and 7 μm.

[0114] like Figures 6-9 As shown, in some embodiments, pixel unit P may include pixel electrode line L.

[0115] like Figure 8 As shown, the pixel electrode line L can be connected to the drain T05 of the thin-film transistor T. The pixel electrode line L can be used to form an electric field when energized, thereby causing the liquid crystal 23 to deflect. The gate T01 of the thin-film transistor T can control the channel T03 between the source T04 and the drain T05 to be turned on or off.

[0116] For example, the pixel electrode line L of a pixel unit P can be connected to a thin-film transistor T.

[0117] in, Figure 6 and Figure 7 The area pointed to by the marker of the pixel electrode line L in the diagram can be intended to illustrate one example of the range of the region where the pixel electrode line L is located. Figure 8 and Figure 9 The line itself, to which the marker of the pixel electrode line L points, can be intended to illustrate an example of how the pixel electrode line L is routed.

[0118] like Figure 8 or Figure 9As shown, exemplarily, the pixel electrode line L can extend generally along the first direction X. For example, the pixel electrode line L may include a bend, or in other words, the signal line S may have a bend. For example, the bend angle and bend position of the pixel electrode line L can be adapted to the bend angle and bend position of the signal line S.

[0119] In this embodiment, the thin-film transistor T connected to the pixel electrode line L of a pixel unit P can be located on the side of the gate line G connected to the pixel unit P away from the pixel unit P. This allows the space occupied by the thin-film transistor T and the required spacing between adjacent gate lines G to be reused.

[0120] In some embodiments, each pair of adjacent gate lines G are insulated from and overlap with the signal line S to form a plurality of pixel units P.

[0121] Multiple thin-film transistors T are disposed between every two adjacent gate lines G. The multiple thin-film transistors T disposed between every two adjacent gate lines G are alternately coupled to the gate lines G on both sides along the second direction Y.

[0122] For example, each pair of adjacent gate lines G can be a gate line group G. A gate line group G can be connected to the pixel units P located on opposite sides of the gate line group along the first direction X, thereby realizing the dual gate line G design.

[0123] like Figure 6 As shown, for example, signal line S may include a fourth signal line S4 and a fifth signal line S5, which are arranged alternately along the second direction Y. For example, the fourth signal line S4 is connected to pixel units P located on opposite sides of the fourth signal line S4, and the fourth signal line S4 is used to transmit data signals. The fifth signal line S5 may not be connected to pixel units P.

[0124] Through the above embodiments, a pixel structure 212 with a dual gate line G design is realized. Furthermore, a thin film transistor T is set between each group of dual gate lines G, and the space occupied by the thin film transistor T and the spacing space that needs to be reserved between adjacent dual gate lines G are reused, which effectively improves the space utilization rate of the non-aperture area of ​​the array substrate 21 with dual gate line G design, thereby reducing the occupied area of ​​the non-aperture area, and thus improving the pixel aperture ratio of the pixel structure 212 with dual gate line G design and even the array substrate 21.

[0125] like Figure 8 As shown, in some examples, the thin-film transistor T includes an active layer T02. The active layer T02 has a channel T03.

[0126] The channels T03 of the active layers T02 of the plurality of thin-film transistors T located between each pair of adjacent gate lines G are arranged along the second direction Y. Alternatively, the channels T03 of the active layers T02 of the plurality of thin-film transistors T located between each pair of adjacent gate lines G are arranged along the extension direction of the gate lines G.

[0127] For example, the channel T03 of the active layer T02 of a plurality of thin-film transistors T located between each pair of adjacent gate lines G intersects the same straight line. For example, this straight line may be parallel to the extension direction of the gate line G.

[0128] For example, the channel T03 of the active layer T02 of multiple thin-film transistors T located between each pair of adjacent gate lines G may not be exactly on a straight line.

[0129] In this embodiment of the present disclosure, the channels T03 of the active layer T02 of the plurality of thin film transistors T disposed between each pair of adjacent gate lines G are arranged along the extension direction of the gate line G, or approximately along the extension direction of the gate line G, which can further improve the regularity of the arrangement of the thin film transistors T, thereby reducing the area occupied by the thin film transistors T, and thus improving the pixel aperture ratio of the pixel structure 212 and even the array substrate 21.

[0130] In some embodiments, every three adjacent gate lines G are insulated from and overlap with the signal line S to form a plurality of pixel units P.

[0131] Multiple thin-film transistors T are disposed between any two gate lines G of every three adjacent gate lines G.

[0132] For example, every three adjacent gate lines G can be a gate line G group. A gate line G group can be connected to the pixel units P located on opposite sides of the gate line G group along the first direction X, thereby realizing the three gate line G design.

[0133] For example, such as Figure 7 As shown, each gate line group G may include a first gate line G1, a second gate line G2 and a third gate line G3, with the second gate line G2 located between the first gate line G1 and the third gate line G3.

[0134] For example, the second gate line G2 may extend along the second direction Y. The second gate line G2 may have a bent structure to avoid the remaining circuit structures in the pixel structure 212, such as the thin film transistor T, thereby helping to reduce the space between the second gate line G2 and the first gate line G1, and / or reduce the space between the second gate line G2 and the third gate line G3, further reducing the area occupied by each gate line G group.

[0135] For example, a portion of the structure of the second gate line G2 can extend along the second direction Y, and another portion of the structure of the second gate line G2 can extend along the first direction X. The two portions of the structure of the second gate line G2 extending along the first direction X and the second direction Y can be connected to form a bent structure.

[0136] like Figure 7 As shown, for example, signal line S may include a first signal line S1, a second signal line S2, and a third signal line S3, which are arranged alternately along the second direction Y. For instance, the first signal line S1 is connected to pixel units P located on opposite sides of the first signal line S1 along the second direction Y, and the third signal line S3 is connected to pixel units P located on one side of the third signal line S3 along the second direction Y. The first signal line S1 and the third signal line S3 are used to transmit data signals. The second signal line S2 may not be connected to pixel unit P.

[0137] Multiple thin-film transistors T are disposed between any two gate lines G of every three adjacent gate lines G, and are alternately coupled to the three gate lines G along the second direction Y.

[0138] For example, a thin-film transistor T located between gate lines G in each gate line group G can be alternately connected to the first gate line G1, the second gate line G2, and the third gate line G3 along the second direction Y.

[0139] Through the above embodiments, a pixel structure 212 with a three-gate-line G design is realized. Furthermore, a thin-film transistor T is set between each group of three-gate-line Gs, and the space occupied by the thin-film transistor T and the spacing space that needs to be reserved between adjacent gate lines G in the three-gate-line Gs are reused, which effectively improves the space utilization rate of the non-aperture area of ​​the array substrate 21 with the three-gate-line G design, thereby reducing the occupied area of ​​the non-aperture area, and thus improving the pixel aperture ratio of the pixel structure 212 with the three-gate-line G design and even the array substrate 21.

[0140] like Figure 9 As shown, in some examples of the above embodiments, each group of three adjacent gate lines G, or each group of gate lines G, includes a first gate line G1, a second gate line G2, and a third gate line G3 arranged along the first direction X.

[0141] The thin-film transistor T includes a first transistor T1 and a second transistor T2. The first transistor T1 is disposed between the first gate line G1 and the second gate line G2, and the second transistor T2 is disposed between the second gate line G2 and the third gate line G3.

[0142] like Figure 9As shown, in some examples, a portion of the structure of the second gate line G2 located on one side of the first transistor T1 has a second spacing D2 with the first gate line G1, and a portion of the structure of the second gate line G2 located on one side of the second transistor T2 has a third spacing D3 with the first gate line G1, where D2>D3.

[0143] In some examples, a portion of the structure of the second gate line G2 located on the side of the first transistor T1 has a fourth spacing D4 with the third gate line G3, and a portion of the structure of the second gate line G2 located on the side of the second transistor T2 has a fifth spacing D5 with the third gate line G3. <D5。

[0144] Through the above embodiments, the thin-film transistor T has different positions in the gate line G group including three gate lines G. By designing the spacing between the gate lines G on both sides of the thin-film transistor T at different positions, the size of the gate line G group along the first direction X can be reduced as much as possible, further improving the space utilization rate of the non-aperture area of ​​the array substrate 21 with three gate lines G design, reducing the occupied area of ​​the non-aperture area, and thus further improving the pixel aperture ratio of the pixel structure 212 and even the array substrate 21 with three gate lines G design.

[0145] In some examples, in a row of thin-film transistors T arranged along the second direction Y, in every three thin-film transistors T connected to a group of gate lines G, two thin-film transistors T are located between two adjacent gate lines G, and one thin-film transistor T is located between one of the two adjacent gate lines G and another of the three gate lines G.

[0146] For example, multiple signal lines S include a first signal line S1, a second signal line S2, and a third signal line S3 arranged alternately along the second direction Y. Multiple thin-film transistors T include a first transistor T1, a second transistor T2, and a third transistor T3 arranged alternately along the second direction Y.

[0147] The first transistor T1 is coupled to the first signal line S1 and the first gate line G1, and the first transistor T1 is located between the first gate line G1 and the second gate line G2.

[0148] The second transistor T2 is coupled to the first signal line S1 and the second gate line G2, and the second transistor T2 is located between the second gate line G2 and the third gate line G3.

[0149] The third transistor T3 is coupled to the third signal line S3 and the third gate line G3. The third transistor T3 is located between the second gate line G2 and the third gate line G3.

[0150] In this embodiment of the disclosure, the first transistor T1, the second transistor T2 and the third transistor T3 can respectively drive the pixel unit P corresponding to the pixel electrode line L connected to its drain, thereby realizing vertical pixel driving.

[0151] Through the above embodiments, thin-film transistors T with different array arrangements are coupled to corresponding signal lines S and gate lines G respectively. By designing the position of thin-film transistors T between gate lines G, the space utilization rate of the non-aperture area of ​​the array substrate 21 with three gate lines G can be improved to a greater extent, the occupied area of ​​the non-aperture area can be reduced, and the pixel aperture ratio of the pixel structure 212 and even the array substrate 21 with three gate lines G can be further improved.

[0152] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A pixel structure, characterized in that, include: Multiple grid lines are arranged along a first direction and extend along a second direction, wherein the first direction and the second direction intersect. Multiple signal lines are arranged along the second direction and extend along the first direction; Each of the multiple gate lines, at least two adjacent gate lines are insulated from the signal line and overlap to form multiple pixel units; A plurality of thin-film transistors are disposed between any two of the at least two adjacent gate lines, and each thin-film transistor is coupled to one of the gate lines and one of the signal lines.

2. The pixel structure according to claim 1, characterized in that, Each pair of adjacent gate lines is insulated from the signal line and overlaps to form multiple pixel units; Multiple thin-film transistors are disposed between each pair of adjacent gate lines; The plurality of thin-film transistors disposed between each pair of adjacent gate lines are alternately coupled to the gate lines on both sides along the second direction.

3. The pixel structure according to claim 2, characterized in that, The thin-film transistor includes an active layer; The active layer is provided with a channel; the channels of the active layers of the plurality of thin-film transistors provided between each pair of adjacent gate lines are arranged along the second direction.

4. The pixel structure according to any one of claims 1-3, characterized in that, Each pair of adjacent gate lines has a first spacing D1, where D1 ≥ 5.5 μm.

5. The pixel structure according to claim 1, characterized in that, Each three adjacent gate lines of the plurality of gate lines are insulated from and overlap with the signal lines to form a plurality of pixel units; The plurality of thin-film transistors are disposed between any two gate lines of each of the three adjacent gate lines; A plurality of thin-film transistors disposed between any two of the three adjacent gate lines are alternately coupled to the three gate lines along the second direction.

6. The pixel structure according to claim 5, characterized in that, Each set of three adjacent grid lines includes: a first grid line, a second grid line, and a third grid line arranged along the first direction; The thin-film transistor includes a first transistor and a second transistor, wherein the first transistor is disposed between the first gate line and the second gate line, and the second transistor is disposed between the second gate line and the third gate line; A portion of the second gate line located on one side of the first transistor has a second spacing D2 with the first gate line, and a portion of the second gate line located on one side of the second transistor has a third spacing D3 with the first gate line, where D2 > D3; and / or, A portion of the second gate line located on one side of the first transistor has a fourth spacing D4 with the third gate line, and a portion of the second gate line located on one side of the second transistor has a fifth spacing D5 with the third gate line. <D5。 7. The pixel structure according to claim 6, characterized in that, The plurality of signal lines include: a first signal line, a second signal line, and a third signal line arranged alternately along the second direction; The plurality of thin-film transistors include: a first transistor, a second transistor, and a third transistor arranged alternately along the second direction; The first transistor is coupled to the first signal line and the first gate line, and the first transistor is located between the first gate line and the second gate line; The second transistor is coupled to the first signal line and the second gate line, and the second transistor is located between the second gate line and the third gate line; The third transistor is coupled to the third signal line and the third gate line, and the third transistor is located between the second gate line and the third gate line.

8. An array substrate, characterized in that, include: Substrate; The pixel structure as described in any one of claims 1-7, wherein the pixel structure is disposed on one side of the substrate.

9. A display panel, characterized in that, include: Color film substrate; The array substrate as described in claim 8, wherein the pixel structure of the array substrate is disposed between the substrate and the color filter substrate; Liquid crystal, which fills the space between the color filter substrate and the array substrate.

10. A display device, characterized in that, include: The display panel as described in claim 9; A driving circuit board, which is electrically connected to the display panel.

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