Type-c interface circuit supporting multiple debug modes

Abstract

The utility model provides a kind of Type-C interface circuit of supporting multiple DEBUG mode, comprising: equipment detection module, the equipment identification signal of detecting the insertion equipment of Type-C interface and generating;Control module, the control signal and the first debugging signal of corresponding generation are received by the equipment identification signal;CPU module, the second debugging signal and the third debugging signal are generated;Switching module, the control signal is received and switched between multiple signal channels, and the first debugging signal, the second debugging signal or the third debugging signal is selectively routed to the Type-C interface.By integrating multiple debugging modes on a single Type-C interface, the complexity of the motherboard design is simplified and the debugging cost is reduced. It can automatically identify and switch to the corresponding debugging mode according to the type of the inserted device, thereby replacing the multiple independent DEBUG interfaces in traditional design with one interface, effectively saving motherboard space and wiring resources.

Description

Technical Field

[0001] This utility model relates to the field of circuits, specifically to a Type-C interface circuit that supports multiple DEBUG modes. Background Technology

[0002] In traditional computer motherboard development, debugging primarily relies on multiple dedicated debug interfaces for system status monitoring and fault diagnosis. These debug interfaces typically include a BIOS debug interface, an EC (embedded controller) debug interface, and a CPU-specific debug interface, used to monitor the BIOS boot process, EC firmware execution status, and processor running status, respectively. Through these interfaces, developers can view the system code execution progress in real time, pinpointing the specific location of system boot freezes or anomalies, thereby quickly identifying and resolving hardware or firmware issues. However, this traditional debugging method has significant limitations: multiple independent debug interfaces not only increase the complexity and cost of motherboard design but also consume valuable motherboard space resources.

[0003] More seriously, these DEBUG interfaces are typically located inside the motherboard, requiring the entire system casing to be disassembled to connect debugging equipment for testing. This design presents significant inconvenience during actual product testing: on the one hand, frequent disassembly and reassembly increase testing workload and the risk of equipment damage; on the other hand, many intermittent faults and environment-related problems are often unreproducible after disassembly, leading to low debugging efficiency. Especially during mass production testing, when rapid testing of a large number of products is required, the traditional disassembly-based debugging method severely impacts production efficiency. Therefore, simplifying the DEBUG interface design and integrating debugging functionality into the system's standard I / O interfaces, enabling system debugging without disassembly, has become a pressing technical problem in the current computer motherboard development field. Utility Model Content

[0004] The purpose of this invention is to solve the technical problem of low debugging efficiency and waste of interface resources caused by the lack of a unified and convenient output interface in the prior art.

[0005] This utility model provides a Type-C interface circuit that supports multiple DEBUG modes, including: The device detection module detects devices inserted through the Type-C interface and generates a device identification signal; The control module receives the device identification signal and generates corresponding control signals and a first debugging signal; The CPU module generates the second and third debug signals; The switching module receives the control signal and switches between multiple signal channels, selectively routing the first debugging signal, the second debugging signal, or the third debugging signal to the Type-C interface.

[0006] Furthermore, the device detection module includes an interface connection unit and a PD detection unit. The interface connection unit is equipped with a Type-C interface, and the PD detection unit identifies the type of the inserted device by detecting the resistance value of the Type-C interface pins and generates the device identification signal.

[0007] Furthermore, the interface connection unit includes a Type-C connector, the first configuration channel pin and the second configuration channel pin of the Type-C connector are respectively connected to the input terminal of the PD detection unit, and the differential signal pin is connected to the output terminal of the switching module.

[0008] Furthermore, the PD detection unit includes a PD chip, and the serial data pin and serial clock pin of the PD chip are connected to the input terminal of the control module.

[0009] Furthermore, the control module includes an EC chip, which communicates with the device detection module via an I2C bus.

[0010] Furthermore, the EC chip's system management bus pin receives the device identification signal, its data pin outputs the control signal, and its serial communication pin outputs the first debugging signal.

[0011] Furthermore, the first debugging signal is the EC-DEBUG signal generated by the EC chip. Furthermore, the CPU module includes a main control chip, whose differential signal pin outputs the second debugging signal, and its serial communication pin outputs the third debugging signal.

[0012] Furthermore, the second debugging signal is a USB 2.0 communication signal generated by the main control chip, and the third debugging signal is a CPU-DEBUG signal generated by the main control chip.

[0013] Furthermore, the first set of input pins of the switching module receives the first debugging signal, the second set of input pins receives the second debugging signal, the third set of input pins receives the third debugging signal, and the output pin is connected to the data pin of the Type-C connector.

[0014] Compared to existing technologies, this invention offers at least the following advantages: By integrating multiple debugging modes onto a single Type-C interface, it simplifies motherboard design complexity and reduces debugging costs. It can automatically identify and switch to the appropriate debugging mode based on the type of inserted device, including EC debugging, USB communication debugging, and CPU-specific debugging, thus replacing multiple independent DEBUG interfaces in traditional designs with a single interface, effectively saving motherboard space and wiring resources. Debugging personnel can perform system debugging and fault diagnosis without disassembling the device, avoiding the problem of difficulty in reproducing faults after disassembly. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained as provided without creative effort.

[0016] Figure 1 This is a schematic diagram of a Type-C interface circuit in one embodiment of the present invention; Figure 2 This is a circuit diagram of the Type-C connector in a Type-C interface circuit according to one embodiment of the present invention; Figure 3 This is a circuit diagram of the PD chip in a Type-C interface circuit according to one embodiment of the present invention; Figure 4 This is a circuit diagram of the EC chip in a Type-C interface circuit according to one embodiment of the present invention; Figure 5 This is another circuit diagram of the EC chip in the Type-C interface circuit of this utility model; Figure 6 This is another circuit diagram of the EC chip in the Type-C interface circuit of this utility model; Figure 7 This is a circuit diagram of the main control chip in the Type-C interface circuit of one embodiment of the present invention; Figure 8 This is another circuit diagram of the main control chip in the Type-C interface circuit of this utility model; Figure 9 This is a circuit diagram of an analog switch in a Type-C interface circuit according to one embodiment of the present invention. Detailed Implementation

[0017] The present invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the present invention. It should be understood that those skilled in the art can modify the present invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being broadly known to those skilled in the art and is not intended to limit the present invention.

[0018] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0019] The present invention will be described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer as will be explained below. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0020] This embodiment provides a Type-C interface circuit that supports multiple DEBUG modes. Please refer to [link / reference]. Figures 1-9 ,include: The device detection module detects devices inserted through the Type-C interface and generates a device identification signal.

[0021] The control module receives the device identification signal and generates corresponding control signals and a first debugging signal.

[0022] The CPU module generates the second and third debug signals.

[0023] The switching module receives the control signal and switches between multiple signal channels, selectively routing the first debugging signal, the second debugging signal, or the third debugging signal to the Type-C interface.

[0024] Specifically, the device detection module is responsible for monitoring the device insertion status of the Type-C interface in real time and generating corresponding device identification signals by analyzing the electrical characteristics of the inserted device. After receiving the identification signal, the control module generates a control signal for selecting the control signal path and outputs a first debugging signal (usually an EC-related UART debugging signal). The CPU module independently generates a second debugging signal (such as a USB 2.0 communication signal) and a third debugging signal (such as a CPU-specific JTAG or SWD debugging signal). The switching module, as the core router of the entire system, intelligently switches between three different debugging signal sources according to the control signal issued by the control module, accurately routing the currently required debugging signal to the Type-C interface, thereby enabling a single physical interface to support multiple debugging modes and meeting the debugging needs of different stages and types of systems.

[0025] By integrating multiple debugging signals into a standard Type-C interface, the problem of requiring multiple independent interfaces in traditional debugging methods is solved. The device detection module automatically identifies the type of the inserted device, the control module selects the appropriate debugging signal based on the identification result, and the switching module handles signal routing. Therefore, only a single Type-C interface is needed to support multiple debugging modes, including EC debugging, USB debugging, and CPU-specific debugging, allowing system debugging without disassembling the device, thus improving debugging efficiency and convenience. Compared to existing technologies, this reduces the number of interfaces, simplifies motherboard design, lowers costs, and maintains the integrity of debugging functionality.

[0026] Furthermore, the device detection module includes an interface connection unit and a PD detection unit. The interface connection unit is equipped with a Type-C interface, and the PD detection unit identifies the type of the inserted device by detecting the resistance value of the Type-C interface pins and generates the device identification signal.

[0027] Specifically, the interface connection unit can be implemented using a Type-C connector, with its first configuration channel pin (CC1) and second configuration channel pin (CC2) connected to the input terminals of the PD detection unit. The PD detection unit is preferably implemented using a PD protocol chip, with its serial data pin (SDA) and serial clock pin (SCL) connected to the input terminals of the control module. In a preferred embodiment, the PD detection unit distinguishes the device type by measuring the resistance to ground of the CC pin. For example, a 5.1kΩ pull-down resistor is detected, identifying it as a UFP device, and a 1.5kΩ pull-up resistor is detected, identifying it as a DFP device. The differential signal pins (D+ / D-) are directly connected to the output terminals of the switching module, thereby achieving a physical connection of the signal channels.

[0028] By integrating PD protocol detection functionality, the system can automatically identify the type of device connected via the Type-C interface and generate an accurate device identification signal accordingly. Compared to the traditional method requiring manual configuration and debugging, this significantly improves the automation level of the debugging system. Furthermore, since device identification is performed using the standard Type-C interface configuration channel, no additional detection circuitry is needed, maintaining interface compatibility while simplifying hardware design complexity.

[0029] Furthermore, the first configuration channel pin and the second configuration channel pin of the Type-C connector are respectively connected to the input terminal of the PD detection unit, and the differential signal pin is connected to the output terminal of the switching module.

[0030] Specifically, the Type-C connector serves as the physical interface for device connection. Its first configuration channel pin (CC1) and second configuration channel pin (CC2) are used to transmit configuration signals. These two pins establish an electrical connection with the PD detection unit, enabling the PD detection unit to detect the type of the inserted device. Differential signal pins (such as D+ and D-) are used to transmit high-speed data signals and are directly connected to the output of the switching module to route debugging signals.

[0031] Please refer to Figure 2 In one possible embodiment, the Type-C connector can be a 24-pin standard package, where CC1 and CC2 correspond to pins A5 and B5 respectively, and the differential signal pins correspond to pins A6 / A7 and B6 / B7. Furthermore, the VBUS pin of the Type-C connector can be connected to a power management module to provide power to the inserted device.

[0032] By optimizing the pin connections of the Type-C connector, the configuration channel pins are dedicated to device type detection, while the differential signal pins are reserved for debug signal transmission. Compared to existing technologies, this achieves physical integration of the debug interface with the standard Type-C interface, avoiding the space occupied by an additional debug interface.

[0033] Furthermore, the PD detection unit includes a PD chip, and the serial data pin and serial clock pin of the PD chip are connected to the input terminal of the control module.

[0034] Specifically, the PD chip is an integrated circuit that supports the USB Power Delivery protocol, used for device type identification and power negotiation via the configuration channel of the Type-C interface. The serial data pin is used to transmit device identification data, and the serial clock pin is used to synchronize data transmission timing. As a preferred implementation, the PD chip can be a CYPD6229 model, communicating with the control module via I2C or SMBus protocols. Furthermore, the configuration channel pins of the PD chip can be connected to the CC1 and CC2 pins of the Type-C interface to detect the resistance value of the inserted device. Thus, the PD chip can accurately identify the device type and generate the corresponding device identification signal, which is transmitted to the control module via the serial interface.

[0035] To address this issue, a dedicated PD chip is integrated to enable device detection, resolving the problem of manually switching signal sources required by traditional debugging interfaces. The PD chip connects to the control module via a standard serial interface, simplifying circuit design and improving signal transmission reliability. Furthermore, due to the adoption of a standard communication protocol, this solution offers excellent compatibility and scalability, adapting to combinations of PD chips and control modules from different manufacturers. Specifically, when a debugging device is inserted into the Type-C interface, the PD chip automatically detects the device type and transmits the identification result to the control module via the serial interface, thereby achieving automatic routing of debugging signals without manual intervention.

[0036] Furthermore, the control module includes an EC chip, which communicates with the device detection module via an I2C bus.

[0037] Specifically, the EC chip, as the core component of the control module, establishes a communication connection with the device detection module via the I2C bus protocol. The I2C bus uses a two-wire structure, including a serial data line (SDA) and a serial clock line (SCL), enabling half-duplex synchronous communication. The EC chip reads the device identification signal generated by the device detection module through the I2C bus and generates corresponding control and debugging signals according to preset logic. As a preferred embodiment, the EC chip can be an embedded controller series chip, such as the IT51366 or IT571VG, whose built-in I2C controller supports standard mode (100kHz) and fast mode (400kHz) communication rates. Furthermore, a level conversion circuit can be added to the I2C bus to accommodate potential operating voltage differences between the device detection module and the EC chip.

[0038] By employing a standardized I2C bus interface to interconnect the control module and the device detection module, the complexity of hardware design is effectively simplified. Compared to traditional parallel buses or custom communication protocols, the I2C bus requires only two signal lines to complete data transmission, reducing PCB routing resources and connector pin usage. Simultaneously, the hot-plug detection mechanism based on the I2C bus can acquire device connection status in real time, ensuring the timeliness and accuracy of debug signal switching. This improves the integration of the DEBUG function, enabling system status monitoring and diagnosis without the need for a dedicated debug interface.

[0039] Furthermore, the EC chip's system management bus pin receives the device identification signal, its data pin outputs the control signal, and its serial communication pin outputs the first debugging signal.

[0040] Specifically, the EC chip receives a device identification signal from the PD detection unit via the system management bus pin. This signal is used to identify the type of device inserted into the Type-C interface. The control signal output from the data pin is used to control the switching module to select among multiple signal channels. The UART debug signal output from the serial communication pin can be routed to the Type-C interface through the switching module to achieve debugging functionality. In a preferred embodiment, the EC chip can be an embedded controller, such as an ITE series or Nuvoton series chip, whose system management bus pin can be configured as an SMBus interface, data pin as a GPIO interface, and serial communication pin as a UART interface.

[0041] The EC chip integrates device identification, control signal generation, and debug signal output functions, simplifying the design of the debug interface. Compared to existing technologies, it eliminates the need for multiple independent DEBUG interfaces on the motherboard, reducing motherboard design complexity and space requirements. Debug signals can be output via a Type-C interface, avoiding disassembly and improving debugging efficiency.

[0042] Furthermore, the first debugging signal is the EC-DEBUG signal generated by the EC chip.

[0043] Specifically, the EC-DEBUG signal generated by the EC chip indicates that this debug signal is a dedicated debug information signal output by the embedded controller (EC) chip. The EC-DEBUG signal typically contains key debug information such as the running status of the EC firmware, boot process, error codes, and register status, and is used to monitor and diagnose the working status of the EC system.

[0044] To address this, this technical solution standardizes the EC chip's debug signals to a UART interface, enabling EC firmware debugging using common serial debugging tools. Compared to existing solutions requiring dedicated debug interfaces, this design simplifies the debug interface type, eliminating the need for a separate EC debug interface on the motherboard. During debugging, developers can directly obtain EC runtime debugging information, including firmware execution status, error codes, and other critical information, via a USB-to-Type-C adapter. This design improves debugging convenience while reducing the number of dedicated debug interfaces on the motherboard.

[0045] Furthermore, the CPU module includes a main control chip, the differential signal pin of which outputs the second debugging signal, and the serial communication pin which outputs the third debugging signal.

[0046] Furthermore, the second debugging signal is a USB 2.0 communication signal generated by the main control chip, and the third debugging signal is a CPU-DEBUG signal generated by the main control chip.

[0047] In one possible embodiment of this invention, the main control chip can be an Intel Panther Lake H444 or an AMD Ryzen 7 255, and those skilled in the art can select the appropriate main control chip as needed. Its differential signal pins achieve signal conversion through an internal USB 2.0 PHY circuit, outputting differential signal pairs D+ and D- conforming to the USB 2.0 specification. The serial communication pins can be configured as a UART interface, using TTL level standards to output TX and RX signals. As a preferred embodiment, the main control chip can integrate a dedicated debug controller to generate a third debug signal via JTAG or SWD protocols. Furthermore, the GPIO pins of the main control chip can be multiplexed as debug signal output terminals, with the output signal type selected through register configuration.

[0048] By integrating multiple debug signal output functions onto the main control chip, a single Type-C interface can be compatible with both USB communication debugging and processor-specific debugging modes. Compared to existing technologies, there is no need to separately arrange a CPU debug interface on the motherboard, reducing hardware design complexity and space occupation. Debug signals are output through the standard Type-C interface, avoiding disassembly and improving testing convenience. Meanwhile, the signal generation circuit integrated within the main control chip ensures the stability and compatibility of the debug signals.

[0049] Furthermore, the switching module includes an analog switch, wherein a first set of input pins of the analog switch receives the first debugging signal, a second set of input pins receives the second debugging signal, a third set of input pins receives the third debugging signal, and the output pin is connected to the data pin of the Type-C connector.

[0050] Specifically, the analog switch can be implemented using a multiplexer or a cross-point switch integrated circuit, wherein the multiplexer is preferably a CMOS analog switch chip with a 4:1 or 8:1 channel configuration. As a preferred embodiment, the control terminal of the analog switch can be connected to the GPIO pin of the control module, and channel selection can be achieved through high and low level combinations.

[0051] Intelligent switching of multiple debug signals is achieved through an analog switch, integrating debugging functions that previously required multiple independent interfaces into a standard Type-C interface. The specific working principle is as follows: When a device is inserted into the Type-C interface, the device detection module detects the inserted device and generates a device identification signal for the control module. The control module automatically selects the corresponding debug signal channel based on the device type. The selected debug signal is then routed to the data pins of the Type-C interface via an analog switch. Compared to existing technologies, this reduces the number of motherboard debug interfaces, avoids the inconvenience of disassembling the device for debugging, and ensures isolation and transmission quality between different debug signals through a hardware switching mechanism.

[0052] The following explains the specific steps: Please refer to Figure 1 , Figure 9 The table shows that pin 3 is chip select pin S1 and pin 17 is chip select pin S0. The analog switch's input terminals select different input channels to conduct to the analog switch's output based on the different levels of chip select pins S0 / S1. When enable EN is low, When S1 / S0 is 00, meaning S1 is low and S0 is low, the input channel CH0 and the output channel are connected. When S1 / S0 is 0 or 1, that is, S1 is low and S0 is high, the input channel CH1 and the output channel are connected. When S1 / S0 is 10, meaning S1 is high and S0 is low, the input channel CH2 and the output channel are connected. When S1 / S0 is 11, that is, S1 is high and S0 is high, the input channel CH3 and the output channel are connected. By using pull-up and pull-down resistors, the chip select S1 / S0 is configured to 10 by default, which means that the input channel CH2 and the output channel are connected, and the default configuration is the normal USB function of the Type-C interface.

[0053] Table 1 The above-described specific examples are for illustrative purposes only and are not intended to limit the scope of this invention. Those skilled in the art to which this invention pertains can make various simple deductions, modifications, or substitutions based on the concept of this invention.

Claims

1. A Type-C interface circuit supporting multiple DEBUG modes, characterized in that, include: The device detection module detects devices inserted through the Type-C interface and generates a device identification signal; The control module receives the device identification signal and generates corresponding control signals and a first debugging signal; The CPU module generates the second and third debug signals; The switching module receives the control signal and switches between multiple signal channels, selectively routing the first debugging signal, the second debugging signal, or the third debugging signal to the Type-C interface.

2. The Type-C interface circuit supporting multiple DEBUG modes as described in claim 1, characterized in that, The device detection module includes an interface connection unit and a PD detection unit. The interface connection unit is equipped with a Type-C interface. The PD detection unit identifies the type of inserted device by detecting the resistance value of the Type-C interface pins and generates the device identification signal.

3. The Type-C interface circuit supporting multiple DEBUG modes as described in claim 2, characterized in that, The interface connection unit includes a Type-C connector. The first configuration channel pin and the second configuration channel pin of the Type-C connector are respectively connected to the input terminal of the PD detection unit, and the differential signal pin is connected to the output terminal of the switching module.

4. The Type-C interface circuit supporting multiple DEBUG modes as described in claim 3, characterized in that, The PD detection unit includes a PD chip, and the serial data pin and serial clock pin of the PD chip are connected to the input terminal of the control module.

5. The Type-C interface circuit supporting multiple DEBUG modes as described in claim 3, characterized in that, The control module includes an EC chip, which communicates with the device detection module via an I2C bus.

6. The Type-C interface circuit supporting multiple DEBUG modes as described in claim 5, characterized in that, The EC chip's system management bus pin receives the device identification signal, its data pin outputs the control signal, and its serial communication pin outputs the first debugging signal.

7. The Type-C interface circuit supporting multiple DEBUG modes as described in claim 6, characterized in that, The first debugging signal is the EC-DEBUG signal generated by the EC chip.

8. The Type-C interface circuit supporting multiple DEBUG modes as described in claim 5, characterized in that, The CPU module includes a main control chip, the differential signal pin of which outputs the second debugging signal, and the serial communication pin outputs the third debugging signal.

9. The Type-C interface circuit supporting multiple DEBUG modes as described in claim 8, characterized in that, The second debugging signal is a USB 2.0 communication signal generated by the main control chip, and the third debugging signal is a CPU-DEBUG signal generated by the main control chip.

10. The Type-C interface circuit supporting multiple DEBUG modes as described in claim 9, characterized in that, The switching module includes an analog switch. The first set of input pins of the analog switch receives the first debugging signal, the second set of input pins receives the second debugging signal, the third set of input pins receives the third debugging signal, and the output pin is connected to the data pin of the Type-C connector.

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