Display device and electronic device

Abstract

A display device and an electronic device are provided. A display device according to an embodiment includes a substrate including a semiconductor layer; a plurality of insulating layers including a first insulating layer which is disposed on the semiconductor layer and a second insulating layer which is disposed on the first insulating layer; a contact hole which exposes the semiconductor layer through the plurality of insulating layers; and a conductive pattern which covers the semiconductor layer and the insulating layers at a portion overlapping the contact hole, the semiconductor layer including a recessed portion recessed toward a direction of the substrate at a portion overlapping the contact hole, the first insulating layer and the second insulating layer including different substances from each other, and the recessed portion of the semiconductor layer and the first insulating layer having a stepped shape.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of display device and electronic device. BACKGROUND

[0002] With the development of information society, the demand for display devices for displaying images increases in various forms. For example, display devices are suitable for various electronic devices such as smartphones, digital cameras, notebook computers, navigators, and smart televisions. Display devices can be flat panel display devices such as liquid crystal display devices, field emission display devices, and organic light emitting display devices. In such flat panel display devices, each of the pixels of the display panel includes a light emitting element that can emit light by itself, so that an image can be displayed even without a backlight unit that provides light to the display panel. SUMMARY

[0003] The utility model aims at providing a display device capable of providing high-resolution images and a manufacturing method of the display device.

[0004] The utility model aims at providing a display device that solves contact failure of a conductive pattern at a portion overlapping a contact hole, an electronic device using the same, and a manufacturing method of the display device.

[0005] The problems of the utility model are not limited to the above-mentioned problems, and other technical problems not mentioned can be clearly understood by those skilled in the art from the following description.

[0006] A display device according to an embodiment for solving the problem includes a substrate including a semiconductor layer; a plurality of insulating layers including a first insulating layer and a second insulating layer disposed on the first insulating layer; a contact hole exposing the semiconductor layer through the plurality of insulating layers; and a conductive pattern covering the semiconductor layer and the insulating layers at a portion overlapping the contact hole, the semiconductor layer including a recessed portion recessed toward a direction of the substrate at the portion overlapping the contact hole, the first insulating layer and the second insulating layer including different materials from each other, and the recessed portion of the semiconductor layer and the first insulating layer having a stepped shape.

[0007] It can be that the first insulating layer is more protruded toward a direction of the contact hole than the second insulating layer, and the recessed portion of the semiconductor layer, the first insulating layer, and the second insulating layer have a stepped shape.

[0008] The first insulating layer can define a first opening at a portion overlapping the contact hole, and the second insulating layer can define a second opening at a portion overlapping the contact hole, a width of the first opening and a width of the second opening being different from each other.

[0009] The width of the first opening can be smaller than the width of the second opening.

[0010] A difference between the width of the first opening and the width of the second opening can be 10 angstroms or more and 300 angstroms or less.

[0011] An aspect ratio of the contact hole defined by a value of dividing a depth of the contact hole by a width of the contact hole can be 0.6 or more.

[0012] The depth of the contact hole can be 1.2 micrometers or more, and the width of the contact hole can be 2.0 micrometers or less.

[0013] The recessed portion of the semiconductor layer can not overlap the plurality of insulating layers in a direction perpendicular to the substrate.

[0014] In a direction parallel to the substrate, a width of the recessed portion of the semiconductor layer can be smaller than a width of the contact hole.

[0015] The semiconductor layer can include polysilicon.

[0016] A side surface of the first insulating layer facing the contact hole and a side surface of the second insulating layer facing the contact hole can be located on a same line.

[0017] The conductive pattern can be in contact with and cover the recessed portion of the semiconductor layer, the first insulating layer, and the second insulating layer at a portion overlapping the contact hole.

[0018] A manufacturing method of a display device according to an embodiment for solving the problem includes forming a plurality of insulating layers on a substrate including a semiconductor layer, performing a dry etching process to remove a portion of the insulating layers, performing a dry cleaning process to form a contact hole, and forming a conductive pattern at a portion overlapping the contact hole, the plurality of insulating layers including a first insulating layer in contact with the semiconductor layer and a second insulating layer in contact with the first insulating layer and including a material different from that of the first insulating layer.

[0019] The semiconductor layer can include a recessed portion recessed toward a direction of the substrate.

[0020] The recessed portion of the semiconductor layer, the first insulating layer, and the second insulating layer can include a stepped portion having a stepped shape.

[0021] An electronic device according to an embodiment for solving the problem can include at least one display device including a substrate including a semiconductor layer, a display device housing portion housing the at least one display device, and an optical member magnifying or converting an optical path of a display image of the at least one display device, the at least one display device including a plurality of insulating layers including a first insulating layer and a second insulating layer disposed to be contiguous to the first insulating layer, a contact hole exposing the semiconductor layer through the plurality of insulating layers, and a conductive pattern covering the semiconductor layer and the insulating layers at a portion overlapping the contact hole, the semiconductor layer including a recessed portion recessed toward a direction of the substrate at the portion overlapping the contact hole, the first insulating layer and the second insulating layer including different materials from each other, and the recessed portion of the semiconductor layer and the first insulating layer having a stepped portion having a stepped shape.

[0022] Details of other embodiments are included in the detailed description and the accompanying drawings.

[0023] According to the display device according to an embodiment, the electronic device using the same, and the manufacturing method thereof, a high-resolution image can be provided, and contact failure of a conductive pattern can be solved at a portion overlapping a contact hole.

[0024] Effects according to embodiments are not limited to what has been described above, and various other effects include those described in this specification. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 FIG. 1 is a perspective view illustrating a head-mounted electronic device according to an embodiment.

[0026] Figure 2 FIG. 2 is an exploded perspective view illustrating an example of the head-mounted electronic device of FIG. 1. Figure 1

[0027] Figure 3 FIG. 3 is a perspective view illustrating a head-mounted electronic device according to an embodiment.

[0028] Figure 4 FIG. 4 is a perspective view illustrating a display device according to an embodiment.

[0029] Figure 5 ​is a cross-sectional view showing a display device according to an embodiment.

[0030] Figure 6 is a plan view showing a display layer of a display device according to an embodiment.

[0031] Figure 7 is a cross-sectional view showing an example of the display layer taken along Figure 6 the X-X' intercept line.

[0032] Figure 8 is a cross-sectional view showing an enlarged "A1" region in Figure 7

[0033] Figure 9 is a cross-sectional view showing a lower region of a first contact hole in Figure 8

[0034] Figure 10 is a cross-sectional view showing an enlarged "A1" region in Figure 7

[0035] Figure 11 is a cross-sectional view showing an enlarged "A1" region in Figure 7

[0036] Figure 12 is a cross-sectional view showing an enlarged "A3" region in Figure 7

[0037] Figure 13 is a flowchart showing a manufacturing process of a first conductive pattern and a second conductive pattern overlapping with a first contact hole and a second contact hole in Figure 7

[0038] Figure 14 is a cross-sectional view showing the S100 step of Figure 13

[0039] Figure 15 is a cross-sectional view showing the S200 step of Figure 16 Figure 13

[0040] Figure 17 is a cross-sectional view showing the S300 step of Figure 13

[0041] Figure 18 is a graph showing a change in etching rate of an inorganic substance according to a change in temperature in a dry cleaning process.

[0042] Figure 19 is a cross-sectional view showing the S300 step of Figure 13

[0043] ​​​​​​​​​​​Figure 20 and Figure 21 is a cross-sectional view illustrating Figure 13 S400 step of FIG. 4.

[0044] Figure 22 is a block diagram of an electronic device according to an embodiment.

[0045] Figure 23 is a schematic diagram of an electronic device according to various embodiments.

[0046] (Reference Numerals)

[0047] 10: display device 100: display panel

[0048] SUB: substrate TFTL: transistor layer

[0049] EML: display element layer TFEL: thin film encapsulation layer

[0050] SCL1: first semiconductor layer ACT1: first active layer

[0051] S1: source region D1: drain region

[0052] GTL1: first conductive layer GTL2: second conductive layer

[0053] GTL3: third conductive layer GTL4: fourth conductive layer

[0054] CP1: first conductive pattern CP2: second conductive pattern

[0055] CP3: third conductive pattern CP4: fourth conductive pattern

[0056] CH1: first contact hole Lch1: lower region

[0057] Uch1: upper region GI1: first insulating layer

[0058] GI2: second insulating layer GI3: third insulating layer

[0059] GI4: fourth insulating layer GI5: fifth insulating layer

[0060] dd1: first face rr1: recessed portion DETAILED DESCRIPTION

[0061] Reference is made to and reliance is appropriately placed on the other Figure 1The advantages and features of the present application and the method of realizing them will become apparent from the following embodiments described in detail. However, the present application is not limited to the embodiments disclosed below, and can be implemented in various forms different from each other, and the present embodiments are provided only to make the present application complete and to convey the scope of the present application to a person having ordinary knowledge in the technical field to which the present application pertains, and the present application is limited only by the scope of the claims.

[0062] "on" another element or layer includes all cases of being directly on the other element or layer or having another layer or element interposed therebetween. Throughout the specification, like reference numerals refer to like constituent elements. The shape, size, ratio, angle, number, and the like disclosed in the drawings for describing the embodiments are exemplary, and thus the present application is not limited to the matters illustrated.

[0063] Although first, second, and the like are used for describing various constituent elements, it is apparent that the constituent elements are not limited to these terms. The terms are used only to distinguish one constituent element from another. Thus, it is apparent that the first constituent element mentioned below can also be the second constituent element within the technical idea of the present application.

[0064] The various features of the embodiments of the present application can be combined with or integrated into each other in part or in whole, and can be technically linked and driven, and each embodiment can be independently implemented or implemented together in an associated relationship with respect to each other.

[0065] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0066] Figure 1 is a perspective view showing a head-mounted electronic device according to an embodiment. Figure 2 is a perspective view showing a head-mounted electronic device according to an embodiment. Figure 1 is an exploded perspective view of an example of the head-mounted electronic device of

[0067] Referring to Figure 1 and Figure 2 , the head-mounted electronic device 1 according to an embodiment includes a display device housing portion 110, a housing portion cover 120, a first eyepiece 131, a second eyepiece 132, a head-mounted band 140, a first display device 10_1, a second display device 10_2, an intermediate frame 160, a first optical member 151, a second optical member 152, a control circuit board 170, and a connector.

[0068] The first display device 10_1 provides an image to the left eye of a user, and the second display device 10_2 provides an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 is described with reference to Figure 4The display devices 10 described are substantially the same. Therefore, the description of the first display device 10_1 and the second display device 10_2 will be based on reference. Figure 4 The explanation is used instead.

[0069] The first optical component 151 may be disposed between the first display device 10_1 and the first eyepiece 131. The second optical component 152 may be disposed between the second display device 10_2 and the second eyepiece 132. Each of the first optical component 151 and the second optical component 152 may include at least one convex lens.

[0070] The intermediate frame 160 can be disposed between the first display device 10_1 and the control circuit board 170, and between the second display device 10_2 and the control circuit board 170. The intermediate frame 160 serves to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 170.

[0071] The control circuit board 170 can be disposed between the intermediate frame 160 and the display device housing 110. The control circuit board 170 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 170 can convert externally input image sources into digital video data (DATA) and transmit the digital video data (DATA) to the first display device 10_1 and the second display device 10_2 via connectors.

[0072] The control circuit board 170 can transmit digital video data (DATA) corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and digital video data (DATA) corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 170 can transmit the same digital video data (DATA) to both the first display device 10_1 and the second display device 10_2.

[0073] The display device housing 110 serves to house the first display device 10_1, the second display device 10_2, the intermediate frame 160, the first optical component 151, the second optical component 152, the control circuit board 170, and the connector. The housing cover 120 is configured to cover the open side of the display device housing 110. The housing cover 120 may include a first eyepiece 131 for the user's left eye and a second eyepiece 132 for the user's right eye. Figure 1 as well as Figure 2 The illustration shows a first eyepiece 131 and a second eyepiece 132 configured separately, but the embodiments described in this specification are not limited thereto. The first eyepiece 131 and the second eyepiece 132 may be combined into one.

[0074] Alternatively, the first eyepiece 131 can be aligned with the first display device 10_1 and the first optical component 151, and the second eyepiece 132 can be aligned with the second display device 10_2 and the second optical component 152. Therefore, the user can see the image of the first display device 10_1 magnified into a virtual image by the first optical component 151 through the first eyepiece 131, and can see the image of the second display device 10_2 magnified into a virtual image by the second optical component 152 through the second eyepiece 132.

[0075] The headband 140 serves to secure the display device housing 110 to the user's head, allowing the first eyepiece 131 and the second eyepiece 132 of the housing cover 120 to remain positioned in the user's left and right eyes, respectively. When the display device housing 110 is made lightweight and compact, the head-mounted electronic device 1 can have the following features: Figure 3 The eyeglass frame shown is used instead of the headband 140.

[0076] In addition, the head-mounted electronic device 1 may also include a battery for power supply, an external memory slot for accommodating external memory, an external connection port for receiving image sources, and a wireless communication module. The external connection port may be a USB (Universal Serial Bus) terminal, a display port, or an HDMI (High-Definition Multimedia Interface) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0077] Figure 3 This is a perspective view showing a head-mounted electronic device according to an embodiment.

[0078] Reference Figure 3 According to one embodiment, the head-mounted electronic device 1_1 may be a display device in the form of lightweight and compact eyeglasses, with the display device housing 120_1 implemented as such. The head-mounted electronic device 1_1 according to one embodiment may include a display device 10_3, a left eye lens 311, a right eye lens 312, a support frame 350, eyeglass temples 341 and 342, an optical component 320, an optical path conversion component 330, and a display device housing 120_1.

[0079] Figure 3 The display device 10_3 shown is the same as the reference. Figure 4 The display device 10 described is substantially the same.

[0080] The display device housing 120_1 may include a display device 10_3, an optical component 320, and a light path conversion component 330. The image displayed on the display device 10_3 can be magnified by the optical component 320, and the light path is converted by the light path conversion component 330 and provided to the user's right eye through the right eye lens 312. Thus, the user can view an augmented reality image—a combination of a virtual image displayed on the display device 10_3 and a real image seen through the right eye lens 312—through their right eye.

[0081] exist Figure 3 The illustration shows the display device receiving portion 120_1 disposed at the right end of the support frame 350, but the embodiments described herein are not limited to this. For example, the display device receiving portion 120_1 may be disposed at the left end of the support frame 350, in which case the image of the display device 10_3 can be provided to the user's left eye. Alternatively, the display device receiving portion 120_1 may be disposed at both the left and right ends of the support frame 350, in which case the user can view the image displayed on the display device 10_3 simultaneously through both the left and right eyes.

[0082] Figure 4 This is a perspective view showing a display device according to an embodiment.

[0083] Reference Figure 4 The display device 10 can be applied to portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic manuals, e-books, PMPs (portable multimedia players), navigators, and UMPCs (ultra-mobile PCs). For example, the display device 10 can be used as the display unit of a television, laptop computer, monitor, billboard, or Internet of Things (IoT) device. As another example, the display device 10 can be applied to wearable devices such as smartwatches, watch phones, glasses displays, and head-mounted displays (HMDs).

[0084] The display device 10 can be constructed from a planar shape similar to a quadrilateral. For example, the display device 10 can have a planar shape similar to a quadrilateral, which has a short side in a first direction DR1 and a long side in a second direction DR2. The angle where the short side in the first direction DR1 and the long side in the second direction DR2 intersect can be rounded to have a predetermined curvature or formed as a right angle. The planar shape of the display device 10 is not limited to a quadrilateral and can be formed similarly to other polygons, circles, or ellipses.

[0085] The display device 10 may include a display panel 100, a display driver unit 200, a circuit board 300, and a touch driver unit 400.

[0086] The display panel 100 may include a main area MA and a sub-area SBA. The main area MA may include a display area DDA containing pixels of the displayed image and a non-display area NDA located around the display area DDA.

[0087] The display area DDA can emit light from multiple light-emitting areas or multiple openings, as described later. For example, the display panel 100 may include pixel circuitry containing switching elements, a pixel defining layer defining the light-emitting areas or openings, and a self-light-emitting element. For example, the self-light-emitting element may include at least one of, but is not limited to, an organic light-emitting diode (OLED) containing an organic light-emitting layer, a quantum dot LED containing a quantum dot light-emitting layer, an inorganic light-emitting diode containing an inorganic semiconductor, and a micro LED. An organic light-emitting diode is illustrated as a self-light-emitting element in the following figures.

[0088] The non-display area NDA can be the outer region of the display area DDA. The non-display area NDA can be defined as the edge region of the main area MA of the display panel 100.

[0089] The sub-region SBA can be a region extending from one side of the main region MA. The sub-region SBA can include a flexible material capable of bending, folding, rolling, etc. For example, when the sub-region SBA is bent, it can overlap with the main region MA in the thickness direction (for example, the third direction DR3). The sub-region SBA can include a display driving unit 200 and pads connected to the circuit board 300. In another embodiment, the sub-region SBA can be omitted, and the display driving unit 200 and pads can be located in the non-display area NDA.

[0090] The display driver unit 200 can output signals and voltages for driving the display panel 100. The display driver unit 200 can be formed as an integrated circuit (IC) and mounted on the display panel 100 using COG (Chip on Glass), COP (Chip on Plastic), or ultrasonic bonding methods. For example, the display driver unit 200 can be located in a sub-region SBA and can overlap with the main region MA in the thickness direction by bending the sub-region SBA. As another example, the display driver unit 200 can be mounted on a circuit board 300.

[0091] The circuit board 300 can be attached to the pad portion of the display panel 100 using an anisotropic conductive film (ACF). The circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film such as chip on film.

[0092] The touch driver unit 400 can be mounted on the circuit board 300. The touch driver unit 400 can be connected to the touch sensor layer used for sensing and driving touches on the display device 10. Figure 5 (TSL).

[0093] Figure 5 This is a cross-sectional view showing a display device according to an embodiment.

[0094] Reference Figure 5 The display panel 100 may include a display layer DPL, a touch sensor layer TSL, and a color filter layer CFL. The display layer DPL may include a substrate SUB, a transistor layer TFTL, a display element layer EML, and a packaging layer TFEL.

[0095] The substrate SUB can be a base substrate or a base component. The substrate SUB can be a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate SUB can include, but is not limited to, a polymer resin such as polyimide (PI). In another embodiment, the substrate SUB can include a glass material or a metal material.

[0096] The transistor layer TFTL can be located on the substrate SUB. The transistor layer TFTL can be located in the portion that overlaps with the display area DDA, the non-display area NDA, and the sub-area SBA.

[0097] The display element layer (EML) may be located on the transistor layer (TFTL). The display element layer (EML) may be located in the portion overlapping with the display area (DDA). The display element layer (EML) may include, but is not limited to, at least one of the following: an organic light-emitting diode (OLED) containing an organic light-emitting layer, a quantum dot LED containing a quantum dot light-emitting layer, an inorganic light-emitting diode (Inorganic LED) containing inorganic semiconductors, and a micro LED.

[0098] The encapsulation layer TFEL can be located on the display element layer EML. The TFEL can be located in the portion overlapping the display area DDA and the non-display area NDA. The TFEL can cover the top and sides of the display element layer EML, protecting it from external oxygen and moisture. The TFEL can include at least one inorganic film and at least one organic film for encapsulating the display element layer EML.

[0099] The touch sensor layer (TSL) can be located on the encapsulation layer (TFEL). The touch sensor layer (TSL) can be located in the portion overlapping the display area (DDA) and the non-display area (NDA). The touch sensor layer (TSL) can sense the user's touch using either mutual capacitance or self-capacitance. In some embodiments, the touch sensor layer (TSL) can be omitted.

[0100] The color filter layer CFL can be located on the touch sensor layer TSL. The color filter layer CFL can be located in the portion overlapping with the display area DDA and the non-display area NDA. The color filter layer CFL can absorb a portion of the light flowing in from the outside of the display device 10 to reduce reflected light caused by external light. Therefore, the color filter layer CFL can prevent color distortion caused by external light reflection.

[0101] The color filter layer CFL is disposed directly on the touch sensor layer TSL, thus the display device 10 does not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 can be relatively small. The color filter layer CFL may also be omitted according to embodiments.

[0102] like Figure 5 As shown, a portion of the display panel 100 that overlaps with the sub-region SBA can be bent. When a portion of the display panel 100 is bent, the display driver 200, the circuit board 300, and the touch driver 400 can overlap with the main region MA on the third-direction DR3.

[0103] When a portion of the display panel 100 is bent, the bending protection layer BPL can protect the underlying structure that overlaps with the sub-region SBA from bending stress.

[0104] Figure 6 This is a plan view showing the display layer of a display device according to an embodiment.

[0105] Reference Figure 6 The display layer DPL may include multiple pixels PX, multiple power lines VL connected to the multiple pixels PX, multiple scan lines SL, multiple light emission control lines EDL, and multiple data lines DL in the part that overlaps with the display area DDA.

[0106] Each of the multiple scan lines SL can extend along a first direction DR1 and can be spaced apart from each other along a second direction DR2 that intersects the first direction DR1. The scan lines SL can be arranged along the second direction DR2. The scan lines SL can sequentially supply scan signals to multiple pixels PX.

[0107] Each of the emission control lines (EDLs) can extend along the first direction DR1 and can be spaced apart from each other along the second direction DR2. The emission control lines (EDLs) can be arranged along the second direction DR2. The emission control lines (EDLs) can sequentially supply emission signals to multiple pixels (PX).

[0108] Data lines DL can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. Data lines DL can be arranged along the first direction DR1. Data lines DL can supply data voltage to multiple pixels PX. The data voltage determines the brightness of each of the multiple pixels PX.

[0109] The power line VL may include a main power line VL1 and a sub-power line VL2. At least one of a first power supply voltage (high potential voltage) and a second power supply voltage (low potential voltage) can be transmitted to the sub-power line VL2 through the main power line VL1, which overlaps with the non-display area NDA. Hereinafter, the main power line VL1 and the sub-power line VL2 may be collectively referred to as power line VL.

[0110] The non-display area NDA may surround the display area DDA. The non-display area NDA may include a scan driving unit 211 and a light emission control driving unit 213.

[0111] The scan driving unit 211 can be configured on the outer side of the display area DDA or on the side of the non-display area NDA. The scan driving unit 211 may include a plurality of driving transistors that generate gate signals based on gate control signals.

[0112] The light emission control driver unit 213 can be configured on the outer side of the display area DDA or on the outer side of the non-display area NDA. The light emission control driver unit 213 may include a plurality of light emission control transistors that generate light emission signals based on light emission control signals.

[0113] In one embodiment, the display layer DPL may include a display driver unit 200 and a plurality of pad electrodes PD in the portion overlapping with the sub-region SBA. The plurality of pad electrodes PD may be arranged spaced apart from each other in the first direction DR1, and each pad electrode PD may be connected to its own different wiring.

[0114] Figure 7 It shows along Figure 6 A cross-sectional view of an example of a display layer, captured by the X-X' intercept line. Figure 7 The diagram shows a schematic cross-sectional view of the substrate SUB, transistor layer TFTL, display element layer EML, and encapsulation layer TFEL included in the display layer DPL.

[0115] Apart from Figures 1 to 6 In addition, refer to Figure 7 The transistor layer TFTL can be located on the substrate SUB. The transistor layer TFTL may include multiple semiconductor layers, multiple conductive layers, and multiple insulating layers.

[0116] As the display device 10 of one embodiment is adapted to a high-resolution electronic device 1, the semiconductor layers and / or conductive layers included in the transistor layer TFTL can be configured with appropriate spacing within a narrow area. Multiple semiconductor layers and / or conductive layers can be stacked on a third-direction DR3, separated by multiple insulating layers.

[0117] In one embodiment, the transistor layer TFTL may include a first semiconductor layer SCL1, a first insulating layer GI1, a first conductive layer GTL1, a second insulating layer GI2, a second conductive layer GTL2, a third insulating layer GI3, a third conductive layer GTL3, a fourth insulating layer GI4, a second semiconductor layer SCL2, a fifth insulating layer GI5, a fourth conductive layer GTL4, a sixth insulating layer GI6, a fifth conductive layer SDL1, a first interlayer insulating layer ILD1, a sixth conductive layer SDL2, a second interlayer insulating layer ILD2, a seventh conductive layer SDL3, and a via layer VIA.

[0118] The first semiconductor layer SCL1 may be located on the substrate SUB. The first semiconductor layer SCL1 may include a first active layer ACT1 contained in the first transistor T1 of the pixel PX.

[0119] The first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 may overlap with the first gate electrode GE1 on the third-direction DR3. The first channel region CHA1 may form a channel corresponding to the voltage applied to the first gate electrode GE1.

[0120] The first source region S1 and the first drain region D1 can be located on opposite sides of the first channel region CHA1. The first source region S1 and the first drain region D1 can have higher conductivity than the first channel region CHA1. For example, the carrier concentration of the first source region S1 and the first drain region D1 can be higher than the carrier concentration of the first channel region CHA1.

[0121] The first insulating layer GI1 can be located on the substrate SUB and the first semiconductor layer SCL1. The first insulating layer GI1 can completely cover the first semiconductor layer SCL1.

[0122] The first conductive layer GTL1 may be located on the first insulating layer GI1. The first conductive layer GTL1 may include a conductive material. As an example, the first conductive layer GTL1 may include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and other metals, alloys thereof, or other conductive materials.

[0123] The first conductive layer GTL1 may include a first gate electrode GE1 contained in the first transistor T1 of the pixel PX.

[0124] The first gate electrode GE1 may overlap with the first channel region CHA1 and the first capacitor electrode CPE1 of the first active layer ACT1 on the third-direction DR3. The first gate electrode GE1 may be disposed separately from the first channel region CHA1 and the first capacitor electrode CPE1 of the first active layer ACT1.

[0125] The second insulating layer GI2 can be located on the first insulating layer GI1 and the first conductive layer GTL1. The second insulating layer GI2 can completely cover the first conductive layer GTL1.

[0126] The second conductive layer GTL2 may be located on the second insulating layer GI2. The second conductive layer GTL2 may include a conductive material. Examples of conductive materials are omitted.

[0127] The second conductive layer GTL2 may include the first capacitor electrode CPE1. When viewed in a plane, in Figure 7 The first capacitor electrode CPE1, shown in the two separate patterns, can be a connected electrode.

[0128] A first capacitor C1 can be formed between the first gate electrode GE1 and the first capacitor electrode CPE1. The first gate electrode GE1 and the first capacitor electrode CPE1 can respectively constitute the first electrode and the second electrode of the first capacitor C1.

[0129] The third insulating layer GI3 can be located on the second insulating layer GI2 and the second conductive layer GTL2. The third insulating layer GI3 can completely cover the second conductive layer GTL2.

[0130] The third conductive layer GTL3 may be located on the third insulating layer GI3. The third conductive layer GTL3 may include a conductive material. Examples of conductive materials are omitted.

[0131] The third conductive layer GTL3 may include a first lower gate electrode BG1 and a second lower gate electrode BG2. The first lower gate electrode BG1 may overlap with the second active layer ACT2 included in the second transistor T2 on the third-direction DR3, and the second lower gate electrode BG2 may overlap with the third active layer ACT3 included in the third transistor T3 on the third-direction DR3.

[0132] The fourth insulating layer GI4 can be located on the third insulating layer GI3 and the third conductive layer GTL3. The fourth insulating layer GI4 can completely cover the third conductive layer GTL3.

[0133] The second semiconductor layer SCL2 may be located on the fourth insulating layer GI4. The second semiconductor layer SCL2 may include a second active layer ACT2 contained in the second transistor T2 and a third active layer ACT3 contained in the third transistor T3.

[0134] The second semiconductor layer SCL2 may include a semiconductor material (for example, polycrystalline silicon, amorphous silicon, oxide semiconductor, or other semiconductor materials).

[0135] In one embodiment, the second active layer ACT2 and the third active layer ACT3 can be formed as a single unit. As an example, the second drain region D2 and the third source region S3 can be a single, integrated region.

[0136] The second active layer ACT2 may include a second channel region CHA2, a second source region S2, and a second drain region D2. The second channel region CHA2 may overlap with the second gate electrode GE2 included in the second transistor T2 on a third-direction DR3. The second channel region CHA2 may form a channel corresponding to the voltage applied to the second gate electrode GE2. The second source region S2 and the second drain region D2 may be disposed on opposite sides of the second channel region CHA2. The second source region S2 and the second drain region D2 may have higher conductivity than the second channel region CHA2.

[0137] The third active layer ACT3 may include a third channel region CHA3, a third source region S3, and a third drain region D3. The third channel region CHA3 may overlap with the third gate electrode GE3 included in the third transistor T3 on the third-direction DR3. The third channel region CHA3 may form a channel corresponding to the voltage applied to the third gate electrode GE3. The third source region S3 and the third drain region D3 may be disposed on both sides of the third channel region CHA3. The third source region S3 and the third drain region D3 may have higher conductivity than the third channel region CHA3.

[0138] In one embodiment, the second source region S2 can be electrically connected to the first gate electrode GE1 through the sixth conductive pattern CP6 and the third conductive pattern CP3.

[0139] The second drain region D2 can be integrated with the third source region S3. The second drain region D2 and the third source region S3 can be electrically connected to the second capacitor electrode CPE2.

[0140] The third drain region D3 can be connected to the first drain region D1 of the first active layer ACT1 through the fifth conductive pattern CP5 and the first conductive pattern CP1. Additionally, the third drain region D3 can be electrically connected to the anode electrode AE ​​of the light-emitting element ED through the fifth conductive pattern CP5 and the seventh conductive pattern CP7.

[0141] The fifth insulating layer GI5 can be located on the fourth insulating layer GI4 and the second semiconductor layer SCL2. The fifth insulating layer GI5 can completely cover the second semiconductor layer SCL2.

[0142] The fourth conductive layer GTL4 may be located on the fifth insulating layer GI5. The fourth conductive layer GTL4 may include a conductive material. Examples of conductive materials are omitted.

[0143] In one embodiment, the fourth conductive layer GTL4 may include a first conductive pattern CP1, a second conductive pattern CP2, a third conductive pattern CP3, a fourth conductive pattern CP4, a second gate electrode GE2, and a third gate electrode GE3. Description of the second gate electrode GE2 and the third gate electrode GE3 is omitted.

[0144] The first conductive pattern CP1 can be electrically connected to the first drain region D1 of the first active layer ACT1 by passing through multiple insulating layers disposed between the first semiconductor layer SCL1 and the fourth conductive layer GTL4. Specifically, the first conductive pattern CP1 can be electrically connected to the first drain region D1 through a first contact hole CH1 that passes through the first insulating layer GI1, the second insulating layer GI2, the third insulating layer GI3, the fourth insulating layer GI4, and the fifth insulating layer GI5. As an example, the first conductive pattern CP1 can be the drain electrode of the first transistor T1, or it can be regarded as a structure included in the first transistor T1.

[0145] The second conductive pattern CP2 can be electrically connected to the first source region S1 of the first active layer ACT1 by passing through multiple insulating layers disposed between the first semiconductor layer SCL1 and the fourth conductive layer GTL4. Specifically, the second conductive pattern CP2 can be electrically connected to the first source region S1 through a second contact hole CH2 that passes through the first insulating layer GI1, the second insulating layer GI2, the third insulating layer GI3, the fourth insulating layer GI4, and the fifth insulating layer GI5 together. In one embodiment, the second conductive pattern CP2 can be the source electrode of the first transistor T1, or it can be regarded as a structure included in the first transistor T1.

[0146] The third conductive pattern CP3 can be electrically connected to the first gate electrode GE1 by passing through multiple insulating layers disposed between the first conductive layer GTL1 and the fourth conductive layer GTL4. Specifically, the third conductive pattern CP3 can be electrically connected to the first gate electrode GE1 through the third contact hole CH3 formed in the second insulating layer GI2, the third insulating layer GI3, the fourth insulating layer GI4, and the fifth insulating layer GI5.

[0147] The fourth conductive pattern CP4 can be electrically connected to the first capacitor electrode CPE1 by penetrating multiple insulating layers disposed between the second conductive layer GTL2 and the fourth conductive layer GTL4. Specifically, the fourth conductive pattern CP4 can be electrically connected to the first capacitor electrode CPE1 through the fourth contact hole CH4 formed in the third insulating layer GI3, the fourth insulating layer GI4, and the fifth insulating layer GI5.

[0148] In one embodiment, the transistor layer TFTL includes a plurality of contact holes that can extend through a plurality of insulating layers. Each contact hole can have a depth corresponding to the thickness of the plurality of insulating layers. In other words, the plurality of contact holes in one embodiment of the transistor layer TFTL can include a deep and narrow width.

[0149] For example, the plurality of contact holes included in a transistor layer TFTL of one embodiment (for example, contact holes formed by penetrating at least three insulating layers) can have an aspect ratio (AR) of 0.6 or more. The aspect ratio (AR) can refer to the value of the contact hole depth divided by the contact hole width (for example, contact hole depth / contact hole width). For example, the width of each of the plurality of contact holes included in a display device 10 of one embodiment can be 2.0 micrometers or less, and the depth of each of the plurality of contact holes can be 1.2 micrometers or more. The aforementioned ranges of aspect ratio (AR), width, and depth of the contact holes can serve as key indicators for transistor layer TFTLs designed for high-resolution display devices.

[0150] In one embodiment, the first to fourth contact holes CH1, CH2, CH3, and CH4 can be formed by penetrating at least three insulating layers, thereby allowing the first to fourth contact holes CH1, CH2, CH3, and CH4 to have the aforementioned aspect ratio (AR), width range, and depth range of contact holes. (Repeated description omitted.)

[0151] The sixth insulating layer GI6 can be located on the fifth insulating layer GI5 and the fourth conductive layer GTL4. The sixth insulating layer GI6 can completely cover the fourth conductive layer GTL4.

[0152] The sixth insulating layer GI6 may comprise an inorganic insulating material. For example, the sixth insulating layer GI6 may comprise a silicon nitride (for example, Si3N4 or SiN...). X ), silicon oxide (for example, SiO2 or SiO), X ), silicon oxynitrides (as an example, SiON), titanium oxides, aluminum oxides, or other inorganic insulating materials.

[0153] The fifth conductive layer SDL1 may be located on the sixth insulating layer GI6. The fifth conductive layer SDL1 may include a conductive material. Examples of conductive materials are omitted.

[0154] The fifth conductive layer SDL1 may include a fifth conductive pattern CP5, a sixth conductive pattern CP6, and a second capacitor electrode CPE2.

[0155] The fifth conductive pattern CP5 can be electrically connected to the first conductive pattern CP1 by penetrating the insulating layer disposed between the fourth conductive layer GTL4 and the fifth conductive layer SDL1. Specifically, the fifth conductive pattern CP5 can be electrically connected to the first conductive pattern CP1 through the fifth contact hole CH5 penetrating the sixth insulating layer GI6. In addition, the fifth conductive pattern CP5 can be electrically connected to the third drain region D3 of the third active layer ACT3 through the sixth contact hole CH6 penetrating both the fifth insulating layer GI5 and the sixth insulating layer GI6.

[0156] In one embodiment, the fifth conductive pattern CP5 can be the drain electrode of the third transistor T3, or it can be considered as a structure included in the third transistor T3.

[0157] The sixth conductive pattern CP6 can be electrically connected to the third conductive pattern CP3 by penetrating the insulating layer disposed between the fourth conductive layer GTL4 and the fifth conductive layer SDL1. Specifically, the sixth conductive pattern CP6 can be electrically connected to the third conductive pattern CP3 through the seventh contact hole CH7 penetrating the sixth insulating layer GI6. Additionally, the sixth conductive pattern CP6 can be electrically connected to the second source region S2 through the eighth contact hole CH8 penetrating both the fifth insulating layer GI5 and the sixth insulating layer GI6. In one embodiment, the sixth conductive pattern CP6 can be the source electrode of the second transistor T2, or it can be considered as a structure included within the second transistor T2.

[0158] In one embodiment, the second capacitor electrode CPE2 may overlap with the data line DL connected to the pixel PX. The second capacitor electrode CPE2 and the data line DL may form a second capacitor C2. The second capacitor electrode CPE2 and the data line DL may respectively constitute the first electrode and the second electrode of the second capacitor C2.

[0159] The second capacitor electrode CPE2 can penetrate multiple insulating layers disposed between the second semiconductor layer SCL2 and the fifth conductive layer SDL1 to be electrically connected to the second drain region D2 of the second active layer ACT2 and the third source region S3 of the third active layer ACT3.

[0160] In one embodiment, the second capacitor electrode CPE2 can be the drain electrode of the second transistor T2 and the source electrode of the third transistor T3, or it can be regarded as a structure included in the second transistor T2 and the third transistor T3.

[0161] In one embodiment, the aspect ratio (AR), depth range, and width range of the fifth to ninth contact holes CH5, CH6, CH7, CH8, CH9 are not limited to specific ranges.

[0162] The first interlayer insulating layer ILD1 can be located on the sixth insulating layer GI6 and the fifth conductive layer SDL1. The first interlayer insulating layer ILD1 can completely cover the fifth conductive layer SDL1.

[0163] The first interlayer insulating layer ILD1 may include an inorganic insulating material. For example, the first interlayer insulating layer ILD1 may include a silicon nitride (for example, Si3N4 or SiN...). X ), silicon oxide (for example, SiO2 or SiO), X), silicon oxynitrides (as an example, SiON), titanium oxides, aluminum oxides, or other inorganic insulating materials.

[0164] The sixth conductive layer SDL2 may be located on the first interlayer insulating layer ILD1. The sixth conductive layer SDL2 may include a conductive material. Examples of conductive materials are omitted.

[0165] The sixth conductive layer SDL2 may include a data line DL connected to pixel PX. The data line DL may form a second capacitor C2 together with the second capacitor electrode CPE2. (Repeated description omitted.)

[0166] The second interlayer insulating layer ILD2 can be located on the first interlayer insulating layer ILD1 and the sixth conductive layer SDL2. The second interlayer insulating layer ILD2 can completely cover the sixth conductive layer SDL2.

[0167] The second interlayer insulation layer ILD2 may include the inorganic insulating material included in the first interlayer insulation layer ILD1. Examples of inorganic insulating materials are omitted.

[0168] The seventh conductive layer SDL3 may be located on the second interlayer insulating layer ILD2. The seventh conductive layer SDL3 may include a conductive material. Examples of conductive materials are omitted.

[0169] The seventh conductive layer SDL3 may include a seventh conductive pattern CP7, an eighth conductive pattern CP8, and a ninth conductive pattern CP9.

[0170] The seventh conductive pattern CP7 can be electrically connected to the fifth conductive pattern CP5 by passing through multiple insulating layers disposed between the fifth conductive layer SDL1 and the seventh conductive layer SDL3. Specifically, the seventh conductive pattern CP7 can be electrically connected to the fifth conductive pattern CP5 through the tenth contact hole CH10 passing through the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2. The seventh conductive pattern CP7 can be electrically connected to the first conductive pattern CP1 and the first drain region D1 of the first active layer ACT1 through the fifth conductive pattern CP5.

[0171] In one embodiment, the aspect ratio (AR), width, and depth of the tenth contact hole CH10 are not limited.

[0172] The eighth conductive pattern CP8 may be located on the second interlayer insulating layer ILD2. The eighth conductive pattern CP8 may include a conductive material. Examples of conductive materials are omitted.

[0173] The eighth conductive pattern CP8 can be the voltage line of pixel PX.

[0174] The eighth conductive pattern CP8 can be electrically connected to the second conductive pattern CP2 by passing through multiple insulating layers disposed between the fourth conductive layer GTL4 and the seventh conductive layer SDL3. Specifically, the eighth conductive pattern CP8 can be electrically connected to the second conductive pattern CP2 through the eleventh contact hole CH11 formed in the sixth insulating layer GI6, the first interlayer insulating layer ILD1, and the second interlayer insulating layer ILD2. The eighth conductive pattern CP8 can be electrically connected to the first source region S1 of the first active layer ACT1 through the second conductive pattern CP2.

[0175] The ninth conductive pattern CP9 may be located on the second interlayer insulating layer ILD2. The ninth conductive pattern CP9 may include a conductive material. Examples of conductive materials are omitted. As an example, the ninth conductive pattern CP9 may be the initialization voltage line of pixel PX.

[0176] The ninth conductive pattern CP9 can be electrically connected to the fourth conductive pattern CP4 by passing through multiple insulating layers disposed between the fourth conductive layer GTL4 and the seventh conductive layer SDL3. Specifically, the ninth conductive pattern CP9 can be electrically connected to the fourth conductive pattern CP4 through the twelfth contact hole CH12 formed in the sixth insulating layer GI6, the first interlayer insulating layer ILD1, and the second interlayer insulating layer ILD2. The ninth conductive pattern CP9 can be electrically connected to the first capacitor electrode CPE1 through the fourth conductive pattern CP4.

[0177] In one embodiment, the eleventh contact hole CH11 and the twelfth contact hole CH12 can be formed through at least three insulating layers, thereby allowing the eleventh contact hole CH11 and the twelfth contact hole CH12 to have the aforementioned aspect ratio (AR), width range, and depth range of contact holes. (Repeated description omitted.)

[0178] The via layer VIA can be located on the second interlayer insulating layer ILD2 and the seventh conductive layer SDL3. The via layer VIA can completely cover the seventh conductive layer SDL3.

[0179] The through-pore layer (VIA) may include organic materials. For example, the through-pore layer (VIA) may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0180] The display element layer (EML) can be disposed on the transistor layer (TFTL). The display element layer (EML) may include a light-emitting element (ED) and a pixel-defining layer (PDL). The light-emitting element (ED) may include an anode electrode (AE), a light-emitting layer (EL), and a cathode electrode (CE).

[0181] The anode electrode AE ​​of the light-emitting element ED can be located on the via layer VIA. The anode electrode AE ​​can be connected to the seventh conductive pattern CP7 of the seventh conductive layer SDL3 through the anode contact hole VH that penetrates the via layer VIA.

[0182] The anode electrode AE ​​can be formed from a single layer of silver (Ag), molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al). Alternatively, to improve reflectivity, it can be formed from a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, or a stacked structure of APC alloy and ITO (ITO / APC / ITO). The APC alloy can be an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0183] The pixel delimiting layer (PDL) can be located on the via layer (VIA). The PDL can define the light-emitting region (EA), exposing the anode electrode (AE) at the portion overlapping with the light-emitting region (EA). The PDL can cover the edge of the anode electrode (AE).

[0184] The pixel boundary layer (PDL) can include organic or inorganic materials.

[0185] As an example, when the pixel defining layer (PDL) includes organic materials, the PDL may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0186] As an example, when the pixel boundary layer (PDL) includes inorganic materials, the PDL may include silicon nitrides (for example, Si3N4 or SiN). X ), silicon oxide (for example, SiO2 or SiO), X ), silicon oxynitrides (as an example, SiON), titanium oxides, aluminum oxides, or other inorganic insulating materials.

[0187] The light-emitting layer (EL) of a light-emitting element (ED) can be located on the anode electrode (AE). The EL can include organic materials to emit light of a predetermined color. For example, the EL can include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer can include a substrate and a dopant. The organic material layer can include a substance that emits the predetermined light, and can be formed using phosphorescent or fluorescent materials.

[0188] The cathode electrode CE of the light-emitting element ED can be located on the light-emitting layer EL. The cathode electrode CE can be configured to cover the light-emitting layer EL. The cathode electrode CE can be a common layer commonly disposed on multiple light-emitting layers EL.

[0189] The cathode electrode (CE) can be formed from transparent conductive materials such as ITO and IZO (TCO), semi-transmissive conductive materials such as magnesium (Mg), silver (Ag), or alloys of magnesium (Mg) and silver (Ag). When the cathode electrode (CE) is formed from a semi-transmissive metallic material, the light extraction efficiency can be improved through a microcavity.

[0190] The encapsulation layer TFEL can be formed on the display element layer EML. To prevent oxygen or moisture from penetrating into the display element layer EML, the encapsulation layer TFEL may include at least one inorganic film, and to protect the display element layer EML from foreign matter such as dust, it may include at least one organic film.

[0191] The encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3.

[0192] The first encapsulation layer TFE1 can be located on the cathode electrode CE and can completely cover the cathode electrode CE.

[0193] The first encapsulation layer TFE1 may include an inorganic insulating material, for example, it may include silicon nitride (for example, Si3N4 or SiN). X ), silicon oxide (for example, SiO2 or SiO), X ), silicon oxynitrides (as an example, SiON), titanium oxides, aluminum oxides, or other inorganic insulating materials.

[0194] The second encapsulation layer TFE2 can be located on the first encapsulation layer TFE1 and can completely cover the first encapsulation layer TFE1. The second encapsulation layer TFE2 can flatten the steps formed by the first encapsulation layer TFE1.

[0195] The second encapsulation layer TFE2 may include organic materials, such as acrylic resin, epoxy resin, silicone resin, silicone-acrylresin, phenolic resin, polyamide resin, and polyimide resin.

[0196] The third encapsulation layer TFE3 can be located on the second encapsulation layer TFE2 and can completely cover the second encapsulation layer TFE2.

[0197] The third encapsulation layer TFE3 may include inorganic insulating materials, such as silicon nitrides (e.g., Si3N4 or SiN). X ), silicon oxide (for example, SiO2 or SiO), X ), silicon oxynitrides (as an example, SiON), titanium oxides, aluminum oxides, or other inorganic insulating materials.

[0198] In one embodiment, the display device 10 may also further include an optical layer disposed on the encapsulation layer TFEL. The optical layer may include at least one of a color filter layer (for example, a color filter layer including color filters corresponding to the emission color of each of the pixels PX) and a light conversion layer (for example, a light conversion layer including a wavelength conversion pattern that converts the color or wavelength of light emitted from at least a portion of the light-emitting elements ED of the pixels PX).

[0199] Figure 8 It is magnification Figure 7 A cross-sectional view of the "A1" region in the diagram.

[0200] Apart from Figures 1 to 7 In addition, refer to Figure 8 The first contact hole CH1 can be formed to extend through the first to fifth insulating layers GI1, GI2, GI3, GI4, and GI5. As previously described, a display device 10 of one embodiment may include a contact hole with a narrow and deep shape. Therefore, the step coverage characteristic of the conductive pattern covering the interior of the contact hole in one embodiment can be relatively lower in the lower region compared to the upper region of the contact hole. This will be described in detail below.

[0201] The aspect ratio (AR) of the first contact hole CH1 can be defined as the value of dividing the depth Dch1 of the first contact hole CH1 by the width Wch1 of the first contact hole CH1 (for example, depth Dch1 / width Wch1).

[0202] In one embodiment, the aspect ratio (AR) of the first contact hole CH1 can be 0.6 or higher. Furthermore, the width Wch1 of the first contact hole CH1 can be 2.0 micrometers or less, and the depth Dch1 can be 1.2 micrometers or more.

[0203] In one embodiment, the first contact hole CH1 may include a lower region Lch1 and an upper region Uch1. The lower region Lch1 of the first contact hole CH1 may be a portion relatively close to the substrate SUB, and the upper region Uch1 of the first contact hole CH1 may be a portion relatively far from the substrate SUB.

[0204] In one embodiment, the first insulating layer GI1 and the second insulating layer GI2 may be located in the portion overlapping with the lower region Lch1 of the first contact hole CH1, and the third insulating layer GI3, the fourth insulating layer GI4 and the fifth insulating layer GI5 may be located in the portion overlapping with the upper region Uch1 of the first contact hole CH1.

[0205] The first active layer ACT1 can be disposed in contact with the substrate SUB. For ease of explanation, the portion overlapping the first drain region D1 of the first active layer ACT1 is shown in enlarged form for explanation, but the structure of the applicable embodiment is not limited thereto. As an example, the first source region S1 of the first active layer ACT1 located in the portion overlapping the second contact hole CH2 can have the same structure and features as the first drain region D1 of the first active layer ACT1 overlapping the first contact hole CH1.

[0206] The first active layer ACT1 may include a semiconductor material (for example, polysilicon). The first active layer ACT1 may have high mobility by including a polysilicon semiconductor material.

[0207] In one embodiment, the first active layer ACT1 may include a first surface dd1. The first surface dd1 may be the side facing the first insulating layer GI1.

[0208] The first surface dd1 of the first active layer ACT1 may include a recess rr1 at the portion overlapping with the first contact hole CH1. The recess rr1 may refer to a portion of the first surface dd1 overlapping with the first contact hole CH1 that is recessed towards the substrate SUB. The recess rr1 of the first active layer ACT1 may be formed during the manufacturing process of the display device 10 by performing a dry etching process. The manufacturing process will be described below.

[0209] The first active layer ACT1 may have a first height Hd11 overlapping with the recess rr1 and a second height Hd12 not overlapping with the recess rr1. The first height Hd11 and the second height Hd12 may be different from each other. As an example, the first height Hd11 may be lower than the second height Hd12.

[0210] In the first direction DR1, the width Wrr1 of the recess rr1 can be smaller than the width Wch1 of the first contact hole CH1. Therefore, the first active layer ACT1 can have a stepped shape at the portion overlapping with the first contact hole CH1.

[0211] The first insulating layer GI1 may be located on the first active layer ACT1. The first insulating layer GI1 may be disposed adjacent to the first active layer ACT1. The first insulating layer GI1 may not overlap with the recess rr1 of the first active layer ACT1 in the third direction DR3.

[0212] The first insulating layer GI1 may define a first opening OP1 at the portion overlapping with the first contact hole CH1, and the first insulating layer GI1 may be disposed around the first opening OP1. The first insulating layer GI1 may expose the first active layer ACT1 at the portion overlapping with the first opening OP1. Specifically, the first insulating layer GI1 may expose the recess rr1 of the first active layer ACT1 at the portion overlapping with the first opening OP1.

[0213] The first insulating layer GI1 may comprise an inorganic insulating material. For example, the first insulating layer GI1 may comprise silicon oxide (for example, SiO2 or SiO2). X ).

[0214] The first insulating layer GI1 can improve the characteristics of the polysilicon included in the first semiconductor layer SCL1 while performing the insulation function of the first semiconductor layer SCL1 and the first conductive layer GTL1.

[0215] The second insulating layer GI2 may be located on the first insulating layer GI1. The second insulating layer GI2 may be disposed adjacent to the first insulating layer GI1. The second insulating layer GI2 may not overlap with the recess rr1 of the first active layer ACT1 in the third direction DR3.

[0216] The second insulating layer GI2 can define the second opening OP2 at the portion that overlaps with the first contact hole CH1, and the second insulating layer GI2 can be arranged around the second opening OP2.

[0217] In one embodiment, the width Wop2 of the second opening OP2 defined by the second insulating layer GI2 can be greater than the width Wop1 of the first opening OP1 defined by the first insulating layer GI1. The difference between the width Wop2 of the second opening OP2 and the width Wop1 of the first opening OP1 can be a value greater than 10 angstroms and less than 300 angstroms. Figure 8 In the figure, the reference numeral Wst can have a value that is half the difference between the width of the second opening Wop2 and the width of the first opening Wop1.

[0218] The second insulating layer GI2 may include an inorganic insulating material. However, the second insulating layer GI2 may include an inorganic insulating material that is different from that of the first insulating layer GI1. For example, the second insulating layer GI2 may include a silicon nitride (for example, Si3N4 or SiN). X ).

[0219] The second insulating layer GI2 can have higher moisture-proof properties than the first insulating layer GI1, while performing the insulating function of the first conductive layer GTL1 and the second conductive layer GTL2.

[0220] In one embodiment, the side gg11 of the first insulating layer GI1 may protrude toward the first contact hole CH1 in a direction greater than the side gg21 of the second insulating layer GI2. Thus, the first insulating layer GI1 and the second insulating layer GI2 can form a stepped structure.

[0221] In other words, the display device 10 of one embodiment may include a stepped portion rr1 in which a first active layer ACT1, a first insulating layer GI1 and a second insulating layer GI2 are sequentially formed at the portion overlapping with the lower region Lch1 of the first contact hole CH1.

[0222] Figure 9 It is used as a comparative example for magnification. Figure 8 A cross-sectional view of the lower region of the first contact hole.

[0223] Reference Figure 8 as well as Figure 9 The first contact hole CH1 included in the comparative example display device EX may have the same aspect ratio (AR), width and depth as the first contact hole CH1 included in the display device 10.

[0224] Furthermore, the first active layer ACT1 included in the comparative example display device EX may have the same structure and features as the first active layer ACT1 included in the display device 10. As an example, the first active layer ACT1 may include a recess rr1 at the portion overlapping with the first contact hole CH1, and the first active layer ACT1 may have a stepped step at the portion overlapping with the first contact hole CH1 along with the recess rr1.

[0225] Furthermore, the first insulating layer GI1 and the second insulating layer GI2 included in the comparative example display device EX may include the same material as the first insulating layer GI1 and the second insulating layer GI2 included in the display device 10.

[0226] The following description of the common structure of the display device EX and the display device 10 for the comparative example will be omitted, and the differences will be described below.

[0227] In the comparative example display device EX, the first insulating layer GI1 can define a first opening OP1c at the portion overlapping with the first contact hole CH1, and the first insulating layer GI1 can be disposed around the first opening OP1c. The first insulating layer GI1 can expose a recess rr1 of the first active layer ACT1 at the portion overlapping with the first opening OP1c.

[0228] The second insulating layer GI2 can be located on the first insulating layer GI1. The second insulating layer GI2 can be disposed adjacent to the first insulating layer GI1.

[0229] In the comparative example display device EX, the second insulating layer GI2 can define a second opening OP2c at the portion overlapping with the first contact hole CH1, and the second insulating layer GI2 can be disposed around the second opening OP2c. The width Wop2c of the second opening OP2c included in the comparative example display device EX can be smaller than the width Wop1c of the first opening OP1c.

[0230] In the comparative example display device EX, the side cc21 of the second insulating layer GI2 can protrude towards the first contact hole CH1 compared to the side cc11 of the first insulating layer GI1. Therefore, an undercut can be formed between the side cc11 of the first insulating layer GI1 and the second insulating layer GI2. In other words, the first insulating layer GI1 and the second insulating layer GI2 included in the comparative example display device EX can form a suspended structure.

[0231] In the manufacturing process of the comparative example display device EX, the first insulating layer GI1 and the second insulating layer GI2 are cleaned using a wet buffered oxide etchant (BOE), so that the first insulating layer GI1 and the second insulating layer GI2 can have an undercut shape.

[0232] For example, when an undercut is formed between the first insulating layer GI1 and the second insulating layer GI2 in the portion overlapping with the lower region Lch1 of the first contact hole CH1, the step coverage characteristics of the first conductive pattern CP1 may be significantly reduced in the portion overlapping with the undercut.

[0233] A decrease in the step coverage characteristics of the first conductive pattern CP1 may lead to poor contact of the first conductive pattern CP1. As an example, poor contact may include defects such as the thickness of the first conductive pattern CP1 being too thin to a suitable range, and defects such as broken lines in the first conductive pattern CP1.

[0234] Therefore, one embodiment of the display device 10 can propose a structure in which the portion overlapping with the lower region Lch1 of the first contact hole CH1 is located between the first insulating layer GI1 and the second insulating layer GI2 without undercutting.

[0235] Refer again Figure 8 In one embodiment of the display device 10, at the portion overlapping with the lower region Lch1 of the first contact hole CH1, the first insulating layer GI1 is formed to protrude towards the first contact hole CH1 more than the second insulating layer GI2, thereby structurally improving the step coverage characteristics of the first conductive pattern CP1 at the portion overlapping with the lower region Lch1. Therefore, in one embodiment, the first conductive pattern CP1 can completely cover the recessed portion rr1 of the first active layer ACT1, the first insulating layer GI1, and the second insulating layer GI2 at the portion overlapping with the lower region Lch1 without poor contact.

[0236] In one embodiment, the third insulating layer GI3, the fourth insulating layer GI4, and the fifth insulating layer GI5 may be located in the portion that overlaps with the upper region Uch1 of the first contact hole CH1.

[0237] The third insulating layer GI3 may be located on the second insulating layer GI2. The third insulating layer GI3 may be disposed adjacent to the second insulating layer GI2. The third insulating layer GI3 may not overlap with the recess rr1 of the first active layer ACT1 in the third direction DR3.

[0238] The third insulating layer GI3 may include an inorganic insulating material. For example, the third insulating layer GI3 may include a silicon nitride (for example, Si3N4 or SiN...). X ).

[0239] The third insulating layer GI3 can have high moisture-proof properties while performing the insulating functions of the second conductive layer GTL2 and the third conductive layer GTL3.

[0240] The third insulating layer GI3 can define the second opening OP2 at the portion that overlaps with the first contact hole CH1, and the third insulating layer GI3 can be arranged around the second opening OP2.

[0241] In one embodiment, the side gg31 of the third insulating layer GI3 may be on the same line as the side gg21 of the second insulating layer GI2.

[0242] Since the second insulating layer GI2 and the third insulating layer GI3 both comprise the same material, they can have the same etching rate regardless of process conditions when a dry cleaning process is performed in the manufacturing process of the display device 10. Therefore, the side surface gg31 of the third insulating layer GI3 can be located on the same line as the side surface gg21 of the second insulating layer GI2. The aforementioned "on the same line" means that there can be a process deviation of up to 10%.

[0243] The fourth insulating layer GI4 may be located on the third insulating layer GI3. The fourth insulating layer GI4 may be disposed adjacent to the third insulating layer GI3. The fourth insulating layer GI4 may not overlap with the recess rr1 of the first active layer ACT1 on the third direction DR3.

[0244] The fourth insulating layer GI4 may comprise an inorganic insulating material. For example, the fourth insulating layer GI4 may comprise silicon oxide (for example, SiO2 or SiO2). X ) and silicon nitrides (for example, Si3N4 or SiN X At least one of them.

[0245] Figure 10 This is an enlarged version of another embodiment. Figure 7 A cross-sectional view of the "A1" region in the diagram.

[0246] Reference Figure 8 as well as Figure 10 The fourth insulating layer GI4 can have various structural features depending on the materials it contains.

[0247] For example, when the fourth insulating layer GI4 comprises silicon oxide (for example, SiO2 or SiO2), X When, such as Figure 8 As shown, the fourth insulating layer GI4 can define the first opening OP1 at the portion overlapping with the first contact hole CH1, and the fourth insulating layer GI4 can be disposed around the first opening OP1.

[0248] At this time, the side gg41 of the fourth insulating layer GI4 can protrude in the direction toward the first contact hole CH1 than the side gg31 of the third insulating layer GI3, and an undercut can be formed between the side gg31 of the third insulating layer GI3 and the fourth insulating layer GI4.

[0249] In some embodiments, the third insulating layer GI3 and the fourth insulating layer GI4, being composed of different materials, can have different etching rates depending on the process conditions when a dry cleaning process is performed in the manufacturing process of the display device 10. Thus, an undercut can be formed between the side gg31 of the third insulating layer GI3 and the fourth insulating layer GI4.

[0250] For example, when the fourth insulating layer GI4 comprises silicon nitride (for example, Si3N4 or SiN...) X When, such as Figure 10 As shown, the fourth insulating layer GI4 included in the display device 10a can define the second opening OP2 at the portion overlapping with the first contact hole CH1, and the fourth insulating layer GI4 can be disposed around the second opening OP2.

[0251] At this time, the side gg41 of the fourth insulating layer GI4 included in the display device 10a can be located on the same line as the side gg31 of the third insulating layer GI3.

[0252] In some embodiments, since the third insulating layer GI3 and the fourth insulating layer GI4 both comprise the same material, they can have the same etching rate regardless of process conditions when a dry cleaning process is performed in the manufacturing process of the display device 10a. Therefore, the side surface gg31 of the third insulating layer GI3 can be located on the same line as the side surface gg41 of the fourth insulating layer GI4. The aforementioned "on the same line" means that there can be a process deviation of up to 10%.

[0253] In one embodiment, the fifth insulating layer GI5 may be located on the fourth insulating layer GI4. The fifth insulating layer GI5 may be disposed adjacent to the fourth insulating layer GI4. The fifth insulating layer GI5 may not overlap with the recess rr1 of the first active layer ACT1 in the third direction DR3.

[0254] The fifth insulating layer GI5 may comprise an inorganic insulating material. For example, the fifth insulating layer GI5 may comprise silicon oxide (for example, SiO2 or SiO2). X ).

[0255] The fifth insulating layer GI5 can define the first opening OP1 at the portion that overlaps with the first contact hole CH1, and the fifth insulating layer GI5 can be disposed around the first opening OP1.

[0256] In some embodiments, when the fourth insulating layer GI4 comprises silicon oxide (for example, SiO2 or SiO2), X When, such as Figure 8 As shown, the side gg51 of the fifth insulating layer GI5 can be on the same line as the side gg41 of the fourth insulating layer GI4. The aforementioned "on the same line" means that there can be a process deviation within 10%. (Repeated explanation omitted.)

[0257] In some embodiments, when the fourth insulating layer GI4 comprises silicon nitride (for example, Si3N4 or SiN), X When, such as Figure 10As shown, the side surface gg51 of the fifth insulating layer GI5 included in the display device 10a may protrude in the direction toward the first contact hole CH1 compared to the side surface gg41 of the fourth insulating layer GI4. Therefore, an undercut can be formed between the fifth insulating layer GI5 and the fourth insulating layer GI4 included in the display device 10a in the direction toward the first contact hole CH1. (Repeated description omitted.)

[0258] As previously stated, the first conductive pattern CP1 can have a relatively higher step coverage characteristic than the lower region Lch1 of the first contact hole CH1 at the portion overlapping with the upper region Uch1. Therefore, even if an undercut is formed between the third insulating layer GI3, the fourth insulating layer GI4, and the fifth insulating layer GI5 at the portion overlapping with the upper region Uch1, the first conductive pattern CP1 can cover the third insulating layer GI3, the fourth insulating layer GI4, and the fifth insulating layer GI5 without poor contact.

[0259] The first conductive pattern CP1 can be formed with a uniform thickness along the contour of the underlying structure. Thus, the first conductive pattern CP1 can include a step at the portion overlapping with the first contact hole CH1. At the portion overlapping with the first contact hole CH1, the step formed by the first conductive pattern CP1 can be planarized by the sixth insulating layer GI6.

[0260] Figure 11 This is an enlarged version of yet another embodiment. Figure 7 A cross-sectional view of the "A1" region in the diagram.

[0261] Apart from Figures 1 to 10 In addition, refer to Figure 11 The first contact hole CH1 included in the display device 10s may have the same aspect ratio (AR), width and depth as the first contact hole CH1 included in the display device 10.

[0262] Furthermore, the first active layer ACT1 included in the display device 10s may have the same structure and features as the first active layer ACT1 included in the display device 10. As an example, the first active layer ACT1 may include a recess rr1 at the portion overlapping with the first contact hole CH1, and the first active layer ACT1 may have a stepped step at the portion overlapping with the first contact hole CH1 along with the recess rr1.

[0263] Furthermore, the first insulating layer GI1 and the second insulating layer GI2 included in the display device 10s may be located in the portion overlapping with the lower region Lch1 of the first contact hole CH1, and the third insulating layer GI3, the fourth insulating layer GI4 and the fifth insulating layer GI5 may be located in the portion overlapping with the upper region Uch1 of the first contact hole CH1.

[0264] The following description of the common structure of display device 10s and display device 10 will be omitted, and the differences will be described below.

[0265] The first insulating layer GI1 included in the display device 10s can define a third opening OP3 at the portion overlapping with the first contact hole CH1, and the first insulating layer GI1 can be disposed around the third opening OP3. The first insulating layer GI1 can expose the first active layer ACT1 at the portion overlapping with the third opening OP3. Specifically, the first insulating layer GI1 can expose the recess rr1 of the first active layer ACT1 at the portion overlapping with the third opening OP3.

[0266] The width Wop3 of the third opening OP3 included in the display device 10s can be the same as the width Wch1 of the first contact hole CH1.

[0267] The first insulating layer GI1 included in the display device 10s may include the same material as the first insulating layer GI1 included in the display device 10.

[0268] The second insulating layer GI2 included in the display device 10s can be located on the first insulating layer GI1. The second insulating layer GI2 can be disposed in conjunction with the first insulating layer GI1.

[0269] The second insulating layer GI2 can define the third opening OP3 at the portion that overlaps with the first contact hole CH1, and the second insulating layer GI2 can be arranged around the third opening OP3.

[0270] The second insulating layer GI2 included in the display device 10s may include the same material as the second insulating layer GI2 included in the display device 10.

[0271] The side surface ss11 of the first insulating layer GI1 included in the display device 10s can be on the same line as the side surface ss21 of the second insulating layer GI2. The aforementioned "on the same line" means that there can be a process deviation of less than 10%.

[0272] The third insulating layer GI3 included in the display device 10s can be located on the second insulating layer GI2. The third insulating layer GI3 can be disposed in conjunction with the second insulating layer GI2.

[0273] The third insulating layer GI3 can define the third opening OP3 at the portion that overlaps with the first contact hole CH1, and the third insulating layer GI3 can be arranged around the third opening OP3.

[0274] The third insulating layer GI3 included in the display device 10s may include the same material as the third insulating layer GI3 included in the display device 10.

[0275] The side surface ss21 of the second insulating layer GI2 included in the display device 10s can be on the same line as the side surface ss31 of the third insulating layer GI3. The aforementioned "on the same line" means that there can be a process deviation of less than 10%.

[0276] The fourth insulating layer GI4 included in the display device 10s can be located on the third insulating layer GI3. The fourth insulating layer GI4 can be disposed in conjunction with the third insulating layer GI3.

[0277] The fourth insulating layer GI4 can define the third opening OP3 at the portion that overlaps with the first contact hole CH1, and the fourth insulating layer GI4 can be disposed around the third opening OP3.

[0278] The fourth insulating layer GI4 included in the display device 10s may include the same material as the fourth insulating layer GI4 included in the display device 10.

[0279] The side surface ss31 of the third insulating layer GI3 included in the display device 10s can be on the same line as the side surface ss41 of the fourth insulating layer GI4. The aforementioned "on the same line" means that there can be a process deviation of less than 10%.

[0280] The fifth insulating layer GI5 included in the display device 10s can be located on the fourth insulating layer GI4. The fifth insulating layer GI5 can be disposed in conjunction with the fourth insulating layer GI4.

[0281] The fifth insulating layer GI5 can define the third opening OP3 at the portion that overlaps with the first contact hole CH1, and the fifth insulating layer GI5 can be arranged around the third opening OP3.

[0282] The fifth insulating layer GI5 included in the display device 10s may include the same material as the fifth insulating layer GI5 included in the display device 10.

[0283] The side surface ss41 of the fourth insulating layer GI4 included in the display device 10s can be on the same line as the side surface ss51 of the fifth insulating layer GI5. The aforementioned "on the same line" means that there can be a process deviation of less than 10%.

[0284] One embodiment of the display device 10s solves the problem of poor contact of the first conductive pattern CP1 by proposing a structure in which the portion overlapping with the lower region Lch1 of the first contact hole CH1 is located between the first insulating layer GI1 and the second insulating layer GI2 without undercutting.

[0285] Specifically, in one embodiment of the display device 10s, at the portion overlapping with the lower region Lch1 of the first contact hole CH1, the side surface ss11 of the first insulating layer GI1 and the side surface ss21 of the second insulating layer GI2 are located on the same line, thereby structurally improving the step coverage characteristics of the first conductive pattern CP1.

[0286] Therefore, the first conductive pattern CP1 at the portion overlapping with the lower region Lch1 can completely cover the recess rr1 of the first active layer ACT1, the first insulating layer GI1, and the second insulating layer GI2 without poor contact.

[0287] The first to fifth insulating layers GI1, GI2, GI3, GI4, and GI5 included in the display device 10s can be dry-cleaned at a specific temperature during the manufacturing process of the display device 10s. Therefore, even if the first to fifth insulating layers GI1, GI2, GI3, GI4, and GI5 included in the display device 10s are made of different materials or the same materials, they can have the same etching rate during the dry-cleaning process. The manufacturing process will be described below.

[0288] Figure 12 It is magnification Figure 7 A cross-sectional view of the "A3" region in the diagram.

[0289] Apart from Figures 1 to 11 In addition, refer to Figure 12 In one embodiment, the third contact hole CH3 can be formed to extend through the second to fifth insulating layers GI2, GI3, GI4, and GI5 together.

[0290] In one embodiment, the aspect ratio (AR) of the third contact hole CH3 can be 0.6 or higher. The width Wch3 of the third contact hole CH3 can be 2.0 micrometers or less, and the depth Dch3 can be 1.2 micrometers or more.

[0291] The third contact hole CH3 may include a lower region Lch3 and an upper region Uch3. The lower region Lch3 of the third contact hole CH3 may be a portion relatively close to the first gate electrode GE1, and the upper region Uch3 of the third contact hole CH3 may be a portion relatively far away from the first gate electrode GE1.

[0292] In one embodiment, the second insulating layer GI2 and the third insulating layer GI3 may be located in the portion overlapping with the lower region Lch3 of the third contact hole CH3, and the fourth insulating layer GI4 and the fifth insulating layer GI5 may be located in the portion overlapping with the upper region Uch3 of the third contact hole CH3.

[0293] The structure and features of the second to fifth insulating layers GI2, GI3, GI4, and GI5 at the portion overlapping with the third contact hole CH3 and the peripheral area of ​​the third contact hole CH3 can be the same as the structure and features of the second to fifth insulating layers GI2, GI3, GI4, and GI5 at the portion overlapping with the first contact hole CH1 and the peripheral area of ​​the first contact hole CH1.

[0294] Specifically, the second insulating layer GI2 and the third insulating layer GI3 may comprise silicon nitrides (for example, Si3N4 or SiN). X The second insulating layer GI2 and the third insulating layer GI3 may define the second opening OP2 at the portion overlapping with the third contact hole CH3, and the second insulating layer GI2 and the third insulating layer GI3 may be arranged around the second opening OP2. The side surface gg21 of the second insulating layer GI2 and the side surface gg31 of the third insulating layer GI3 may be located on the same line and may have a process deviation of less than 10%.

[0295] Repeated descriptions of the fourth insulating layer GI4 and the fifth insulating layer GI5 are omitted.

[0296] One embodiment of the display device 10 solves the problem of poor contact of the third conductive pattern CP3 by proposing a structure in which the portion overlapping with the lower region Lch3 of the third contact hole CH3 is located between the second insulating layer GI2 and the third insulating layer GI3 without undercutting.

[0297] Specifically, in one embodiment of the display device 10, at the portion overlapping with the lower region Lch3 of the third contact hole CH3, the side surface gg21 of the second insulating layer GI2 and the side surface gg31 of the third insulating layer GI3 are located on the same line, thereby structurally improving the step coverage characteristics of the third conductive pattern CP3.

[0298] Therefore, the third conductive pattern CP3 at the portion overlapping with the lower region Lch3 can completely cover the first gate electrode GE1, the second insulating layer GI2, and the third insulating layer GI3 without poor contact.

[0299] The third conductive pattern CP3 can be formed with a uniform thickness along the contour of the underlying structure. Therefore, the third conductive pattern CP3 can include a step at the portion overlapping with the third contact hole CH3. At the portion overlapping with the third contact hole CH3, the step formed by the third conductive pattern CP3 can be planarized by the sixth insulating layer GI6.

[0300] Figure 13 It is shown Figure 7 A flowchart of the manufacturing process of the first conductive pattern and the second conductive pattern that overlap with the first contact hole and the second contact hole.

[0301] Reference Figure 13 According to one embodiment, the display device 10 (refer to...) Figure 4 The manufacturing method FC may include the steps of forming a plurality of insulating layers on a substrate including a semiconductor layer (S100), performing a dry etching process to remove a portion of the insulating layer (S200), performing a dry cleaning process to form a contact hole (S300), and forming a conductive pattern in the portion overlapping with the contact hole (S400).

[0302] Figure 14 It is shown Figure 13 A cross-sectional view of step S100.

[0303] Apart from Figures 1 to 13 In addition, refer to Figure 14 This describes the step of forming multiple insulating layers on a substrate including a semiconductor layer (S100).

[0304] First, a first active layer ACT1, comprising a first semiconductor layer SCL1, is formed on a substrate SUB. The first active layer ACT1 can be divided into multiple regions having different characteristics. For example, the first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1. The first source region S1 and the first drain region D1 may be regions that are more conductive than the first channel region CHA1. In this specification, the first active layer ACT1 may be referred to as a semiconductor and / or semiconductor layer.

[0305] In this process, the first active layer ACT1 can be formed through semiconductor film deposition and semiconductor patterning processes. For ease of explanation, in Figure 14 The portion overlapping with the first channel region CHA1 is omitted, and the portion overlapping with the first source region S1 and the first drain region D1 is shown in an enlarged form.

[0306] Next, first to fifth insulating layers GI1, GI2, GI3, GI4, and GI5 are sequentially formed on the first active layer ACT1. Each of the first to fifth insulating layers GI1, GI2, GI3, GI4, and GI5 can be formed by a vapor deposition process for forming a film of the insulating material (inorganic insulating material, for example) described in the previous example.

[0307] A first conductive layer GTL1, a second conductive layer GTL2, a third conductive layer GTL3, and a second semiconductor layer SCL2 can be sequentially formed between the first to fifth insulating layers GI1, GI2, GI3, GI4, and GI5. Each of the first conductive layer GTL1, second conductive layer GTL2, and third conductive layer GTL3 can be formed using metal deposition processes (e.g., vapor deposition) and metal patterning processes (e.g., etching using a mask). Features and references of the first conductive layer GTL1, second conductive layer GTL2, and third conductive layer GTL3 are provided. Figure 7 The situations described are the same. Repeated explanations are omitted.

[0308] Figure 15 as well as Figure 16 It is shown Figure 13 A cross-sectional view of step S200.

[0309] Reference Figure 15 as well as Figure 16 This describes the step of performing a dry etching process to remove a portion of the insulating layer (S200).

[0310] First, multiple photoresist PRs are formed on the fifth insulating layer GI5. In this process, the photoresist PRs can be formed as a part of the first source region S1 and a part of the first drain region D1 that expose the first active layer ACT1.

[0311] Next, a dry etching process is performed. For example, the dry etching process can be formed using a RIE (Reactive Ion Etching) process that utilizes reactive gases such as CHF3, CH3F, CH2F2, CF4, C2F6, and C3F6, and sputtering gases such as Ar and O2 / Ar. In this case, an ICP (Inductively Coupled Plasma) source or a CCP (Capacitively Coupled Plasma) source can be used as the plasma source.

[0312] In this process, portions of the first to fifth insulating layers GI1, GI2, GI3, GI4, and GI5, which do not overlap with the photoresist PR, can be removed together. Therefore, a hole HOL can be formed in the portion overlapping with the first source region S1 and the first drain region D1 of the first active layer ACT1. The first active layer ACT1 can be exposed at the portion overlapping with the hole HOL.

[0313] In this process, the first active layer ACT1 may include a recess rr1 at the portion overlapping with the first source region S1 and the first drain region D1. The recess rr1 of the first active layer ACT1 may be formed by removing a portion of the first active layer ACT1 through a dry etching process.

[0314] In this process, the first to fifth insulating layers GI1, GI2, GI3, GI4, and GI5 can be removed isotropically. As a result, at the portion overlapping with the hole HOL, the first to fifth insulating layers GI1, GI2, GI3, GI4, and GI5 can have uniform side surfaces.

[0315] As previously mentioned, the first active layer ACT1 may include polysilicon. Consequently, after a dry etching process, etching residues such as native oxides may form inside the hole HOL. Therefore, in one embodiment of the display device 10 (see...) Figure 4 A cleaning process to remove etching residues may be necessary after a dry etching process.

[0316] Figure 17 as well as Figure 19 It is shown Figure 13 Cross-sectional view of step S300. Figures 17 to 19 This is a graph showing the change in etching rate of inorganic materials with temperature variations during a dry cleaning process.

[0317] Reference Figure 4 This describes the step of performing a dry cleaning process to form contact holes (S300).

[0318] Next, a dry cleaning process is performed. For example, the dry cleaning process can be performed using HF (hydrogen fluoride) gas. This process can be performed without a separate mask or photoresist.

[0319] In this process, display device 10 (refer to) can be used. Figures 1 to 17 All etching residues included in the process can be removed. In addition, a portion of the first to fifth insulating layers GI1, GI2, GI3, GI4, and GI5 that overlap with the hole HOL can be removed.

[0320] In this process, the dry cleaning process can be performed with variations in process conditions such as temperature, pressure, and HF gas flow rate. Among the aforementioned dry cleaning process conditions, temperature is the primary factor affecting the etching rate of inorganic materials.

[0321] As previously described, in one embodiment, the first insulating layer GI1 and the fifth insulating layer GI5 may comprise silicon oxide (for example, SiO2 or SiO2). X The second insulating layer GI2 and the third insulating layer GI3 may include silicon nitrides (for example, Si3N4 or SiN). X The fourth insulating layer GI4 may include silicon nitrides (for example, Si3N4 or SiN). X ) and silicon oxides (for example, SiO2 or SiO) X At least one of them.

[0322] In this process, the shapes of the first to fifth insulating layers GI1, GI2, GI3, GI4, and GI5 that overlap with the hole HOL can be formed differently depending on the temperature of the dry cleaning process.

[0323] Apart from Figure 18 In addition, refer to Figure 11 The graph shown illustrates the change in etching rate as a function of the inorganic material's temperature during a dry cleaning process. Specifically, in the graph, the X-axis represents the process temperature (°C), and the Y-axis represents the etching rate of the inorganic material (Etch Rate). ).

[0324] In the diagram shown, the first temperature Tm1 can represent the highest temperature, and the third temperature Tm3 can represent the lowest temperature. As an example, the process temperature can be adjusted within a range above 0°C and below 100°C. The first temperature Tm1 and the third temperature Tm3 can have an absolute deviation of 5°C or more and 10°C from the second temperature Tm2.

[0325] As shown in the figure, when a dry cleaning process is performed at a second temperature Tm2, ​​silicon nitrides (for example, Si3N4 or SiN) X The etching rate of silicon oxide (for example, SiO2 or SiO2) and the etching rate of silicon oxide (for example, SiO2 or SiO2) X The etching rates of the two methods can be the same.

[0326] This can mean that when the process is performed at a second temperature Tm2, ​​it includes silicon oxide (for example, SiO2 or SiO2). X The first insulating layer GI1 and the silicon nitride (for example, Si3N4 or SiN) X The second insulating layer GI2 has the same etch rate.

[0327] Therefore, when this process is performed at the second temperature Tm2, ​​the first to fifth insulating layers GI1, GI2, GI3, GI4, and GI5 can have the same etching rate, thereby enabling the etching of the first to fifth insulating layers at the same rate. Figure 8 The display device 10s is formed in the form shown.

[0328] That is, when a dry cleaning process is performed at a second temperature Tm2 in the manufacturing process of the display device 10, the sides ss11, ss21, ss31, ss41, and ss51 of the first to fifth insulating layers GI1, GI2, GI3, GI4, and GI5 can be located on the same line. (Repeated description omitted.)

[0329] Additionally, as shown in the diagram, when a dry cleaning process is performed within the temperature range between the first temperature Tm1 and the second temperature Tm2, ​​silicon nitrides (for example, Si3N4 or SiN) X The etching rate of silicon oxide (for example, SiO2 or SiO2) can be higher than that of silicon oxide (for example, SiO2 or SiO2). X Etch rate.

[0330] This can mean that when the process is performed at a first temperature Tm1 and a temperature range between the first temperature Tm1 and the second temperature Tm2, ​​the first insulating layer GI1 has an etch rate lower than that of the second insulating layer GI2.

[0331] Therefore, when this process is performed at a temperature range between a first temperature Tm1 and a second temperature Tm2, ​​the first to fifth insulating layers GI1, GI2, GI3, GI4, and GI5 can be... Figure 10 The display device 10 shown and Figure 9 The display device 10a shown is formed in the form of the device shown.

[0332] That is, in the manufacturing process of the display device 10, when a dry cleaning process is performed at a temperature range between a first temperature Tm1 and a second temperature Tm2, ​​the side gg11 of the first insulating layer GI1 and the side gg51 of the fifth insulating layer GI5 may protrude toward the hole HOL in a direction greater than the side gg21 of the second insulating layer GI2 and the side gg31 of the third insulating layer GI3.

[0333] The display device 10 and display device 10a of one embodiment can be manufactured with ease of use by using a process temperature (T) that includes a relatively wide range.

[0334] Furthermore, as shown in the chart, when a dry cleaning process is performed at a third temperature Tm3 and within the temperature range between the third temperature Tm3 and the second temperature Tm2, ​​silicon nitrides (for example, Si3N4 or SiN) exhibit significant degradation. X The etching rate of silicon oxide (for example, SiO2 or SiO2) can be lower than that of silicon oxide. X Etch Rate.

[0335] This can mean that when the process is performed at a third temperature Tm3 and in the temperature range between the third temperature Tm3 and the second temperature Tm2, ​​the first insulating layer GI1 has an etch rate higher than that of the second insulating layer GI2.

[0336] Therefore, when this process is performed at the third temperature Tm3 and the temperature range between the third temperature Tm3 and the second temperature Tm2, ​​such as Figure 19 As shown in the comparative example display device EX, the first insulating layer GI1 and the second insulating layer GI2 may have an undercut shape.

[0337] As previously mentioned, when an undercut is formed between the first insulating layer GI1 and the second insulating layer GI2, poor contact of the conductive patterns may occur in the subsequent process of forming the conductive patterns. Therefore, a dry cleaning process of one embodiment can be performed at at least one temperature in the range of a second temperature Tm2 or higher and a first temperature Tm1 or lower.

[0338] Thus, a first contact hole CH1 and a second contact hole CH2 can be formed.

[0339] In this process, the first contact hole CH1 can be located in the portion overlapping with the first drain region D1 of the first active layer ACT1, and the second contact hole CH2 can be located in the portion overlapping with the first source region S1 of the first active layer ACT1. The recessed portion rr1 of the first active layer ACT1 can be located in the portion overlapping with the first contact hole CH1 and the second contact hole CH2.

[0340] In this process, the width Wch1 of the first contact hole CH1 can be less than 2.0 micrometers, and the depth Dch1 can be more than 1.2 micrometers. The aspect ratio (AR) of dividing the depth Dch1 of the first contact hole CH1 by the width Wch1 of the first contact hole CH1 can be more than 0.6. Furthermore, the width Wch2 of the second contact hole CH2 can be less than 2.0 micrometers, the depth Dch2 can be more than 1.2 micrometers, and the aspect ratio (AR) of the second contact hole CH2 can be more than 0.6.

[0341] For ease of explanation, Figure 8 It shows Figure 10 The display device 10 includes the structure of the first to fifth insulating layers GI1, GI2, GI3, GI4, and GI5, but the shapes of the first to fifth insulating layers GI1, GI2, GI3, GI4, and GI5 can include... Figure 11 The display device 10a includes the following forms and Figure 20 The display device 10s includes all forms. Other repetitive descriptions are omitted.

[0342] In this process, the first contact hole CH1 and the second contact hole CH2 may include a lower region Lch and an upper region Uch. Specifically, the lower region Lch may be the portion relatively close to the substrate SUB, and the upper region Uch may be the portion relatively far from the substrate SUB.

[0343] Figure 21 as well as Figure 13 It is shown Figure 20 A cross-sectional view of step S400.

[0344] Reference Figure 21 as well as Figure 7 This describes the step of forming a conductive pattern in the portion overlapping with the contact hole (S400).

[0345] First, conductive patterns CP are deposited on the first active layer ACT1 and the first to fifth insulating layers GI1, GI2, GI3, GI4, and GI5.

[0346] In this process, the deposition pathway of the material forming the conductive pattern CP can be performed not only in a direction perpendicular to the substrate SUB, but also in an inclined direction. Therefore, the material forming the conductive pattern CP can also be formed inside the first contact hole CH1 and the second contact hole CH2.

[0347] However, in one embodiment, the contact hole has a narrow and deep shape, so the step coverage characteristics of the material forming the conductive pattern CP can be relatively lower than the upper region Uch of the first contact hole CH1 and the second contact hole CH2 formed in the lower region Lch.

[0348] Therefore, in one embodiment, the display devices 10 and 10s form the first insulating layer GI1 to protrude beyond the second insulating layer GI2 at the portion overlapping with the lower region Lch of the first contact hole CH1 and the second contact hole CH2, or form the side surface ss11 of the first insulating layer GI1 and the side surface ss21 of the second insulating layer GI2 to be on the same line, thereby structurally improving the limitation of the step coverage characteristics of the conductive pattern CP. (Repeated description omitted.)

[0349] Although not shown in the accompanying drawings, a patterning process for the conductive pattern CP is performed after the deposition process. This process can use a photoresist or a mask to remove a portion of the material forming the conductive pattern CP that is deposited over the entire surface.

[0350] In this process, the material forming the conductive pattern CP can be formed in the form of a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 can be formed on the portion overlapping with the first contact hole CH1, and the second conductive pattern CP2 can be formed on the portion overlapping with the second contact hole CH2.

[0351] The first conductive pattern CP1 and the second conductive pattern CP2 can be connected to and cover the recessed portion rr1 of the first active layer ACT1, and extend therefrom, so that at the portion overlapping with the first contact hole CH1 and the second contact hole CH2, they can be connected to and cover the first to fifth insulating layers GI1, GI2, GI3, GI4, and GI5.

[0352] Therefore, it can be formed Figure 22 The first conductive pattern CP1 and the second conductive pattern CP2.

[0353] Figures 1 to 21 This is a block diagram of an electronic device according to an embodiment.

[0354] Apart fromFigure 22 In addition, refer to Figure 23 The display device 10 according to the embodiment can be applied to various electronic devices 1. The electronic device 1 according to one embodiment may include the above-described display device 10, and may also include modules or devices with other additional functions in addition to the display device 10.

[0355] An electronic device 1 according to one embodiment may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0356] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0357] The memory 13 may store data information required for the operation of the processor 12 or the display module 11. For example, if the processor 12 executes an application program stored in the memory 13, image data signals and / or input control signals are transmitted to the display module 11, which processes the received signals to output image information through the display screen.

[0358] The power module 14 may include a power supply module such as a power adapter or battery device and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 1.

[0359] At least one of the structures of the electronic device 1 described above may be included within the display device according to the above embodiments. Alternatively, a portion of a separate module functionally included in one module may be included within the display device, while another portion may be provided separately from the display device. For example, the display device may include a display module 11, while the processor 12, memory 13, and power module 14 may be provided as other devices within the electronic device 1, rather than as the display device.

[0360] Figure 23 These are schematic diagrams of electronic devices according to various embodiments.

[0361] Reference Figure 4 Applicable to the display device 10 according to the embodiment (refer to) ​The various electronic devices 1 can include not only image display electronic devices such as smartphones 1_1a, tablet PCs 1_1b, laptop computers 1_1c, TVs 1_1d, and desktop monitors 1_1e, but also wearable electronic devices including display modules such as smart glasses 1_2a, head-mounted displays 1_2b, and smartwatches 1_2c, as well as vehicle electronic devices 1_3 including display modules such as car dashboards, central dashboards, CID (Center Information Display) configured in the instrument panel, and room mirror displays.

[0362] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, those skilled in the art to which this invention pertains will understand that it can be implemented in other specific ways without altering the technical concept or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not limiting.

Claims

1. A display device, characterized in that, include: Substrate, including semiconductor layer; Multiple insulating layers, including a first insulating layer connected to the semiconductor layer and a second insulating layer connected to the first insulating layer; Contact holes that penetrate the plurality of insulating layers to expose the semiconductor layer; as well as A conductive pattern covers the semiconductor layer and the insulating layer at the portion overlapping with the contact hole. The semiconductor layer includes a recessed portion that is recessed toward the substrate at the portion overlapping with the contact hole. The first insulating layer and the second insulating layer comprise different materials from each other. Furthermore, the recessed portion of the semiconductor layer and the first insulating layer have stepped steps.

2. The display device according to claim 1, characterized in that, The first insulating layer protrudes more than the second insulating layer in the direction toward the contact hole. The recessed portion of the semiconductor layer, the first insulating layer, and the second insulating layer have stepped steps.

3. The display device according to claim 2, characterized in that, The first insulating layer defines a first opening at the portion that overlaps with the contact hole. The second insulating layer defines a second opening at the portion that overlaps with the contact hole. The widths of the first opening and the second opening are different from each other.

4. The display device according to claim 3, characterized in that, The width of the first opening is smaller than the width of the second opening.

5. The display device according to claim 4, characterized in that, The difference between the width of the first opening and the width of the second opening is more than 10 angstroms and less than 300 angstroms.

6. The display device according to claim 1, characterized in that, The aspect ratio of the contact hole is defined as the value of dividing the depth of the contact hole by the width of the contact hole. The aspect ratio of the contact hole is 0.6 or higher.

7. The display device according to claim 6, characterized in that, The depth of the contact hole is greater than 1.2 micrometers, and the width of the contact hole is less than 2.0 micrometers.

8. The display device according to claim 1, characterized in that, The recessed portion of the semiconductor layer does not overlap with the plurality of insulating layers in a direction perpendicular to the substrate.

9. The display device according to claim 8, characterized in that, In a direction parallel to the substrate, the width of the recess in the semiconductor layer is smaller than the width of the contact hole.

10. The display device according to claim 1, characterized in that, The semiconductor layer comprises polycrystalline silicon.

11. The display device according to claim 1, characterized in that, The side of the first insulating layer facing the contact hole and the side of the second insulating layer facing the contact hole are on the same line.

12. The display device according to claim 1, characterized in that, At the portion overlapping with the contact hole, the conductive pattern is in contact with and covers the recess of the semiconductor layer, the first insulating layer, and the second insulating layer.

13. An electronic device, characterized in that, have: At least one display device includes a substrate, the substrate including a semiconductor layer; Display device housing, accommodating the at least one display device; as well as Optical components amplify or convert the optical path of the displayed image of the at least one display device. The at least one display device includes: Multiple insulating layers, including a first insulating layer connected to the semiconductor layer and a second insulating layer connected to the first insulating layer; Contact holes, penetrating the plurality of insulating layers to expose the semiconductor layer; and A conductive pattern covers the semiconductor layer and the insulating layer at the portion overlapping with the contact hole. The semiconductor layer includes a recessed portion that is recessed toward the substrate at the portion overlapping with the contact hole. The first insulating layer and the second insulating layer comprise different materials from each other. Furthermore, the recessed portion of the semiconductor layer and the first insulating layer have stepped steps.

14. The electronic device according to claim 13, characterized in that, The first insulating layer protrudes more than the second insulating layer in the direction toward the contact hole. The recessed portion of the semiconductor layer, the first insulating layer, and the second insulating layer have stepped steps.

15. The electronic device according to claim 14, characterized in that, The first insulating layer defines a first opening at the portion that overlaps with the contact hole. The second insulating layer defines a second opening at the portion that overlaps with the contact hole. The width of the first opening is smaller than the width of the second opening.

16. The electronic device according to claim 15, characterized in that, The difference between the width of the first opening and the width of the second opening is more than 10 angstroms and less than 300 angstroms.

17. The electronic device according to claim 13, characterized in that, The aspect ratio of the contact hole is defined as the value of dividing the depth of the contact hole by the width of the contact hole. The aspect ratio of the contact hole is 0.6 or higher.

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