Display panel and display device

Abstract

The present disclosure provides a display panel, comprising a display area and a binding area, the display area comprising a plurality of sub-pixels arranged on a substrate, at least one sub-pixel comprising a pixel driving circuit and a light emitting unit. The display panel comprises a plurality of gate lines, a plurality of data signal lines and a plurality of data fan-out lines, at least one of the plurality of data fan-out lines comprising a first fan-out line and a second fan-out line arranged on different conductive layers of the display panel. The pixel driving circuit comprises at least one capacitor and at least one transistor, two poles of the at least one capacitor being formed on the first conductive layer and the second conductive layer respectively, an active region of the at least one transistor being formed on a semiconductor layer, the first conductive layer and the second conductive layer being arranged between the substrate and the semiconductor layer, and a projection of at least one pole of the at least one capacitor on the substrate at least partially overlapping with a projection of the active region of the at least one transistor on the substrate. The present disclosure also provides a display device and an electronic equipment.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel, a display device including the display panel, and an electronic device including the display device. Background Technology

[0002] The development of display technology has led to an increasing demand for narrower bezels, and fanout-in-panel (FIP) technology is an important solution for achieving narrow bezels. In medium and large-sized display panels, oxide thin-film transistors (TFTs) have become the material for fabricating next-generation display circuits due to their low leakage current, high switching current ratio, and low manufacturing cost.

[0003] How to achieve a narrow bezel in an oxide panel based on oxide pixel circuitry and combined with FIP is a problem that needs to be solved. Utility Model Content

[0004] This disclosure aims to provide a display panel that achieves a narrow bezel effect without reducing resolution. Additionally, this disclosure also provides a display device including the display panel according to embodiments of this disclosure, and an electronic device including the display device according to embodiments of this disclosure.

[0005] This disclosure provides a display panel including a display area and a bonding area. The display area includes a plurality of sub-pixels disposed on a substrate. At least one of the plurality of sub-pixels includes a pixel driving circuit and a light-emitting unit. The plurality of sub-pixels are arranged in multiple rows along a first direction and in multiple columns along a second direction intersecting the first direction. The display panel includes a plurality of gate lines extending along the first direction and a plurality of data signal lines extending along the second direction. At least one of the plurality of data signal lines is configured to provide a data signal to at least one of the sub-pixels in a corresponding column, and at least one of the plurality of gate lines is configured to provide a gate driving signal to at least one of the sub-pixels in a corresponding row. The display area further includes a plurality of data fan-out lines, at least one of which includes a first fan-out line extending along the first direction and a second fan-out line extending along the second direction. The second fan-out line is disposed on a different conductive layer of the display panel than the first fan-out line. The first end of the first fan-out line is coupled to one of the plurality of data signal lines, and the second end of the first fan-out line is coupled to the first end of the second fan-out line. The second end of the second fan-out line extends to the bonding area. The pixel driving circuit includes at least one capacitor and at least one transistor. The two plates of the at least one capacitor are respectively formed on the first conductive layer and the second conductive layer of the display panel. The active region of the at least one transistor is formed on the semiconductor layer of the display panel. The first conductive layer and the second conductive layer are disposed between the substrate and the semiconductor layer. The projection of at least one plate of the at least one capacitor on the substrate at least partially overlaps with the projection of the active region of the at least one transistor on the substrate.

[0006] By introducing data fan-out lines in the display area of ​​the display panel, the data signal lines no longer need to be diagonally fanned out from the bezel area, reducing the fan-out space and thus reducing the width of the bezel.

[0007] The at least one transistor can be used as a driving transistor in a pixel driving circuit. By placing at least one plate of the at least one capacitor below the active region of the at least one transistor, the active region of the at least one transistor can be shielded from light, thereby mitigating or even eliminating the effect of oxide transistors being more sensitive to light.

[0008] According to embodiments of this disclosure, a second fan-out line is provided every three columns of sub-pixels, and a first fan-out line is provided between two adjacent rows of sub-pixels.

[0009] According to embodiments of this disclosure, a second fan-out line is provided every other column of sub-pixels, and three first fan-out lines are provided between two adjacent rows of sub-pixels.

[0010] According to embodiments of this disclosure, three second fan-out lines are provided every three columns of sub-pixels, and three first fan-out lines are provided between adjacent rows of sub-pixels.

[0011] The embodiments of this disclosure propose several FIP implementation schemes that can achieve the effect of narrow bezels without reducing the resolution.

[0012] According to embodiments of this disclosure, three columns of sub-pixels located in the same row constitute a pixel unit, and the distance between two adjacent pixel units is greater than the distance between two adjacent sub-pixels in a pixel unit.

[0013] According to embodiments of this disclosure, the three first sector lines are respectively coupled to different data signal lines.

[0014] According to an embodiment of this disclosure, the display panel includes a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, a fourth conductive layer, a planarization layer, and a fifth conductive layer sequentially disposed on the substrate; the plurality of gate lines and the first fan-out line are disposed on the fourth conductive layer, and the plurality of data signal lines and the second fan-out line are disposed on the fifth conductive layer.

[0015] According to an embodiment of this disclosure, a first end of the first fan-out line is coupled to one of the plurality of data signal lines via a first via through the planarization layer, and a second end of the first fan-out line is coupled to a first end of the second fan-out line via a second via through the planarization layer.

[0016] According to an embodiment of this disclosure, the first fan-out line overlaps with the first through hole and the second through hole, the data signal line overlaps with the first through hole, and the second fan-out line overlaps with the second through hole.

[0017] According to an embodiment of this disclosure, the first fan-out line has a first width, and the first fan-out line has a second width greater than the first width at the position where it overlaps with the first through hole and the second through hole.

[0018] According to embodiments of this disclosure, the display panel further includes repair lines disposed in the second conductive layer.

[0019] According to embodiments of this disclosure, the pixel driving circuit includes a first transistor to a seventh transistor, a first capacitor and a second capacitor, and a first node to a fifth node. The display panel further includes a first initial signal line, a second initial signal line, a first reset signal line, a second reset signal line, a third reset signal line, a first light-emitting signal line, a second light-emitting signal line, a first power supply line, and a second power supply line. The first terminal of the first transistor is coupled to the first initial signal line, the control terminal of the first transistor is coupled to the first reset signal line, and the second terminal of the first transistor is coupled to the first node. The first terminal of the second transistor is coupled to the first initial signal line, the control terminal of the second transistor is coupled to the second reset signal line, and the second terminal of the second transistor is coupled to the fourth node. The first terminal of the third transistor is coupled to the second node, the control terminal of the third transistor is coupled to the first node, and the second terminal of the third transistor is coupled to the third node. The first terminal of the fourth transistor is coupled to the... One of multiple data signal lines; the control terminal of the fourth transistor is coupled to one of the multiple gate lines, and the second terminal of the fourth transistor is coupled to the first node; the first terminal of the fifth transistor is coupled to the first power line, the control terminal of the fifth transistor is coupled to the first light-emitting signal line, and the second terminal of the fifth transistor is coupled to the second node; the first terminal of the sixth transistor is coupled to the third node, the control terminal of the sixth transistor is coupled to the second light-emitting signal line, and the second terminal of the sixth transistor is coupled to the fifth node; the first terminal of the seventh transistor is coupled to the second initial signal line, the control terminal of the seventh transistor is coupled to the third reset signal line, and the second terminal of the seventh transistor is coupled to the fifth node; the first plate of the first capacitor is coupled to the third node, and the second plate of the first capacitor is coupled to the fourth node; the first plate of the second capacitor is coupled to the first node, and the second plate of the second capacitor is coupled to the fourth node.

[0020] According to an embodiment of this disclosure, the second plates of the first capacitor and the second capacitor are integrally formed as a common capacitor plate on the first conductive layer; a first portion of the first light-emitting signal line, a first portion of the third reset signal line, the first plate of the first capacitor, the first plate of the second capacitor, the first gate of the first transistor, the first gate of the second transistor, the first gate of the fourth transistor, and the first gate of the sixth transistor are disposed on the second conductive layer; the active regions of the first transistor to the seventh transistor are disposed on the semiconductor layer; a second portion of the first light-emitting signal line, a second portion of the third reset signal line, the second gate of the first transistor, and the second transistor... The second gate of the transistor, the gate of the third transistor, the second gate of the fourth transistor, and the second gate of the sixth transistor are disposed on the third conductive layer; the plurality of gate lines, the first portion of the first power line, the first initial signal line, the second initial signal line, the first reset signal line, the second reset signal line, the second light-emitting signal line, and the anode transition portion are disposed on the fourth conductive layer; the plurality of data signal lines, the second portion of the first power line, the second power line, and the anode connection electrode are disposed on the fifth conductive layer, and the anode connection electrode is coupled to the anode transition portion via an anode transition via formed in the planarization layer; the anode connection electrode and the second power line are coupled to the light-emitting unit.

[0021] By integrally forming the second plates of the first capacitor and the second capacitor on the first conductive layer as a common capacitor plate, the manufacturing process can be simplified.

[0022] According to an embodiment of this disclosure, the projection of a first portion of the first light-emitting signal line onto the substrate overlaps with the projection of a second portion of the first light-emitting signal line onto the substrate; the projection of a first portion of the third reset signal line onto the substrate overlaps with the projection of a second portion of the third reset signal line onto the substrate.

[0023] According to embodiments of this disclosure, the semiconductor layer includes a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern; the active regions of the first transistor and the fourth transistor are integrally disposed through the first semiconductor pattern; the active regions of the third transistor, the fifth transistor, the sixth transistor, and the seventh transistor are integrally disposed through the second semiconductor pattern; the third semiconductor pattern includes the active region of the second transistor.

[0024] According to embodiments of this disclosure, the aspect ratio of the active region of the third transistor is greater than that of the other transistors.

[0025] According to embodiments of this disclosure, the third transistor can be used as a driving transistor, and the active region of the driving transistor has a larger width-to-length ratio, which can increase the current.

[0026] According to an embodiment of this disclosure, the third semiconductor pattern includes a first bend, a second bend, and a third bend. The second bend connects the first bend and the third bend. The first bend and the third bend extend along a second direction, and the extension direction of the second bend intersects the extension directions of the first bend and the third bend. In the first direction, the third bend is configured to be away from the adjacent first semiconductor pattern, and the first semiconductor pattern includes a fourth bend configured to be away from the adjacent third semiconductor pattern in the first direction.

[0027] According to an embodiment of this disclosure, the third bend of the third semiconductor pattern is used to form the active region of the second transistor, and the fourth bend of the first semiconductor pattern is used to form the active region of the first transistor. According to the above-described arrangement of the third bend and the fourth bend, the active regions of the second transistor and the active regions of the first transistor protrude in opposite directions in the row direction, which can make reasonable use of space while ensuring that the first transistor and the second transistor do not interfere with each other.

[0028] According to an embodiment of the present disclosure, the first fan-out line includes a break, and the projection of the break of the first fan-out line on the substrate overlaps with the projection of the second portion of the first power line on the substrate, or the projection of the break of the first fan-out line on the substrate overlaps with the projection of the second power line on the substrate.

[0029] By covering the break in the first fan-out line with the first power line or the second power line, parallax can be effectively reduced.

[0030] According to an embodiment of this disclosure, the break in the first fan-out line divides the first fan-out line into an effective portion coupled to the data signal line and the second fan-out line, and a redundant portion not coupled to the data signal line and the second fan-out line, wherein the redundant portion of the first fan-out line is coupled to the second power line.

[0031] By coupling the redundant portion to the second power line, a constant potential can be achieved on the redundant portion, which can prevent crosstalk.

[0032] According to embodiments of this disclosure, the redundant portion is coupled to the second power line via a via formed in the planarization layer, or the redundant portion is coupled to the second power line or the first initial signal line in the bezel area of ​​the display panel.

[0033] According to an embodiment of this disclosure, the second fan-out line includes a break, and the projection of the break of the second fan-out line on the substrate overlaps with the projection of the third reset signal line on the substrate.

[0034] By covering the break in the second fan-out line with the third reset signal line, parallax can be effectively reduced.

[0035] According to an embodiment of this disclosure, the second power line has a widened portion, and the projection of the widened portion of the second power line onto the substrate overlaps with the projection of the active region of the third transistor onto the substrate.

[0036] According to an embodiment of this disclosure, the distance between the second fan-out line and the adjacent common capacitor plate in the first direction is less than the distance between the second fan-out line and the adjacent data signal line in the first direction.

[0037] When the second transistor is turned on, the common capacitor plate is coupled to the first initial signal line, and the above-described arrangement of the second fan-out line and the common capacitor plate helps to reduce crosstalk.

[0038] According to an embodiment of this disclosure, the projection of the second fan-out line on the substrate overlaps with the projection portion of the common capacitor plate on the substrate.

[0039] According to an embodiment of this disclosure, the projection of the second fan-out line on the substrate overlaps with the projection of the first bent portion on the substrate.

[0040] The projection of the second fan-out line onto the substrate overlaps with the projection of the first bend onto the substrate, allowing for better utilization of space for wiring. Furthermore, according to embodiments of this disclosure, the first bend can serve as the first terminal of the second transistor, connected to a common capacitor plate formed by the first and second capacitors, thus maintaining a constant potential and preventing crosstalk.

[0041] According to an embodiment of this disclosure, the second conductive layer further includes a repair line, and the fourth conductive layer further includes a repair pad; the repair pad is integrally formed with the anode adapter, and the projection of the repair line on the substrate overlaps with the projection of the repair pad on the substrate.

[0042] According to an embodiment of this disclosure, the projection of the repair line on the substrate is located between the projection of the anode adapter via on the substrate and the projection of the second initial signal line on the substrate.

[0043] This disclosure also provides a display device, including a display panel according to an embodiment of this disclosure.

[0044] According to the embodiments of the present disclosure, a narrow bezel scheme is achieved in an oxide panel based on oxide pixel circuitry combined with FIP. Attached Figure Description

[0045] The accompanying drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which: Figure 1 A comparative schematic diagram showing a panel with FIP and a panel without FIP ​​is shown; Figure 2 A schematic diagram of a display panel according to an embodiment of the present disclosure is shown; Figure 3 Another schematic diagram of a display panel according to an embodiment of the present disclosure is shown; Figure 4 Another schematic diagram of a display panel according to an embodiment of the present disclosure is shown; Figure 5 A pixel driving circuit for a sub-pixel of a display panel according to an embodiment of the present disclosure is shown; Figure 6 It shows the control Figure 5 The signal timing diagram of the pixel driving circuit is shown below; Figures 7 to 21 The implementation based on the 2SD scheme is shown. Figure 5 The multi-layer structure of the pixel driving circuit is shown. Figures 22 to 27F It shows in Figures 7 to 21 Based on the 2SD scheme shown, implement Figures 2 to 4 The example shown; Figures 28 to 42 The implementation based on the 2SD scheme is shown. Figure 5 Another multi-layer structure of the pixel driving circuit shown; Figures 43 to 48E It shows in Figures 28 to 42 Based on the 2SD scheme shown, implement Figures 2 to 4 The example shown; Figures 49 to 54 The implementation based on the 3SD scheme is shown. Figure 5 The multi-layer structure of the pixel driving circuit is shown. Figures 55 to 60E It shows in Figures 50 to 54 Based on the 3SD solution shown, implement Figures 2 to 4The example shown; Figures 61A to 61C The anode arrangement of a display panel according to an embodiment of the present disclosure is shown; Figure 62 This is a block diagram illustrating a display device according to an embodiment of the present disclosure; Figure 63 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0046] To enable those skilled in the art to better understand the technical solutions of this disclosure, the array substrate and its manufacturing method, as well as the display panel including the array substrate, provided in this disclosure will be described in detail below with reference to the accompanying drawings.

[0047] Exemplary embodiments will be described more fully below with reference to the accompanying drawings; however, these exemplary embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth in this disclosure. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this disclosure.

[0048] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0049] As used in this disclosure, the term "and / or" includes any and all combinations of at least one of the related enumerated entries.

[0050] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of at least one other feature, integral, step, operation, element, component, and / or group thereof is not excluded.

[0051] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0052] It will be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various elements, components, and / or parts, these elements, components, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, or part from another. Therefore, the first element, component, or part discussed below may be referred to as the second element, component, or part without departing from the teachings of this disclosure.

[0053] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0054] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0055] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0056] In this disclosure, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel layer between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow through the drain, the channel layer, and the source. Note that in this specification, the channel layer refers to the region through which current primarily flows.

[0057] In this disclosure, the first terminal of a transistor can be the drain and the second terminal can be the source, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" of a transistor can be interchanged, and the "first terminal" and "second terminal" of a transistor can be interchanged.

[0058] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function" as long as it allows for the transmission and reception of electrical signals between the constituent elements to be connected. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0059] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes a state in which the angle is greater than or equal to -5° and less than 5°. In addition, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes a state in which the angle is greater than or equal to 85° and less than 95°.

[0060] In this disclosure, "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0061] In this disclosure, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined, but can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, and chamfers, curved edges, and other deformations are possible.

[0062] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0063] In medium and large-sized panels, FIP is an important solution for achieving narrow bezels. Figure 1 A comparative diagram showing a panel with and without a FIP (Fill in the Air) is provided. Figure 1 As shown, a panel with FIP can utilize a narrower bezel to achieve the bonding area of ​​the display panel.

[0064] like Figure 1As shown, medium and large-sized display panels have a large number of data signal lines. With a fixed number of integrated circuits (ICs), the data signal lines are connected sequentially, increasing the fan-out space and thus the width of the bottom bezel. The bezel area of ​​the display panel surrounds the display area and is used to shield the traces outside the display area. In medium and large-sized panels, the number of ICs is usually two or more, making the corresponding traces more complex. Using a FIP (Film In-line Package) solution, by introducing FIP traces into the display area of ​​the display panel, the data signal lines no longer need to be fanned out diagonally from the bezel area, reducing the fan-out space and consequently reducing the bezel width.

[0065] This disclosure presents a scheme for achieving narrow bezels in oxide panels based on oxide pixel circuitry combined with FIP (Fixed In-line Printed Circuit). Based on oxide backplate (BP) circuitry, this disclosure proposes several FIP implementation schemes to achieve the effect of narrow bezels without reducing resolution.

[0066] Figure 2 A schematic diagram of a display panel according to an embodiment of the present disclosure is shown.

[0067] See Figure 1 and Figure 2 According to an embodiment of the present disclosure, a display panel includes a display area and a bonding area. The display area includes a plurality of sub-pixels 101 disposed on a substrate 10. At least one of the plurality of sub-pixels 101 includes a pixel driving circuit and a light-emitting unit. The plurality of sub-pixels 101 are arranged in a plurality of rows along a first direction X and in a plurality of columns along a second direction Y intersecting the first direction X. The display panel includes a plurality of gate lines GL extending along the first direction X and a plurality of data signal lines DL extending along the second direction Y. At least one of the plurality of data signal lines DL is configured to provide a data signal to at least one of the sub-pixels 101 in a corresponding column, and at least one of the plurality of gate lines GL is configured to provide a gate driving signal to at least one of the sub-pixels 101 in a corresponding row. The display panel also includes a plurality of data fan-out lines DFL, at least one of the plurality of data fan-out lines DFL including a first fan-out line DFL1 extending along the first direction X and a second fan-out line DFL2 extending along the second direction Y. The second fan-out line DFL2 and the first fan-out line DFL1 are disposed in different conductive layers of the display panel. The first end of the first fan-out line DFL1 is coupled to one of the multiple data signal lines DL, the second end of the first fan-out line is coupled to the first end of the second fan-out line, and the second end of the second fan-out line extends to the bonding area.

[0068] According to embodiments of this disclosure, such as Figure 2 As shown, a second fan-out line DFL2 is set every three columns of sub-pixels 101, and a first fan-out line DFL1 is set between two adjacent rows of sub-pixels 101.

[0069] According to embodiments of this disclosure, such as Figure 3 As shown, a second fan-out line DFL2 is set every other column of sub-pixels 101, and three first fan-out lines DFL1 are set between two adjacent rows of sub-pixels 101.

[0070] According to embodiments of this disclosure, such as Figure 4 As shown, three second fan-out lines DFL2 are set every three columns of sub-pixels 101, and three first fan-out lines DFL1 are set between two adjacent rows of sub-pixels 101.

[0071] Figure 5 The pixel driving circuit of a sub-pixel of a display panel according to an embodiment of the present disclosure is shown. Figure 6 It shows the control Figure 5 The signal timing diagram of the pixel driving circuit is shown.

[0072] like Figure 5 As shown, the pixel driving circuit of the sub-pixels of the display panel according to an embodiment of the present disclosure includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7, a first capacitor C1 and a second capacitor C2, and a first node N1, a second node N2, a third node N3, a fourth node N4 and a fifth node N5. The display panel also includes a first initial signal line Init1, a second initial signal line Init2, a first reset signal line Reset1, a second reset signal line Reset2, a third reset signal line Reset3, a first light emission signal line EM1, a second light emission signal line EM2, a first power supply line VDD, and a second power supply line VSS.

[0073] The first terminal of the first transistor T1 is coupled to the first initial signal line Init1, the control terminal of the first transistor T1 is coupled to the first reset signal line Reset1, and the second terminal of the first transistor T1 is coupled to the first node N1.

[0074] The first terminal of the second transistor T2 is coupled to the first initial signal line Init1, the control terminal of the second transistor T2 is coupled to the second reset signal line Reset2, and the second terminal of the second transistor T2 is coupled to the fourth node N4.

[0075] The first terminal of the third transistor T3 is coupled to the second node N2, the control terminal of the third transistor T3 is coupled to the first node N1, and the second terminal of the third transistor T3 is coupled to the third node N3. The third transistor T3 can also be called a driving transistor, and it is configured to cause the sub-pixel to emit light at a desired brightness based on the voltage between its second terminal and its control terminal (also called the gate).

[0076] The first terminal of the fourth transistor T4 is coupled to one of the multiple data signal lines, DL; the control terminal of the fourth transistor T4 is coupled to one of the multiple gate lines, GL; and the second terminal of the fourth transistor T4 is coupled to the first node N1.

[0077] The first terminal of the fifth transistor T5 is coupled to the first power supply line VDD, the control terminal of the fifth transistor T5 is coupled to the first light-emitting signal line EM1, and the second terminal of the fifth transistor T5 is coupled to the second node N2.

[0078] The first terminal of the sixth transistor T6 is coupled to the third node N3, the control terminal of the sixth transistor T6 is coupled to the second light-emitting signal line EM2, and the second terminal of the sixth transistor T6 is coupled to the fifth node N5.

[0079] The first terminal of the seventh transistor T7 is coupled to the second initial signal line Init2, the control terminal of the seventh transistor T7 is coupled to the third reset signal line Reset3, and the second terminal of the seventh transistor T7 is coupled to the fifth node N5.

[0080] The first terminal of the first capacitor C1 is coupled to the third node N3, and the second terminal of the first capacitor C1 is coupled to the fourth node N4.

[0081] The first terminal of the second capacitor C2 is coupled to the first node N1, and the second terminal of the second capacitor C1 is coupled to the fourth node N4.

[0082] In addition, such as Figure 5 As shown, the light-emitting element is connected between the fifth node and the second power line VSS. In some embodiments, the light-emitting element may include an organic light-emitting diode (OLED), which includes a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or the light-emitting element may include a quantum dot light-emitting diode (QLED), which includes a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0083] In some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can include both P-type and N-type transistors.

[0084] In some embodiments, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include an oxide thin-film transistor (OST). The active region of the OST uses oxide semiconductor, and OSTs have advantages such as low leakage current. Using OSTs facilitates the implementation of narrow bezels.

[0085] In some implementations, taking the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 as examples, all of which are N-type transistors. Figure 6 The working process of the pixel driving circuit is shown.

[0086] like Figure 6 As shown, at time t1, during the reset phase, the signals (e.g., high-level signals) on the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, and the second light-emitting signal line EM2 cause the first transistor T1, the second transistor T2, the seventh transistor T7, and the sixth transistor T6 to conduct, resetting nodes N1 and N4 to the voltage V on the first initial signal line Init1. init1 And reset nodes N3 and N5 to the voltage V on the second initial signal line Init2. init2 .

[0087] At time t2, during the compensation phase, the signal on the first light-emitting signal line EM1 (e.g., a high-level signal) turns on the fifth transistor T5, the signal on the second light-emitting signal line EM2 (e.g., a low-level signal) turns off the sixth transistor T6, the signals on the first reset signal line Reset1 and the second reset signal line Reset2 (e.g., high-level signals) turn on the first transistor T1 and the second transistor T2, and the signal on the third reset signal line Reset3 (e.g., a low-level signal) turns off the seventh transistor T7. Nodes N1 and N4 represent the voltage V on the first initial signal line. init1 Node N5 maintains the voltage V on the second initial signal line Init2. init2 The voltage at node N3 is the voltage V on the first initial signal line Init1. init1 With threshold voltage V th The difference, i.e., V init1 -V th .

[0088] At time t3, the signal on the first light-emitting signal line EM1 (e.g., a low-level signal) causes the fifth transistor T5 to turn off, and the signal on the first reset signal line Reset1 (e.g., a low-level signal) causes the first transistor T1 to turn off. The voltage of each node is the same as the voltage at time t2.

[0089] At time t4, the signal on the gate line GL (e.g., a high-level signal) turns on the fourth transistor T4, and the voltage on node N1 is the data voltage Data on the data signal line DL.

[0090] At time t5, during the light-emitting phase, the signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 (e.g., high-level signals) turn on the fifth transistor T5 and the sixth transistor T6. The voltage at node N1 can be expressed as Data + VSS + V OLED -V init1 +V th The voltages at nodes N3 and N5 can be expressed as VSS + V OLED Drive current Ids = 1 / 2 × μ × C ox ×(Data-V init1 ) 2 μ is the field-effect mobility, C ox Capacitance per unit area of ​​insulating layer.

[0091] Figures 7 to 21 An embodiment of the display panel of the present disclosure is shown, which includes a substrate 10 and a first conductive layer 100, a second conductive layer 200, a semiconductor layer 250, a third conductive layer 300, a fourth conductive layer 400 and a fifth conductive layer 500 sequentially disposed on the substrate 10.

[0092] The implementation of a multi-layer structure for the pixel driving circuit of the sub-pixels of the display panel to achieve... Figure 5 The pixel driving circuit shown is illustrated. Figures 7 to 21 The image shows three sub-pixels in the same row, specifically in columns N, N+1, and N+2. Figures 7 to 21 In the multilayer structure shown, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 have a dual-gate structure.

[0093] According to embodiments of this disclosure, the substrate 10 may include a glass substrate, a quartz substrate, a plastic substrate, etc. The substrate 10 can be a rigid substrate or a flexible substrate. In some embodiments, the substrate 10 may include a structure in which multiple organic and inorganic films overlap, wherein the organic film layers may be polyimide (PI), and the inorganic film layers may be formed from inorganic materials such as silicon nitride or silicon oxide.

[0094] According to an embodiment of the present disclosure, the pixel driving circuit includes at least one capacitor and at least one transistor. The two plates of the at least one capacitor are respectively formed on a first conductive layer 100 and a second conductive layer 200 of the display panel. The active region of the at least one transistor is formed on a semiconductor layer 250 of the display panel. The first conductive layer 100 and the second conductive layer 200 are disposed between a substrate and a semiconductor layer 250. The projection of at least one plate of the at least one capacitor on the substrate at least partially overlaps with the projection of the active region of the at least one transistor on the substrate.

[0095] Figure 7 A top view of the first conductive layer 100, also known as Gate 1, is shown. Figure 7 As shown, the second plates of the first capacitor C1 and the second plates of the second capacitor C2 are disposed in the first conductive layer 100. In some embodiments, to simplify the manufacturing process, the second plates of the first capacitor C1 and the second plates of the second capacitor C2 are integrally formed as a plate 1001 (i.e., a common capacitor plate). In other embodiments, the second plates of the first capacitor C1 and the second plates of the second capacitor C2 are formed separately.

[0096] like Figure 7 As shown, the electrode plate 1001 can be rectangular in shape, with chamfered corners. The upper left portion of the electrode plate 1001 has a recess to avoid obstructing the first gate of the fourth transistor T4 formed in the second conductive layer 200. The shape of the electrode plate 1001 generally corresponds to the shape of the first electrode plate of the first capacitor C1 and the first electrode plate of the second capacitor C2 formed in the second conductive layer 200. The lower right side of the electrode plate 1001 has a protruding portion for coupling via a through-hole 3509 to the fifth connecting member 4005 formed in the fourth conductive layer 400, and further to the third semiconductor pattern 2503 formed in the semiconductor layer 250.

[0097] In some embodiments, the first conductive layer 100 may be made of a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo.

[0098] Figure 8 A top view of the second conductive layer 200, also known as Gate 2, is shown. Figure 8As shown, the first part EM1_1 of the first light-emitting signal line EM1, the first part Reset3_1 of the third reset signal line Reset3, the first plate 2001 of the first capacitor C1, the first plate 2002 of the second capacitor C2, the first gate 2003 of the first transistor T1, the first gate 2004 of the second transistor T2, the first gate 2005 of the fourth transistor T4, and the first gate 2006 of the sixth transistor T6 are disposed on the second conductive layer 200.

[0099] like Figure 8 As shown, the first electrode 2001 of the first capacitor C1 is generally rectangular in shape, with chamfered corners. The lower left side of the first electrode 2001 of the first capacitor C1 has a protruding portion for coupling via a through-hole 3510 to a fourth connecting member 4004 formed on the fourth conductive layer 400, and further to a second semiconductor pattern 2502 formed on the semiconductor layer 250. The first electrode 2002 of the second capacitor C2 is generally rectangular in shape, with chamfered corners. The upper left side of the first electrode 2002 of the second capacitor C2 has a recess to avoid obstructing the first gate 2004 of the fourth transistor T4. The first electrode 2002 of the second capacitor C2 is coupled via a through-hole 3506 to a second connecting member 4002 formed on the fourth conductive layer 400, and further to a first semiconductor pattern 2501 formed on the semiconductor layer 250.

[0100] like Figure 8As shown, the first gate 2003 of the first transistor T1 can be an island structure. The projection of the first gate 2003 of the first transistor T1 on the substrate 10 overlaps with the projection of the portion of the active region of the first semiconductor pattern 2501 of the semiconductor layer 250, which is the first transistor T1, on the substrate 10. The first gate 2003 of the first transistor T1 is coupled to the first reset signal line Reset1 formed on the fourth conductive layer 400 via the via 3516, and then coupled to the second gate 3001 of the first transistor T1 formed on the third conductive layer 300. The first gate 2004 of the second transistor T2 can be an island structure. The projection of the first gate 2004 of the second transistor T2 on the substrate 10 overlaps with the projection of the portion of the active region of the second transistor T2 in the third semiconductor pattern 2503 of the semiconductor layer 250 on the substrate 10. The first gate 2004 of the second transistor T2 is coupled to the second reset signal line Reset2 formed on the fourth conductive layer 400 via the via 3518, and further coupled to the second gate 3002 of the second transistor T2 formed on the third conductive layer 300. The first gate 2005 of the fourth transistor T4 can be an island structure. The projection of the first gate 2005 of the fourth transistor T4 on the substrate 10 overlaps with the projection of the portion of the active region of the fourth transistor T4 in the first semiconductor pattern 2501 of the semiconductor layer 250 on the substrate 10. The first gate 2005 of the fourth transistor T4 is coupled to the gate line GL formed on the fourth conductive layer 400 via the via 3504, and then coupled to the second gate 3004 of the fourth transistor T4 formed on the third conductive layer 300. The first gate 2006 of the sixth transistor T6 can be an island structure. The projection of the first gate 2006 of the sixth transistor T6 on the substrate 10 overlaps with the projection of the portion of the active region of the sixth transistor T6 in the second semiconductor pattern 2502 of the semiconductor layer 250 on the substrate 10. The first gate 2006 of the sixth transistor T6 is coupled to the second light-emitting signal line EM2 formed on the fourth conductive layer 400 through the via 3514, and then coupled to the second gate 3005 of the sixth transistor T6 formed on the third conductive layer 300.

[0101] like Figure 8As shown, the first portion EM1_1 of the first light-emitting signal line EM1 and the first portion Reset3_1 of the third reset signal line Reset3 can have a linear shape extending along the row direction. The projection of the first portion EM1_1 of the first light-emitting signal line EM1 onto the substrate 10 overlaps with the projection of the second semiconductor pattern 2502 of the semiconductor layer 250 onto the substrate 10, and the overlapping portion of the first portion EM1_1 of the first light-emitting signal line EM1 serves as the first gate of the fifth transistor T5. The projection of the first portion Reset3_1 of the third reset signal line Reset3 onto the substrate 10 overlaps with the projection of the second semiconductor pattern 2502 of the semiconductor layer 250 onto the substrate 10, and the overlapping portion of the first portion Reset3_1 of the third reset signal line Reset3 serves as the first gate of the seventh transistor T5.

[0102] In some embodiments, the second conductive layer 200 may be made of a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo.

[0103] Figure 9 A top view is shown after the first conductive layer 100 and the second conductive layer 200 are stacked. Figure 9 As shown, the projection of the second electrode plate (i.e., electrode plate 1001) integrally formed by the first capacitor C1 and the second capacitor C2 onto the substrate covers the projection of the first electrode plate 2001 of the first capacitor C1 onto the substrate, and covers the projection of the first electrode plate 2002 of the second capacitor C2 onto the substrate.

[0104] Figure 10 A top view of semiconductor layer 250, which can also be referred to as a metal oxide layer, is shown. Figure 10 As shown, semiconductor layer 250 includes a first semiconductor pattern 2501, a second semiconductor pattern 2502, and a third semiconductor pattern 2503. The active regions of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are disposed on the first semiconductor pattern 2501, the second semiconductor pattern 2502, and the third semiconductor pattern 2503 of semiconductor layer 250; that is, the active regions of all transistors in the pixel driving circuit are disposed on the same layer. According to embodiments of this disclosure, semiconductor layer 250 includes a metal oxide, such as indium gallium zinc oxide (IGZO).

[0105] like Figure 10As shown, the first semiconductor pattern 2501 may have a portion extending along the column direction. The first semiconductor pattern 2501 includes four connection portions respectively disposed at two ends and the middle. Following the top-to-bottom order shown in the figure, the second connection portion 2501_2 is located midway between the first connection portion 2501_1 and the third connection portion 2501_3, and the third connection portion 2501_3 is located midway between the first connection portion 2501_1 and the fourth connection portion 2501_4. The first connection portion 2501_1 of the first semiconductor pattern 2501 is coupled via a via 3502 to a first connection member 4001 formed on the fourth conductive layer 400, and further coupled to a data signal line DL formed on the fifth conductive layer 500. The first connection portion 2501_1 of the first semiconductor pattern 2501 can serve as the first terminal of the fourth transistor T4. The second connection portion 2501_2 of the first semiconductor pattern 2501 is coupled to the second connection member 4002 formed on the fourth conductive layer 400 via a via 3505, and further coupled to the first electrode 2002 of the second capacitor C2 formed on the second conductive layer 200. The second connection portion 2501_2 of the first semiconductor pattern 2501 can serve as the second terminal of the fourth transistor T4. The third connection portion 2501_3 of the first semiconductor pattern 2501 is coupled to the third connection member 4003 formed on the fourth conductive layer 400 via a via 3507, and further coupled to the gate 3003 of the third transistor T3 formed on the semiconductor layer 250. The third connection portion 2501_3 of the first semiconductor pattern 2501 can serve as the second terminal of the first transistor T1. The fourth connection portion 2501_4 of the first semiconductor pattern 2501 is coupled to the first initial signal line Init1 formed on the fourth conductive layer 400 via a via 3519. The fourth connection portion 2501_4 of the first semiconductor pattern 2501 can serve as the first terminal of the first transistor T1.

[0106] like Figure 10As shown, the second semiconductor pattern 2502 may have a portion extending along the column direction. The second semiconductor pattern 2502 includes four connection portions respectively disposed at two ends and the middle. Following the top-to-bottom order shown in the figure, the second connection portion 2502_2 is located midway between the first connection portion 2502_1 and the third connection portion 2502_3, with the third connection portion 2502_3 close to the fourth connection portion 2502_4. The first connection portion 2502_1 of the second semiconductor pattern 2502 is coupled via a via 3501 to a first portion VDD_1 of the first power line VDD formed on the fourth conductive layer 400. The first connection portion 2502_1 of the second semiconductor pattern 2502 can serve as the first terminal of the fifth transistor T5. The second connection portion 2502_2 of the second semiconductor pattern 2502 is coupled via a via 3511 to a fourth connection member 4004 formed on the fourth conductive layer 400, and further coupled to a first electrode 2001 of the first capacitor C1 formed on the second conductive layer 200. The second connection portion 2502_2 of the second semiconductor pattern 2502 can serve as the second terminal of the third transistor T3. The second terminal of the fifth transistor 5T and the first terminal of the third transistor T3 are integrally formed by the second semiconductor pattern 2502. The third connection portion 2502_3 of the second semiconductor pattern 2502 is coupled to the sixth connection member 4006 formed on the fourth conductive layer 400 via a via 3520, and further coupled to the first anode connection electrode 5001 formed on the fifth conductive layer 500. The third connection portion 2502_3 of the second semiconductor pattern 2502 can serve as the second terminal of the seventh transistor T7. The fourth connection portion 2502_4 of the second semiconductor pattern 2502 is coupled to the second initial signal line Init2 formed on the fourth conductive layer 400 via a via 3522. The fourth connection portion 2502_4 of the second semiconductor pattern 2502 can serve as the first terminal of the seventh transistor T7.

[0107] like Figure 10 As shown, the third semiconductor pattern 2503 may have a portion extending along the column direction, and the third semiconductor pattern 2503 includes two connection portions respectively disposed at two ends. The first connection portion 2503_1 of the third semiconductor pattern 2503 is coupled to the fifth connection member 4005 formed on the fourth conductive layer 400 via a through-hole 3512, and further coupled to the electrode 1001 formed on the first conductive layer 100. The first connection portion 2503_1 of the third semiconductor pattern 2503 can serve as the second end of the second transistor T2. The second connection portion 2503_2 of the third semiconductor pattern 2503 is coupled to the first initial signal line Init1 formed on the fourth conductive layer 400 via a through-hole 3521. The second connection portion 2503_2 of the third semiconductor pattern 2503 can serve as the first end of the second transistor T2.

[0108] According to embodiments of the present disclosure, each connecting portion of the first semiconductor pattern 2501 to the third semiconductor pattern 2503 may have a shape that protrudes outward from its location.

[0109] Figure 11 A top view is shown after the first conductive layer 100, the second conductive layer 200, and the semiconductor layer 250 are stacked. Figure 11 As shown, the two plates of the first capacitor C1 and the second capacitor C2 respectively form a first conductive layer 100 and a second conductive layer 200. The active regions of each transistor are formed on the semiconductor layer 250. The first conductive layer 100 and the second conductive layer 200 are disposed between the substrate 10 and the semiconductor layer 250. The projections of the two plates of the first capacitor C1 and the second capacitor C2 onto the substrate 10 at least partially overlap with the projection of the portion of the second semiconductor pattern 2502 used as the active region of the third transistor T3 onto the substrate 10. The third transistor T3 is used as a driving transistor in the pixel driving circuit. By placing the plates of the first capacitor C1 and the second capacitor C2 below the active region of the third transistor T3, the active region (or channel region) of the third transistor T3 can be shielded from light, thereby mitigating or even eliminating the effect of the IGZO transistor being more sensitive to light.

[0110] Figure 12 A top view of the third conductive layer 300, also known as Gate 3, is shown. Figure 12 As shown, the second part EM1_2 of the first light-emitting signal line EM1, the second part Reset3_2 of the third reset signal line Reset3, the second gate 3001 of the first transistor T1, the second gate 3002 of the second transistor T2, the gate 3003 of the third transistor T3, the second gate 3004 of the fourth transistor T4, and the second gate 3005 of the sixth transistor T6 are disposed on the third conductive layer 300.

[0111] like Figure 12As shown, the second gate 3001 of the first transistor T1 can be an island structure. The projection of the second gate 3001 of the first transistor T1 on the substrate 10 overlaps with the projection of the portion of the active region of the first semiconductor pattern 2501 of the semiconductor layer 250, which is the first transistor T1, on the substrate 10. The second gate 3001 of the first transistor T1 is coupled to the first reset signal line Reset1 formed on the fourth conductive layer 400 via the via 3515, and then coupled to the first gate 2003 of the first transistor T1 formed on the second conductive layer 200. The second gate 3002 of the second transistor T2 can be an island structure. The projection of the second gate 3002 of the second transistor T2 on the substrate 10 overlaps with the projection of the portion of the active region of the second transistor T2 in the third semiconductor pattern 2503 of the semiconductor layer 250 on the substrate 10. The second gate 3002 of the second transistor T2 is coupled to the second reset signal line Reset2 formed on the fourth conductive layer 400 via the via 3517, and then coupled to the first gate 2004 of the second transistor T2 formed on the second conductive layer 200. The gate 3003 of the third transistor T3 can be rectangular, and the corners of the rectangle can be chamfered. The projection of the gate 3003 of the third transistor T3 on the substrate 10 overlaps with the projection of the portion of the active region of the third transistor T3 in the second semiconductor pattern 2502 of the semiconductor layer 250 on the substrate 10. The gate 3003 of the third transistor T3 is coupled to the third connection member 4003 formed on the fourth conductive layer 400 through the via 3508, and then coupled to the first semiconductor pattern 2501 formed on the semiconductor layer 250. The second gate 3004 of the fourth transistor T4 can be an island structure. The projection of the second gate 3004 of the fourth transistor T4 on the substrate 10 overlaps with the projection of the portion of the active region of the fourth transistor T4 in the first semiconductor pattern 2501 of the semiconductor layer 250 on the substrate 10. The second gate 3004 of the fourth transistor T4 is coupled to the gate line GL formed on the fourth conductive layer 400 via the via 3503, and then coupled to the first gate 2005 of the fourth transistor T4 formed on the second conductive layer 200. The second gate 3005 of the sixth transistor T6 can be an island structure. The projection of the second gate 3005 of the sixth transistor T6 on the substrate 10 overlaps with the projection of the portion of the active region of the sixth transistor T6 in the second semiconductor pattern 2502 of the semiconductor layer 250 on the substrate 10. The second gate 3005 of the sixth transistor T6 is coupled to the second light-emitting signal line EM2 formed on the fourth conductive layer 400 through the via 3513, and then coupled to the first gate 2006 of the sixth transistor T6 formed on the second conductive layer 200.

[0112] like Figure 12As shown, the second portion EM1_2 of the first light-emitting signal line EM1 and the second portion Reset3_2 of the third reset signal line Reset3 can have a linear shape extending along the row direction. The projection of the second portion EM1_2 of the first light-emitting signal line EM1 onto the substrate 10 overlaps with the projection of the second semiconductor pattern 2502 of the semiconductor layer 250 onto the substrate 10, and the overlapping portion of the second portion EM1_2 of the first light-emitting signal line EM1 serves as the second gate of the fifth transistor T5. The projection of the second portion Reset3_2 of the third reset signal line Reset3 onto the substrate 10 overlaps with the projection of the second semiconductor pattern 2502 of the semiconductor layer 250 onto the substrate 10, and the overlapping portion of the second portion Reset3_2 of the third reset signal line Reset3 serves as the second gate of the seventh transistor T7.

[0113] In some embodiments, the third conductive layer 300 may be made of a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo.

[0114] Figure 13 A top view showing the stacked first conductive layer 100, second conductive layer 200, semiconductor layer 250, and third conductive layer 300 is shown. Figure 13 As shown, the first portion EM1_1 and the second portion EM1_2 of the first light-emitting signal line EM1 formed on the second conductive layer 200 and the third conductive layer 300 respectively constitute the dual-gate structure of the fifth transistor T5. The first portion Reset3_1 and the second portion Reset3_2 of the third reset signal line Reset3 formed on the second conductive layer 200 and the third conductive layer 300 respectively constitute the dual-gate structure of the seventh transistor T7. Furthermore, the first and second gates of the first transistor T1, the first and second gates of the second transistor T2, the first and second gates of the fourth transistor T4, and the first and second gates of the sixth transistor T6 formed on the second conductive layer 200 and the third conductive layer 300 respectively constitute the dual-gate structures of the first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 respectively.

[0115] The projection of the first portion EM1_1 of the first light-emitting signal line EM1 onto the substrate 10 at least partially coincides with the projection of the second portion EM1_2 of the first light-emitting signal line EM1 onto the substrate 10. The first portion EM1_1 and the second portion EM1_2 of the first light-emitting signal line EM1 together constitute the first light-emitting signal line EM1. The projection of the first portion Reset3_1 of the third reset signal line Reset3 onto the substrate 10 at least partially coincides with the projection of the second portion Reset3_2 of the third reset signal line Reset3 onto the substrate 10. The first portion Reset3_1 and the second portion Reset3_2 of the third reset signal line Reset3 together constitute the third reset signal line Reset3.

[0116] See Figures 9 to 13 The overlapping portion of the first semiconductor pattern 2501 and the first gate 2005 and the second gate 3004 of the fourth transistor T4 serves as the active region of the fourth transistor T4, and the overlapping portion of the first semiconductor pattern 2501 and the first gate 2003 and the second gate 3001 of the first transistor T1 serves as the active region of the first transistor T1. That is, the fourth transistor T4 and the first transistor T1 are integrally formed by the first semiconductor pattern 2501. The overlapping portion of the second semiconductor pattern 2502 with the first portion EM1_1 and the second portion EM_2 of the first light-emitting signal line EM1 serves as the active region of the fifth transistor T5. The overlapping portion of the second semiconductor pattern 2502 with the gate 3003 of the third transistor T3 serves as the active region of the third transistor T3. The overlapping portion of the second semiconductor pattern 2502 with the first gate 2006 and the second gate 3005 of the sixth transistor T6 serves as the active region of the sixth transistor T6. The overlapping portion of the second semiconductor pattern 2502 with the first portion Reset3_1 and the second portion Reset3_2 of the third reset signal line Reset3 serves as the active region of the seventh transistor T7. That is, the fifth transistor T5, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are integrally formed by the second semiconductor pattern 2502. The overlapping portion of the third semiconductor pattern 2503 with the first gate 2004 and the second gate 3002 of the second transistor T2 serves as the active region of the second transistor T2. See also Figure 10The third semiconductor pattern 2503 includes a first bend 25031, a second bend 25032, and a third bend 25033. In the row direction, the third bend 25033 is positioned away from the adjacent first semiconductor pattern 2501. The first bend 25031 and the third bend 25033 are connected by the second bend 25032. The extension direction of the second bend 25032 intersects the extension directions of the first bend 25031 and the third bend 25033. In some embodiments, the first bend 25031 and the third bend 25033 may extend along the column direction. The first semiconductor pattern 2501 may include a fourth bend 25014 positioned away from the adjacent third semiconductor pattern 2503 in the row direction. The third bend 25033 includes the active region of the second transistor T2, and the fourth bend 25014 includes the active region of the first transistor T1. In this implementation, the active regions of the second transistor T2 and the first transistor T1 protrude in opposite directions in the row direction, which can make reasonable use of space while ensuring that the first transistor T1 and the second transistor T2 do not interfere with each other.

[0117] like Figure 13 As shown, the aspect ratio of the active region of the third transistor T3 is greater than that of the other transistors. The active region of the third transistor T3, which is used as a driving transistor, has a larger aspect ratio, which can increase the current.

[0118] Figure 14 An inter-layer dielectric (ILD) layer 350 is shown between the third conductive layer 300 and the fourth conductive layer 400. Figure 15 The vias formed in the interlayer dielectric layer 350 are shown stacked. Figure 13 Above the structure shown.

[0119] like Figure 14 and Figure 15 As shown, a plurality of vias 3501 to 3522 are formed in the interlayer dielectric layer 350. The structure formed in the fourth conductive layer 400 is coupled to the structures formed in the first conductive layer 100, the second conductive layer 200, the semiconductor layer 250, and the third conductive layer 300 via each via. (This will be discussed later.) Figure 16 and Figure 17 The connection relationship between the structure formed in the fourth conductive layer 400 and the various structures formed in the first conductive layer 100, the second conductive layer 200, the semiconductor layer 250 and the third conductive layer 300 will be explained.

[0120] In some embodiments, the interlayer dielectric layer 350 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer.

[0121] Figure 16 A top view of the fourth conductive layer 400, also known as the SD1 layer, is shown. Figure 17 The various structural layers formed in the fourth conductive layer 400 are shown in the diagram. Figure 15 Above the structure shown, in order to illustrate the connection relationship, on Figure 17 In the stacked structure shown, each structure in the fourth conductive layer 400 is made transparent to show the structure it covers.

[0122] like Figure 16 and 17 As shown, the gate line GL, the first part of the first power line VDD VDD_1, the first initial signal line Init1, the second initial signal line Init2, the first reset signal line Reset1, the second reset signal line Reset2, the second light emission signal line EM2, the first connecting component 4001, the second connecting component 4002, the third connecting component 4003, the fourth connecting component 4004, the fifth connecting component 4005, and the sixth connecting component 4006 are disposed on the fourth conductive layer 400.

[0123] like Figure 16 As shown, the first connecting component 4001, the second connecting component 4002, the third connecting component 4003, the fourth connecting component 4004, the fifth connecting component 4005, and the sixth connecting component 4006 can be island-shaped structures. The gate line GL, the first portion VDD_1 of the first power line VDD, the first initial signal line Init1, the second initial signal line Init2, the first reset signal line Reset1, the second reset signal line Reset2, and the second light emission signal line EM2 can have a linear shape extending along the row direction.

[0124] In some embodiments, the fourth conductive layer 400 may be made of a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo.

[0125] See Figures 15 to 17A first portion of the first power line VDD, VDD_1, is coupled to a second semiconductor pattern 2502 formed on the semiconductor layer 250 via a via 3501. A first connection member 4001 is coupled to the first semiconductor pattern 2501 formed on the semiconductor layer 250 via a via 3502. A gate line GL is coupled to the second gate 3004 of the fourth transistor T4 formed on the third conductive layer 300 via a via 3503, and to the first gate 2005 of the fourth transistor T4 formed on the second conductive layer 200 via a via 3504. A second connection member 4002 is coupled to the first semiconductor pattern 2501 formed on the semiconductor layer 250 via a via 3505, and to the first plate 2002 of the second capacitor C2 formed on the second conductive layer 200 via a via 3506. The third connection member 4003 is coupled to the first semiconductor pattern 2501 formed on the semiconductor layer 250 via via 3507, and to the gate 3003 of the third transistor T3 formed on the third conductive layer 300 via via 3508. The fourth connection member 4004 is coupled to the first electrode 2001 of the first capacitor C1 formed on the second conductive layer 200 via via 3510, and to the second semiconductor pattern 2502 formed on the semiconductor layer 250 via via 3511. The fifth connection member 4005 is coupled to the electrode 1001 formed on the first conductive layer 100 via via 3509, and to the third semiconductor pattern 2503 formed on the semiconductor layer 250 via via 3512. The second light-emitting signal line EM2 is coupled to the second gate 3005 of the sixth transistor T6 formed in the third conductive layer 300 via via 3513, and to the first gate 2006 of the sixth transistor T6 formed in the second conductive layer 200 via via 3514. The first reset signal line Reset1 is coupled to the second gate 3001 of the first transistor T1 formed in the third conductive layer 300 via via 3515, and to the first gate 2003 of the first transistor T1 formed in the second conductive layer 200 via via 3516. The second reset signal line Reset2 is coupled to the second gate 3002 of the second transistor T2 formed in the third conductive layer 300 via via 3517, and to the first gate 2004 of the second transistor T2 formed in the second conductive layer 200 via via 3518. The first initial signal line Init1 is coupled to the first semiconductor pattern 2501 formed on the semiconductor layer 250 via via 3519, and to the third semiconductor pattern 2503 formed on the semiconductor layer 250 via via 3521. The sixth connection member 4006 is coupled to the second semiconductor pattern 2502 formed on the semiconductor layer 250 via via 3520. The second initial signal line Init2 is coupled to the second semiconductor pattern 2502 formed on the semiconductor layer 250 via via 3522.By setting connecting components in the fourth conductive layer 400, the resistance of each signal line can be effectively reduced, thus reducing the load.

[0126] Figure 18 A first planarization layer 450 is shown between the fourth conductive layer 400 and the fifth conductive layer 500. Figure 19 This illustrates the stacking of various vias formed in the first planarization layer 450. Figure 17 Above the structure shown.

[0127] like Figure 18 and Figure 19 As shown, a plurality of vias 4501 to 4502 are formed in the first planarization layer 450, and the structures formed in the fifth conductive layer 500 are coupled to the structures formed in the fourth conductive layer 400 via each via. (This will be discussed later.) Figure 20 and Figure 21 The connection relationship between the structure formed in the fifth conductive layer 500 and the various structures formed in the fourth conductive layer 400 is explained.

[0128] In some embodiments, the first planarization layer 450 may be made of organic materials, such as resin.

[0129] Figure 20 A top view of the fifth conductive layer 500, also known as the SD2 layer, is shown. Figure 21 The various structural layers formed in the fifth conductive layer 500 are shown in the diagram. Figure 19 Above the structure shown, in order to illustrate the connection relationship, on Figure 21 In the stacked structure shown, each structure in the fifth conductive layer 500 is made transparent to show the structure it covers.

[0130] like Figure 20 and Figure 21 As shown, the data signal line DL, the second part VDD_2 of the first power line VDD, the second power line VSS, and the first anode connection electrode 5001 are disposed on the fifth conductive layer 500.

[0131] like Figure 20 As shown, the first anode connection electrode 5001 can be an island-shaped structure. The data signal line DL, the second portion VDD_2 of the first power line VDD, and the second power line VSS can have a linear shape extending along the column direction. The second power line VSS has a widened portion, and the projection of the widened portion of the second power line VSS onto the substrate 10 overlaps with the projection of the active region of the third transistor T3 (i.e., the driving transistor) onto the substrate 10. That is, in the top view, the widened portion of the second power line VSS formed on the fifth conductive layer 500 covers the active region of the third transistor T3 formed on the semiconductor layer 250.

[0132] In some embodiments, the fifth conductive layer 500 may be made of a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo.

[0133] See Figures 19 to 21 The data signal line DL is coupled to a first connection member 4001 formed on the fourth conductor layer 400 via a via 4501 formed in the first planarization layer 450, and further coupled to a first semiconductor pattern 2501 formed on the semiconductor layer 250. The first anode connection electrode 5001 is coupled to a sixth connection member 4006 formed on the fourth conductor layer 400 via a via 4502, and further coupled to a second semiconductor pattern 2502 formed on the semiconductor layer 250. The via 4502 is also called an anode transition via, and the sixth connection member 4006 is also called an anode transition portion.

[0134] It should be recognized that, Figures 7 to 21 This illustrates a 2SD solution implemented in the portion of the display panel excluding the data fan-out line (DFL). Figure 5 The pixel driving circuit shown below. (The following is in conjunction with...) Figures 22 to 27A This will explain how to form a data fan-out line (DFL).

[0135] Figure 22 A top view of the fourth conductive layer 400' is shown. Figure 23 The various structural layers formed in the fourth conductive layer 400' are shown in the diagram. Figure 15 Above the structure shown, in order to illustrate the connection relationship, on Figure 23 In the stacked structure shown, each structure in the fourth conductive layer 400' is made transparent to show the structure it covers.

[0136] like Figure 22 and Figure 23 As shown, the first fan-out line DFL1 is disposed in the fourth conductive layer 400'.

[0137] like Figure 22 As shown, the first fan-out line DFL1 can have a linear shape that extends along the row direction.

[0138] Figure 24 The first planarization layer 450' between the fourth conductive layer 400' and the fifth conductive layer 500' is shown. Figure 25 This illustrates the stacking of various vias formed in the first planarization layer 450'. Figure 23 Above the structure shown.

[0139] like Figure 24and Figure 25 As shown, a plurality of vias are formed in the first planarization layer 450', and the structures formed in the fifth conductive layer 500' are coupled to the structures formed in the fourth conductive layer 400' via each via. In particular, a first via V1 and a second via V2 are formed in the first planarization layer 450'.

[0140] Figure 26 A top view of the fifth conductive layer 500' is shown. Figure 27A The various structural layers formed in the fifth conductive layer 500' are shown in the diagram. Figure 25 Above the structure shown, in order to illustrate the connection relationship, on Figure 27A In the stacked structure shown, each structure in the fifth conductive layer 500' is made transparent to show the structure it covers.

[0141] like Figure 26 and Figure 27A As shown, the second fan-out line DFL2 is disposed in the fifth conductive layer 500'.

[0142] See Figures 22 to 27A The first end of the first fan-out line DFL1 formed in the fourth conductive layer 400' is coupled to one of the multiple data signal lines DL formed in the fifth conductive layer 500' via a first via V1 passing through the first planarization layer 450'. The second end of the first fan-out line DFL1 is coupled to the first end of the second fan-out line DFL2 formed in the fifth conductive layer 500' via a second via V2 passing through the first planarization layer 450'. The second end of the second fan-out line DFL2 extends to the bonding area (not shown in the figure).

[0143] like Figure 26 and Figure 27A As shown, the data signal line DL has a protruding portion at the position where it is coupled to the first via V1, while the data signal line DL that is not coupled to the first via V1 does not have a protruding portion at the corresponding position. In order to ensure visual uniformity and eliminate screen-off mura, holes can be left blank at these positions, or non-via holes can be drilled in the planarization layer.

[0144] Figure 27B The diagram shows a two-row, three-column pixel driving circuit. It should be recognized that... Figure 27B The two rows of pixel driving circuits shown have three pixel driving circuits in the bottom row. Figure 27A The three pixel driving circuits are shown. According to... Figure 27B In the illustrated embodiment, the lateral traces (i.e., the first fan-out line DFL1) and the vertical traces (i.e., the second fan-out line DFL2) of the data fan-out lines DFL are both located outside the complete pixel driving circuitry. Figure 27A and Figure 27BIn the embodiment shown, every three sub-pixels form a pixel unit, and the distance between two adjacent pixel units is greater than the distance between two adjacent sub-pixels within a pixel unit.

[0145] like Figure 27B As shown, the first fan-out line DFL1, after being coupled to the data signal line DL via the first via V1, continues to extend laterally to the left in the figure and has a break, as shown in the enlarged view at the lower right of Figure 27. The projection of the second power line VSS on the substrate 10 overlaps with the projection of the break of the first fan-out line DFL1 on the substrate 10. That is, in the top view, the second power line VSS formed on the fifth conductive layer 500 (i.e., the SD2 layer) covers the break of the first fan-out line DFL1 formed on the fourth conductive layer 400 (i.e., the SD1 layer), thereby reducing parallax. It should be understood that, although not shown in the figure, the first fan-out line DFL1, after being coupled to the second fan-out line DFL2 via the second via V2, continues to extend laterally to the right in the figure and has a break, which is covered by the second portion VDD_2 (not shown) of the first power line located to the right of the second fan-out line DFL2 or the second power line VSS (not shown). The portion of the first fan-out line DFL1 separated from the first via V1 and the second via V2 by the break point can be referred to as a dummy first fan-out line (or redundant portion). The dummy first fan-out line can be coupled to the second power line VSS via a via formed in the first planarization layer 450, or the dummy first fan-out line can be coupled to the second power line VSS or a trace with a constant potential, such as the first initial signal line Init1, in the border area.

[0146] like Figure 27B As shown, the second fan-out line DFL2 is coupled to the first fan-out line DFL1 via the second via V2 and continues to extend longitudinally upwards in the figure, and has a break, as shown in the enlarged view on the upper right of Figure 27. The projection of the third reset signal line Reset3 on the substrate 10 overlaps with the projection of the break of the second fan-out line DFL2 on the substrate 10. That is, in the top view, the break of the second fan-out line DFL2 formed on the fifth conductive layer 500 (i.e., the SD2 layer) overlaps with the third reset signal line Reset3 formed on the second conductive layer 200 and the third conductive layer 300, thereby reducing parallax.

[0147] like Figure 27A and Figure 27BAs shown in the top view, the second fan-out line DFL2 is positioned between the adjacent data signal line DL and the active region of the adjacent second transistor T2, and the second fan-out line DFL2 overlaps with the portion extending from the active region of the second transistor T2 along the column direction. That is, the projection of the second fan-out line DFL2 on the substrate 10 partially overlaps with the projection of the third semiconductor pattern 2503 on the substrate 10, thereby allowing for better utilization of space for wiring. See also Figure 10 The first bend 25031 of the third semiconductor pattern 2503 partially overlaps with the second fan-out line DFL2. The first bend 25031 can be connected as the first end of the second transistor T2 to the second plate (i.e., plate 1001) formed by the first capacitor C1 and the second capacitor C2, which is a constant potential and can prevent crosstalk.

[0148] It should be recognized that, Figure 27A and Figure 27B As shown Figure 2 The embodiment shown (also known as the 3 dot in 1 scheme) is that a second fan-out line DFL2 is set every three columns of sub-pixels, and a first fan-out line DFL1 is set between two adjacent rows of sub-pixels.

[0149] Figure 27C and Figure 27D As shown Figure 3 The embodiment shown (also known as the 1 dot in 1 scheme) is that a second fan-out line DFL2 is set every other column of sub-pixels, and three first fan-out lines DFL1 are set between two adjacent rows of sub-pixels. Figure 27C Corresponding to Figure 25 The diagram shows the structure of a first conductive layer 100, a second conductive layer 200, a semiconductor layer 250, a third conductive layer 300, an interlayer dielectric layer 350, a fourth conductive layer 400', and a first planarization layer 450' stacked together. Figure 27D Corresponding to Figure 27A This shows the fifth conductive layer 500' stacked on... Figure 27C Above the structure shown. See also Figure 27C and Figure 27DThe second fan-out line DFL2_1 on the far right of the figure is coupled to the first fan-out line DFL1_1 at the top of the figure via the second through hole V2, and then coupled to the data signal line DL in the Nth column via the first through hole V1. The second fan-out line DFL2_2 on the right of the figure is coupled to the second first fan-out line DFL1_2 at the top of the figure via the second through hole V2, and then coupled to the data signal line DL in the N+1th column via the first through hole V1. The third fan-out line DFL2_3 on the right of the figure is coupled to the third first fan-out line DFL1_3 at the top of the figure via the second through hole V2, and then coupled to the data signal line DL in the N+2th column via the first through hole V1.

[0150] Figure 27C and Figure 27D A pixel driving circuit with one row and five columns is shown. According to... Figure 27D In the illustrated embodiment, the lateral traces (i.e., the first fan-out line DFL1) and vertical traces (i.e., the second fan-out line DFL2) of the data fan-out lines DFL are both located outside the complete pixel driving circuitry. Figure 27A and Figure 27B Compared to the embodiments shown, in Figure 27C and Figure 27D In the embodiment shown, the distance between adjacent rows of sub-pixels is increased, and three first fan-out lines DFL1_1, DFL1_2 and DFL1_3 are provided between them, and are respectively coupled to different data signal lines DL, that is, different data signals are transmitted in these three first fan-out lines DFL1.

[0151] like Figure 27D As shown, the lateral distance between the second fan-out line DFL2 and the adjacent electrode 1001 formed in the first conductive layer 100 is smaller than the lateral distance between the second fan-out line DFL2 and the adjacent data signal line DL. When the second transistor T2 is turned on, the electrode 1001 is coupled to the first initial signal line Init1, and the arrangement of the second fan-out line DFL2 and the electrode 1001 helps to reduce crosstalk. According to other embodiments of this disclosure, the projection of the second fan-out line DFL2 on the substrate 10 and the projection of the electrode 1001 on the substrate 10 may partially overlap.

[0152] Figure 27E and Figure 27F As shown Figure 4 The embodiment shown (also known as the 3 dot in 3 scheme) is that three second fan-out lines DFL2 are set every three columns of sub-pixels, and three first fan-out lines DFL1 are set between two adjacent rows of sub-pixels. Figure 27E Corresponding to Figure 25The diagram shows the structure of a first conductive layer 100, a second conductive layer 200, a semiconductor layer 250, a third conductive layer 300, an interlayer dielectric layer 350, a fourth conductive layer 400', and a first planarization layer 450' stacked together. Figure 27F Corresponding to Figure 27A This shows the fifth conductive layer 500' stacked on... Figure 27E Above the structure shown. See also Figure 27E and Figure 27F The second fan-out line DFL2_1 on the far right of the figure is coupled to the first fan-out line DFL1_1 at the top of the figure via the second through hole V2, and then coupled to the data signal line DL in the Nth column via the first through hole V1. The second fan-out line DFL2_2 on the right of the figure is coupled to the second first fan-out line DFL1_2 at the top of the figure via the second through hole V2, and then coupled to the data signal line DL in the N+1th column via the first through hole V1. The third fan-out line DFL2_3 on the right of the figure is coupled to the third first fan-out line DFL1_3 at the top of the figure via the second through hole V2, and then coupled to the data signal line DL in the N+2th column via the first through hole V1.

[0153] In the context of this disclosure, "between two adjacent rows of subpixels" refers to the distance between the fifth transistor T5 in the Nth row and the seventh transistor T7 in the N+1th row, and "between columns of subpixels" refers to the distance between the second transistor T2 and the adjacent first transistor T1.

[0154] In the above embodiment, a second through-hole V2 is formed in the first planarization layer at the junction of the first fan-out line DFL1 and the second fan-out line DFL2, and the first fan-out line DFL1 and the second fan-out line DFL2 overlap at the second through-hole V2. The above embodiment shows that the second fan-out line DFL2 has a larger dimension at the overlap location. According to other embodiments of this disclosure, the first fan-out line DFL1 may also have a larger dimension at the overlap location; that is, the first fan-out line DFL1 may have a first width, and the first fan-out line DFL1 may have a second width at the overlap location that is greater than the first width.

[0155] According to embodiments of this disclosure, the display panel further includes repair lines disposed in the second conductive layer and repair pads disposed in the fourth conductive layer.

[0156] Figures 28 to 42 The multi-layer structure of the pixel driving circuitry for the sub-pixels of a display panel implemented according to the 2SD scheme is shown to achieve... Figure 5 The pixel driving circuit shown includes repair lines and repair pads. Figures 28 to 42 The image shows three sub-pixels in the same row, specifically in columns N, N+1, and N+2. Figures 28 to 42In the multilayer structure shown, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 have a dual-gate structure.

[0157] Figure 28 The first conductive layer 110 shown is Figure 7 The first conductive layer 100 shown is identical, and its detailed description is omitted.

[0158] and Figure 8 and Figure 9 Compared to the second conductive layer 200 shown, Figure 29 and Figure 30 The second conductive layer 210 shown also includes repair lines. For example... Figure 29 and Figure 30 As shown, the Repair line can have a line shape that extends along the row direction.

[0159] and Figure 10 and Figure 11 Compared to the semiconductor layer 250 shown, Figure 31 and Figure 32 The second semiconductor pattern 2502 of the semiconductor layer 260 shown extends across the repair line formed in the second conductive layer 210.

[0160] Figure 33 and Figure 34 The third conductive layer 310 shown is Figure 12 and Figure 13 The third conductive layer 300 shown is basically the same, so its detailed description is omitted.

[0161] Figure 35 and Figure 36 The interlayer dielectric layer 360 shown is... Figure 14 and Figure 15 The interlayer dielectric layer 350 shown is basically the same, so its detailed description is omitted.

[0162] and Figure 16 and Figure 17 Compared to the fourth conductive layer 400 shown, Figure 37 and Figure 38 The fourth conductive layer 410 shown also includes repair pads 4006'. For example... Figure 37 and Figure 38 As shown, the repair pad 4006' is integrally formed with the sixth connecting component (i.e., the anode transition portion) and overlaps with the repair line formed in the second conductive layer 210, that is, the projection of the repair line on the substrate 10 overlaps with the projection of the repair pad 4006' on the substrate 10.

[0163] Figure 39 and Figure 40The first planarization layer 460 shown and Figure 18 and Figure 19 The first planarization layer 450 shown is consistent with this, and its detailed description is omitted. For example... Figure 40 As shown in the top view, the Repair line is located between the through hole 4502 (i.e., the anode adapter through hole) and the second initial signal line Init2.

[0164] Figure 41 and Figure 42 The fifth conductive layer 510 shown is... Figure 20 and Figure 21 The fifth conductive layer 500 shown is essentially the same, and its detailed description is omitted.

[0165] It should be recognized that, Figures 28 to 42 This illustrates a 2SD solution implemented in the portion of the display panel excluding the data fan-out line (DFL). Figure 5 The pixel driving circuit shown is illustrated, and a repair line has been added. The following section combines... Figures 43 to 4 8 illustrates how to form the data fan-out line (DFL).

[0166] Figure 43 A top view of the fourth conductive layer 410' is shown. Figure 44 The various structural layers formed in the fourth conductive layer 410' are shown in the diagram. Figure 36 Above the structure shown, in order to illustrate the connection relationship, on Figure 44 In the stacked structure shown, each structure in the fourth conductive metal layer 410' is made transparent to show the structure it covers.

[0167] like Figure 43 and Figure 44 As shown, the first fan-out line DFL1 is disposed in the fourth conductive layer 410'.

[0168] like Figure 43 As shown, the first fan-out line DFL1 can have a linear shape that extends along the row direction.

[0169] Figure 45 The first planarization layer 460' between the fourth conductive layer 410' and the fifth conductive layer 510' is shown. Figure 46 This illustrates the stacking of various vias formed in the first planarization layer 460'. Figure 44 Above the structure shown.

[0170] like Figure 45 and Figure 46As shown, a plurality of vias are formed in the first planarization layer 460', and the structures formed in the fifth conductive layer 510' are coupled to the structures formed in the fourth conductive layer 410' via each via. In particular, a first via V1 and a second via V2 are formed in the first planarization layer 460'.

[0171] Figure 47 A top view of the fifth conductive layer 510' is shown. Figure 48A The various structural layers formed in the fifth conductive layer 510' are shown in the diagram. Figure 46 Above the structure shown, in order to illustrate the connection relationship, on Figure 48A In the stacked structure shown, each structure in the fifth conductive layer 510' is made transparent to show the structure it covers.

[0172] like Figure 47 and Figure 48A As shown, the second fan-out line DFL2 is disposed in the fifth conductive layer 510'.

[0173] See Figures 43 to 48A The first end of the first fan-out line DFL1 formed in the fourth conductive layer 410' is coupled to one of the multiple data signal lines DL formed in the fifth conductive layer 510' via a first via V1 passing through the first planarization layer 460'. The second end of the first fan-out line DFL1 is coupled to the first end of the second fan-out line DFL2 formed in the fifth conductive layer 510' via a second via V2 passing through the first planarization layer 460'. The second end of the second fan-out line DFL2 extends to the bonding area (not shown in the figure).

[0174] It should be recognized that, Figures 43 to 48A As shown Figure 2 In the embodiment shown, a second fan-out line DFL2 is set every three columns of sub-pixels, and a first fan-out line DFL1 is set between two adjacent rows of sub-pixels.

[0175] Figure 48B and Figure 48C As shown Figure 3 In the embodiment shown, a second fan-out line DFL2 is set every other column of sub-pixels, and three first fan-out lines DFL1 are set between two adjacent rows of sub-pixels. Figure 48B Corresponding to Figure 46 The diagram shows the structure of the stacked first conductive layer 110, second conductive layer 210, semiconductor layer 260, third conductive layer 310, interlayer dielectric layer 360, fourth conductive layer 410, and first planarization layer 460. Figure 48C Corresponding to Figure 48A This shows the fifth conductive layer 510 stacked on top of... Figure 48B Above the structure shown. See also Figure 48Band Figure 48C The second fan-out line DFL2_1 on the far right of the figure is coupled to the first fan-out line DFL1_1 at the top of the figure via the second through hole V2, and then coupled to the data signal line DL in the Nth column via the first through hole V1. The second fan-out line DFL2_2 on the right of the figure is coupled to the second first fan-out line DFL1_2 at the top of the figure via the second through hole V2, and then coupled to the data signal line DL in the N+1th column via the first through hole V1. The third fan-out line DFL2_3 on the right of the figure is coupled to the third first fan-out line DFL1_3 at the top of the figure via the second through hole V2, and then coupled to the data signal line DL in the N+2th column via the first through hole V1.

[0176] Figure 48D and Figure 48E As shown Figure 4 In the embodiment shown, three second fan-out lines DFL2 are set every three columns of sub-pixels, and three first fan-out lines DFL1 are set between two adjacent rows of sub-pixels. Figure 48D Corresponding to Figure 46 The diagram shows the structure of the stacked first conductive layer 110, second conductive layer 210, semiconductor layer 260, third conductive layer 310, interlayer dielectric layer 360, fourth conductive layer 410, and first planarization layer 460. Figure 48E Corresponding to Figure 48A This shows the fifth conductive layer 510 stacked on top of... Figure 48D Above the structure shown. See also Figure 48D and Figure 48E The second fan-out line DFL2_1 on the far right of the figure is coupled to the first fan-out line DFL1_1 at the top of the figure via the second through hole V2, and then coupled to the data signal line DL in the Nth column via the first through hole V1. The second fan-out line DFL2_2 on the right of the figure is coupled to the second first fan-out line DFL1_2 at the top of the figure via the second through hole V2, and then coupled to the data signal line DL in the N+1th column via the first through hole V1. The third fan-out line DFL2_3 on the right of the figure is coupled to the third first fan-out line DFL1_3 at the top of the figure via the second through hole V2, and then coupled to the data signal line DL in the N+2th column via the first through hole V1.

[0177] Already combined Figures 7 to 48E A multi-layer structure of a pixel driving circuit for a sub-pixel of a display panel implemented according to a 2SD scheme is described, and how a data fan-out line (DFL) is implemented in the multi-layer structure. According to embodiments of this disclosure, a multi-layer structure of a pixel driving circuit for a sub-pixel of a display panel can be implemented according to a 3SD scheme (i.e., in this scheme, three conductive layers are used as SD layers).

[0178] Figures 7 to 19 and Figures 49 to 54 The multi-layer structure of the pixel driving circuit of the sub-pixels of the display panel implemented according to the 3SD scheme is shown, with references omitted. Figures 7 to 19 A detailed description.

[0179] Figure 49 A top view of the fifth conductive layer 520, also known as the SD2 layer, is shown. Figure 50 The various structural layers formed in the fifth conductive layer 520 are shown in the diagram. Figure 19 Above the structure shown, in order to illustrate the connection relationship, on Figure 50 In the stacked structure shown, each structure in the fifth conductive layer 500 is made transparent to show the structure it covers.

[0180] like Figure 49 and Figure 50 As shown, the second part VDD_2 of the first power line VDD, the second power line VSS, the first anode connection electrode 5001 and the data signal line connection electrode 5002 are disposed in the fifth conductive layer 520.

[0181] like Figure 49 As shown, the first anode connection electrode 5001 and the data signal line connection electrode 5002 can be island-shaped structures. The second portion VDD_2 of the first power line VDD and the second power line VSS can have a linear shape extending along the column direction. The second power line VSS has a widened portion, and the projection of the widened portion of the second power line VSS on the substrate 10 overlaps with the projection of the active region of the third transistor T3 (i.e., the driving transistor) on the substrate 10. That is, in the top view, the widened portion of the second power line VSS formed on the fifth conductive layer 520 covers the active region of the third transistor T3 formed on the semiconductor layer 250.

[0182] Figure 51 A second planarization layer 550 is shown between the fifth conductive layer 520 and the sixth conductive layer 600. Figure 52 This illustrates the stacking of various vias formed in the second planarization layer 550. Figure 50 Above the structure shown.

[0183] like Figure 51 and Figure 52 As shown, a plurality of vias 5501 to 5502 are formed in the second planarization layer 550, and the structures formed in the sixth conductive layer 600 are coupled to the structures formed in the fifth conductive layer 520 via each via. (This will be discussed later.) Figure 53 and Figure 54 The connection relationship between the structure formed in the sixth conductive layer 600 and the various structures formed in the fifth conductive layer 520 is explained.

[0184] In some embodiments, the second planarization layer 550 may be made of organic materials, such as resin.

[0185] Figure 53 A top view of the sixth conductive layer 600, also known as the SD3 layer, is shown. Figure 54 The various structural layers formed in the sixth conductive layer 600 are shown in the diagram. Figure 52 Above the structure shown, in order to illustrate the connection relationship, on Figure 54 In the stacked structure shown, each structure in the sixth conductive layer 600 is made transparent to show the structure it covers.

[0186] like Figure 53 and Figure 54 As shown, the data signal line DL and the second anode connection electrode 6001 are disposed in the sixth conductive layer 600.

[0187] like Figure 53 As shown, the second anode connection electrode 6001 can be an island structure, and the data signal line DL can have a linear shape extending along the column direction.

[0188] See Figure 19 and Figures 49 to 54 The data signal line DL formed on the sixth conductive layer 600 (i.e., the SD3 layer) is coupled to the data signal line connection electrode 5002 formed on the fifth conductive layer 520 (i.e., the SD2 layer) via a via 5501 formed in the second planarization layer 550, and further coupled to the first connection member 4001 formed on the fourth conductor layer 400 via a via 4501 formed in the first planarization layer 450 (see...). Figure 19 Finally, it is coupled to the first semiconductor pattern 2501 formed on the semiconductor layer 250. The second anode connection electrode 6001 formed on the sixth conductive layer 600 is coupled to the first anode connection electrode 5001 formed on the fifth conductive layer 520 via a via 5502 (also called the second anode transition via) formed in the second planarization layer 550, and further coupled to the sixth connection member 4006 formed on the fourth conductive layer 400 (see See) via a via 4502 (also called the first anode transition via) formed in the first planarization layer 450. Figure 19 Finally, it is coupled to the second semiconductor pattern 2502 formed on the semiconductor layer 250.

[0189] It should be recognized that the configuration of the data signal line DL is not limited to... Figures 49 to 54As shown in the embodiment of this disclosure, two adjacent data signal lines DL can be alternately disposed on the fifth conductive layer 520 and the sixth conductive layer 600. Disposing the data signal lines DL on the sixth conductive layer 600 increases the distance between the data signal lines DL and the fourth conductive layer 400, thereby reducing interference caused by the signals on the data signal lines DL to other signal lines. Furthermore, using two conductive layers (i.e., the fifth conductive layer 520 and the sixth conductive layer 600) to configure the data signal lines DL provides a more flexible wiring method.

[0190] It should be recognized that, Figures 7 to 19 and Figures 49 to 54 This illustrates a 3SD solution implemented in the display panel excluding the data fan-out line (DFL). Figure 5 The pixel driving circuit shown below. (The following is in conjunction with...) Figures 55 to 59 This will explain how to form a data fan-out line (DFL).

[0191] Figure 55 A top view of the fifth conductive layer 520', also known as the SD2 layer, is shown. Figure 56 The various structural layers formed in the fifth conductive layer 520' are shown in the diagram. Figure 25 Above the structure shown, in order to illustrate the connection relationship, on Figure 56 In the stacked structure shown, each structure in the fifth conductive layer 520' is made transparent to show the structure it covers.

[0192] like Figure 55 and Figure 56 As shown, the second part VDD_2 of the first power line VDD, the second power line VSS, the first anode connection electrode 5001, the data signal line connection electrode 5002, the first through hole connection electrode 5003, and the second through hole connection electrode 5004 are disposed in the fifth conductive layer 520'.

[0193] like Figure 55 As shown, the first anode connection electrode 5001, the data signal line connection electrode 5002, the first via connection electrode 5003, and the second via connection electrode 5004 can be island-shaped structures. The second portion VDD_2 of the first power line VDD and the second power line VSS can have a linear shape extending along the column direction. The second power line VSS has a widened portion, and the projection of the widened portion of the second power line VSS on the substrate 10 overlaps with the projection of the active region of the third transistor T3 (i.e., the driving transistor) on the substrate 10. That is, in the top view, the widened portion of the second power line VSS formed on the fifth conductive layer 520' covers the active region of the third transistor T3 formed on the semiconductor layer 250. Figure 25 The first through hole V1 and the second through hole V2 shown in the figure are in Figure 56The holes are relabeled as first through hole V1_1 and second through hole V2_1, respectively. The first through hole connecting electrode 5003 overlaps with the first through hole V1_1, and the second through hole connecting electrode 5004 overlaps with the second through hole V2_1.

[0194] Figure 57 A second planarization layer 550' is shown between the fifth conductive layer 520' and the sixth conductive layer 600'. Figure 58 This illustrates the stacking of various vias formed in the second planarization layer 550'. Figure 56 Above the structure shown.

[0195] like Figure 57 and Figure 58 As shown, a plurality of vias 5501 to 5502 are formed in the second planarization layer 550', and the structure formed in the sixth conductive layer 600' is coupled to the respective structures formed in the fifth conductive layer 520' via each via. It should be noted that in the second planarization layer 550', at positions corresponding to the first via V1_1 and the second via V2_1, a first via V1_2 and a second via V2_2 are formed, such that the structure formed in the sixth conductive layer 600' can be coupled to the first fan-out line DFL1 formed in the fourth conductive layer 400' via a first via V1 consisting of the first via V1_1, the first via connecting electrode 5003, and the first via V1_2, and a second via V2 consisting of the second via V2_1, the second via connecting electrode 5004, and the second via V2_2 (see...). Figure 22 and Figure 23 ).

[0196] See Figure 24 , Figure 25 , Figure 57 and Figure 58 The first through-hole V1_1 formed in the first planarization layer 450' and the first through-hole V1_2 formed in the second planarization layer 550' extend in the same direction, and the second through-hole V2_1 formed in the first planarization layer 450' and the second through-hole V2_2 formed in the second planarization layer 550' extend in the same direction, but this disclosure is not limited thereto. According to other embodiments of this disclosure, the extension directions of the first through-hole V1_1 formed in the first planarization layer 450' and the first through-hole V1_2 formed in the second planarization layer 550' may intersect, and the extension directions of the second through-hole V2_1 formed in the first planarization layer 450' and the second through-hole V2_2 formed in the second planarization layer 550' may intersect, in order to save space.

[0197] Combining later Figure 59 and Figure 60AThe connection relationship between the structure formed in the sixth conductive layer 600' and the various structures formed in the fifth conductive layer 520' is explained.

[0198] In some embodiments, the second planarization layer 550' may be made of organic materials, such as resin.

[0199] Figure 59 A top view of the sixth conductive layer 600' is shown. Figure 60A The various structural layers formed in the sixth conductive layer 600' are shown in the diagram. Figure 58 Above the structure shown, in order to illustrate the coupling relationship, on Figure 60A In the stacked structure shown, each structure in the sixth conductive layer 600' is made transparent to show the structure it covers.

[0200] like Figure 59 and Figure 60A As shown, the data signal line DL, the second fan-out line DFL2, and the second anode connection electrode 6001 are disposed in the sixth conductive layer 600'.

[0201] like Figure 59 As shown, the second anode connection electrode 6001 can be an island structure, and the data signal line DL and the second fan-out line DFL2 can have a linear shape extending along the column direction.

[0202] See Figures 22 to 25 and Figures 55 to 60A The first end of the first fan-out line DFL1 formed in the fourth conductive layer 400' is coupled to one of the multiple data signal lines DL formed in the sixth conductive layer 600' via a first through-hole V1 formed by a first through-hole V1_1, a first through-hole connecting electrode 5003, and a first through-hole V1_2. The second end of the first fan-out line DFL1 is coupled to the first end of the second fan-out line DFL2 formed by a second through-hole V2_1, a second through-hole connecting electrode 5004, and a second through-hole V2_2. The second end of the second fan-out line DFL2 extends to the bonding area (not shown in the figure). In addition, the data signal line DL formed in the sixth conductive layer 600' is coupled to the data signal line connecting electrode 5002 formed in the fifth conductive layer 520' via a through-hole 5501 formed in the second planarization layer 550', and then coupled to the first connecting member 4001 formed in the fourth conductive layer 400 (see figure) via a through-hole 4501 formed in the first planarization layer 450. Figure 19Finally, it is coupled to the first semiconductor pattern 2501 formed on the semiconductor layer 250. The second anode connection electrode 6001 formed on the sixth conductive layer 600' is coupled to the first anode connection electrode 5001 formed on the fifth conductive layer 520' via a via 5502 formed in the second planarization layer 550', and further coupled to the sixth connection member 4006 formed on the fourth conductive layer 400 via a via 4502 formed in the first planarization layer 450 (see Figure 19 Finally, it is coupled to the second semiconductor pattern 2502 formed on the semiconductor layer 250.

[0203] It should be recognized that, Figures 22 to 25 and Figures 55 to 60A As shown Figure 2 In the embodiment shown, a second fan-out line DFL2 is set every three columns of sub-pixels, and a first fan-out line DFL1 is set between two adjacent rows of sub-pixels.

[0204] Figure 60B and Figure 60C As shown Figure 3 In the embodiment shown, a second fan-out line DFL2 is set every other column of sub-pixels, and three first fan-out lines DFL1 are set between two adjacent rows of sub-pixels. Figure 60B Corresponding to Figure 58 The diagram shows the structure of a first conductive layer 100, a second conductive layer 200, a semiconductor layer 250, a third conductive layer 300, an interlayer dielectric layer 350, a fourth conductive layer 400', a first planarization layer 450', a fifth conductive layer 520', and a second planarization layer 550' stacked together. Figure 60C Corresponding to Figure 60A This shows the sixth conductive layer 600' stacked on... Figure 60B Above the structure shown. See also Figure 60B and Figure 60C The second fan-out line DFL2_1 on the far right of the figure is coupled to the first fan-out line DFL1_1 at the top of the figure via the second through hole V2, and then coupled to the data signal line DL in the Nth column via the first through hole V1. The second fan-out line DFL2_2 on the right of the figure is coupled to the second first fan-out line DFL1_2 at the top of the figure via the second through hole V2, and then coupled to the data signal line DL in the N+1th column via the first through hole V1. The third fan-out line DFL2_3 on the right of the figure is coupled to the third first fan-out line DFL1_3 at the top of the figure via the second through hole V2, and then coupled to the data signal line DL in the N+2th column via the first through hole V1.

[0205] Figure 60D and Figure 60E As shown Figure 4In the embodiment shown, three second fan-out lines DFL2 are set every three columns of sub-pixels, and three first fan-out lines DFL1 are set between two adjacent rows of sub-pixels. Figure 60D Corresponding to Figure 58 The diagram shows the structure of a first conductive layer 100, a second conductive layer 200, a semiconductor layer 250, a third conductive layer 300, an interlayer dielectric layer 350, a fourth conductive layer 400', a first planarization layer 450', a fifth conductive layer 520', and a second planarization layer 550' stacked together. Figure 60E Corresponding to Figure 60A This shows the sixth conductive layer 600' stacked on... Figure 60D Above the structure shown. See also Figure 60D and Figure 60E The second fan-out line DFL2_1 on the far right of the figure is coupled to the first fan-out line DFL1_1 at the top of the figure via the second through hole V2, and then coupled to the data signal line DL in the Nth column via the first through hole V1. The second fan-out line DFL2_2 on the right of the figure is coupled to the second first fan-out line DFL1_2 at the top of the figure via the second through hole V2, and then coupled to the data signal line DL in the N+1th column via the first through hole V1. The third fan-out line DFL2_3 on the right of the figure is coupled to the third first fan-out line DFL1_3 at the top of the figure via the second through hole V2, and then coupled to the data signal line DL in the N+2th column via the first through hole V1.

[0206] Furthermore, it should be recognized that, Figures 22 to 25 and Figures 55 to 60E The data signal line DL and the second fan-out line DFL2 are shown to be formed on the sixth conductive layer 600', but embodiments of the present disclosure are not limited thereto. Due to the greater routing flexibility offered by the 3SD scheme, the data signal line DL and / or the second fan-out line DFL2 can be respectively disposed on the fifth conductive layer (i.e., the SD2 layer) and the sixth conductive layer (i.e., the SD3 layer). According to other embodiments of the present disclosure, the data signal line DL and the second fan-out line DFL2 can be alternately disposed on the fifth and sixth conductive layers; for example, the data signal line DL can be disposed on the fifth conductive layer, and the second fan-out line DFL2 can be disposed on the sixth conductive layer.

[0207] According to other embodiments of this disclosure, the plurality of sub-pixels may include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. The light-emitting unit of the first color sub-pixel emits first-color light, the light-emitting unit of the second color sub-pixel emits second-color light, and the light-emitting unit of the third color sub-pixel emits third-color light. The data signal line DL and the second fan-out line DFL2 corresponding to one of the first, second, and third color sub-pixels may be disposed in the sixth conductive layer, and the data signal line DL corresponding to the other color sub-pixels may be disposed in the fifth conductive layer.

[0208] According to other embodiments of this disclosure, three columns of sub-pixels located in the same row constitute a pixel unit. At least one second fan-out line can be provided between two adjacent pixel units. The data signal line DL and the second fan-out line DFL2 corresponding to one sub-pixel in a pixel unit can be provided in the sixth conductive layer, and the two data signal lines DL corresponding to the other two sub-pixels can be provided in the fifth conductive layer. This is such that the projection of the two data signal lines provided in the fifth conductive layer onto the substrate 10 is located between the projection of the data signal lines provided in the sixth conductive layer onto the substrate 10 and the projection of the second fan-out line onto the substrate 10, so as to further reduce crosstalk.

[0209] In the 3SD solution, when the data signal line DL is located on the fifth conductive layer, the data signal line connection electrode 5002 can be omitted, and there is no need to form a corresponding via 5501 in the second planarization layer. Furthermore, when the data signal line DL and / or the second fan-out line DFL2 are located on the fifth conductive layer, the first via connection electrode 5003 and / or the second via connection electrode 5004 can be omitted, and there is no need to form the first via V1_2 and / or the second via V2_2 in the second planarization layer.

[0210] It should be recognized that, in combination Figures 28 to 42 The described embodiment with repair lines and repair pads can also be implemented using a 3SD solution, where the repair lines are formed on the second conductive layer 210, and the repair pads 4006' are integrally formed on the fourth conductive layer 410 with the sixth connecting component. The specific formation method is the same as that in the 2SD solution, and will not be described again here.

[0211] Figures 61A to 61C An anode arrangement of a display panel according to an embodiment of the present disclosure is shown.

[0212] According to embodiments of this disclosure, the light-emitting unit includes an anode, an organic light-emitting layer, and a cathode stacked sequentially. An anode connection electrode 5001 or a second anode connection electrode 6001 is coupled to the anode of the light-emitting unit, and a second power line VSS is coupled to the cathode of the light-emitting unit.

[0213] According to embodiments of the present disclosure, the light-emitting unit may include a first light-emitting unit that emits a first color light, a second light-emitting unit that emits a second color light, and a third light-emitting unit that emits a third color light.

[0214] like Figure 61A As shown, anodes 701, 702, and 703 are rectangular. When arranging the anodes, the positions indicated by the dashed boxes in the diagram should be avoided. These positions correspond to... Figure 5 Node N5 in the circuit diagram shows the drilling location for repair. When the repair function is activated, the laser acts on these locations from the front of the display panel, therefore these locations must be avoided when arranging the anode. Figure 61A In the illustrated embodiment, anode 701 may correspond to a blue sub-pixel, anode 702 may correspond to a red sub-pixel, and anode 703 may correspond to a green sub-pixel.

[0215] When arranging the anode location, it is also necessary to avoid the break points of the data fan-out lines, that is, to avoid the port locations of the data fan-out lines, such as... Figure 61B The location is shown in the dashed box. Furthermore, when arranging the anode, the data signal line DL must be avoided.

[0216] like Figure 61B As shown, anodes 704 and 706 are formed as two parallel parts connected by a transparent conductive structure (e.g., indium tin oxide (ITO)), making anodes 704 and 706 form an "H" shape. Figure 61B As shown, the organic light-emitting layer is stacked on the longitudinal portion of the "H" shape in anodes 704 and 706, but not on the transverse portion of the "H" shape. Therefore, only the longitudinal portion of the "H" shape emits light, while the transverse portion does not. Anode 705 is formed in an "L" shape to avoid the port positions of data fan-out lines and data signal lines. Figure 61B As shown, the organic light-emitting layer is stacked on the longitudinal and transverse portions of the "L" shape of the anode 705, thus both the longitudinal and transverse portions of the "L" shape can emit light. Figure 61B In the embodiment shown, anode 704 can correspond to a blue sub-pixel, anode 705 can correspond to a red sub-pixel, and anode 706 can correspond to a green sub-pixel.

[0217] like Figure 61C As shown, the anode 707 includes a first portion and a second portion arranged along the row direction, and a third portion connecting the first and second portions together, such that the anode 707 is formed in a "U" shape. The length of the third portion in the column direction is less than the lengths of the first and second portions in the column direction to avoid data signal lines. Figure 61CAs shown, the organic light-emitting layer is stacked on the longitudinal and transverse portions of the "U" shape of the anode 707, thus both the longitudinal and transverse portions of the "U" shape can emit light. Figure 61C In the embodiment shown, anode 707 may correspond to blue sub-pixel.

[0218] Figure 62 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0219] like Figure 62 As shown, embodiments of this disclosure also provide a display device, including a display panel according to various embodiments of this disclosure.

[0220] Figure 63 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0221] like Figure 63 As shown, this disclosure also provides an electronic device, including a display device according to an embodiment of this disclosure.

[0222] This disclosure has disclosed exemplary embodiments, and although specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some embodiments, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A display panel, comprising a display area and a bonding area, the display area comprising a plurality of sub-pixels disposed on a substrate, at least one of the plurality of sub-pixels comprising a pixel driving circuit and a light-emitting unit, the plurality of sub-pixels being arranged in a plurality of rows along a first direction and in a plurality of columns along a second direction intersecting the first direction; The display panel includes a plurality of gate lines extending along the first direction and a plurality of data signal lines extending along the second direction; At least one of the plurality of data signal lines is configured to provide a data signal to at least one of the sub-pixels in the corresponding column, and at least one of the plurality of gate lines is configured to provide a gate drive signal to at least one of the sub-pixels in the corresponding row. in, The display area also includes multiple data fan-out lines, at least one of which includes a first fan-out line extending along the first direction and a second fan-out line extending along the second direction. The second fan-out line and the first fan-out line are disposed on different conductive layers of the display panel. A first end of the first fan-out line is coupled to one of the multiple data signal lines, a second end of the first fan-out line is coupled to a first end of the second fan-out line, and a second end of the second fan-out line extends to the bonding area. The pixel driving circuit includes at least one capacitor and at least one transistor. The two plates of the at least one capacitor are respectively formed in a first conductive layer and a second conductive layer of the display panel. The active region of the at least one transistor is formed in a semiconductor layer of the display panel. The first conductive layer and the second conductive layer are disposed between the substrate and the semiconductor layer. The projection of at least one plate of the at least one capacitor on the substrate and the projection of the active region of the at least one transistor on the substrate at least partially overlap.

2. The display panel according to claim 1, wherein, A second fan-out line is set every three columns of sub-pixels, and a first fan-out line is set between two adjacent rows of sub-pixels.

3. The display panel according to claim 1, wherein, A second fan-out line is set every other column of sub-pixels, and three first fan-out lines are set between two adjacent rows of sub-pixels.

4. The display panel according to claim 1, wherein, Three second fan-out lines are set every three columns of sub-pixels, and three first fan-out lines are set between two adjacent rows of sub-pixels.

5. The display panel according to claim 2 or 4, wherein, Three columns of sub-pixels in the same row constitute a pixel unit, and the distance between two adjacent pixel units is greater than the distance between two adjacent sub-pixels in a pixel unit.

6. The display panel according to claim 3 or 4, wherein, The three first fan-out lines are respectively coupled to different data signal lines.

7. The display panel according to claim 1, wherein, The display panel includes a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, a fourth conductive layer, a planarization layer, and a fifth conductive layer sequentially disposed on the substrate. The plurality of gate lines and the first fan-out line are disposed on the fourth conductive layer, and the plurality of data signal lines and the second fan-out line are disposed on the fifth conductive layer.

8. The display panel according to claim 7, wherein, The first end of the first fan-out line is coupled to one of the plurality of data signal lines via a first via through the planarization layer, and the second end of the first fan-out line is coupled to the first end of the second fan-out line via a second via through the planarization layer.

9. The display panel according to claim 8, wherein, The first fan-out line overlaps with the first through hole and the second through hole, the data signal line overlaps with the first through hole, and the second fan-out line overlaps with the second through hole.

10. The display panel according to claim 9, wherein, The first fan-out line has a first width, and the first fan-out line has a second width greater than the first width at the position where it overlaps with the first through hole and the second through hole.

11. The display panel according to any one of claims 2 to 4 and 7 to 10, wherein, The display panel also includes repair lines disposed on the second conductive layer.

12. The display panel according to claim 7, wherein, The pixel driving circuit includes a first to a seventh transistor, a first capacitor, a second capacitor, and a first to a fifth node. The display panel also includes a first initial signal line, a second initial signal line, a first reset signal line, a second reset signal line, a third reset signal line, a first light-emitting signal line, a second light-emitting signal line, a first power line, and a second power line. The first terminal of the first transistor is coupled to the first initial signal line, the control terminal of the first transistor is coupled to the first reset signal line, and the second terminal of the first transistor is coupled to the first node; The first terminal of the second transistor is coupled to the first initial signal line, the control terminal of the second transistor is coupled to the second reset signal line, and the second terminal of the second transistor is coupled to the fourth node; The first terminal of the third transistor is coupled to the second node, the control terminal of the third transistor is coupled to the first node, and the second terminal of the third transistor is coupled to the third node; The first terminal of the fourth transistor is coupled to one of the plurality of data signal lines, the control terminal of the fourth transistor is coupled to one of the plurality of gate lines, and the second terminal of the fourth transistor is coupled to the first node; The first terminal of the fifth transistor is coupled to the first power line, the control terminal of the fifth transistor is coupled to the first light-emitting signal line, and the second terminal of the fifth transistor is coupled to the second node; The first terminal of the sixth transistor is coupled to the third node, the control terminal of the sixth transistor is coupled to the second light-emitting signal line, and the second terminal of the sixth transistor is coupled to the fifth node; The first terminal of the seventh transistor is coupled to the second initial signal line, the control terminal of the seventh transistor is coupled to the third reset signal line, and the second terminal of the seventh transistor is coupled to the fifth node; The first plate of the first capacitor is coupled to the third node, and the second plate of the first capacitor is coupled to the fourth node; The first plate of the second capacitor is coupled to the first node, and the second plate of the second capacitor is coupled to the fourth node.

13. The display panel according to claim 12, wherein, The second electrode of the first capacitor and the second electrode of the second capacitor are integrally formed as a common capacitor electrode in the first conductive layer; The first portion of the first light-emitting signal line, the first portion of the third reset signal line, the first electrode of the first capacitor, the first electrode of the second capacitor, the first gate of the first transistor, the first gate of the second transistor, the first gate of the fourth transistor, and the first gate of the sixth transistor are disposed in the second conductive layer; The active regions of the first transistor to the seventh transistor are disposed in the semiconductor layer; The second portion of the first light-emitting signal line, the second portion of the third reset signal line, the second gate of the first transistor, the second gate of the second transistor, the gate of the third transistor, the second gate of the fourth transistor, and the second gate of the sixth transistor are disposed on the third conductive layer; The plurality of gate lines, the first portion of the first power line, the first initial signal line, the second initial signal line, the first reset signal line, the second reset signal line, the second light-emitting signal line, and the anode adapter are disposed on the fourth conductive layer; The multiple data signal lines, the second part of the first power line, the second power line and the anode connection electrode are disposed on the fifth conductive layer, and the anode connection electrode is coupled to the anode transition portion via an anode transition via formed in the planarization layer; The anode connecting electrode and the second power line are coupled to the light-emitting unit.

14. The display panel according to claim 13, wherein, The projection of the first portion of the first light-emitting signal line onto the substrate overlaps with the projection of the second portion of the first light-emitting signal line onto the substrate; The projection of the first portion of the third reset signal line onto the substrate overlaps with the projection of the second portion of the third reset signal line onto the substrate.

15. The display panel according to claim 13, wherein, The semiconductor layer includes a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern; The active regions of the first transistor and the fourth transistor are integrally formed by the first semiconductor pattern. The active regions of the third transistor, the fifth transistor, the sixth transistor, and the seventh transistor are integrally formed by the second semiconductor pattern. The third semiconductor pattern includes the active region of the second transistor.

16. The display panel according to claim 15, wherein, The aspect ratio of the active region of the third transistor is greater than that of the other transistors.

17. The display panel according to claim 15, wherein, The third semiconductor pattern includes a first bend, a second bend, and a third bend. The second bend connects the first bend and the third bend. The first bend and the third bend extend along the second direction, and the extension direction of the second bend intersects the extension directions of the first bend and the third bend. In the first direction, the third bend is configured to be away from the adjacent first semiconductor pattern, and the first semiconductor pattern includes a fourth bend configured to be away from the adjacent third semiconductor pattern in the first direction.

18. The display panel according to claim 13, wherein, The first fan-out line includes a break. The projection of the break in the first fan-out line onto the substrate overlaps with the projection of the second portion of the first power line onto the substrate, or The projection of the break in the first fan-out line onto the substrate overlaps with the projection of the second power line onto the substrate.

19. The display panel according to claim 18, wherein, The break in the first fan-out line divides it into an effective portion coupled to the data signal line and the second fan-out line, and a redundant portion not coupled to the data signal line and the second fan-out line. The redundant portion of the first fan-out line is coupled to the second power line.

20. The display panel according to claim 19, wherein, The redundant portion is coupled to the second power line via a via formed in the planarization layer, or The redundant portion is coupled to the second power line or the first initial signal line in the bezel area of ​​the display panel.

21. The display panel according to claim 13, wherein, The second fan-out line includes a break. The projection of the break in the second fan-out line onto the substrate overlaps with the projection of the third reset signal line onto the substrate.

22. The display panel according to claim 13, wherein, The second power line has a widened portion, and the projection of the widened portion of the second power line onto the substrate overlaps with the projection of the active region of the third transistor onto the substrate.

23. The display panel according to claim 13, wherein, The distance between the second fan-out line and the adjacent common capacitor plate in the first direction is less than the distance between the second fan-out line and the adjacent data signal line in the first direction.

24. The display panel according to claim 23, wherein, The projection of the second fan-out line onto the substrate overlaps with the projection of the common capacitor plate onto the substrate.

25. The display panel according to claim 15, wherein, The projection of the second fan-out line on the substrate overlaps with the projection of the first bend on the substrate.

26. The display panel according to claim 13, wherein, The second conductive layer further includes repair lines, and the fourth conductive layer further includes repair pads; The repair pad is integrally formed with the anode adapter, and the projection of the repair line on the substrate overlaps with the projection of the repair pad on the substrate.

27. The display panel according to claim 26, wherein, The projection of the repair line onto the substrate lies between the projection of the anode adapter via onto the substrate and the projection of the second initial signal line onto the substrate.

28. A display device comprising a display panel according to any one of claims 1 to 27.

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