Display device

Abstract

A display device is provided. The display device includes a substrate; a first electrode on the substrate; a pixel definition film on the first electrode; an emission stack on the first electrode and the pixel definition film; a second electrode on the emission stack; and an encapsulation layer on the second electrode, wherein the encapsulation layer includes a first sub-encapsulation layer on the second electrode and a second sub-encapsulation layer on the first sub-encapsulation layer, and the second sub-encapsulation layer includes a transparent conductive material. Further, an electronic device including the display device is also provided. The display device according to an embodiment of the disclosure has an improved moisture vapor penetration prevention function.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0107274, filed on August 12, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more embodiments of this disclosure relate to display devices, such as display devices and electronic devices that both have improved moisture penetration protection. Background Technology

[0003] A head-mounted display (HMD) is an image display device worn on a user's head in the form of glasses or a helmet to focus an image at close range in front of the user's eyes. Head-mounted displays can enable virtual reality (VR) or augmented reality (AR).

[0004] Head-mounted displays magnify images displayed on small display devices using multiple lenses, and then display the magnified images. Therefore, display devices used in head-mounted displays need to provide high-resolution images, for example, images with a resolution of 3000 PPI (pixels per inch) or higher. For this purpose, organic light-emitting diode-on-silicon (OLEDoS) display devices, as high-resolution small organic light-emitting display devices, are used as display devices for head-mounted displays. An OLEDoS display device is an image display device in which organic light-emitting diodes (OLEDs) are arranged on a semiconductor wafer substrate on which complementary metal-oxide-semiconductor (CMOS) circuitry is arranged. Utility Model Content

[0005] The purpose of this invention is to provide a display device and electronic device with improved moisture penetration resistance. Further aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practice of the disclosed embodiments.

[0006] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a first electrode on the substrate; a pixel defining film on the first electrode; a light-emitting stack on the first electrode and the pixel defining film; a second electrode on the light-emitting stack; and an encapsulation layer on the second electrode, wherein the encapsulation layer includes a first sub-encapsulation layer on the second electrode and a second sub-encapsulation layer on the first sub-encapsulation layer, and the second sub-encapsulation layer comprises a transparent conductive material.

[0007] According to one or more embodiments of the present disclosure, an electronic device includes a display device, the display device including (e.g., generating) an image, wherein the display device includes: a substrate; a first electrode on the substrate; a pixel defining film on the first electrode; a light-emitting stack on the first electrode and the pixel defining film; a second electrode on the light-emitting stack; and an encapsulation layer on the second electrode, wherein the encapsulation layer includes a first sub-encapsulation layer on the second electrode and a second sub-encapsulation layer on the first sub-encapsulation layer, and the second sub-encapsulation layer comprises a transparent conductive material.

[0008] The encapsulation layer of the display device according to one or more embodiments may include transparent conductive oxide (e.g., IZO) and aluminum oxide (AlO). x (e.g., Al2O3). Display devices can have small size, reduced moisture permeability, improved packaging capabilities, high current drive capability, and low current reduction rate after reliability testing.

[0009] However, the effects and aspects of this disclosure are not limited to the embodiments set forth herein. The above and other effects and aspects of this disclosure will become more apparent to those skilled in the art upon which this disclosure pertains by referring to the claims. Attached Figure Description

[0010] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and constitute a part of this disclosure. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. The above and other aspects and features of this disclosure will become more apparent and readily understood from the following description of exemplary embodiments thereof, with reference to the accompanying drawings, in which:

[0011] Figure 1 This is an exploded perspective view showing a display device according to one or more embodiments of the present disclosure;

[0012] Figure 2 This is a block diagram illustrating a display device according to one or more embodiments of the present disclosure;

[0013] Figure 3 This is an equivalent circuit diagram of a first sub-pixel according to one or more embodiments of the present disclosure;

[0014] Figure 4 This is a layout diagram illustrating examples of display panels according to one or more embodiments of the present disclosure;

[0015] Figure 5 and Figure 6 All are shown Figure 4 A layout diagram of an example display area;

[0016] Figure 7 It shows along Figure 5 A cross-sectional view of an example display panel, taken by line I1-I1';

[0017] Figure 8 To show in more detail Figure 7 A sectional view of region A1;

[0018] Figure 9 It is shown in detail Figure 8 A cross-sectional view of an example of region A2;

[0019] Figure 10 It is a diagram used to illustrate the current increase effect and brightness improvement effect of a display device according to one or more embodiments of the present disclosure;

[0020] Figure 11 It is a graph used to illustrate the current reduction improvement effect of a display device according to one or more embodiments of the present disclosure;

[0021] Figure 12 This is a perspective view showing a head-mounted display according to one or more embodiments of the present disclosure;

[0022] Figure 13 It is shown Figure 12 An exploded perspective view of an example of a head-mounted display;

[0023] Figure 14 This is a perspective view showing a head-mounted display according to one or more embodiments of the present disclosure;

[0024] Figure 15 This is a block diagram of an electronic device according to one or more embodiments of the present disclosure; and

[0025] Figure 16 , Figure 17 and Figure 18 These are schematic diagrams of electronic devices according to one or more embodiments of the present disclosure. Detailed Implementation

[0026] This disclosure will now be described more fully below with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are illustrated. However, this disclosure may be implemented in various forms and should not be construed as limited to the one or more embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0027] It will also be understood that if (for example, when) a layer is referred to as being "on" another layer or substrate, then the layer may be directly on said other layer or substrate, or one or more intervening layers may exist between them. Conversely, "directly on" may mean that there is no additional intervening element or intervening layer between an element or layer and another element or layer. Throughout the disclosure, the same or identical reference numerals indicate the same or identical components, and for the sake of brevity, their repeated description may not be provided. In the figures, the thickness of layers and / or regions may be exaggerated for clarity.

[0028] Although the terms “first,” “second,” etc., may be used herein to describe one or more suitable elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another. Therefore, without departing from the teachings of one or more embodiments, the first element in discussion may be referred to as the second element. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. In one or more embodiments, the terms “first,” “second,” etc., may also be used herein to distinguish elements of different categories or groups. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first group),” “second category (or second group),” etc.

[0029] Features of one or more suitable embodiments of this disclosure may be combined in part or in whole. As will be clearly understood by those skilled in the art, one or more suitable interactions and operations are technically possible. Various embodiments may be practiced individually or in combination.

[0030] In the following, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0031] Figure 1 This is an exploded perspective view showing a display device according to one or more embodiments of the present disclosure. Figure 2 This is a block diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0032] Reference Figure 1 and Figure 2The display device 10 according to one or more embodiments is a device for displaying moving or still images. The display device 10 according to one or more embodiments can be applied to portable electronic devices, such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, ultra-mobile PCs (UMPCs), etc. For example, the display device 10 according to one or more embodiments can be applied as a display unit in a television, laptop computer, monitor, billboard, or Internet of Things (IoT) terminal. In one or more embodiments, the display device 10 can be applied to smartwatches, smartwatch phones, head-mounted displays (HMDs) for implementing virtual and augmented reality, etc.

[0033] The display device 10 according to one or more embodiments includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0034] In one or more embodiments, the display panel 100 may have a planar shape, for example, similar to a quadrilateral. For instance, the display panel 100 may have a planar shape similar to a quadrilateral having a short side on a first direction DR1 and a long side on a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side on the first direction DR1 and the long side on the second direction DR2 intersect may be a right angle or rounded with a set or predetermined curvature. The planar shape of the display panel 100 is not limited to a quadrilateral shape and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may conform to the planar shape of the display panel 100, but the embodiments of this disclosure are not limited thereto.

[0035] The display panel 100 may include multiple pixels PX, multiple scan lines SL, multiple emission control lines EL, multiple data lines DL, a scan driver 610, an emission driver 620, and a data driver 700. For example... Figure 2 As shown, the display panel 100 can be divided into a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0036] Multiple pixels PX can be arranged in the display area DAA. In one or more embodiments, the multiple pixels PX can be arranged in a matrix in a first direction DR1 and a second direction DR2. Multiple scan lines SL and multiple emission control lines EL can extend in the first direction DR1 and be arranged in the second direction DR2. Multiple data lines DL can extend in the second direction DR2 and be arranged in the first direction DR1.

[0037] The multiple scan lines SL include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. The multiple emit control lines EL include multiple first emit control lines EL1 and multiple second emit control lines EL2.

[0038] Multiple pixels PX include multiple sub-pixels SP1, SP2, and SP3. The multiple sub-pixels SP1, SP2, and SP3 can each include, for example: Figure 3 The multiple pixel transistors shown can be formed and arranged on a semiconductor substrate SSUB using semiconductor processes (see...). Figure 7 For example, in one or more embodiments, the plurality of pixel transistors of the data driver 700 may be formed of complementary metal-oxide-semiconductor (CMOS), but embodiments of the present disclosure are not limited thereto.

[0039] Each of the plurality of sub-pixels SP1, SP2, and SP3 can be connected to a write scan line GWL selected from a plurality of write scan lines GWL (e.g., any one), a control scan line GCL selected from a plurality of control scan lines GCL (e.g., any one), a bias scan line GBL selected from a plurality of bias scan lines GBL (e.g., any one), a first emission control line EL1 selected from a plurality of first emission control lines EL1 (e.g., any one), a second emission control line EL2 selected from a plurality of second emission control lines EL2 (e.g., any one), and a data line DL selected from a plurality of data lines DL (e.g., any one). Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive a data voltage from the data line DL in response to a write scan signal of the write scan line GWL, and emit light from the light-emitting element according to the data voltage.

[0040] In one or more embodiments, the scan driver 610, the transmit driver 620, and the data driver 700 may all be arranged in the non-display area NDA.

[0041] The scan driver 610 includes multiple scan transistors, and the emitter driver 620 includes multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed on a semiconductor substrate SSUB using semiconductor processes (see [link to semiconductor diagram]). Figure 7 For example, in one or more embodiments, the plurality of scanning transistors and the plurality of light-emitting transistors may be formed by CMOS, but the embodiments of this disclosure are not limited thereto.

[0042] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS from the timing control circuit 400 and output them sequentially to the write scan line GWL. The control scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS and output them sequentially to the control scan line GCL. The bias scan signal output unit 613 may generate bias scan signals according to the scan timing control signal SCS and output them sequentially to the bias scan line GBL.

[0043] The transmit driver 620 includes a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 can receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 can generate a first transmit control signal based on the transmit timing control signal ECS and outputs it sequentially to a first transmit control line EL1. The second transmit control driver 622 can generate a second transmit control signal based on the transmit timing control signal ECS and outputs it sequentially to a second transmit control line EL2.

[0044] The data driver 700 may include multiple data transistors, and the multiple data transistors may be formed on a semiconductor substrate SSUB (see [reference needed]) using semiconductor processes. Figure 7 For example, in one or more embodiments, multiple data transistors may be formed by CMOS, but embodiments of this disclosure are not limited thereto.

[0045] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this regard, sub-pixels SP1, SP2, and SP3 can be selected by the write scan signal of the scan driver 610, and the data voltage (i.e., the analog data voltage) can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0046] The heat dissipation layer 200 can be stacked on the display panel 100 in a third-direction DR3, where DR3 is the thickness direction of the display panel 100. The heat dissipation layer 200 can be disposed on one (e.g., a) surface of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a layer comprising a material having high thermal conductivity, such as graphite, silver (Ag), copper (Cu), and / or aluminum (Al)

[0047] Circuit board 300 can be electrically connected to the first pad (or "soldering pad") portion of display panel 100 PDA1 (see [link to PDA1]) using conductive adhesive components such as anisotropic conductive film. Figure 4 Multiple first pads PD1 (see) Figure 4 In one or more embodiments, circuit board 300 may be a flexible printed circuit board having a flexible material or flexible film. Although circuit board 300 in Figure 1 The circuit board 300 is shown unfolded, but it can be bent. In these embodiments, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The other end of the circuit board 300 may be attached to the first pad portion PDA1 of the display panel 100 (see [link to PDA1]) using conductive adhesive members. Figure 4 Multiple first pads PD1 (see) Figure 4 One end of the circuit board 300 may be the opposite end of the other end of the circuit board 300.

[0048] The timing control circuit 400 can receive digital video data and timing signals input from an external source. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can output digital video data DATA and the data timing control signal DCS to the data driver 700.

[0049] The power supply circuit 500 can generate multiple panel driving voltages based on external power voltage. For example, in one or more embodiments, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. This will be discussed later in conjunction with... Figure 3 The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT are described in more detail.

[0050] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. In this regard, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 via the circuit board 300. Furthermore, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 via the circuit board 300.

[0051] In one or more embodiments, similar to scan driver 610, transmit driver 620, and data driver 700, each of timing control circuitry 400 and power supply circuitry 500 may be arranged in the non-display area NDA of display panel 100. In these embodiments, timing control circuitry 400 may include a plurality of timing transistors, and power supply circuitry 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed on a semiconductor substrate SSUB (see [link to semiconductor diagram]) using semiconductor processes. Figure 7 On. For example, in one or more embodiments, the plurality of timing transistors and the plurality of power transistors may be formed by CMOS, but embodiments of this disclosure are not limited thereto. In one or more embodiments, each of the timing control circuitry 400 and the power supply circuitry 500 may be arranged on the data driver 700 and the first pad portion PDA1 (see Figure 4 )between.

[0052] Figure 3 This is an equivalent circuit diagram of a first sub-pixel according to one or more embodiments of the present disclosure.

[0053] Reference Figure 3 The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emit control line EL1, the second emit control line EL2, and the data line DL. Furthermore, the first sub-pixel SP1 can be connected to the first driving voltage line VSL, the second driving voltage line VDL, and the third driving voltage line VIL. A first driving voltage VSS, corresponding to a low potential voltage, is applied to the first driving voltage line VSL; a second driving voltage VDD, corresponding to a high potential voltage, is applied to the second driving voltage line VDL; and a third driving voltage VINT, corresponding to the initialization voltage, is applied to the third driving voltage line VIL. For example, in one or more embodiments, the first driving voltage line VSL can be a low potential voltage line, the second driving voltage line VDL can be a high potential voltage line, and the third driving voltage line VIL can be an initialization voltage line. In these embodiments, the first driving voltage VSS can be lower than the third driving voltage VINT, and the second driving voltage VDD can be higher than the third driving voltage VINT.

[0054] In one or more embodiments, the first sub-pixel SP1 includes a plurality of transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0055] The light-emitting element LE emits light in response to a drive current flowing through the channel of the first transistor T1. The emission amount (e.g., emission intensity) of the light-emitting element LE can be proportional to the drive current. The light-emitting element LE can be disposed between the fourth transistor T4 and the first drive voltage line VSL. The first electrode of the light-emitting element LE can be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE can be connected to the first drive voltage line VSL. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. In one or more embodiments, the light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but the embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. In these embodiments, the light-emitting element LE can be a micro light-emitting diode.

[0056] The first transistor T1 may be a drive transistor that controls the source-drain current (hereinafter referred to as the "drive current") flowing between its source and drain electrodes according to the voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to the drain electrode of a sixth transistor T6, and a drain electrode connected to a second node N2.

[0057] A second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect the one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to the one electrode of the first capacitor CP1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to the one electrode of the first capacitor CP1.

[0058] A third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal from the control scan line GCL to connect the first node N1 to the second node N2. Therefore, if (for example, when) the gate and source electrodes of the first transistor T1 are connected, the first transistor T1 can operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0059] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first emitter control signal on the first emitter control line EL1 to connect the second node N2 to the third node N3. Therefore, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emitter control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0060] A fifth transistor T5 can be positioned between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal from the bias scan line GBL to connect the third node N3 to the third driving voltage line VIL. Therefore, the third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0061] A sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by a second emitter control signal of the second emitter control line EL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, a second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emitter control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0062] A first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0063] A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second drive voltage line VDL.

[0064] The first node N1 is the node between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is the node between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is the node between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0065] Each of the first transistors T1 to the sixth transistor T6 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, in one or more embodiments, each of the first transistors T1 to the sixth transistor T6 may be a P-type MOSFET, but the embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, each of the first transistors T1 to the sixth transistor T6 may be an N-type MOSFET. In one or more embodiments, some of the first transistors T1 to the sixth transistor T6 may be P-type MOSFETs, and each of the remaining transistors may be an N-type MOSFET.

[0066] Despite Figure 3 The diagram shows the first sub-pixel SP1 comprising six transistors T1 to T6 and two capacitors C1 and C2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to... Figure 3 The equivalent circuit diagram is shown. For example, the number of transistors and capacitors in the first sub-pixel SP1 is not limited to... Figure 3 The quantities shown.

[0067] Furthermore, the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 can both be combined with... Figure 3 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, the description of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 will not be repeated in this disclosure.

[0068] Figure 4 This is a layout diagram illustrating an example of a display panel according to one or more embodiments of the present disclosure.

[0069] Reference Figure 4The display area DAA of the display panel 100 according to one or more embodiments includes a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to one or more embodiments includes a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0070] The scan driver 610 can be arranged on a first side of the display area DAA, and the transmit driver 620 can be arranged on a second side of the display area DAA. For example, in one or more embodiments, the scan driver 610 can be arranged on one side of the display area DAA in a first direction DR1, and the transmit driver 620 can be arranged on the other side of the display area DAA in the first direction DR1. For example, as Figure 4 As shown, the scan driver 610 may be arranged on the left side of the display area DAA, and the transmit driver 620 may be arranged on the right side of the display area DAA. However, embodiments of this disclosure are not limited to this; for example, the scan driver 610 and the transmit driver 620 may be arranged (e.g., simultaneously) on both the first and second sides of the display area DAA.

[0071] The first pad portion PDA1 may include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 via conductive adhesive members. The first pad portion PDA1 may be disposed on a third side of the display area DAA. For example, in one or more embodiments, the first pad portion PDA1 may be disposed on one side of the display area DAA in the second direction DR2. The first pad portion PDA1 may be disposed on the second direction DR2 outside the data driver 700. For example, the first pad portion PDA1 may be disposed closer to the edge of the display panel 100 than the data driver 700.

[0072] The second pad portion PDA2 may include multiple second pads PD2 corresponding to the inspection pads used to test whether the display panel 100 is operating correctly. The multiple second pads PD2 may be connected to a fixture or probe pins during the inspection process, or they may be connected to a circuit board used for inspection. The circuit board used for inspection may be a rigid printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0073] The second pad portion PDA2 can be disposed on the fourth side of the display area DAA. For example, in one or more embodiments, the second pad portion PDA2 can be disposed on the other side of the display area DAA in the second direction DR2. The second pad portion PDA2 can be disposed outside the second distribution circuit 720 in the second direction DR2. For example, the second pad portion PDA2 can be disposed closer to the edge of the display panel 100 than the second distribution circuit 720.

[0074] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to multiple data lines DL. For example, in one or more embodiments, the first distribution circuit 710 can distribute the data voltage applied through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or greater) data lines DL, thereby reducing the number of multiple first pads PD1. The first distribution circuit 710 can be arranged on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be arranged on one side of the display area DAA in the second direction DR2. For example, the first distribution circuit 710 can be arranged on the lower side of the display area DAA.

[0075] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be arranged on a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be arranged on the other side of the display area DAA in the second direction DR2. For example, the second distribution circuit 720 can be arranged on the upper side of the display area DAA.

[0076] In the context of this disclosure, "one side of the display area DAA on the second direction DR2" refers to a specific side of the display area DAA along the direction designated DR2. For example, if the second direction DR2 represents a vertical direction, this could indicate the bottom side of the display area DAA. Conversely, "the other side of the display area DAA on the second direction DR2" refers to the opposite side of the display area DAA along the same second direction DR2, continuing the previous example, which could indicate the top side of the display area DAA. These phrases are used to describe the positioning of components (such as distribution circuitry) on opposite sides of the display area DAA along the specified second direction DR2.

[0077] Figure 5 and Figure 6 All are shown Figure 4 An example layout diagram of the display area.

[0078] Reference Figure 5 and Figure 6 Each of the pixels PX may include a first emission region EA1 as the emission region of the first sub-pixel SP1, a second emission region EA2 as the emission region of the second sub-pixel SP2, and a third emission region EA3 as the emission region of the third sub-pixel SP3.

[0079] Each of the first launch area EA1, the second launch area EA2, and the third launch area EA3 can have a polygonal shape, a circular shape, an elliptical shape, or an atypical shape in the plan view.

[0080] In one or more embodiments, the maximum length of the third transmission region EA3 in the first direction DR1 may be less than the maximum length of the second transmission region EA2 in the first direction DR1 and the maximum length of the first transmission region EA1 in the first direction DR1. The maximum length of the second transmission region EA2 in the first direction DR1 and the maximum length of the first transmission region EA1 in the first direction DR1 may be substantially the same.

[0081] In one or more embodiments, the maximum length of the third transmission region EA3 in the second direction DR2 may be greater than the maximum length of the second transmission region EA2 in the second direction DR2 and the maximum length of the first transmission region EA1 in the second direction DR2. The maximum length of the second transmission region EA2 in the second direction DR2 may be less than the maximum length of the third transmission region EA3 in the second direction DR2. The maximum length of the first transmission region EA1 in the second direction DR2 may be greater than the maximum length of the second transmission region EA2 in the second direction DR2.

[0082] In one or more embodiments, the first transmission region EA1, the second transmission region EA2, and the third transmission region EA3 may all have the following characteristics in a plan view: Figure 6 The hexagonal shape formed by six straight lines shown is not limited to this embodiment of the present disclosure. The first emission region EA1, the second emission region EA2, and the third emission region EA3 may each independently have a polygonal shape, a circular shape, an elliptical shape, or an atypical shape other than a hexagon in the plan view.

[0083] like Figure 5 As shown, in one or more embodiments, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the second direction DR2. Furthermore, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different.

[0084] In one or more embodiments, such as Figure 6As shown, the first transmission region EA1 and the second transmission region EA2 can be adjacent to each other in the first direction DR1, but the second transmission region EA2 and the third transmission region EA3 can be adjacent to each other in the first diagonal direction DD1, and the first transmission region EA1 and the third transmission region EA3 can be adjacent to each other in the second diagonal direction DD2. The first diagonal direction DD1 can be the direction between the first direction DR1 and the second direction DR2, and can refer to a direction inclined at 45 degrees relative to the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 can be a direction orthogonal (e.g., perpendicular) to the first diagonal direction DD1.

[0085] The first emission region EA1 can emit light of a first color, the second emission region EA2 can emit light of a second color, and the third emission region EA3 can emit light of a third color. In one or more embodiments, the first color light can be light in the blue band, the second color light can be light in the green band, and the third color light can be light in the red band. For example, the blue band can be a band of light whose main peak wavelength is in the range of approximately 370 nanometers (nm) to approximately 460 nm, the green band can be a band of light whose main peak wavelength is in the range of approximately 480 nm to approximately 560 nm, and the red band can be a band of light whose main peak wavelength is in the range of approximately 600 nm to approximately 750 nm.

[0086] exist Figure 5 and Figure 6 The illustration shows that each of a plurality of pixels PX includes three emission regions EA1, EA2, and EA3, but embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, each of the plurality of pixels PX may include four emission regions.

[0087] Furthermore, the layout of the emission regions of multiple pixel PXs is not limited to Figure 5 and Figure 6 The layout shown is illustrated. For example, in one or more embodiments, the emission regions of a plurality of pixels PX can be arranged in a stripe structure where the emission regions are arranged in a first direction DR1, or in a diamond-shaped PenTile. ® The structure, or the emission region within it that has a hexagonal shape in a planar view, such as Figure 6 The hexagonal structure arranged as shown in the image. (PenTile) ® It is an officially registered trademark of Samsung Display Co., Ltd.

[0088] Figure 7 It shows along Figure 5 A cross-sectional view of an example display panel taken by line I1-I1'. Figure 8 To show in more detail Figure 7 A sectional view of region A1.

[0089] Reference Figure 7 and Figure 8 The display panel 100 may include a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), a packaging layer (TFE), an optical layer (OPL), a cover layer (CVL), and a polarizer (POL).

[0090] The semiconductor backplane (SBP) includes a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) may include (e.g., are) references Figure 3 The first transistor T1 to the sixth transistor T6 are described.

[0091] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type (type) of impurity. Multiple well regions WA can be arranged on the top surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a second type (type) of impurity. The second type (type) of impurity can be different from the aforementioned first type (type) of impurity. For example, in one or more embodiments, if (e.g., when) the first type (type) of impurity is a P-type impurity, then the second type (type) of impurity can be an N-type impurity. In one or more embodiments, if (e.g., when) the first type (type) of impurity is an N-type impurity, then the second type (type) of impurity can be a P-type impurity.

[0092] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0093] The lower insulating film (BINS) can be disposed between the gate electrode GE and the well region WA. The side insulating film (SINS) can be disposed on the side surface of the gate electrode GE. The side insulating film (SINS) can also be disposed on the lower insulating film (BINS).

[0094] Each of the source region SA and drain region DA can be a region doped with a first type (species) impurity. The gate electrode GE of the pixel transistor PTR can be stacked with the well region WA on the third-direction DR3. The channel region CH can be stacked with the gate electrode GE on the third-direction DR3. The source region SA can be arranged on one side of the gate electrode GE, and the drain region DA can be arranged on the other side of the gate electrode GE.

[0095] Each of the multiple well regions WA may further include a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 may be a region having a lower impurity concentration than the drain region DA due to the lower insulating film BINS. The distance between the source region SA and the drain region DA may be increased due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH in each of the pixel transistors PTRs can be increased, thereby reducing or preventing punch-through and hot carrier phenomena that may be caused by short channels.

[0096] The first semiconductor insulating film SINS1 can be disposed on the semiconductor substrate SSUB. In one or more embodiments, the first semiconductor insulating film SINS1 can be made of silicon carbonitride (SiCN)-type inorganic film or silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0097] A second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1. In one or more embodiments, the second semiconductor insulating film SINS2 can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0098] Multiple contact terminals (CTEs) can be arranged on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to any one of the gate electrode (GE), source region (SA), and drain region (DA) of each pixel transistor (PTR) through a hole penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (INS2). The multiple contact terminals (CTEs) can all be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound comprising any one of them.

[0099] A third semiconductor insulating film (SINS3) can be disposed on the side surface of each of the plurality of contact terminals (CTEs). The top surface of each of the plurality of contact terminals (CTEs) can be exposed and not covered by the third semiconductor insulating film (SINS3). In one or more embodiments, the third semiconductor insulating film (SINS3) can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0100] In one or more embodiments, the semiconductor substrate SSUB can be replaced by a glass substrate or a polymeric resin substrate such as polyimide. In these embodiments, the thin-film transistor can be disposed on the glass substrate or the polymeric resin substrate. The glass substrate can be a rigid substrate that does not bend, and the polymeric resin substrate can be a flexible substrate that can be bent or flexed.

[0101] The backplane (EBP) of the light-emitting element includes multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple insulating films INS1 to INS9. In one or more embodiments, the backplane (EBP) of the light-emitting element includes multiple insulating films INS1 to INS9 disposed between the third semiconductor insulating film SINS3 and the first conductive layer ML1, between the first conductive layer ML1 to the eighth conductive layer ML8, and between the eighth conductive layer ML8 and the display element layer EML.

[0102] The first conductive layers ML1 to the eighth conductive layers ML8 are used to connect multiple contact terminals CTE exposed from the semiconductor backplane SBP, thereby achieving Figure 3 The circuitry of the first sub-pixel SP1 is shown. For example, in one or more embodiments, the first transistors T1 to the sixth transistor T6 are formed only in the semiconductor backplane SBP, and the connection between the first transistors T1 to the sixth transistor T6 and the first capacitor C1 and the second capacitor C2 is achieved through the first conductive layer ML1 to the eighth conductive layer ML8. Furthermore, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light-emitting element LE is also achieved through the first conductive layer ML1 to the eighth conductive layer ML8.

[0103] A first insulating film INS1 may be disposed on a semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first insulating film INS1 and connect to a contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first conductive layers ML1 may be disposed on the first insulating film INS1 and may connect to the first via VA1.

[0104] A second insulating film INS2 can be disposed on the first insulating film INS1 and the first conductive layer ML1. Each of the second vias VA2 can penetrate the second insulating film INS2 and connect to the exposed first conductive layer ML1. Each of the second conductive layers ML2 can be disposed on the second insulating film INS2 and can connect to the second via VA2.

[0105] A third insulating film INS3 can be disposed on the second insulating film INS2 and the second conductive layer ML2. Each of the third vias VA3 can penetrate the third insulating film INS3 and connect to the exposed second conductive layer ML2. Each of the third conductive layers ML3 can be disposed on the third insulating film INS3 and can connect to the third via VA3.

[0106] A fourth insulating film INS4 can be disposed on the third insulating film INS3 and the third conductive layer ML3. Each of the fourth vias VA4 can penetrate the fourth insulating film INS4 and connect to the exposed third conductive layer ML3. Each of the fourth conductive layers ML4 can be disposed on the fourth insulating film INS4 and can connect to the fourth via VA4.

[0107] A fifth insulating film INS5 can be disposed on the fourth insulating film INS4 and the fourth conductive layer ML4. Each of the fifth vias VA5 can penetrate the fifth insulating film INS5 and connect to the exposed fourth conductive layer ML4. Each of the fifth conductive layers ML5 can be disposed on the fifth insulating film INS5 and can connect to the fifth via VA5.

[0108] A sixth insulating film INS6 can be disposed on the fifth insulating film INS5 and the fifth conductive layer ML5. Each of the sixth vias VA6 can penetrate the sixth insulating film INS6 and connect to the exposed fifth conductive layer ML5. Each of the sixth conductive layers ML6 can be disposed on the sixth insulating film INS6 and can connect to the sixth via VA6.

[0109] A seventh insulating film INS7 can be disposed on the sixth insulating film INS6 and the sixth conductive layer ML6. Each of the seventh vias VA7 can penetrate the seventh insulating film INS7 and connect to the exposed sixth conductive layer ML6. Each of the seventh conductive layers ML7 can be disposed on the seventh insulating film INS7 and can connect to the seventh via VA7.

[0110] The eighth insulating film INS8 can be disposed on the seventh insulating film INS7 and the seventh conductive layer ML7. Each of the eighth vias VA8 can penetrate the eighth insulating film INS8 and connect to the exposed seventh conductive layer ML7. Each of the eighth conductive layers ML8 can be disposed on the eighth insulating film INS8 and can connect to the eighth via VA8.

[0111] The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be formed of substantially the same material. In one or more embodiments, the first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can all be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound thereof. The first vias VA1 to VA8 can be made of substantially the same material. The first insulating films INS1 to INS8 can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0112] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be substantially the same. For example, in one or more embodiments, the thickness of the first conductive layer ML1 can be approximately 1360 angstroms (Å) (i.e., 10...). -10 The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be approximately 1440 Å. The thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 may be approximately 1150 Å.

[0113] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of each of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the seventh via VA7 and the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 may be greater than the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be substantially the same. For example, in one or more embodiments, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be approximately 9000 Å. The thickness of each of the seventh via VA7 and the eighth via VA8 may be approximately 6000 Å.

[0114] The ninth insulating film INS9 can be disposed on the eighth insulating film INS8 and the eighth conductive layer ML8. In one or more embodiments, the ninth insulating film INS9 can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0115] Each of the ninth vias VA9 can penetrate the ninth insulating film INS9 and connect to the exposed eighth conductive layer ML8. The ninth via VA9 can be formed of any alloy or compound selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). In one or more embodiments, the thickness of the ninth via VA9 can be approximately 16,500 Å.

[0116] The display element layer (EML) can be disposed on the light-emitting element backplane (EBP). The display element layer (EML) may include: light-emitting elements (LEs), each of which includes a first electrode AND, a light-emitting stack IL, and a second electrode CAT; a reflective electrode layer RL; a tenth insulating film INS10; a tenth via VA10; a pixel defining film (PDL); and multiple trenches TRC.

[0117] The reflective electrode layer RL can be disposed on the ninth insulating film INS9. The reflective electrode layer RL may include at least one of reflective electrodes RL1, RL2, RL3, and RL4, and a step layer STPL. For example, Figure 7 The illustration shows one or more reflective electrodes RL1, RL2, RL3 and RL4 including a first reflective electrode to a fourth reflective electrode RL1, RL2, RL3 and RL4, but the embodiments of this disclosure are not limited thereto.

[0118] Each of the first reflective electrodes RL1 may be disposed on the ninth insulating film INS9 and may be connected to the ninth via VA9. The first reflective electrodes RL1 may be formed of any alloy or compound selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, in one or more embodiments, the first reflective electrodes RL1 may comprise titanium nitride (TiN).

[0119] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrodes RL2 may be formed of any one or an alloy or compound selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, in one or more embodiments, the second reflective electrode RL2 may comprise aluminum (Al).

[0120] In the third sub-pixel SP3, the stepped layer STPL can be arranged on the second reflective electrode RL2. The stepped layer STPL may not be arranged on the second reflective electrode RL2 in the second sub-pixel SP2 and the first sub-pixel SP1.

[0121] The thickness of the stepped layer STPL can be set taking into account the wavelength of the third color light and the distance from the light-emitting stack IL of the third sub-pixel SP3 to the fourth reflective electrode RL4, so as to advantageously reflect the third color light emitted from the light-emitting stack IL.

[0122] In one or more embodiments, the stepped layer STPL can be composed of an inorganic film such as silicon carbonitride (SiCN) or silicon oxide (SiO). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0123] In the first sub-pixel SP1, the third reflective electrode RL3 can be disposed on the second reflective electrode RL2. In the second sub-pixel SP2, the third reflective electrode RL3 can be disposed on the second reflective electrode RL2. In the third sub-pixel SP3, the third reflective electrode RL3 can be disposed on the stepped layer STPL. The third reflective electrode RL3 can be formed of any alloy or compound selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the third reflective electrode RL3 may include titanium nitride (TiN).

[0124] In one or more embodiments, at least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 may not be provided.

[0125] A fourth reflective electrode RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may be a layer that reflects light from the light-emitting stack IL. The fourth reflective electrode RL4 may include a metal with high reflectivity to advantageously reflect light. Furthermore, because the fourth reflective electrode RL4 is the electrode that substantially reflects light from the light-emitting element LE, the thickness of the fourth reflective electrode RL4 may be greater than the thickness of each of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3. The fourth reflective electrode RL4 may be formed of any alloy or compound selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, in one or more embodiments, the fourth reflective electrode RL4 may include aluminum (Al) or titanium (Ti).

[0126] The tenth insulating film INS10 can be disposed on the ninth insulating film INS9 and the fourth reflective electrode RL4. The tenth insulating film INS10 can be an optical auxiliary layer through which light reflected from the light emitted by the light-emitting element LE by the reflective electrode layer RL passes. In one or more embodiments, the tenth insulating film INS10 can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0127] Each of the tenth vias VA10 can penetrate the tenth insulating film INS10 and connect to the exposed reflective electrode layer RL (e.g., the exposed fourth reflective electrode RL4). The tenth vias VA10 can be formed of any alloy or compound selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or including any of them.

[0128] The thickness of the tenth via VA10 can vary among the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 to adjust the resonant distance of light emitted from the light-emitting element LE in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, in one or more embodiments, the thickness of the tenth via VA10 in the third sub-pixel SP3 can be less than the thickness of the tenth via VA10 in each of the first sub-pixel SP1 and the second sub-pixel SP2. Furthermore, the thickness of the tenth via VA10 in the second sub-pixel SP2 can be less than the thickness of the tenth via VA10 in the first sub-pixel SP1. For example, in one or more embodiments, the distance between the light-emitting stack IL and the reflective electrode layer RL can be different among the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0129] In summary, in order to adjust the distance between the light-emitting stack IL and the reflective electrode layer RL according to the dominant wavelength (e.g., peak wavelength) of the light emitted from the third sub-pixel SP3, the presence or absence of the step layer STPL in the first sub-pixel SP1, the second sub-pixel SP2 and / or the third sub-pixel SP3, as well as the thickness of the step layer STPL, can be set.

[0130] The first electrode AND of each of the light-emitting elements LE can be disposed on the tenth insulating film INS10 and connected to the tenth via VA10. The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the tenth via VA10, the first reflective electrodes RL1 to the fourth reflective electrodes RL4, the first via VA1 to the ninth via VA9, the first conductive layer ML1 to the eighth conductive layer ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound comprising any one of them. For example, in one or more embodiments, the first electrode AND of each of the light-emitting elements LE can be titanium nitride (TiN).

[0131] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL can be used to separate a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3.

[0132] The first emission region EA1 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission region EA2 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission region EA3 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0133] The pixel-defining film (PDL) may include first pixel-defining films to third pixel-defining films PDL1, PDL2, and PDL3. The first pixel-defining film PDL1 may be disposed on the edge of the first electrode AND of each of the light-emitting elements (LEs), the second pixel-defining film PDL2 may be disposed on the first pixel-defining film PDL1, and the third pixel-defining film PDL3 may be disposed on the second pixel-defining film PDL2. In one or more embodiments, the first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 may all be made of silicon oxide (SiO2). x The present disclosure describes the formation of inorganic films, but the embodiments are not limited thereto. In one or more embodiments, the first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 may each have a thickness of about 500 Å.

[0134] When the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 form a single pixel defining film, the height of this single pixel defining film increases, making the first sub-encapsulation layer TFE1 potentially cut due to step coverage. Step coverage refers to the ratio of the degree of film coating on the inclined portion to the degree of film coating on the flat portion. The lower the step coverage, the easier it is for the film to be cut at the inclined portion.

[0135] Therefore, to reduce or prevent the possibility of the first sub-encapsulation layer TFE1 being cut off due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may have a cross-sectional structure with stepped portions. For example, in one or more embodiments, the width of the first pixel defining film PDL1 may be greater than the width of the second pixel defining film PDL2 and the width of the third pixel defining film PDL3, and the width of the second pixel defining film PDL2 may be greater than the width of the third pixel defining film PDL3. The width of the first pixel defining film PDL1 refers to the horizontal length of the first pixel defining film PDL1 defined in the first direction DR1 and the second direction DR2.

[0136] Each of the multiple trench TRCs can penetrate the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. Furthermore, the tenth insulating film INS10 can be partially recessed at each of the multiple trench TRCs.

[0137] In one or more embodiments, at least one trench TRC may be arranged between adjacent sub-pixels SP1, SP2, and SP3. Although Figure 7 Two trench TRCs are shown arranged between adjacent sub-pixels SP1, SP2 and SP3, but embodiments of this disclosure are not limited thereto.

[0138] The light-emitting stack (IL) can include multiple intermediate layers. Figure 7 The illustration shows a light-emitting stack IL having a three-tiered structure comprising a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3; however, embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, the light-emitting stack IL may have a two-tiered structure comprising two stacked layers.

[0139] In a three-tiered structure, the light-emitting stack IL can have a series structure comprising multiple stacked layers IL1, IL2, and IL3 that emit different colors of light. For example, in one or more embodiments, the light-emitting stack IL may include a first stacked layer IL1 that emits light of a first color, a second stacked layer IL2 that emits light of a second color, and a third stacked layer IL3 that emits light of a third color. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 may be stacked sequentially.

[0140] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a second color, and a second electron transport layer are sequentially stacked. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of a third color, and a third electron transport layer are sequentially stacked.

[0141] In one or more embodiments, a first charge-generating layer for supplying holes to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The first charge-generating layer may include an N-type charge-generating layer that supplies electrons to the first stacked layer IL1 and a P-type charge-generating layer that supplies holes to the second stacked layer IL2. The N-type charge-generating layer may include a dopant of a metallic material.

[0142] A second charge generation layer for supplying holes to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be disposed between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer that supplies electrons to the second stacked layer IL2 and a P-type charge generation layer that supplies holes to the third stacked layer IL3.

[0143] A first stacked layer IL1 can be disposed on the first electrode AND and the pixel defining film PDL. A remaining stacked layer RIL, made of the same material as the first stacked layer IL1, can be disposed on the bottom surface of each of the trench TRCs. Due to the trench TRCs, the first stacked layer IL1 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A second stacked layer IL2 can be disposed on the first stacked layer IL1. Due to the trench TRCs, the second stacked layer IL2 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A void ESS, or empty space, can be disposed in each trench TRC between the remaining stacked layer RIL and the second stacked layer IL2. A third stacked layer IL3 can be disposed on the second stacked layer IL2. The third stacked layer IL3 is not cut by the trench TRCs and can be disposed to cover the second stacked layer IL2 in each trench of the trench TRC. For example, in one or more embodiments, in a three-in-line structure, each of the plurality of trench TRCs may be a structure for cutting off the first stacked layer IL1 and the second stacked layer IL2, the first charge generation layer and the second charge generation layer of the display element layer EML between adjacent sub-pixels SP1, SP2 and SP3.

[0144] Furthermore, in the dual-series structure, each of the multiple trench TRCs can be a structure for cutting off the lower stacked layer and the charge-generating layer disposed between the lower stacked layer and the upper stacked layer.

[0145] To stably cut the first stacked layer IL1 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of trench TRCs can be greater than the height of the pixel defining film PDL. The height of each of the plurality of trench TRCs refers to the length of each of the plurality of trench TRCs in the third direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL in the third direction DR3. In one or more embodiments, to cut the first to third stacked layers IL1, IL2, and IL3 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, another structure may exist instead of trench TRCs. For example, instead of trench TRCs, inverted conical partition walls may be arranged on the pixel defining film PDL.

[0146] also, Figure 7 and Figure 8The illustration shows that all three stacked layers IL1, IL2, and IL3 are arranged within the first emission region EA1, the second emission region EA2, and the third emission region EA3; however, the embodiments disclosed herein are not limited to this. For example, in one or more embodiments, the first stacked layer IL1 may be arranged within the first emission region EA1 and may not be located within the second and third emission regions EA2 and EA3. Furthermore, the second stacked layer IL2 may be arranged within the second emission region EA2 and may not be located within the first and third emission regions EA1 and EA3. Additionally, the third stacked layer IL3 may be arranged within the third emission region EA3 and may not be located within the first and second emission regions EA1 and EA2. In these embodiments, the first to third color filters CF1, CF2, and CF3 of the optical layers OPL may not be present.

[0147] The second electrode CAT can be disposed on the third stacked layer IL3. The second electrode CAT can be disposed on the third stacked layer IL3 in each of the multiple trench TRCs. The second electrode CAT can be formed of a transparent conductive material (TCO) that can transmit light (such as indium tin oxide (ITO) or indium zinc oxide (IZO)) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag). When the second electrode CAT is formed of a semi-transmissive conductive material, the luminous efficiency can be improved in each of the first to third sub-pixels SP1, SP2, and SP3 due to the microcavity effect.

[0148] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE may include at least one of inorganic films TFE1, TFE2, TFE4, and TFE5 to reduce or prevent oxygen and / or moisture penetration into the display element layer EML. For example, in one or more embodiments, the encapsulation layer TFE may include a first sub-encapsulation layer TFE1, a second sub-encapsulation layer TFE2, a third sub-encapsulation layer TFE3, a fourth sub-encapsulation layer TFE4, and a fifth sub-encapsulation layer TFE5 sequentially stacked along the thickness direction of the encapsulation layer TFE (e.g., third direction DR3). Here, the first sub-encapsulation layer TFE1, the second sub-encapsulation layer TFE2, the fourth sub-encapsulation layer TFE4, and the fifth sub-encapsulation layer TFE5 may all comprise inorganic materials, and the third sub-encapsulation layer TFE3 may comprise organic materials.

[0149] The first sub-encapsulation layer TFE1 can be disposed on the second electrode CAT. The first sub-encapsulation layer TFE1 can be formed in which silicon nitride (SiN) is disposed. x ) membrane, silicon oxynitride (SiON) membrane and silicon oxide (SiO) membrane xThe membrane is a multilayer of one or more inorganic membranes stacked alternately. The first sub-encapsulation layer TFE1 can be formed by chemical vapor deposition (CVD). The thickness of the first sub-encapsulation layer TFE1 can be less than or equal to 1 micrometer (μm).

[0150] The second sub-encapsulation layer TFE2 may be disposed on the first sub-encapsulation layer TFE1. For example, the second sub-encapsulation layer TFE2 may be disposed between the first sub-encapsulation layer TFE1 and the third sub-encapsulation layer TFE3. The second sub-encapsulation layer TFE2 may be in contact (or in direct contact) with each of the first sub-encapsulation layer TFE1 and the third sub-encapsulation layer TFE3. The second sub-encapsulation layer TFE2 may include a transparent conductive material (e.g., a transparent conductive film). For example, in one or more embodiments, the second sub-encapsulation layer TFE2 may include at least one material selected from transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and zinc aluminum oxide (AZO). The thickness of the second sub-encapsulation layer TFE2 may be greater than or equal to 90 nm.

[0151] The third sub-encapsulation layer TFE3 can be disposed on the second sub-encapsulation layer TFE2. For example, the third sub-encapsulation layer TFE3 can be disposed between the second sub-encapsulation layer TFE2 and the fourth sub-encapsulation layer TFE4. The third sub-encapsulation layer TFE3 can be in contact (or in direct contact) with each of the second sub-encapsulation layer TFE2 and the fourth sub-encapsulation layer TFE4. The third sub-encapsulation layer TFE3 can be an organic film formed of materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. The thickness of the third sub-encapsulation layer TFE3 can be less than or equal to 1 μm.

[0152] The fourth sub-package layer TFE4 can be disposed on the third sub-package layer TFE3. For example, the fourth sub-package layer TFE4 can be disposed between the third sub-package layer TFE3 and the fifth sub-package layer TFE5. The fourth sub-package layer TFE4 can be in contact (or in direct contact) with each of the third sub-package layer TFE3 and the fifth sub-package layer TFE5. The fourth sub-package layer TFE4 can be formed in which silicon nitride (SiN) is formed. x ) membrane, silicon oxynitride (SiON) membrane and silicon oxide (SiO) membrane x The membrane is a multilayer consisting of one or more inorganic membranes stacked alternately. The fourth sub-encapsulation layer TFE4 can be formed by chemical vapor deposition (CVD). The thickness of the fourth sub-encapsulation layer TFE4 can be less than or equal to 0.5 μm.

[0153] The fifth sub-encapsulation layer TFE5 can be disposed on the fourth sub-encapsulation layer TFE4. For example, the fifth sub-encapsulation layer TFE5 can be disposed between the fourth sub-encapsulation layer TFE4 and the organic membrane APL. The fifth sub-encapsulation layer TFE5 can be in contact (or in direct contact) with each of the fourth sub-encapsulation layer TFE4 and the organic membrane APL. The fifth sub-encapsulation layer TFE5 can be disposed at the uppermost position among the sub-encapsulation layers TFE1 to TFE5 of the encapsulation layer TFE. The fifth sub-encapsulation layer TFE5 can be made of titanium oxide (TiO2). x ) or aluminum oxide (AlO x For example, it can be formed using Al2O3, but the embodiments disclosed herein are not limited thereto. The fifth sub-encapsulation layer TFE5 can be formed using an atomic layer deposition (ALD) process. The thickness of the fifth sub-encapsulation layer TFE5 can be less than or equal to 100 nm.

[0154] Organic film APL can be a layer used to increase the interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. Organic film APL can be an organic film formed from resins such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0155] The optical layer OPL includes multiple color filters CF1, CF2, and CF3, multiple lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include first to third color filters CF1, CF2, and CF3. The first to third color filters CF1, CF2, and CF3 may all be arranged on the organic film APL.

[0156] The first color filter CF1 can be superimposed on the first emission region EA1 of the first sub-pixel SP1. The first color filter CF1 can transmit light of a first color, such as light in the red band. Therefore, the first color filter CF1 can transmit light of the first color emitted from the first emission region EA1.

[0157] The second color filter CF2 can be superimposed on the second emission region EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of a second color, such as light in the green band. Therefore, the second color filter CF2 can transmit light of a second color emitted from the second emission region EA2.

[0158] The third color filter CF3 can be superimposed on the third emission region EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of a third color, such as light in the blue band. Therefore, the third color filter CF3 can transmit light of a third color emitted from the third emission region EA3.

[0159] Multiple lenses LNS can be arranged on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the multiple lenses LNS can be a structure for increasing the proportion of light directed to the front of the display device 10. Although each of the lenses LNS is shown as having an upwardly convex cross-sectional shape, the embodiments of this disclosure are not limited thereto.

[0160] A filler layer (FIL) can be disposed on multiple lens lenses (LNS). The filler layer FIL can have a set or predetermined refractive index, such that light travels in the third direction (DR3) at the interface between the filler layer FIL and the multiple lens lenses (LNS). Furthermore, the filler layer FIL can also be a planarization layer. The filler layer FIL can be an organic film formed from resins such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0161] A cover layer CVL can be disposed on a filler layer FIL. The cover layer CVL can be a glass substrate or a polymer resin. In one or more embodiments, the cover layer CVL is a glass substrate that can be attached to the filler layer FIL. In these embodiments, the filler layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate. In one or more embodiments, the cover layer CVL is a polymer resin that can be applied directly to the filler layer FIL.

[0162] A polarizer (POL) can be disposed on (e.g., one) surface of a CVL (CVL) cover layer. The polarizer POL can be a structure used to reduce or prevent visibility degradation caused by reflection of external light. The polarizer POL can include a linear polarizer and a phase retardation film. For example, in one or more embodiments, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but embodiments of this disclosure are not limited thereto. However, if (e.g., when) visibility degradation caused by reflection of external light is sufficiently overcome by the first to third color filters CF1, CF2, and CF3, a polarizer POL may not be required.

[0163] Figure 9 Specifically illustrating one or more embodiments according to this disclosure Figure 8 A cross-sectional view of region A2.

[0164] Reference Figure 9 In one or more embodiments, the trench TRC can be a structure for cutting off the charge-generating layer between the first stacked layer IL1 and the second stacked layer IL2 of the light-emitting stack IL. The trench TRC can be defined as a hole penetrating the pixel defining film PDL and in which the tenth insulating film INS10 is partially recessed. The trench TRC can be formed by a photolithography process using argon fluoride (ArF) laser etching.

[0165] The trench TRC may include the inlet ENT, the sidewall SW, and the bottom surface FS.

[0166] The entrance ENT of a trench TRC can be an opening region at the top of the trench TRC defined by the third pixel defining film PDL3. The entrance ENT of the trench TRC can be covered by the light-emitting stack IL. For example, in one or more embodiments, a first stack layer IL1 and a second stack layer IL2 can be sequentially arranged at the edge of the entrance ENT of the trench TRC. The entrance ENT of the trench TRC exposed when not covered by the first stack layer IL1 and the second stack layer IL2 can be covered by the third stack layer IL3.

[0167] The sidewall SW of the trench TRC can be a side surface that connects the inlet ENT of the trench TRC to the bottom surface FS of the trench TRC. The sidewall SW of the trench TRC can be defined by a tenth insulating film INS10 and a pixel defining film PDL. The length of the sidewall SW of the trench TRC defined by the tenth insulating film INS10 can be greater than the length of the sidewall SW of the trench TRC defined by the pixel defining film PDL.

[0168] The bottom surface FS of the trench TRC can be a closed region at the bottom of the trench TRC defined by the tenth insulating film INS10. The remaining stacked layers RIL, made of the same material as the first stacked layer IL1, can be disposed on the bottom surface FS of the trench TRC.

[0169] The height Htrc of the trench TRC can be defined as the maximum distance from the bottom surface FS of the trench TRC to the entrance ENT of the trench TRC on the third-direction DR3. In one or more embodiments, in order to cut off the first stacked layer IL1 and the second stacked layer IL2, the first charge generation layer and the second charge generation layer in each of the trenches TR, the height Htrc of the trench TRC can be in the range of approximately 6000 Å to 10000 Å. In these embodiments, the height of the pixel defining film PDL can be approximately 1500 Å. For example, in one or more embodiments, the sum of the thicknesses of the first pixel defining film PDL1, the second pixel defining film PDL2 and the third pixel defining film PDL3 can be less than or equal to 1 / 4 of the height Htrc of the trench TRC.

[0170] In one or more embodiments, in order to cut off the first stacked layer IL1 and the second stacked layer IL2, the first charge generation layer and the second charge generation layer in each of the trench TRCs, an angle θent1 is formed at the entrance ENT of the trench TRC between the tangent TL of the sidewall SW of the trench TRC and the top surface of the third pixel defining film PDL3, which can be in the range of 80° to 90°. Therefore, the maximum width Wsw1 of the trench TRC in one direction at the center of the sidewall SW can be greater than the width Went1 of the entrance ENT in one direction and the width Wfs1 of the bottom surface FS in one direction. For example, each of the trench TRCs can have a can-shaped profile.

[0171] Furthermore, in one or more embodiments, in order to cut off the first stacked layer IL1 and the second stacked layer IL2, the first charge generation layer and the second charge generation layer in each of the trench TRCs, the width Went1 of the trench TRC's entrance ENT can be approximately greater than 100 nm and less than 130 nm. Additionally, the width Wfs1 of the bottom surface FS of the trench TRC in one direction can be smaller than the width Went1 of the trench TRC's entrance ENT in one direction.

[0172] The first stacked layer IL1 and the second stacked layer IL2 can be sequentially arranged at the edge of the entrance ENT of each trench TRC. The first stacked layer IL1 can be arranged closer to the edge of the entrance ENT of each trench TRC than the second stacked layer IL2. The third stacked layer IL3 can be arranged to cover the remaining portion of the entrance ENT of each trench TRC that is not covered by the first stacked layer IL1 and the second stacked layer IL2.

[0173] According to one or more embodiments, in addition to inorganic and organic films, the encapsulation layer TFE may also include transparent conductive oxides (e.g., IZO) and alumina (e.g., Al2O3). Therefore, the moisture-proofing function and sealing force of the encapsulation layer TFE can be improved. Specifically, the display device 10 including trench TRC may have a structure that allows moisture to easily permeate from the outside through the voids ESS (e.g., voids in the microcells) created by the trench TRC. However, the encapsulation layer TFE of one or more embodiments can prevent or reduce such moisture permeation through the voids.

[0174] Furthermore, the thickness of the encapsulation layer TFE can be further reduced, enabling the display device 10 to be thinner (e.g., made thinner). For example, the encapsulation layer TFE of the display device 10 according to one or more embodiments may have a thickness of about 20,140 Å, which may be less than the thickness of the encapsulation layer of a typical display device (e.g., about 105,000 Å).

[0175] According to one or more embodiments, in the encapsulation layer TFE having the aforementioned thickness (e.g., approximately 20,140 Å), the first sub-encapsulation layer TFE1 may have a thickness of 700 Å, the second sub-encapsulation layer TFE2 may have a thickness of 900 Å, the third sub-encapsulation layer TFE3 may have a thickness of 11,000 Å, the fourth sub-encapsulation layer TFE4 may have a thickness of 7,000 Å, and the fifth sub-encapsulation layer TFE5 may have a thickness of 540 Å. Here, the thickness can be a dimension (e.g., length) on the third-direction DR3.

[0176] Furthermore, as described above, since the encapsulation layer TFE according to one or more embodiments also includes a transparent conductive oxide (e.g., IZO), the current of the display device 10 (e.g., the current supplied to the light-emitting element LE of the display device 10) can be increased. This will be referred to... Figure 10 and Figure 11 To describe in more detail.

[0177] Figure 10 This is a diagram used to illustrate the current increase effect and brightness improvement effect of a display device according to one or more embodiments of the present disclosure.

[0178] exist Figure 10 In the first embodiment, the display device EMB1, and in the second embodiment, the encapsulation layer TFE of each may include IZO. For example, the encapsulation layer TFE of the display device EMB1 in the first embodiment may include a first sub-encapsulation layer TFE1, a second sub-encapsulation layer TFE2 (e.g., a second sub-encapsulation layer TFE2 including IZO), a third sub-encapsulation layer TFE3, and a fourth sub-encapsulation layer TFE4, and the encapsulation layer TFE of the display device EMB2 in the second embodiment may also have the same structure as the encapsulation layer TFE of the display device EMB1 in the first embodiment. Meanwhile, in Figure 10 In the comparative example, the encapsulation layer of the display device REF may not include (e.g., may exclude) (e.g., any) transparent conductive oxide. For example, the encapsulation layer of the display device REF according to the comparative example may include a first sub-encapsulation layer TFE1, a third sub-encapsulation layer TFE3, and a fourth sub-encapsulation layer TFE4.

[0179] like Figure 10As shown, the display device EMB1 according to the first embodiment and the display device EMB2 according to the second embodiment can both carry a greater current than the current of the display device REF of the comparative example. Therefore, the display device EMB1 according to the first embodiment and the display device EMB2 according to the second embodiment can provide images with a brightness higher than that of the display device REF of the comparative example. For example, the median brightness Med, average brightness Avg, and maximum brightness Max of the display device EMB1 according to the first embodiment can be greater than the median brightness Med, average brightness Avg, and maximum brightness Max of the display device REF of the comparative example, respectively. At the same time, the standard brightness deviation stdev of the display device EMB1 according to the first embodiment can be smaller than the standard brightness deviation stdev of the display device REF of the comparative example.

[0180] Furthermore, the median brightness (Med), average brightness (Avg), and maximum brightness (Max) of the display device EMB2 according to the second embodiment can be greater than those of the display device REF in the comparative example. Meanwhile, the standard brightness deviation (stdev) of the display device EMB2 according to the second embodiment can be smaller than that of the display device REF in the comparative example.

[0181] Figure 11 This is a diagram used to illustrate the current reduction improvement effect of a display device according to one or more embodiments of the present disclosure.

[0182] exist Figure 11 In this context, the encapsulation layer TFE of the display device according to one or more embodiments may include IZO. For example, the encapsulation layer TFE of the display device EMB3 according to the third embodiment may include a first sub-encapsulation layer TFE1, a second sub-encapsulation layer TFE2 (e.g., a second sub-encapsulation layer TFE2 including IZO), a third sub-encapsulation layer TFE3, and a fourth sub-encapsulation layer TFE4. Meanwhile, in... Figure 11 In the comparative example, the encapsulation layer of the display device REF may not include (e.g., may exclude) transparent conductive oxide. For example, the encapsulation layer of the display device REF according to the comparative example may include a first sub-encapsulation layer TFE1, a third sub-encapsulation layer TFE3, and a fourth sub-encapsulation layer TFE4.

[0183] Figure 11 The current values ​​measured during wafer visual inspection (WVI) and product visual inspection (PVI) are shown. Additionally, Figure 11 The diagram also shows the current values ​​of the display device measured during product visual inspection prior to reliability testing and during product visual inspection after reliability testing. Here, reliability testing may include performance testing of the display device under harsh conditions (e.g., high temperature).

[0184] like Figure 11 As shown, the current of the display device EMB3 of the third embodiment during wafer visual inspection (WVI) and product visual inspection (PVI) can be greater than the current of the display device REF of the comparative example during wafer visual inspection (WVI) and product visual inspection (PVI). Specifically, before (B) and after (A) the reliability test, the current of the display device EMB3 of the third embodiment (e.g., the current measured during the product visual test) can be greater than the current of the display device REF of the comparative example (e.g., the current measured during the product visual test). Therefore, the amount and rate of change of current measured before and after the reliability test can be smaller in the display device EMB3 according to the third embodiment than in the display device REF of the comparative example. For example, after the reliability test, it was found that the current reduction of the display device EMB3 of the third embodiment is less than the current reduction of the display device REF of the comparative example.

[0185] In this way, it has components including transparent conductive oxides (e.g., IZO) and aluminum oxide (AlO). x For example, a display device 10 with an Al2O3 encapsulation layer TFE can have a small size, reduced moisture permeability, improved encapsulation functionality, high current drive capability, and low current reduction rate after reliability testing.

[0186] Figure 12 This is a perspective view illustrating a head-mounted display according to one or more embodiments of the present disclosure. Figure 13 It is shown Figure 12 An exploded perspective view of an example of a head-mounted display.

[0187] Reference Figure 12 and Figure 13 A head-mounted display 1000 according to one or more embodiments includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0188] The first display device 10_1 provides an image to the user's left eye, and the second display device 10_2 provides an image to the user's right eye. This is because each of the first display device 10_1 and the second display device 10_2 is combined with... Figure 1 and Figure 2 The display devices 10 described are substantially the same, so descriptions of the first display device 10_1 and the second display device 10_2 will not be provided.

[0189] The first optical component 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0190] The intermediate frame 1400 can be arranged between the first display device 10_1 and the control circuit board 1600, and between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0191] The control circuit board 1600 can be arranged between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 1600 can convert externally input image sources into digital video data DATA, and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 via connectors.

[0192] In one or more embodiments, the control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image that is improved or optimized for the user's left eye to the first display device 10_1, and can transmit digital video data DATA corresponding to a right-eye image that is improved or optimized for the user's right eye to the second display device 10_2. In one or more embodiments, the control circuit board 1600 can transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0193] The display device housing 1100 is used to house a first display device 10_1, a second display device 10_2, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600. A housing cover 1200 is arranged to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Figure 12 and Figure 13 The first eyepiece 1210 and the second eyepiece 1220 are shown arranged separately, but the embodiments of this disclosure are not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined into one.

[0194] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical component 1520. Therefore, the user can view the image of the first display device 10_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0195] The headband 1300 is used to secure the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are positioned over the user's left and right eyes, respectively. In one or more embodiments, when the display device housing 1100 is implemented to be lightweight and compact, the head-mounted display 1000 can be configured as follows: Figure 14 The eyeglasses frame shown is not the headband 1300.

[0196] In one or more embodiments, the head-mounted display 1000 may further include a battery for supplying power, an external memory slot for accommodating external memory, and an external connection port and a wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) terminal, a display port, or a High Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0197] Figure 14 This is a perspective view illustrating a head-mounted display according to one or more embodiments of the present disclosure.

[0198] Reference Figure 14 The head-mounted display 1000_1 according to one or more embodiments may be an eyeglass-type (or similar) display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display 1000_1 according to one or more embodiments may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, a light path changing component 1070, and a display device housing 1200_1.

[0199] The display device housing 1200_1 can accommodate the display device 10_3, the optical component 1060, and the light path changing component 1070. The image displayed on the display device 10_3 can be magnified by the optical component 1060 and, after its light path is changed by the light path changing component 1070, provided to the user's right eye through the right eye lens 1020. As a result, the user can view an augmented reality image through their right eye, which combines the virtual image displayed on the display device 10_3 with the real image seen through the right eye lens 1020.

[0200] Figure 14 The illustration shows the display device housing 1200_1 positioned at the right end of the support frame 1030, but embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, the display device housing 1200_1 may be positioned at the left end of the support frame 1030, and in these embodiments, the image on the display device 10_3 may be provided to the user's left eye. In one or more embodiments, the display device housing 1200_1 may be positioned (e.g., simultaneously) at both the left and right ends of the support frame 1030, and in these embodiments, the user may (e.g., simultaneously) view the image displayed on the display device 10_3 through both the left and right eyes.

[0201] The display device according to one or more embodiments can be applied to one or more suitable electronic devices. The electronic device according to one or more embodiments may include the above-described display device, and may also include modules or devices with additional functions in addition to the display device.

[0202] Figure 15 This is a block diagram of an electronic device according to one or more embodiments of the present disclosure. (See also...) Figure 15 The electronic device 50 according to one or more embodiments may include a display module 11 (e.g., a display device), a processor 12, a memory 13, and a power module 14. In one or more embodiments, the electronic device 50 may also include an input module 15, an output module 16 (e.g., a non-image output module), and / or a communication module 17.

[0203] Electronic device 50 can output one or more suitable pieces of information in the form of images via display module 11. When processor 12 executes an application stored in memory 13, the image information provided by the application can be provided to the user via display module 11. Power module 14 may include a power module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power module to generate the power desired or required for the operation of electronic device 50. Input module 15 can provide input information to processor 12 and / or display module 11. Output module 16 can receive / output information other than images sent from processor 12 (such as sound, touch, and light) and provide that information to the user. Communication module 17 is responsible for sending and receiving information between electronic device 50 and external devices, and may include receiving unit and sending unit.

[0204] At least one of the components of the electronic device 50 described above may be included in the display device according to one or more of the above embodiments. In one or more embodiments, some of the modules that are functionally included in a single module may be included in the display device, and other modules may be disposed separately from the display device. For example, in one or more embodiments, the display device may include a display module 11, and the processor 12, memory 13, and power module 14 may be disposed in the form of other devices within the electronic device 50 besides the display device.

[0205] Figure 16 , Figure 17 and Figure 18 These are schematic diagrams illustrating electronic devices according to one or more suitable embodiments of the present disclosure. Figures 16 to 18 Examples of one or more suitable electronic devices that employ a display device according to one or more embodiments are shown.

[0206] Figure 16 Examples of electronic devices are shown, including a smartphone 10_1a, a tablet PC 10_1b, a laptop computer 10_1c, a TV 10_1d, and a desktop monitor 10_1e.

[0207] In addition to the display module 11, the smartphone 10_1a may also include an input module such as a touch sensor and a communication module. The smartphone 10_1a can process information received through the communication module or other input modules and display the information through the display module of the display device.

[0208] In the case of tablet PC 10_1b, laptop computer 10_1c, TV 10_1d, and desktop monitor 10_1e, they also include a display module and an input module similar to smartphone 10_1a, and in some cases may additionally include a communication module.

[0209] Figure 17 An example of an electronic device is shown, including a display module for use in wearable electronic devices. Wearable electronic devices may include smart glasses 10_2a, head-mounted displays 10_2b, smartwatches 10_2c, etc.

[0210] Both the smart glasses 10_2a and the head-mounted display 10_2b may include a display module that emits a display image and a reflector that reflects the emitted display image and provides it to the user's eyes, thereby providing the user with virtual reality or augmented reality images.

[0211] The smartwatch 10_2c may include a biometric sensor as an input device and may provide the user with biometric information identified by the biometric sensor through a display module. Figure 18 An embodiment in which an electronic device including a display module is applied to a vehicle is shown. For example, the electronic device 10_4 can be applied to the vehicle's dashboard, center console, etc., or it can be applied to a CID (Central Information Display) placed on the vehicle's dashboard and / or an interior mirror display that replaces the side mirrors.

[0212] In this disclosure, it will be understood that the terms “comprising,” “including,” or “having” indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Furthermore, the terms “comprising,” “including,” “having,” or other similar terms include or support the terms “consisting of” and “substantially consisting of” that indicate the presence of the stated features, integrals, steps, operations, elements, and / or components without or substantially without other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0213] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.”

[0214] In this disclosure, expressions such as “at least one of…”, “one of…”, and “selected from…” modify the entire column of elements after / before it, without modifying individual elements within that column. For example, “at least one of a, b, and c”, “at least one selected from a, b, and c”, “at least one selected from a to c”, etc., can refer to only a, only b, only c, (e.g., both a and b), (e.g., both a and c), (e.g., both b and c), all of a, b, and c, or variations thereof.

[0215] In the context of this application and unless otherwise defined, the term “use” and its variations may be considered synonymous with the term “utilize” and its variations, respectively.

[0216] As used herein, the terms “substantially,” “about,” “approximately,” or similar terms are used as approximate terms rather than terms of degree and are intended to explain the inherent biases of measured or calculated values ​​that would be recognized by one of ordinary skill in the art. As used herein, “about” or “approximately” includes the stated value and indicates that, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system), it falls within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0217] Any numerical range described herein is intended to include all subranges with the same numerical precision contained within the described range. For example, the range “1.0 to 10.0” is intended to include all subranges between the described minimum value 1.0 and the described maximum value 10.0 (and including both the described minimum value 1.0 and the described maximum value 10.0), such as having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained herein, and any minimum numerical limit described in this disclosure is intended to include all higher numerical limits contained herein. Therefore, the applicant reserves the right to amend the disclosure (including the claims) to expressly describe any subranges contained within the range expressly described herein.

[0218] The light-emitting elements, display modules, display devices, electronic devices / equipment, device manufacturing equipment, or any other related devices or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of the device can be formed on an integrated circuit (IC) chip or on separate IC chips. Furthermore, various components of the device can be implemented on flexible printed circuit films, tape-on-a-carrier packages (TCPs), printed circuit boards (PCBs), or formed on a substrate. Additionally, various components of the device can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which can be implemented in a computing device using standard memory devices, such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media, such as CD-ROMs, flash drives, etc. Furthermore, those skilled in the art will recognize that, without departing from the scope of the embodiments of this disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0219] Those skilled in the art will understand that, in view of the overall content of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or combined with one another, and may be technically interlocked and operated in a variety of suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently of one another or in any suitable combination with one another.

[0220] Those skilled in the art to which this disclosure pertains will understand that this disclosure may be implemented in other specific forms without altering its technical spirit or essential characteristics. Therefore, it should be understood that the foregoing exemplary embodiments are illustrative in all or in any respect, and not restrictive. It should be understood that the scope of this disclosure is defined by the appended claims and their equivalents, rather than by the detailed description above, and that all modifications and alterations derived from the claims and their equivalents fall within the scope of this disclosure.

Claims

1. A display device, characterized in that, The display device includes: Base; The first electrode is on the substrate; A pixel-defining film is disposed on the first electrode; A light-emitting stack is formed on the first electrode and the pixel defining film; The second electrode is located on the light-emitting stack; and Encapsulation layer, on the second electrode, The encapsulation layer includes a first sub-encapsulation layer on the second electrode and a second sub-encapsulation layer on the first sub-encapsulation layer. The second sub-encapsulation layer includes a transparent conductive film.

2. The display device according to claim 1, characterized in that, The second sub-encapsulation layer is formed from one of indium tin oxide, indium zinc oxide, zinc oxide, indium oxide, indium gallium oxide, and aluminum zinc oxide.

3. The display device according to claim 1, characterized in that, The second sub-encapsulation layer is formed of indium zinc oxide.

4. The display device according to claim 1, characterized in that, The display device further includes a trench that penetrates the pixel defining film and is superimposed on the second electrode.

5. The display device according to claim 1, characterized in that, The encapsulation layer also includes a third sub-encapsulation layer on top of the second sub-encapsulation layer.

6. The display device according to claim 5, characterized in that, The second sub-encapsulation layer contacts each of the first and third sub-encapsulation layers, and is located between the first and third sub-encapsulation layers.

7. The display device according to claim 5, characterized in that, The third sub-encapsulation layer includes an organic film.

8. The display device according to claim 5, characterized in that, The encapsulation layer also includes a fourth sub-encapsulation layer on top of the third sub-encapsulation layer.

9. The display device according to claim 8, characterized in that, The encapsulation layer also includes a fifth sub-encapsulation layer on top of the fourth sub-encapsulation layer.

10. The display device according to claim 9, characterized in that, The fifth sub-encapsulation layer is formed of aluminum oxide.

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