A chip package structure
By combining gallium nitride FETs and silicon-based MOSFETs in a chip package structure and connecting them with leads to achieve current dispersion, the current congestion problem of horizontal GaN FET chips is solved, improving the current dispersion and heat dissipation performance of the package structure, making it suitable for high-power applications.
Patent Information
- Application Number
- CN202521291035.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-23
- Publication Date
- 2026-08-25
- Estimated Expiration
- 2035-06-23
AI Technical Summary
Horizontal GaN FET chips suffer from current congestion, resulting in poor package structure performance, especially poor heat dissipation under high power density and high frequency operating conditions.
A combined packaging structure of gallium nitride FET chip and silicon-based MOSFET chip is adopted. Multiple leads are set to connect the electrodes to achieve current dispersion and heat dissipation. This includes setting a conductive substrate on the lead frame and independently connecting the first gate and second gate of the gallium nitride FET chip to the source of the silicon-based MOSFET chip to enhance the current dispersion effect.
A low-resistance, well-heat-dissipating chip packaging structure has been achieved, which can meet the needs of high-power applications and improve the current dissipation capability and heat dissipation performance of the packaging structure.
Smart Images
Figure CN224684687U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to a chip packaging structure. Background Technology
[0002] GaN power devices (FETs) have broad application prospects in smart home appliances, AC / DC converters, photovoltaic inverters, and electric vehicles due to the unique properties of their wide bandgap materials. However, the high power density and high-frequency operating characteristics of GaN FETs pose significant challenges to device packaging. The packaging structure, materials, and processes play a crucial role in fully realizing their excellent performance. Horizontal GaN FET chips are a commonly used GaN FET structure in device packaging; however, horizontal GaN FETs exhibit current congestion characteristics, which leads to problems such as high resistance and poor heat dissipation in the packaging structure, resulting in poor performance.
[0003] Therefore, how to solve the current congestion problem of horizontal GaN FETs in the packaging structure and improve the performance of the packaging structure has become an urgent problem to be solved. Utility Model Content
[0004] Therefore, in order to solve the above problems, this utility model provides a chip packaging structure that encapsulates a gallium nitride FET chip and a silicon-based MOSFET chip, and has the effects of low resistance, current dispersion, high heat dissipation, and can meet the requirements of high power use.
[0005] Therefore, this utility model provides a chip packaging structure, including:
[0006] The lead frame has a conductive substrate in its chip carrier area;
[0007] A gallium nitride FET chip has a first surface having a first drain, a first source, a first gate, and a second gate, and a second surface being disposed in the chip carrier region;
[0008] A silicon-based MOSFET chip has a first surface having a second source, a third source, and a third gate, a second surface having a second drain, and the second surface being disposed on a conductive substrate.
[0009] The first gate and the second gate are electrically connected to the second source and the third source, respectively, and the first source is electrically connected to the conductive substrate.
[0010] The system has a drain pin, a source pin, and a gate pin. The first drain is electrically connected to the drain pin, the second and third sources are both electrically connected to the source pin, and the third gate is electrically connected to the gate pin.
[0011] Optionally, the first drain is electrically connected to the drain pin through multiple first leads, with one end of each first lead evenly arranged and bonded to the first drain.
[0012] Optionally, the drain pin is connected to the chip carrier region, and the other end of the first lead is bonded to the chip carrier region and electrically connected to the drain pin.
[0013] Optionally, the first leader has 12 or more lines.
[0014] Optionally, the first source electrode is electrically connected to the conductive substrate through multiple second leads, with one end of each second lead evenly arranged and bonded to the first source electrode.
[0015] Optionally, the second lead has 12 or more lines.
[0016] Optionally, the source pins include a power source pin and a Kelvin source pin, and both the second source and the third source are electrically connected to the power source pin and to the Kelvin source pin.
[0017] Optionally, the second source is electrically connected to the power source pin via at least six third leads, and the third source is electrically connected to the power source pin via at least six third leads; the second source is connected to the Kelvin source pin via one third lead, and the third source is connected to the Kelvin source pin via one third lead.
[0018] Optionally, the first gate and the second gate are respectively disposed at the two ends of the first source.
[0019] Optionally, the first gate is electrically connected to the second source via a fifth lead, and the second gate is electrically connected to the third source via a fifth lead.
[0020] The technical solution provided by this utility model has the following advantages:
[0021] 1. The chip packaging structure provided by this utility model meets the usage requirements of high-power application scenarios by setting a gallium nitride FET chip and a silicon-based MOSFET chip on the lead frame. At the same time, by setting the gallium nitride FET chip to have a first gate and a second gate, and the silicon-based MOSFET chip to have a second source and a third source, and setting the first gate and the second gate to be independently connected to the second source and the third source respectively, it can achieve the effect of current dispersion. To a certain extent, it solves the current congestion problem of horizontal gallium nitride FET chip structure, so that the chip packaging structure can have the effects of low resistance, current dispersion and heat dissipation, and further improve its power level.
[0022] 2. The chip packaging structure provided by this utility model, by setting the first drain of the gallium nitride FET chip to be electrically connected to the drain pin through multiple first leads, and setting one end of the multiple first leads to be evenly arranged and bonded to the first drain, can further achieve the effect of current dispersion, thereby further enhancing the low resistance, current dispersion and heat dissipation effect of the chip packaging structure, and further improving its power level. Attached Figure Description
[0023] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0024] Figure 1 A schematic diagram of a chip packaging structure provided in this embodiment of the present invention;
[0025] Explanation of reference numerals in the attached figures:
[0026] 1-Lead frame; 11-Chip carrier area; 111-Conductive substrate;
[0027] 2-Gallium nitride FET chip;
[0028] 3-Silicon-based MOSFET chip;
[0029] 4-Drain pin;
[0030] 5 - Source pin; 51 - Power source pin; 52 - Kelvin source pin;
[0031] 6-Gate pin;
[0032] 71 - First lead; 72 - Second lead; 73 - Third lead; 74 - Fourth lead; 75 - Fifth lead; 76 - Sixth lead. Detailed Implementation
[0033] The technical solution of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.
[0034] In the description of this utility model, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0035] This embodiment provides a chip packaging structure, such as Figure 1 As shown (the structure outside the dashed line is not shown), the chip package structure includes a lead frame 1, a gallium nitride FET chip 2, a silicon-based MOSFET chip 3, a drain pin 4, a source pin 5, and a gate pin 6. The lead frame 1 contains a chip carrier region 11, and the chip carrier region 11 also contains a conductive substrate 111. The first surface of the gallium nitride FET chip 2 has a first drain D1, a first source S1, a first gate G1, and a second gate G2, and the second surface is located in the chip carrier region 11. The silicon-based MOSFET chip 3... The first surface is provided with a second source S2, a third source S3 and a third gate G3, and the second surface is provided with a second drain (not shown in the figure). The second surface of the silicon-based MOSFET chip 3 is disposed on a conductive substrate 111. The first gate G1 and the second gate G2 are electrically connected to the second source S2 and the third source S3 respectively. The first source S1 is electrically connected to the conductive substrate 111. The first drain D1 is electrically connected to the drain pin 4. The second source S2 and the third source S3 are both electrically connected to the source pin 5. The third gate G3 is electrically connected to the gate pin 6.
[0036] Specifically, the chip packaging structure in this embodiment can be set to a TO-247 package structure, and it can be set to a 3-pin TO-247 package structure.
[0037] In optional specific embodiments, in order to improve the performance of the chip packaging structure in this embodiment, such as... Figure 1 As shown, the chip package structure in this embodiment can also be configured as a 4-pin TO-247 package structure. In this case, the source pin 5 can be configured to include a power source pin 51 and a Kelvin source pin 52. The second source S2 and the third source S3 are both electrically connected to the power source pin 51 and to the Kelvin source pin 52. Specifically, the drain pin 4, the power source pin 51, the Kelvin source pin 52, and the gate pin 6 are arranged sequentially. In specific implementation, the drain pin 4 can be connected to the chip carrier region 11, while the power source pin 51, the Kelvin source pin 52, and the gate pin 6 are all spaced apart from the chip carrier region 11.
[0038] In this embodiment, the conductive substrate 111 can be set as a DPC substrate or a DBC substrate.
[0039] In this embodiment, when the drain pin 4 is connected to the chip carrier area 11 (that is, the drain pin 4 is electrically connected to the chip carrier area 11), the first drain D1 can be electrically connected to the chip carrier area 11, thereby realizing the electrical connection between the first drain D1 and the drain pin 4.
[0040] In specific implementation, the electrical connections between the first gate G1 and the second source S2, between the second gate G2 and the third source S3, between the first source S1 and the conductive substrate 111, between the drain pin 4 and the chip carrier area 11, between the second source S2 and the power source pin 51, between the third source S3 and the power source pin 51, between the second source S2 and the Kelvin source pin 52, and between the third source S3 and the Kelvin source pin 52, and between the third gate G3 and the gate pin 6 can all be achieved by wire bonding.
[0041] In practice, the aforementioned leads can be set to be 1.0mil to 1.5mil copper wires.
[0042] In specific implementation, such as Figure 1 As shown, the first gate G1 and the second gate G2 can be respectively set at the two ends of the first source S1.
[0043] In this embodiment, the chip packaging structure, by setting a gallium nitride FET chip 2 and a silicon-based MOSFET chip 3 on the lead frame 1, significantly increases both the current and voltage withstand of the packaging structure, meeting the requirements of high-power applications. Simultaneously, by setting the gallium nitride FET chip 2 to have a first gate G1 and a second gate G2, and the silicon-based MOSFET chip 3 to have a second source S2 and a third source S3, and by setting the first gate G1 and the second gate G2 to be independently connected to the second source S2 and the third source S3 respectively, the first gate G1 and the second gate G2 can effectively disperse the gate current, thus solving the current congestion problem of the horizontally structured gallium nitride FET chip 2 to a certain extent. This allows the chip packaging structure to achieve low resistance and high current, further improving its power level.
[0044] In optional embodiments, to further achieve the effect of current dispersion and thus further improve the power level of the chip package structure, such as... Figure 1 As shown, the first drain D1 of the gallium nitride FET chip 2 can be electrically connected to the drain pin 4 through multiple first leads 71, with one end of the multiple first leads 71 evenly arranged and bonded to the first drain D1.
[0045] In this embodiment, when the drain pin 4 is connected to the chip carrier area 11, the other end of the first lead 71 can be bonded to the chip carrier area 11.
[0046] In practice, the first lead 71 can be set to have 12 or more leads; Figure 1 The example shown uses 12 first leads 71. In actual implementation, the number of first leads 71 can also be 13, 15, 16, etc.
[0047] In optional specific implementations, such as Figure 1 As shown, the first source S1 can also be electrically connected to the conductive substrate 111 through multiple second leads 72, with one end of the multiple second leads 72 evenly arranged and bonded to the first source S1; the other end of the multiple second leads 72 is bonded to the conductive substrate 111.
[0048] In practice, the second lead 72 can be set to 12 lines; Figure 1 The example shown uses 12 second leads 72. In actual implementation, the number of second leads 72 can also be 13, 15, 16, etc.
[0049] In specific implementation, when the source pin 5 includes a power source pin 51 and a Kelvin source pin 52, the second source S2 can also be electrically connected to the power source pin 51 through at least 6 third leads 73, and the third source S3 can be electrically connected to the power source pin 51 through at least 6 third leads 73; the second source S2 can be connected to the Kelvin source pin 52 through at least 1 fourth lead 74, and the third source S3 can be connected to the Kelvin source pin 52 through at least 1 fourth lead 74.
[0050] In a specific implementation, the first gate G1 can be electrically connected to the second source S2 through at least one fifth lead 75, the second gate G2 can be electrically connected to the third source S3 through at least one fifth lead 75, and the third gate G3 can be electrically connected to the gate pin 6 through at least one sixth lead 76.
[0051] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the protection scope of this utility model.
Claims
1. A chip packaging structure, characterized in that, include: The lead frame has a conductive substrate in its chip carrier area; A gallium nitride FET chip has a first surface having a first drain, a first source, a first gate, and a second gate, and a second surface being disposed in the chip carrier region; A silicon-based MOSFET chip has a first surface having a second source, a third source, and a third gate, a second surface having a second drain, and the second surface being disposed on the conductive substrate. The first gate and the second gate are electrically connected to the second source and the third source, respectively, and the first source is electrically connected to the conductive substrate. The device comprises a drain pin, a source pin, and a gate pin. The first drain is electrically connected to the drain pin, the second source and the third source are both electrically connected to the source pin, and the third gate is electrically connected to the gate pin.
2. The chip packaging structure according to claim 1, characterized in that, The first drain is electrically connected to the drain pin through multiple first leads, and one end of the multiple first leads is evenly arranged and bonded to the first drain.
3. The chip packaging structure according to claim 2, characterized in that, The drain pin is connected to the chip carrier area, and the other end of the first lead is bonded to the chip carrier area and electrically connected to the drain pin.
4. The chip packaging structure according to claim 3, characterized in that, The first lead has 12 or more leads.
5. The chip packaging structure according to claim 1, characterized in that, The first source electrode is electrically connected to the conductive substrate through multiple second leads, one end of which is evenly arranged and bonded to the first source electrode.
6. The chip packaging structure according to claim 5, characterized in that, The second lead has 12 or more leads.
7. The chip packaging structure according to any one of claims 1-6, characterized in that, The source pins include a power source pin and a Kelvin source pin. The second source and the third source are both electrically connected to the power source pin and the Kelvin source pin.
8. The chip packaging structure according to claim 7, characterized in that, The second source is electrically connected to the power source pin via at least six third leads, and the third source is electrically connected to the power source pin via at least six third leads; the second source is connected to the Kelvin source pin via one fourth lead, and the third source is connected to the Kelvin source pin via one fourth lead.
9. The chip packaging structure according to claim 1, characterized in that, The first gate and the second gate are respectively disposed at both ends of the first source.
10. The chip packaging structure according to claim 9, characterized in that, The first gate is electrically connected to the second source via a fifth lead, and the second gate is electrically connected to the third source via a fifth lead.