Semiconductor structure

Abstract

Some embodiments of the present utility model provide a kind of semiconductor structure. By forming a first mold compound around a first semiconductor die, a top surface of the first mold compound is co-planar with a top dielectric surface of the first semiconductor die. At least one bonding level dielectric layer, a plurality of first bonding pads, and a plurality of dummy pads are formed over the first semiconductor die and the first mold compound, wherein each of the bonding pads is directly formed on a corresponding conductive structure within the first semiconductor die. A second semiconductor die including a plurality of second bonding pads is attached to the first semiconductor die by performing a bonding process, the bonding process bonds the second bonding pads to the first bonding pads through metal-to-metal bonding, such that a first subset of the dummy pads has an area overlap with the second semiconductor die when viewed from above.

Description

Technical Field

[0001] Some embodiments of this utility model relate to a semiconductor structure, and more particularly to a semiconductor structure including a bonding layer. Background Technology

[0002] Stress at the bonding interface between mating pair semiconductor dies can lead to cracks in gap fill materials such as silicon dioxide. These cracks tend to propagate around the bonding interface and adversely affect the reliability of mated assemblies comprising mating pairs of semiconductor dies through various mechanisms. For example, the ingress of moisture and contaminants can cause component corrosion and degrade electrical properties. Furthermore, the structural integrity of the mating assembly may be compromised, leading to mechanical failures and thus shortening the overall lifespan and / or performance of the semiconductor device within the mating assembly. The presence of such cracks can also increase thermal resistance, adversely affecting the thermal management and operational stability of the mating assembly. Utility Model Content

[0003] The purpose of this invention is to propose a semiconductor structure to solve at least one of the above-mentioned problems.

[0004] Some embodiments of this utility model provide a semiconductor structure. The semiconductor structure includes a molding compound, at least one bonding-level dielectric layer, and a second semiconductor die. The molding compound laterally surrounds a first semiconductor die and has a top surface coplanar with a top dielectric surface of the first semiconductor die. The at least one bonding-level dielectric layer has a plurality of first bonding pads and a plurality of dummy pads formed therein, and is located above the first semiconductor die and the molding compound, wherein each of the first bonding pads is electrically connected to a corresponding conductive structure within the first semiconductor die. The second semiconductor die includes a plurality of second bonding pads bonded to the first bonding pads by metal-to-metal bonding, wherein a first subset of the dummy pads overlaps with the second semiconductor die in a top view.

[0005] According to one embodiment of the present invention, the second semiconductor die includes an edge sealing ring structure that extends continuously along all sidewalls of the second semiconductor die; and at least one dummy pad in the first subset of the plurality of dummy pads overlaps with the edge sealing ring structure when viewed from above.

[0006] According to one embodiment of the present invention, the second semiconductor die includes an edge sealing ring structure that extends continuously along all sidewalls of the second semiconductor die; and at least one dummy pad in the first subset of the plurality of dummy pads is at least partially located in a region surrounded by the edge sealing ring structure when viewed from above.

[0007] According to one embodiment of the present invention, the second semiconductor die includes an edge sealing ring structure that extends continuously along all sidewalls of the second semiconductor die; and when viewed from above, at least one dummy pad in the first subset of the plurality of dummy pads is at least partially located within a frame-shaped region, the frame-shaped region being located between an outer edge of the edge sealing ring structure and the plurality of sidewalls of the second semiconductor die.

[0008] According to one embodiment of the present invention, the material composition of one of the plurality of dummy pads is different from the material composition of the plurality of first bonding pads.

[0009] According to one embodiment of the present invention, one of the plurality of dummy pads has a top surface that is vertically offset from a horizontal plane comprising a plurality of top surfaces of the plurality of first bonding pads.

[0010] According to one embodiment of the present invention, one of the plurality of dummy pads has a bottom surface that is vertically offset from a first horizontal plane comprising a plurality of bottom surfaces of the plurality of first bonding pads.

[0011] According to one embodiment of the present invention, one of the plurality of dummy pads includes a via portion that extends to the first horizontal plane and contacts an additional conductive structure within the first semiconductor die, and the additional dummy pad is spaced apart from any conductive structure located on or within the second semiconductor die.

[0012] According to one embodiment of the present invention, the at least one bonding layer dielectric layer includes a first subset and a second subset located above the first subset of the at least one bonding layer dielectric layer, a plurality of dummy pads are formed in the first subset of the bonding layer dielectric layer, and a plurality of the first bonding pads are formed to pass through the first subset of the bonding layer dielectric layer and through the second subset of the bonding layer dielectric layer.

[0013] According to one embodiment of the present invention, the thickness of any one of the plurality of dummy pads is less than or equal to the thickness of the at least one bonding layer dielectric layer. Attached Figure Description

[0014] The present invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, based on standard industry practice, the various features are not shown to scale. In fact, the dimensions of various features may be increased or decreased arbitrarily for clarity.

[0015] Figure 1This is a top view of an exemplary structure according to some aspects of the present invention, the exemplary structure including a carrier substrate having an array of first semiconductor grains thereon.

[0016] Figures 2A to 2F This is a sequential vertical cross-sectional view of a unit region of an exemplary structure during the formation of a reconstructed wafer comprising a two-dimensional array of composite grains having a first configuration and dicing it into separate composite grains, according to some aspects of the present invention.

[0017] Figure 3 This is a through-hole top view of composite grains with a first configuration according to some embodiments of the present invention.

[0018] Figures 4A to 4E This is a sequential vertical cross-sectional view of the regions of a first configuration of an exemplary structure surrounding at least one bonding-level dielectric layer during the formation of dummy pads and bonding pads, according to some embodiments of the present invention.

[0019] Figures 5A to 5E This is a sequential vertical cross-sectional view of the regions of a second configuration of an exemplary structure surrounding at least one bonding level dielectric layer during the formation of dummy pads and bonding pads, according to some embodiments of the present invention.

[0020] Figure 5F This is a vertical cross-sectional view of composite grains with a second configuration according to some embodiments of the present invention.

[0021] Figures 6A to 6E This is a sequential vertical cross-sectional view of the third configuration of an exemplary structure surrounding at least one bonding level dielectric layer during the formation of dummy pads and bonding pads, according to some embodiments of the present invention.

[0022] Figure 6F This is a vertical cross-sectional view of composite grains with a third configuration according to some embodiments of the present invention.

[0023] Figures 7A to 7E This is a sequential vertical cross-sectional view of the fourth configuration of an exemplary structure surrounding at least one bonding level dielectric layer during the formation of dummy pads and bonding pads, according to some embodiments of the present invention.

[0024] Figure 7F This is a vertical cross-sectional view of composite grains with a fourth configuration according to some embodiments of the present invention.

[0025] Figures 8A to 8F This is a sequential vertical cross-sectional view of the fifth configuration of an exemplary structure surrounding at least one bonding level dielectric layer during the formation of dummy pads and bonding pads, according to some embodiments of the present invention.

[0026] Figure 8F This is a vertical cross-sectional view of composite grains with a fifth configuration according to some embodiments of the present invention.

[0027] Figures 9A to 9D This is a sequential vertical cross-sectional view of the sixth configuration region of an exemplary structure surrounding at least one bonding level dielectric layer during the formation of dummy pads and bonding pads, according to some embodiments of the present invention.

[0028] Figure 9E This is a vertical cross-sectional view of composite grains with a sixth configuration according to some embodiments of the present invention.

[0029] Figures 10A to 10E This is a sequential vertical cross-sectional view of the seventh configuration region of an exemplary structure surrounding at least one bonding level dielectric layer during the formation of dummy pads and bonding pads, according to some embodiments of the present invention.

[0030] Figure 10F This is a vertical cross-sectional view of a composite grain with a seventh configuration according to some embodiments of the present invention.

[0031] Figures 11A to 11C This is a sequential vertical cross-sectional view of the eighth configuration region of an exemplary structure surrounding at least one bonding level dielectric layer during the formation of dummy pads and bonding pads, according to some embodiments of the present invention.

[0032] Figure 11D This is a vertical cross-sectional view of a composite grain with an eighth configuration according to some embodiments of the present invention.

[0033] Figures 12A to 12G This is a sequential vertical cross-sectional view of the ninth configuration region of an exemplary structure surrounding at least one bonding level dielectric layer during the formation of dummy pads and bonding pads, according to some embodiments of the present invention.

[0034] Figure 12H This is a vertical cross-sectional view of a composite grain with a ninth configuration according to some embodiments of the present invention.

[0035] Figures 13A to 13G This is a sequential vertical cross-sectional view of the tenth configuration of an exemplary structure surrounding at least one bonding level dielectric layer during the formation of dummy pads and bonding pads, according to some embodiments of the present invention.

[0036] Figure 13H This is a vertical cross-sectional view of a composite grain with a tenth configuration according to some embodiments of the present invention.

[0037] Figures 14A to 14FThis is a sequential vertical cross-sectional view of the eleventh configuration region of an exemplary structure surrounding at least one bonding level dielectric layer during the formation of dummy pads and bonding pads, according to some embodiments of the present invention.

[0038] Figure 14G This is a vertical cross-sectional view of composite grains with an eleventh configuration according to some embodiments of the present invention.

[0039] Figures 15A to 15F This is a sequential vertical cross-sectional view of the twelfth configuration region of an exemplary structure surrounding at least one bonding level dielectric layer during the formation of dummy pads and bonding pads, according to some embodiments of the present invention.

[0040] Figure 15G This is a vertical cross-sectional view of a composite grain with a twelfth configuration according to some embodiments of the present invention.

[0041] Figures 16A to 16E This is a sequential vertical cross-sectional view of the thirteenth configuration of an exemplary structure surrounding at least one bonding level dielectric layer during the formation of dummy pads and bonding pads, according to some embodiments of the present invention.

[0042] Figure 16F This is a vertical cross-sectional view of a composite grain with a thirteenth configuration according to some embodiments of the present invention.

[0043] Figures 17A to 17E This is a sequential vertical cross-sectional view of the fourteenth configuration region of an exemplary structure surrounding at least one bonding level dielectric layer during the formation of dummy pads and bonding pads, according to some embodiments of the present invention.

[0044] Figure 17F This is a vertical cross-sectional view of a composite grain with a fourteenth configuration according to some embodiments of the present invention.

[0045] Figures 18A to 18E This is a sequential vertical cross-sectional view of the fifteenth configuration region of an exemplary structure surrounding at least one bonding level dielectric layer during the formation of dummy pads and bonding pads, according to some embodiments of the present invention.

[0046] Figure 18F This is a vertical cross-sectional view of a composite grain with a fifteenth configuration according to some embodiments of the present invention.

[0047] Figures 19A to 19D This is a sequential vertical cross-sectional view of the sixteenth configuration region of an exemplary structure surrounding at least one bonding level dielectric layer during the formation of dummy pads and bonding pads, according to some embodiments of the present invention.

[0048] Figure 19EThis is a vertical cross-sectional view of a composite grain with a sixteenth configuration according to some embodiments of the present invention.

[0049] Figures 20A to 20E This is a sequential vertical cross-sectional view of the seventeenth configuration region of an exemplary structure surrounding at least one bonding level dielectric layer during the formation of dummy pads and bonding pads, according to some embodiments of the present invention.

[0050] Figures 21A to 21C This is a vertical cross-sectional view of various embodiments of composite grains having a seventeenth configuration according to some embodiments of the present invention.

[0051] Figures 22A to 22E This is a sequential vertical cross-sectional view of the eighteenth configuration of an exemplary structure surrounding at least one bonding level dielectric layer during the formation of dummy pads and bonding pads, according to some embodiments of the present invention.

[0052] Figure 22F This is a vertical cross-sectional view of a composite grain with an eighteenth configuration according to some embodiments of the present invention.

[0053] Figures 23A to 23E This is a sequential vertical cross-sectional view of the nineteenth configuration region of an exemplary structure surrounding at least one bonding level dielectric layer during the formation of dummy pads and bonding pads, according to some embodiments of the present invention.

[0054] Figure 23F This is a vertical cross-sectional view of a composite grain with a nineteenth configuration according to some embodiments of the present invention.

[0055] Figure 24 This is a vertical cross-sectional view of a composite grain with a twentieth configuration according to some embodiments of the present invention.

[0056] Figures 25A to 25E This is a perspective top view of composite grains with various configurations according to some embodiments of the present invention.

[0057] Figure 26 This is a first flowchart illustrating the steps for forming a semiconductor structure according to some embodiments of the present invention.

[0058] Figure 27 This is a second flowchart illustrating the steps for forming a semiconductor structure according to some embodiments of the present invention.

[0059] The attached figures are labeled as follows:

[0060] 23C: concave part

[0061] 100: First semiconductor die

[0062] 109: First Semiconductor Substrate

[0063] 112: First shallow trench isolation structure

[0064] 113: Dielectric sheath

[0065] 114: Substrate through-hole structure

[0066] 117: First back-side dielectric layer

[0067] 120: First Semiconductor Device

[0068] 160: First dielectric material layer

[0069] 170: First grain edge sealing ring structure

[0070] 180: First metal interconnect structure

[0071] 188: Package bonding structure

[0072] 190: First front bonding layer dielectric layer

[0073] 200: First mold sealing grain unit

[0074] 220: At least one bonding layer dielectric layer

[0075] 221: Lower bonding layer dielectric layer

[0076] 222: Upper bonding layer dielectric layer

[0077] 227: Joint pad cavity

[0078] 228: First joint pad

[0079] 235: Guide hole cavity

[0080] 237: Empty cavity with dummy pad

[0081] 238: Virtual Pad

[0082] 260: First molding compound matrix / molding compound

[0083] 300: Second semiconductor die

[0084] 309: Second semiconductor substrate

[0085] 312: Second shallow trench isolation structure

[0086] 320: Second semiconductor device

[0087] 360: Second dielectric material layer

[0088] 370: Second grain edge sealing ring structure / edge sealing ring structure

[0089] 380: Second metal interconnect structure

[0090] 388: Second bonding pad

[0091] 390: Second front bonding layer dielectric layer

[0092] 400: Second mold sealing grain unit

[0093] 460: Second molding compound matrix

[0094] 600: Carrier substrate

[0095] 601: Adhesive layer

[0096] 900: Composite grains

[0097] 2610: Steps

[0098] 2620: Steps

[0099] 2630: Steps

[0100] 2710: Steps

[0101] 2720: Steps

[0102] 2730: Steps

[0103] 2740: Steps

[0104] 2750: Steps

[0105] 2760: Steps

[0106] d1: First depth

[0107] d2: Second depth

[0108] hd1: First horizontal direction

[0109] hd2: Second horizontal direction

[0110] s1: Spacing

[0111] s2: Spacing

[0112] t: thickness

[0113] t1: First thickness

[0114] t1': First thickness

[0115] t2: Second thickness

[0116] t2': Second thickness

[0117] w1: First horizontal dimension

[0118] w2: Second horizontal dimension Detailed Implementation

[0119] The following disclosure provides many different embodiments or examples to implement different features of this utility model. Specific examples of components and arrangements are described below to simplify the utility model. Of course, these are merely examples and are not intended to be limiting. For example, if the specification describes a first feature formed above or on a second feature, it indicates that embodiments may include situations where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, in various examples, the utility model may use repeated symbols and / or letters. Such repetition is for simplification and clarity and does not imply any association between the various embodiments and / or configurations discussed.

[0120] Furthermore, the spatially related terms used, such as "below," "below," "lower," "above," "higher," etc., are for the convenience of describing the relationship between one element or feature and another element(s) in the accompanying drawings. In addition to the orientations shown in the drawings, these spatially related terms are intended to cover different orientations of the device in use or operation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related terms used herein may be interpreted similarly. Unless otherwise stated, elements with the same symbol are assumed to have the same material composition and thickness within the same thickness range.

[0121] Some embodiments of this invention relate to methods for bonding semiconductor dies using dummy pads and bonding pads. Dummy pads and bonding pads can be used to provide metal-to-metal bonding or hybrid bonding between a pair of semiconductor dies that are bonded together, while reducing crack defects and improving bonding yield. Dummy pads can be formed above a first semiconductor die and below and around the peripheral region of a second semiconductor die to which it will subsequently be attached. Dummy pads alleviate stress-related problems and prevent crack formation in the gap filler material applied around the second semiconductor die. Various aspects of this invention will now be described with reference to the accompanying drawings.

[0122] Please refer to Figure 1 The diagram shows a top view of an exemplary structure. This exemplary structure includes a carrier substrate 600 having an array of first semiconductor dies 100 thereon. The carrier substrate 600 can be any type of carrier substrate adapted to support the array of semiconductor dies thereon. For example, the carrier substrate 600 can be a glass substrate, a semiconductor substrate, or a conductive substrate. Figure 1As shown, the carrier substrate 600 may have a circular shape. In other embodiments (not shown), the carrier substrate may have a rectangular shape, or any other shape suitable for carrying an array of semiconductor dies thereon. The first semiconductor die 100 may be any type of semiconductor die known in the art. For example, the first semiconductor die 100 may include a logic die, which includes at least one central processing unit (CPU), at least one graphics processing unit (GPU), at least one neural processing unit (NPU), at least one memory array, and / or any other type of semiconductor device known in the art. An adhesive layer may be used to attach the array of the first semiconductor dies 100 to the carrier substrate 600. The array of the first semiconductor dies 100 may be arranged in a periodic two-dimensional array. In this specification, the region forming the smallest repeating unit within the periodic two-dimensional array is referred to as the unit area.

[0123] Figures 2A to 2F This is a sequential vertical cross-sectional view of a unit region of an exemplary structure during the formation of a reconstructed wafer comprising a two-dimensional array of composite grains 900 having a first configuration and dicing it into separate composite grains 900, according to some aspects of the present invention.

[0124] Please refer to Figure 2A It shows Figure 1 The figure shows a vertical cross-sectional view of a unit region of an exemplary structure. In the illustrated example, the first semiconductor die 100 can be attached to the carrier substrate 600 by an adhesive layer 601, which may be a thermally-decomposable adhesive layer, such as a polyimide layer, or an ultraviolet-decomposable adhesive layer, such as an ultraviolet-sensitive tape.

[0125] The first semiconductor die 100 may include a first semiconductor substrate 109, a first semiconductor device 120 located on the first semiconductor substrate 109, a first metal interconnect structure 180 formed within a first dielectric material layer 160, a first front-side bonding level dielectric layer 190, and a package bonding structure 188 formed within the first front-side bonding level dielectric layer 190. The package bonding structure 188 serves as the bonding structure for a subsequently formed composite die, and may be configured for solder-mediated bonding (e.g., wafer connection bonding, i.e., microbump bonding or controlled collapse chip connection, C4 bonding, i.e., C4 bonding) or may be configured for metal-to-metal bonding. A first die edge sealing ring structure 170 may extend vertically through the first dielectric material layer 160 and the first front-side bonding level dielectric layer 190, and may laterally surround the entire first metal interconnect structure 180.

[0126] The first semiconductor device 120 may include any semiconductor device known in the art, such as a field-effect transistor and a passive device. A first shallow trench isolation structure 112 may be disposed within the first semiconductor substrate 109 such that an adjacent pair of first semiconductor devices 120 may be electrically isolated from each other. The first semiconductor die 100 may include a through-substrate via (TSV) structure 114 extending vertically through the first semiconductor substrate 109 and optionally through a subset of the first dielectric layer 160. The through-substrate via structure 114 may be electrically isolated from the first semiconductor substrate 109 by a dielectric liner 113. A first back-side dielectric layer 117 may be disposed on the back side of the first semiconductor substrate 109. In some embodiments, the through-substrate via structures 114 may be arranged in a periodic pattern having the same period as the pattern of the first bonding pads subsequently formed over the first back-side dielectric layer 117. Each sidewall of the first semiconductor die 100 may be physically exposed.

[0127] Please refer to Figure 2BA first molding compound can be applied to the gap between adjacent pairs of first semiconductor grains 100. The first molding compound may include an epoxy-containing material that can be hardened (i.e., cured) to provide a dielectric portion with sufficient rigidity and mechanical strength. The first molding compound may include epoxy resin, a hardener, silica (as a filler), and other additives. The first molding compound may be provided in liquid or solid form depending on viscosity and flowability. Liquid first molding compounds offer better operability, good flowability, fewer voids, better filling, and fewer flow marks. Solid molding compounds offer less curing shrinkage, better stand-off, and less grain drift. High filler content (e.g., 85% by weight) in the molding compound can shorten molding time, reduce molding shrinkage, and reduce molding warpage. Uniform filler size distribution in the molding compound can reduce flow marks and increase flowability. In embodiments where the adhesive layer 601 includes a thermally-debonding material, the curing temperature of the molding compound may be lower than the release (debonding) temperature of the adhesive layer 601. For example, the curing temperature of the first molding compound may be in the range of 125°C to 150°C.

[0128] A first molding compound can be cured at a curing temperature to form a first molding compound matrix 260 that laterally surrounds a two-dimensional array of first molding compound grains 100. The first molding compound matrix 260 includes a plurality of first molding compound grain frames interconnected with each other. Each first molding compound grain frame is part of the first molding compound matrix 260 and is located within a region of repeating units in a two-dimensional periodic array of a structure covering the carrier substrate 600. Therefore, each first molding compound grain frame laterally surrounds and embeds the first semiconductor grain 100.

[0129] A planarization process can be used to remove a portion of the first molding compound matrix 260 covering the horizontal surface of the top surface of the first semiconductor die 100. For example, a chemical mechanical planarization (CMP) process can be used to remove this portion. The remaining portion of the first molding compound matrix 260, combined with the array of the first semiconductor dies 100, forms a reconstructed wafer. Each portion of the first molding compound matrix 260 located within a unit region constitutes a first molding compound die framework. Typically, the first molding compound matrix 260 can be formed around the first semiconductor die 100 such that the top surface of the first molding compound matrix 260 is coplanar with the top dielectric surface of the first semiconductor die 100.

[0130] Please refer to Figure 2C At least one combination of a bonding layer 220, a first bonding pad 228, and a dummy pad 238 may be formed over the first semiconductor die 100 and the first molding compound matrix 260. Each first bonding pad 228 may be formed directly on a corresponding conductive structure (e.g., a substrate via structure 114) within the first semiconductor die 100. In this specification, each portion of the exemplary structure within a unit area is referred to as a first molding die unit 200, which includes the first semiconductor die 100 and a first die group of a portion of the first molding compound matrix 260, and a combination of at least one bonding layer 220, a first bonding pad 228, and a dummy pad 238 located within the unit area.

[0131] Typically, each dummy pad 238 may have the same or different material composition as the first bonding pad 228. In some embodiments, all dummy pads 238 may have the same material composition as the first bonding pad 228. In other embodiments, all dummy pads 238 may have a different material composition than the first bonding pad 228. In still other embodiments, a first subset of the dummy pads 238 may have the same material composition as the first bonding pad 228, and a second subset of the dummy pads 238 may have a different material composition than the first bonding pad 228. Figure 2C In the configuration shown, each dummy pad 238 has a different material composition than the first bonding pad 228.

[0132] At least one bonding-level dielectric layer 220 may comprise a single bonding-level dielectric layer 220, or at least one bonding-level dielectric layer 220 may comprise multiple bonding-level dielectric layers 220. Each dummy pad 238 may comprise a corresponding thickness t, which is not greater than or may be less than the thickness of at least one bonding-level dielectric layer 220. Each dummy pad 238 may have the same thickness t. Alternatively, the dummy pads 238 may comprise a first subset of dummy pads 238 having a first thickness and a second subset of dummy pads 238 having a second thickness, etc., wherein the second thickness is different from the first thickness.

[0133] Typically, each dummy pad 238 may have a top surface vertically offset from the horizontal plane including the top surface of the first bonding pad 228, or each dummy pad 238 may have a top surface formed within the horizontal plane including the top surface of the first bonding pad 228. In some embodiments, a first subset of the dummy pads 238 may have a top surface vertically offset from the horizontal plane including the top surface of the first bonding pad 228, and a second subset of the dummy pads 238 may have a top surface formed within the horizontal plane including the top surface of the first bonding pad 228. Figure 2CIn the illustrated configuration, each dummy pad 238 has a top surface that is vertically offset from the horizontal plane including the top surface of the first mating pad 228. In this specification, in embodiments where the dummy pad 238 has a top surface that is vertically offset from the horizontal plane including the top surface of the first mating pad 228, the vertical distance between the top surface of the dummy pad 238 and the horizontal plane including the top surface of the first mating pad 228 is referred to as the first spacing s1 or the upper spacing.

[0134] Typically, each dummy pad 238 may have a bottom surface vertically offset from the horizontal plane including the bottom surface of the first bonding pad 228, or each dummy pad 238 may have a bottom surface formed within the horizontal plane including the bottom surface of the first bonding pad 228. In some embodiments, a first subset of the dummy pads 238 may have a bottom surface vertically offset from the horizontal plane including the bottom surface of the first bonding pad 228, and a second subset of the dummy pads 238 may have a bottom surface formed within the horizontal plane including the bottom surface of the first bonding pad 228. Figure 2C In the illustrated configuration, each dummy pad 238 has a bottom surface that is vertically offset from the horizontal plane including the bottom surface of the first bonding pad 228. In this specification, in embodiments where the dummy pad 238 has a bottom surface that is vertically offset from the horizontal plane including the bottom surface of the first bonding pad 228, the vertical distance between the bottom surface of the dummy pad 238 and the horizontal plane including the bottom surface of the first bonding pad 228 is referred to as the second spacing s2 or the lower spacing.

[0135] Please refer to Figure 2D A second semiconductor die 300 having a second bonding pad 388 can be bonded to a corresponding first semiconductor die 100 via metal-to-metal bonding. Each second semiconductor die 300 can be bonded to a corresponding first semiconductor die 100 by performing a bonding process, wherein the bonding process is to bond the second bonding pad 388 of the second semiconductor die 300 to the first bonding pad 228 in a corresponding unit region containing the first semiconductor die 100 via metal-to-metal bonding, such that a first subset of the dummy pads 238 overlaps with the second semiconductor die 300 in top view.

[0136] Each second semiconductor die 300 may include a second semiconductor substrate 309, a second semiconductor device 320 located on the second semiconductor substrate 309, a second metal interconnect structure 380 formed within a second dielectric material layer 360, a second front-side bonding level dielectric layer 390, and a second bonding pad 388 formed within the second front-side bonding level dielectric layer 390. The second bonding pad 388 may be configured for metal-to-metal bonding, for example, copper-to-copper bonding. In this specification, metal-to-metal bonding refers to the direct bonding of metal surfaces without the use of intermediate adhesives or solders. Metal-to-metal bonding can be provided between two metal surfaces in direct contact by thermocompression bonding and / or diffusion bonding through an annealing process performed at high temperature.

[0137] The second die edge sealing ring structure 370 (also referred to as edge sealing ring structure 370) may extend vertically through the second dielectric material layer 360 and the second front bonding level dielectric layer 390, and may laterally surround the entirety of the second metal interconnect structure 380. The second semiconductor device 320 may include any semiconductor device known in the art, such as a field-effect transistor and a passive device. A second shallow trench isolation structure 312 may be disposed within the second semiconductor substrate 309 such that an adjacent pair of second semiconductor devices 320 are electrically isolated from each other. Each sidewall of the second semiconductor die 300 may be physically exposed.

[0138] The second bonding pad 388 can be bonded to the first bonding pad 228 via a metal-to-metal bonding process, such as copper-to-copper bonding. Furthermore, the horizontal bottom surface of the second front-side bonding level dielectric layer 390 can be bonded to the top surface of at least one bonding level dielectric layer 220 via a dielectric-to-dielectric bonding process, such as silicon oxide-to-silicon oxide bonding. In the illustrated example, the second bonding pad 388 of the second semiconductor die 300 can be aligned with the first bonding pad 228 of the first molding die unit 200, and a thermoforming bonding process can be performed to bond the paired first bonding pad 228 and second bonding pad 388.

[0139] According to some aspects of this invention, in a top view (e.g., a top view along the vertical direction), a first subset of the dummy pads 238 has regional overlap with the second semiconductor die 300. In a top view, a second subset of the dummy pads 238 does not have regional overlap with the second semiconductor die 300.

[0140] In some embodiments, the second semiconductor die 300 includes an edge sealing ring structure 370 that extends continuously along all sidewalls of the second semiconductor die 300. In some embodiments, at least one dummy pad 238 of a first subset of dummy pads 238 overlaps with the edge sealing ring structure 370 when viewed from above. Additionally or alternatively, at least one dummy pad 238 of the first subset of dummy pads 238 is at least partially located within the region enclosed by the edge sealing ring structure 370 when viewed from above. Additionally or alternatively, at least one dummy pad 238 of the first subset of dummy pads 238 is at least partially located within a frame-shaped region located between the outer edge of the edge sealing ring structure 370 and the sidewalls of the second semiconductor die 300.

[0141] Please refer to Figure 2E A second molding compound matrix 460 can be formed around the second semiconductor die 300. Specifically, the second molding compound can be applied to the gap between an adjacent pair of second semiconductor dies 300. The second molding compound can include any material that can serve as the first molding compound. Typically, the second molding compound and the first molding compound can have the same material composition or can have different material compositions. The second molding compound can be cured at a curing temperature to form a second molding compound matrix 460 that laterally surrounds a two-dimensional array of the second semiconductor dies 300. The second molding compound matrix 460 includes a plurality of second molding compound die frames interconnected with each other. Each second molding compound die frame is part of the second molding compound matrix 460 and is located within a region of repeating units in a two-dimensional periodic array of structures covering the carrier substrate 600. Thus, each second molding compound die frame laterally surrounds and embeds a corresponding second semiconductor die 300.

[0142] A planarization process can be used to remove a portion of the second molding compound matrix 460 covering the horizontal plane of the top surface of the second semiconductor die 300. For example, a chemical mechanical planarization process can be used to remove the portion of the second molding compound matrix 460 covering the horizontal plane. The remaining portion of the second molding compound matrix 460, combined with the array of the second semiconductor dies 300, forms a second molding die unit 400. Each second molding die unit 400 includes a second semiconductor die 300 and a portion of the second molding compound matrix 460 located within a unit region. Each portion of the second molding compound matrix 460 located within the unit region constitutes a second molding compound die framework. Typically, the second molding compound matrix 460 can be formed around the second semiconductor die 300 such that the top surface of the second molding compound matrix 460 is coplanar with the top surface of the second semiconductor die 300. The first molding die unit 200 and each of the second molding die units 400 are vertically stacked to form a composite die 900. A two-dimensional array of composite dies 900 can be formed above the carrier substrate 600.

[0143] Please refer to Figure 2F The carrier substrate 600 can be separated from the reconstructed wafer including the two-dimensional array of composite grains 900 by decomposing the adhesive layer 601. The adhesive layer 601 can be decomposed using a thermal annealing process or an ultraviolet irradiation process. A suitable cleaning process can be performed to clean the exposed surfaces of the first front bonding level dielectric layer 190 and the encapsulation bonding structure 188.

[0144] The wafer can be cut and reconstructed along the dicing channel to divide the composite die 900. Each composite die 900 includes a first semiconductor die 100; a first molding compound matrix 260 (which is a first molding compound die framework); a combination of at least one bonding layer dielectric layer 220, a first bonding pad 228, and a dummy pad 238; a second semiconductor die 300 (including a second bonding pad 388 bonded to the first bonding pad 228 by metal-to-metal bonding); and a second molding compound matrix 460 (which is a second molding compound die framework).

[0145] Please refer to Figure 3 The diagram shows a through-hole top view of a composite die 900 with a first configuration. In top view, the second semiconductor die 300 may have a region entirely located within the region of the first semiconductor die 100. As described above, the second semiconductor die 300 may include an edge sealing ring structure 370 extending continuously along all sidewalls of the second semiconductor die 300. In some embodiments, in top view, at least one dummy pad 238 in a first subset of dummy pads 238 overlaps with the edge sealing ring structure 370. Additionally or alternatively, in top view, at least one dummy pad 238 in the first subset of dummy pads 238 is at least partially located within the region surrounded by the edge sealing ring structure 370. In other words, in top view, at least one dummy pad 238 in the first subset of dummy pads 238 may be at least partially located within the region defined by the inner sidewall of the edge sealing ring structure 370. Additionally or alternatively, at least one dummy pad 238 in the first subset of dummy pads 238 is at least partially located within a frame-shaped region between the outer edge of the edge sealing ring structure 370 and the sidewall of the second semiconductor die 300. The outermost sidewall of the edge sealing ring structure 370 defines the outer edge of the edge sealing ring structure 370.

[0146] In some embodiments, each of the first semiconductor die 100 and the second semiconductor die 300 may have a corresponding pair of first sidewalls extending laterally along a first horizontal direction hd1 and a corresponding pair of second sidewalls extending laterally along a second horizontal direction hd2 (perpendicular to the first horizontal direction hd1). In some embodiments, the dummy pad 238 may include at least one row of dummy pads 238 arranged along the second horizontal direction hd2 and / or at least one column of dummy pads 238 arranged along the first horizontal direction hd1. The shapes of the dummy pads 238 may be the same or different from each other. For example, each dummy pad 238 may have a corresponding shape of a circle, rectangle, rounded rectangle, or any other two-dimensional curved shape with a closed perimeter. In some embodiments, one or more of the dummy pads 238 may have a corresponding opening therethrough.

[0147] The first lateral dimension w1 (e.g., diameter, side length, or any other maximum dimension along the lateral direction) of each dummy pad 238 along the first horizontal direction hd1 can range from 0.1 micrometers to 10 millimeters, for example, 0.3 micrometers to 30 micrometers; however, smaller and larger lateral dimensions may also be used. The second lateral dimension w2 of each dummy pad 238 along the second horizontal direction hd2 can range from 0.1 micrometers to 10 millimeters, for example, 0.3 micrometers to 30 micrometers; however, smaller and larger lateral dimensions may also be used. The first lateral spacing s1 between adjacent pairs of dummy pads 238 along the first horizontal direction hd1 can range from 0.1 micrometers to 10 millimeters, for example, 0.3 micrometers to 30 micrometers; however, smaller and larger lateral spacing may also be used. The second lateral spacing s2 between adjacent pairs of dummy pads 238 along the second horizontal direction hd2 can range from 0.1 micrometers to 10 millimeters, for example, 0.6 micrometers to 60 micrometers; however, smaller and larger lateral spacing may also be used. The thickness of each dummy pad 238 can range from 0.1 micrometers to 100 micrometers, for example, from 0.3 micrometers to 10 micrometers, but smaller and larger thicknesses can also be used.

[0148] The total number of dummy pads 238 can be determined based on the stress loading generated during the bonding of the second semiconductor die 300 to the first molding die unit 200. Similarly, the loading factor (i.e., the ratio of the total area occupied by the dummy pads 238 to the total area of ​​the top surface of the single first molding die unit 200) can be optimized based on the stress loading generated during the bonding of the second semiconductor die 300 to the first molding die unit 200. Typically, the loading factor can be in the range of 0.0001 to 0.1, however, smaller and larger loading factors can also be used.

[0149] Figures 4A to 4EThis is a sequential vertical cross-sectional view of the regions of a first configuration of an exemplary structure surrounding at least one bonding level dielectric layer 220 during the formation of the dummy pad 238 and the first bonding pad 228, according to some embodiments of the present invention. Figures 4A to 4E An exemplary sequence of process steps is shown, which can be used to form in Figure 2C The combination of at least one bonding layer dielectric layer 220, first bonding pad 228, and dummy pad 238 in the process steps.

[0150] Please refer to Figure 4A The lower bonding layer dielectric layer 221 can be deposited on a reconstructed wafer comprising a two-dimensional array including a first semiconductor die 100 and a first molding compound matrix 260 (i.e., as shown in the image). Figure 2B The lower bonding layer 221 may comprise any interlayer dielectric (ILD) material known in the art, such as undoped silicate glass, doped silicate glass, etc. The lower bonding layer 221 is a first subset of at least one bonding layer 220 as described above. The thickness of the lower bonding layer 221 may range from 0.2 micrometers to 200 micrometers, for example, from 3 micrometers to 100 micrometers; however, smaller and larger thicknesses may also be used.

[0151] A photoresist layer (not shown) can be applied over the underlying bonding layer dielectric layer 221, and the photoresist layer can be photolithographically patterned to form openings in the region where the dummy pad 238 will subsequently be formed. An anisotropic etching process can be performed to transfer the pattern of the openings in the photoresist layer to the upper portion of the underlying bonding layer dielectric layer 221. The dummy pad cavity 237 can be formed to have a first depth, which may be the same as the thickness t of the dummy pad 238 to be formed subsequently. The photoresist layer can then be removed, for example, by an ashing process.

[0152] Please refer to Figure 4BA first filler material having a first material composition is deposited into the dummy pad cavity 237 by performing a first deposition process. The first filler material has a different material composition from the underlying bonding layer dielectric layer 221. The first filler material may be different from or the same as the second filler material subsequently used to form the first bonding pad 228. The first filler material may include any combination of the following: at least one metal (e.g., copper (Cu), aluminum (Al), etc.), at least one metal compound material (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), at least one organic filler material (e.g., polyimide, resin, molding compound material, etc.), dielectric filler material (e.g., silicon nitride (SiN), silicon carbide (SiC)), dielectric metal oxide, etc.). In some embodiments, the first filler material may include at least one metal and / or may be substantially composed of at least one metal. In some embodiments, the first filler material may include at least one metal compound material and / or may be substantially composed of at least one metal compound material. In some embodiments, the first filler material may include at least one organic filler material and / or may be substantially composed of at least one organic filler material. In some embodiments, the first filler material may include a dielectric filler material and / or may consist substantially of a dielectric filler material.

[0153] A first planarization process, such as a chemical mechanical polishing process, can be performed to remove the first filler material from a horizontal plane above the top surface of the underlying bonding layer dielectric layer 221. Each residual portion of the first filler material filling the respective dummy pad cavities 237 constitutes a dummy pad 238. Each dummy pad 238 has a thickness t, which can range from 0.1 micrometers to 100 micrometers, although smaller and larger thicknesses may also be used. The vertical distance between the bottom surface of the dummy pad 238 and the horizontal plane including the bottom surface of the underlying bonding layer dielectric layer 221 is a second distance s2 or a lower distance. The second distance s2 can range from 0.1 micrometers to 100 micrometers, for example, from 0.3 micrometers to 10 micrometers, although smaller and larger thicknesses may also be used.

[0154] Please refer to Figure 4CAn upper bonding-level dielectric layer 222 can be deposited over a lower bonding-level dielectric layer 221. The upper bonding-level dielectric layer 222 can include any interlayer dielectric material known in the art, such as undoped silicate glass, doped silicate glass, etc. The upper bonding-level dielectric layer 222 is a second subset of at least one bonding-level dielectric layer 220 as described above. Therefore, a second subset of at least one bonding-level dielectric layer 220 can be deposited over a first subset of at least one bonding-level dielectric layer 220. The thickness of the upper bonding-level dielectric layer 222 can range from 0.1 micrometers to 100 micrometers, for example, from 1 micrometer to 50 micrometers; however, smaller and larger thicknesses are also possible. The thickness of the upper bonding-level dielectric layer 222 can be the same as the first spacing s1 or the upper spacing. The combination of the lower bonding-level dielectric layer 221 and the upper bonding-level dielectric layer 222 constitutes at least one bonding-level dielectric layer 220 as described above.

[0155] Please refer to Figure 4D A photoresist layer (not shown) can be applied over the upper bonding level dielectric layer 222, and the photoresist layer can be photolithographically patterned to form openings in the region where the first bonding pad 228 will subsequently be formed. An anisotropic etching process can be performed to transfer the pattern of the openings in the photoresist layer through the entirety of at least one bonding level dielectric layer 220, i.e., through each layer of at least one bonding level dielectric layer 220. A bonding pad cavity 227 having a second depth can be formed through at least one bonding level dielectric layer 220. The second depth can be equivalent to the total thickness of at least one bonding level dielectric layer 220. Therefore, the second depth is greater than the first depth of the dummy pad cavity 237. Subsequently, the photoresist layer can be removed, for example, by an ashing process. In the illustrated example, the bonding pad cavity 227 is formed after performing a first planarization process.

[0156] Please refer to Figure 4E A second filler material having a second material composition is deposited into the bonding pad cavity 227 by performing a second deposition process. The second filler material differs from the first filler material and has a metallic composition that facilitates metal-to-metal bonding. For example, the second filler material may comprise a combination of a thin metallic barrier liner material (e.g., TiN, TaN, WN, and / or MoN) and a copper filler material that is substantially composed of copper.

[0157] A second planarization process, such as a chemical mechanical polishing process, can be performed to remove excess portions of the second filler material from a horizontal plane above the top surface of the at least one bonding level dielectric layer 220. Each residual portion of the second filler material filling the respective bonding pad cavities 227 constitutes a first bonding pad 228. Each first bonding pad 228 has a thickness equivalent to the total thickness of the at least one bonding level dielectric layer 220. Typically, each first bonding pad 228 can be formed directly on a corresponding conductive structure (e.g., substrate via structure 114) within the first semiconductor die 100, as per [reference to...]. Figure 2C As described.

[0158] Typically, dummy pads 238 are formed by depositing and patterning a first filler material within a first subset of at least one bonding-level dielectric layer 220; first bonding pads 228 are formed by depositing and patterning a second filler material within at least one bonding-level dielectric layer 220, such that each first bonding pad 228 extends vertically from the bottom surface of at least one bonding-level dielectric layer 220 to the top surface of at least one bonding-level dielectric layer 220. The first subset of at least one bonding-level dielectric layer 220 may be less than or equal to the entirety of at least one bonding-level dielectric layer. The second filler material may be the same as or different from the first filler material. The dummy pads 238 are formed by depositing the first filler material using a first deposition process and planarizing the first filler material using a first planarization process; the first bonding pads 228 are formed by depositing the second filler material using a second deposition process and planarizing the second filler material using a second planarization process. Typically, the second deposition process may be the same as or different from the first deposition process. Typically, the second planarization process may be the same as or different from the first planarization process.

[0159] In some embodiments, a second subset of at least one bonding-level dielectric layer 220 may be deposited over the dummy pad 238 (e.g., as shown in the figure). Figure 4C (As shown); the mating pad cavity 227 may be formed to pass through the second subset and the first subset. A first mating pad 228 is formed in the mating pad cavity 227.

[0160] It can be adjusted in various ways regarding Figures 4A to 4E The described sequence of process steps provides alternative configurations for the dummy pad 238 and the first bonding pad 228. Therefore, a number of alternative configurations can be used to form a combination of at least one bonding-level dielectric layer 220, the first bonding pad 228, and the dummy pad 238 over the first semiconductor die 100 and the first molding compound matrix 260.

[0161] Figures 5A to 5EThis is a sequential vertical cross-sectional view of the second configuration of an exemplary structure surrounding at least one bonding level dielectric layer 220 during the formation of the dummy pad 238 and the first bonding pad 228, according to some embodiments of the present invention. Figure 5F This is a vertical cross-sectional view of a composite grain 900 having a second configuration according to some embodiments of the present invention. (See also: [link to relevant information]) Figures 4A to 4E The described process sequence is derived by using the same filler material for both the first and second filler materials. Figures 5A to 5E The process sequence is shown. In such an embodiment, in Figures 5A to 5E The first filler material used during the process sequence shown can be related to... Figure 4E The second filler material described is the same. Therefore, Figure 5E as well as Figure 5F The dummy pad 238 and the first bonding pad 228 may comprise the same metal or a group of the same metal materials (e.g., a combination of thin metal barrier pad materials (e.g., TiN, TaN, WN and / or MoN) and copper-filled materials that are essentially composed of copper).

[0162] Figures 6A to 6E This is a sequential vertical cross-sectional view of a third configuration of an exemplary structure surrounding at least one bonding level dielectric layer 220 during the formation of the dummy pad 238 and the first bonding pad 228, according to some embodiments of the present invention. Figure 6F This is a vertical cross-sectional view of a composite grain 900 with a third configuration according to some embodiments of the present invention. (See also: [link to relevant information]) Figures 4A to 4E The described process sequence is derived by increasing the depth of the dummy pad cavity 237 so that the depth of the dummy pad cavity 237 is equal to the thickness of the underlying bonding layer dielectric layer 221. Figures 6A to 6E The process sequence is shown. In other words, the second pitch s2 or the lower pitch is zero. Therefore, the thickness of each dummy pad 238 can be equal to the thickness of the lower bonding layer dielectric layer 221, and each dummy pad 238 can contact the horizontal surface of the first semiconductor die 100 (e.g., the surface of the first back-side dielectric layer 117).

[0163] Figures 7A to 7E This is a sequential vertical cross-sectional view of the fourth configuration of an exemplary structure surrounding at least one bonding level dielectric layer 220 during the formation of the dummy pad 238 and the first bonding pad 228, according to some embodiments of the present invention. Figure 7F This is a vertical cross-sectional view of a composite grain 900 having a fourth configuration according to some embodiments of the present invention. (See also: [link to relevant information]) Figures 6A to 6E The described process sequence is derived by using the same filler material for both the first and second filler materials. Figures 7A to 7EThe process sequence is shown. In such an embodiment, in Figures 6A to 6E The first filler material used during the process sequence shown can be related to... Figure 4E The second filler material described is the same. Therefore, Figure 7E as well as Figure 7F The dummy pad 238 and the first bonding pad 228 may comprise the same metal or a group of the same metal materials (e.g., a combination of thin metal barrier pad materials (e.g., TiN, TaN, WN and / or MoN) and copper-filled materials that are essentially composed of copper).

[0164] Figures 8A to 8F This is a sequential vertical cross-sectional view of the fifth configuration of an exemplary structure surrounding at least one bonding level dielectric layer 220 during the formation of the dummy pad 238 and the first bonding pad 228, according to some embodiments of the present invention. Figure 8F This is a vertical cross-sectional view of a composite grain 900 having a fifth configuration according to some embodiments of the present invention. (See also: [link to relevant information]) Figures 5A to 5E The described process sequence is derived by depositing at least one bonding-level dielectric layer 220 integrally prior to forming the dummy pad cavity 237. Figures 8A to 8F The process sequence is shown. In such an embodiment, a single bonding level dielectric layer can serve as at least one bonding level dielectric layer 220. Details regarding... Figure 4C The described process steps, and the anisotropic etching process for forming the bonding pad cavity 227 can be adjusted as needed to accommodate variations in the material composition and / or thickness of at least one bonding level dielectric layer 220. In such a configuration, the first vertical pitch s1 or the upper pitch is zero. The top surface of the dummy pad 238 can be formed in the same horizontal plane as the top surface of the first bonding pad 228. The first filling material of the dummy pad 238 can be different from the second filling material (which is a metallic filling material) of the first bonding pad 228.

[0165] Figures 9A to 9D This is a sequential vertical cross-sectional view of a sixth configuration of an exemplary structure surrounding at least one bonding level dielectric layer 220 during the formation of the dummy pad 238 and the first bonding pad 228, according to some embodiments of the present invention. Figure 9E This is a vertical cross-sectional view of a composite grain 900 with a sixth configuration according to some embodiments of the present invention. (See also: [link to relevant information]) Figures 8A to 8F The described process sequence is derived by using the same filler material for both the first and second filler materials. Figures 9A to 9DThe process sequence is shown. In such an embodiment, dummy pad cavities 237 and bonding pad cavities 227 can be formed in at least one bonding-level dielectric layer 220 in any sequence. The first filler material is the same as the second filler material, and therefore the first filler material and the second filler material are deposited in the same deposition step. The planarization of the first filler material and the second filler material can be performed simultaneously using a single planarization process (e.g., chemical mechanical polishing) to form dummy pads 238 and first bonding pads 228. Therefore, Figure 9D The dummy pad 238 and the first bonding pad 228 may comprise the same metal or a group of the same metal materials (e.g., a combination of thin metal barrier pad materials (e.g., TiN, TaN, WN and / or MoN) and copper-filled materials that are essentially composed of copper).

[0166] Figures 10A to 10E This is a sequential vertical cross-sectional view of a seventh configuration region of an exemplary structure surrounding at least one bonding level dielectric layer 220 during the formation of the dummy pad 238 and the first bonding pad 228, according to some embodiments of the present invention. Figure 10F This is a vertical cross-sectional view of a composite grain 900 having a seventh configuration according to some embodiments of the present invention. (See also: [link to relevant information]) Figures 8A to 8F The described process sequence is derived by increasing the depth of the dummy pad cavity 237 so that the depth of the dummy pad cavity 237 is equal to the thickness of at least one bonding level dielectric layer 220. Figures 10A to 10E The process sequence is shown. In other words, the second pitch s2 or the lower pitch is zero. The first pitch s1 or the upper pitch is also zero. Therefore, the thickness of each dummy pad 238 can be equivalent to the thickness of at least one bonding level dielectric layer 220, and each dummy pad 238 can contact the horizontal surface of the first semiconductor die 100 (e.g., the surface of the first back-side dielectric layer 117). The dummy pads 238 and the first bonding pads 228 can have the same thickness, which is equivalent to the thickness of at least one bonding level dielectric layer 220.

[0167] Figures 11A to 11C This is a sequential vertical cross-sectional view of the eighth configuration of an exemplary structure surrounding at least one bonding level dielectric layer 220 during the formation of the dummy pad 238 and the first bonding pad 228, according to some embodiments of the present invention. Figure 11D This is a vertical cross-sectional view of a composite grain 900 having an eighth configuration according to some embodiments of the present invention. (See also: [link to relevant information]) Figures 10A to 10E The described process sequence is derived by using the same filler material for both the first and second filler materials. Figures 11A to 11CThe process sequence is shown. In such an embodiment, the dummy pad cavity 237 and the bonding pad cavity 227 can be formed simultaneously through at least one bonding-level dielectric layer 220 using the same photolithography patterned etching mask (e.g., a patterned photoresist layer) and the same anisotropic etching process. The first filler material is the same as the second filler material, and therefore the first filler material and the second filler material are deposited in the same deposition step. The planarization of the first filler material and the second filler material can be performed simultaneously using a single planarization process (e.g., chemical mechanical polishing) to form the dummy pad 238 and the first bonding pad 228. Therefore, Figure 11C The dummy pad 238 and the first bonding pad 228 may have the same thickness and may include the same metal or a group of the same metal materials (e.g., a combination of thin metal barrier pad materials (e.g., TiN, TaN, WN and / or MoN) and copper filler materials that are essentially composed of copper).

[0168] Figures 12A to 12G This is a sequential vertical cross-sectional view of the ninth configuration region of an exemplary structure surrounding at least one bonding level dielectric layer 220 during the formation of the dummy pad 238 and the first bonding pad 228, according to some embodiments of the present invention. Figure 12H This is a vertical cross-sectional view of a composite grain 900 having a ninth configuration according to some embodiments of the present invention. (See also: [link to relevant information]) Figures 4A to 4E The described process sequence is adjusted Figure 4A The pattern of the virtual pad cavity 237 formed in the process steps makes it possible to... Figure 12A In the process steps shown, only the first subset of the dummy pad cavity 237 is patterned and derived. Figures 12A to 12G The process sequence is shown. Subsequently, regarding... Figure 4B as well as Figure 4C The described process steps can be found separately in Figure 12B as well as Figure 12C The process is performed in the following steps. A first subset of dummy pads 238 is formed within a first subset of the dummy pad cavity 237. Typically, the first subset of dummy pads 238 may include the same or different material as the first bonding pad 228 that will subsequently be formed. Figures 12A to 12G In the ninth configuration shown, the first subset of the dummy pad 238 comprises the same material as the first bonding pad 228 that will subsequently be formed.

[0169] Please refer to Figure 12D Executable about Figure 4A The described process steps involve adjusting the etching pattern such that a second subset of the dummy pad cavities 237 is patterned. Therefore, the top periphery of the second subset of the dummy pad cavities 237 is vertically offset by a first spacing s1, i.e., the upper spacing, relative to the top periphery of the first subset of the dummy pad cavities 237. Figure 12D The depth of the second subset of the dummy pad cavity 237 formed in the process steps can be compared with... Figure 12A The depths of the first subset of the virtual pad cavities 237 formed in the process steps are the same or different.

[0170] Please refer to Figures 12E to 12G Executable about Figure 4B , Figure 4D , Figure 4E The described process steps form a second subset of dummy pads 238 and a first bonding pad 228. Typically, the second subset of dummy pads 238 may include materials that are the same as or different from the material of the first bonding pad 228. Figures 12A to 12G In the ninth configuration shown, the second subset of the dummy pad 238 includes a material different from that of the first bonding pad 228.

[0171] Figures 13A to 13G This is a sequential vertical cross-sectional view of the tenth configuration of an exemplary structure surrounding at least one bonding level dielectric layer 220 during the formation of the dummy pad 238 and the first bonding pad 228, according to some embodiments of the present invention. Figure 13H This is a vertical cross-sectional view of a composite grain 900 having a tenth configuration according to some embodiments of the present invention. (See also: [link to relevant information]) Figures 12A to 12G The described process sequence is derived by forming a first subset of dummy pads 238 using a material different from that of the first bonding pad 228. Figures 13A to 13G The process sequence is shown.

[0172] Figures 14A to 14F This is a sequential vertical cross-sectional view of the eleventh configuration region of an exemplary structure surrounding at least one bonding level dielectric layer 220 during the formation of the dummy pad 238 and the first bonding pad 228, according to some embodiments of the present invention. Figure 14G This is a vertical cross-sectional view of a composite grain 900 having an eleventh configuration according to some embodiments of the present invention. (See also: [link to relevant information]) Figures 12A to 12G The described process sequence is derived by forming a first subset of dummy pads 238 using a material different from that of the first bonding pad 228, and forming a second subset of dummy pads 238 using the same material as that of the first bonding pad 228. Figures 14A to 14FThe process sequence is shown. In such an embodiment, the second subset of dummy pad cavities 237 and bonding pad cavities 227 can be formed sequentially in any order, and the second subset of dummy pad cavities 237 and bonding pad cavities 227 can be simultaneously filled with a second filler material to form a first bonding pad 228. A planarization process can be performed to remove the second filler material above a horizontal plane including the top surface of the upper bonding layer dielectric layer 222. The remaining portion of the second filler material can form the second subset of dummy pads 238 and the first bonding pad 228.

[0173] Figures 15A to 15F This is a sequential vertical cross-sectional view of the twelfth configuration region of an exemplary structure surrounding at least one bonding level dielectric layer 220 during the formation of the dummy pad 238 and the first bonding pad 228, according to some embodiments of the present invention. Figure 15G This is a vertical cross-sectional view of a composite grain 900 having a twelfth configuration according to some embodiments of the present invention. (See also: [link to relevant information]) Figures 14A to 14F The described process sequence is derived by forming a first subset of the dummy pads 238 using the same material as the first bonding pad 228. Figures 15A to 15F The process sequence is shown. Therefore, Figure 15F as well as Figure 15G The first subset of dummy pads 238, the second subset of dummy pads 238, and the first bonding pad 228 may include the same metal or a group of the same metal materials (e.g., a combination of thin metal barrier pad materials (e.g., TiN, TaN, WN and / or MoN) and copper-filled materials that are essentially composed of copper).

[0174] Figures 16A to 16E This is a sequential vertical cross-sectional view of the thirteenth configuration of an exemplary structure surrounding at least one bonding level dielectric layer 220 during the formation of the dummy pad 238 and the first bonding pad 228, according to some embodiments of the present invention. Figure 14G This is a vertical cross-sectional view of a composite grain 900 with a thirteenth configuration according to some embodiments of the present invention. (See also: [link to relevant information]) Figures 8A to 8F The described process sequence is derived by forming two sets of dummy pad cavities 237 through a two-step patterning process sequence. Figures 16A to 16EThe process sequence is shown. For example, a first subset of the dummy pad cavities 237 can be formed with a first depth d1, and a second subset of the dummy pad cavities 237 can be formed with a second depth d2, where the second depth d2 is different from the first depth d1. The top surface of all dummy pads 238 may be coplanar with the top surface of at least one bonding level dielectric layer 220. Typically, the material of the first subset of dummy pads 238 may be the same as or different from the material of the second subset of dummy pads 238. The material of the first subset of dummy pads 238 may be the same as or different from the material of the first bonding pad 228. The material of the second subset of dummy pads 238 may be the same as or different from the material of the first bonding pad 228.

[0175] Figures 17A to 17E This is a sequential vertical cross-sectional view of the fourteenth configuration region of an exemplary structure surrounding at least one bonding level dielectric layer 220 during the formation of the dummy pad 238 and the first bonding pad 228, according to some embodiments of the present invention. Figure 17F This is a vertical cross-sectional view of a composite grain 900 having a fourteenth configuration according to some embodiments of the present invention. (See also: Regarding...) Figures 16A to 16E The described process sequence is derived by sequentially forming a first subset of dummy pads 238 having a first thickness t1 and a second subset of dummy pads 238 having a second thickness t2. Figures 16A to 16E The process sequence is shown below. Please refer to it. Figure 17A This forms a first subset of the dummy pad cavity 237 with a first depth d1. Please refer to... Figure 17B The first subset of dummy pads 238 is formed by depositing filling material within the first subset of dummy pad cavities 237 and performing a first planarization process. Figures 17A to 17E In the fourteenth configuration shown, the material of the first subset of the dummy pad 238 is different from the second filling material of the first bonding pad 228 that will subsequently be formed. Please refer to... Figure 17C This can form a second subset of the dummy pad cavity 237 with a second depth d2. The second depth d2 may be the same as or different from the first depth d1. Please refer to... Figure 17D The bonding pad cavity 227 can be formed by a combination of photolithography and anisotropic etching processes. Please refer to [reference needed]. Figure 17E A second filler material can be deposited in the second subset of the dummy pad cavity 237 and the bonding pad cavity 227, and can subsequently be planarized to form the second subset of the dummy pad 238 and the first bonding pad 228. In the fourteenth configuration, the second subset of the dummy pad 238 and the first bonding pad 228 comprise the same metal or a group of the same metallic materials (e.g., a combination of thin metallic barrier pad materials (e.g., TiN, TaN, WN, and / or MoN) and a copper filler material that is substantially composed of copper). The first subset of the dummy pad 238 comprises materials different from those of the second subset of the dummy pad 238 and the first bonding pad 228.

[0176] Figures 18A to 18E This is a sequential vertical cross-sectional view of the fifteenth configuration region of an exemplary structure surrounding at least one bonding level dielectric layer 220 during the formation of the dummy pad 238 and the first bonding pad 228, according to some embodiments of the present invention. Figure 18F This is a vertical cross-sectional view of a composite grain 900 having a fifteenth configuration according to some embodiments of the present invention. (See also: [link to relevant information]) Figures 17A to 17E The described process sequence is derived by exchanging the patterns of the first subset of the dummy pad cavities 237 and the patterns of the second subset of the dummy pad cavities 237. Figures 17A to 17E The process sequence is shown. In the fifteenth configuration, the first subset of dummy pads 238 (having a first thickness t1) and the first bonding pad 228 comprise the same metal or a group of the same metallic materials (e.g., a combination of thin metallic barrier pad materials (e.g., TiN, TaN, WN, and / or MoN) and copper-filled materials that are substantially composed of copper). The second subset of dummy pads 238 (having a second thickness t2) comprises materials different from those of the second subset of dummy pads 238 and the first bonding pad 228.

[0177] Figures 19A to 19D This is a sequential vertical cross-sectional view of the sixteenth configuration of an exemplary structure surrounding at least one bonding level dielectric layer 220 during the formation of the dummy pad 238 and the first bonding pad 228, according to some embodiments of the present invention. Figure 19E This is a vertical cross-sectional view of a composite grain 900 having a sixteenth configuration according to some embodiments of the present invention. (See also: Regarding...) Figures 16A to 16E The described process sequence is derived by using the same metal material for the first subset of dummy pad cavities 237, the second subset of dummy pad cavities 237, and the mating pad cavity 227. Figures 19A to 19D The process sequence is shown. In such an embodiment, a first subset of dummy pad cavities 237, a second subset of dummy pad cavities 237, and bonding pad cavities 227 with different depths can be formed in any sequence. Furthermore, a metal filler material can be deposited and planarized to form the first subset of dummy pads 238 with a first thickness t1, the second subset of dummy pads 238 with a second thickness t2, and the first bonding pad 228 with a thickness greater than that of the dummy pads 238. In a sixteenth configuration, the first subset of dummy pads 238 (with a first thickness t1), the second subset of dummy pads 238 (with a second thickness t2), and the first bonding pad 228 comprise the same metal or a group of the same metal materials (e.g., a combination of thin metal barrier pad materials (e.g., TiN, TaN, WN, and / or MoN) and a copper filler material that is substantially composed of copper).

[0178] Figures 20A to 20EThis is a sequential vertical cross-sectional view of the seventeenth configuration region of an exemplary structure surrounding at least one bonding-level dielectric layer 220 during the formation of the dummy pad 238 and the first bonding pad 228, according to some embodiments of the present invention. (See also: [link to relevant information]) Figures 5A to 5E The described process sequence is derived by forming a guide hole cavity 235 under a subset of the dummy pad cavity 237. Figures 20A to 20E The process sequence is shown below. Please refer to it. Figure 20A The dummy pad cavities 237 formed in the lower bonding layer dielectric layer 221 may be the same as or different from the dummy pad cavities 237 described with respect to FIG. 5. Subsequently, a photoresist layer (not shown) may be applied over the lower bonding layer dielectric layer 221, and the photoresist layer may be photolithographically patterned to form openings in a subset of the dummy pad cavities 237. An anisotropic etching process may be performed to form via cavities 235 in the areas of the dummy pad cavities 237 not covered by the photoresist layer. The via cavities 235 may extend vertically to the bottom surface of the lower bonding layer dielectric layer 221, and the top surface of the first semiconductor die 100 may be substantially exposed below each via cavity 235. The photoresist layer may be removed, for example, by an ashing process. Subsequently, a process may be performed regarding... Figures 5B to 5E The described process steps.

[0179] In the seventeenth configuration, at least one dummy pad 238 may have a bottom surface that is vertically offset from a first horizontal plane including the bottom surface of the first bonding pad 228. At least one additional via portion of the dummy pad 238 includes a surface (typically a conductive surface, a semiconductor surface, or an insulating surface) that extends to the first horizontal plane and contacts the first semiconductor die 100.

[0180] Figures 21A to 21C This is a vertical cross-sectional view of various embodiments of the composite grains 900 having a seventeenth configuration according to some embodiments of the present invention.

[0181] Please refer to Figure 21A The illustration shows an embodiment of the seventeenth configuration, wherein a first subset of the dummy pad 238 includes corresponding via portions that contact the insulating surface of the first semiconductor die 100 (e.g., the surface of the first back-side dielectric layer 117).

[0182] Please refer to Figure 21BThis illustrates some other embodiments of the seventeenth configuration, wherein a first subset of the dummy pads 238 includes corresponding via portions that contact a conductive structure within the first semiconductor die 100. In the illustrated embodiments, the conductive structure may be an electrically floating substrate via structure 114. Typically, at least one additional dummy pad 238 includes a via portion extending to a first horizontal plane and contacting an additional conductive structure (e.g., substrate via structure 114) within the first semiconductor die 100. In some embodiments, an additional dummy pad 238 may not directly contact any conductive structure (e.g., substrate via structure 114) located on or within the second semiconductor die 300.

[0183] Please refer to Figure 21C This illustrates further embodiments of the seventeenth configuration, wherein a first subset of the dummy pad 238 includes corresponding via portions that contact a conductive structure within the first semiconductor die 100. In the illustrated example, the conductive structure may be a substrate via structure 114 electrically connected to the first semiconductor device 120. Typically, at least one additional dummy pad 238 includes a via structure extending to a first horizontal plane and contacting an additional conductive structure (e.g., substrate via structure 114) within the first semiconductor die 100. In some embodiments, an additional dummy pad 238 may not directly contact any conductive structure (e.g., substrate via structure 114) located on or within the second semiconductor die 300.

[0184] Typically, a first subset of dummy pads 238 can be electrically connected to a first semiconductor device 120 via a connecting conductive structure (e.g., but not limited to, substrate via structure 114). The connecting conductive structure may include, for example, a redistribution wiring structure within a redistribution dielectric layer, a metal interconnect structure such as a metal wire or metal via structure, or a metal pad structure. The first semiconductor device 120 to which the first subset of dummy pads 238 may be electrically connected may include a capacitor, resistor, heater, fuse, or any semiconductor device that can benefit from a connected heat sink. In some embodiments, electrically connecting the first subset of dummy pads 238 to the first semiconductor device 120 may improve the performance of the first semiconductor device 120 by increasing resistance, capacitance, or thermoelasticity (due to the additional heat dissipation provided by the dummy pads 238).

[0185] Figures 22A to 22E This is a sequential vertical cross-sectional view of the eighteenth configuration of an exemplary structure surrounding at least one bonding level dielectric layer 220 during the formation of the dummy pad 238 and the first bonding pad 228, according to some embodiments of the present invention. Figure 22FThis is a vertical cross-sectional view of a composite grain 900 having an eighteenth configuration according to some embodiments of the present invention. (See also: [link to relevant information]) Figures 4A to 4E The described sequence of process steps is derived by forming additional process steps after forming the dummy pad cavity 237 (which forms the connecting recess 23C between a selected pair of adjacent dummy pad cavities 237). Figures 22A to 22E The sequence of process steps is shown. For example, a photoresist layer (not shown) may be applied over the underlying bonding layer dielectric layer 221 after the dummy pad cavities 237 are formed, and the photoresist layer may be photolithographically patterned to form openings between adjacent pairs of dummy pad cavities 237. An etching process may be performed to form the connection recesses 23C, for example, an anisotropic etching process or an isotropic etching process. Subsequently, the photoresist layer may be removed, for example, by an ashing process. Subsequently, procedures regarding... Figures 4B to 4E The described process steps form the dummy pad 238.

[0186] A first subset of the dummy pad 238 can be formed as a plurality of main portions having a first thickness t1' and at least one connecting portion having a second thickness t2', wherein the second thickness t2' is less than the first thickness t1'. Typically, the dummy pad 238 may comprise the same or a different material than the first bonding pad 228. In an eighteenth configuration, the material of the dummy pad 238 is different from the material of the first bonding pad 228. The connecting portion of the dummy pad 238 may be more prone to deformation, bending, and loss of connection than the main portions of the dummy pad 238, and therefore the connecting portion of the dummy pad 238 can better absorb mechanical stress than the main portions of the dummy pad 238. Therefore, the connecting portion of the dummy pad 238 can enhance protection through deformation during or after the formation of the second molding compound matrix.

[0187] Figures 23A to 23E This is a sequential vertical cross-sectional view of the nineteenth configuration of an exemplary structure surrounding at least one bonding level dielectric layer 220 during the formation of the dummy pad 238 and the first bonding pad 228, according to some embodiments of the present invention. Figure 23F This is a vertical cross-sectional view of a composite grain 900 having a nineteenth configuration according to some embodiments of the present invention. (See also: [link to relevant information]) Figures 22A to 22E The described sequence of process steps is derived by using the same material as the first bonding pad 228 for the dummy pad 238. Figures 23A to 23E The sequence of process steps is shown. Therefore, the dummy pad 238 and the first bonding pad 228 may comprise the same metal or a group of the same metal materials (e.g., a combination of thin metal barrier pad materials (e.g., TiN, TaN, WN and / or MoN) and copper filler materials that are essentially composed of copper).

[0188] Figure 24This is a vertical cross-sectional view of a composite die 900 having a twentieth configuration according to some embodiments of the present invention. The twentieth configuration of the composite die 900 can be derived from any of the configurations described above by forming at least one conductive structure extending through the first semiconductor die 100 to a first horizontal plane including the bottom surface of the first bonding pad 228. For example, at least one conductive structure may include a substrate via structure 114. Such a conductive structure is advantageous for electrical and / or thermal coupling with the subsets of the dummy pad 238 to improve heat dissipation generated by the first semiconductor device 120. Although it is desirable for the conductive structure to directly contact the dummy pad 238, direct contact is not necessary for providing heat dissipation functionality.

[0189] Figures 25A to 25E This is a through-hole top view of composite grains with various configurations according to some embodiments of the present invention. Typically, the layout of the dummy pads 238 can be adjusted to minimize the effects of stress generated during the formation of the second molding compound matrix 460. Therefore, the number, shape, size, and pattern density of the dummy pads 238 can be selected in a manner that minimizes the effects of mechanical stress generated during the formation of the second molding compound matrix 460 and avoids the formation of cracks within the second molding compound matrix 460.

[0190] Figure 25A An example is shown where, when viewed from above, the density of dummy pads 238 within the region of the second semiconductor die 300 is less than the density of dummy pads 238 outside the region of the second semiconductor die 300 when viewed from above.

[0191] Figure 25B An example is shown of selecting the position of the dummy pad 238 by positioning the nearest row of dummy pads 238 directly below the straight section of the edge sealing ring structure 370 (parallel to the sidewall of the second semiconductor die 300), such that the overlap between the area enclosed by the edge sealing ring structure 370 and the dummy pad 238 is not zero (but at a minimal level).

[0192] Figure 25C This illustrates minimizing the overlap between the edge sealing ring structure 370 and the dummy pad 238 by positioning the nearest row of dummy pads 238 within the area enclosed by the sidewalls inside the edge sealing ring structure 370.

[0193] Figure 25D This illustrates an example of adjusting the size of the dummy pad 238 to be a function of proximity when viewed from above, in order to minimize the effects of mechanical stress generated during the formation of the second molding compound matrix 460.

[0194] Figure 25E This illustrates an example of adjusting the pattern density of the dummy pad 238 as a function of its proximity to the geometric center of the second semiconductor die 300 when viewed from above, in order to minimize the effects of mechanical stress generated during the formation of the second molding compound matrix 460.

[0195] Please refer to this as well. Figure 3 as well as Figures 25A to 25E The second semiconductor die 300 may include an edge sealing ring structure 370 that extends continuously along all sidewalls of the second semiconductor die 300. In some embodiments, at least one dummy pad 238 of a first subset of dummy pads 238 overlaps with the edge sealing ring structure 370 when viewed from above. Additionally or alternatively, at least one dummy pad 238 of the first subset of dummy pads 238 is at least partially located within the region enclosed by the edge sealing ring structure 370 when viewed from above. Additionally or alternatively, at least one dummy pad 238 of the first subset of dummy pads 238 is at least partially located within a frame-shaped region between the outer edge of the edge sealing ring structure 370 and the sidewalls of the second semiconductor die 300.

[0196] Please refer to this as well. Figures 1 to 25E According to various embodiments of the present invention, the semiconductor structure includes a molding compound 260, at least one bonding-level dielectric layer 220, and a second semiconductor die 300. The molding compound 260 laterally surrounds the first semiconductor die 100 and has a top surface coplanar with the top dielectric surface of the first semiconductor die 100. The at least one bonding-level dielectric layer 220 has first bonding pads 228 and dummy pads 238 formed therein, and the at least one bonding-level dielectric layer 220 is located above the first semiconductor die 100 and the molding compound 260, wherein each first bonding pad 228 is electrically connected to a corresponding conductive structure (e.g., a substrate via structure 114) within the first semiconductor die 100. The second semiconductor die 300 includes second bonding pads 388 bonded to the first bonding pads 228 by metal-to-metal bonding, wherein a first subset of the dummy pads 238 overlaps with the second semiconductor die 300 in plan view.

[0197] In some embodiments, the second semiconductor die 300 includes an edge sealing ring structure 370 that extends continuously along all sidewalls of the second semiconductor die 300. The second semiconductor die 300 also includes at least one dummy pad 238 from a first subset of dummy pads 238 that overlaps with the edge sealing ring structure 370 when viewed from above. In some embodiments, one of the dummy pads 238 has a different material composition than the first bonding pad 228. In some embodiments, one of the dummy pads 238 has a top surface that is vertically offset from the horizontal plane including the top surface of the first bonding pad 228.

[0198] In some embodiments, one of the dummy pads 238 has a bottom surface that is vertically offset from a first horizontal plane including the bottom surface of the first bonding pad 228. In some embodiments, one of the dummy pads 238 is additionally provided with a via portion including an additional conductive structure (e.g., substrate via structure 114) extending to the first horizontal plane and contacting within the first semiconductor die 100. In some embodiments, one of the dummy pads 238 is additionally provided with a conductive structure (e.g., substrate via structure 114) that may or may not directly contact any conductive structure located on or within the second semiconductor die 300.

[0199] Figure 26 This is a first flowchart illustrating the steps for forming a semiconductor structure according to some embodiments of the present invention.

[0200] Please refer to step 2610 and... Figure 1 , Figure 2A , Figure 2B A first molding compound matrix 260 can be formed around the first semiconductor die 100, such that the top surface of the first molding compound matrix 260 is coplanar with the top dielectric surface of the first semiconductor die 100.

[0201] Please refer to step 2620 and... Figure 2C , Figures 3 to 25E At least one combination of a bonding layer dielectric layer 220, a first bonding pad 228, and a dummy pad 238 may be formed over the first semiconductor die 100 and the first molding compound matrix 260. Each first bonding pad 228 is formed directly on a corresponding conductive structure (e.g., a substrate via structure 114) within the first semiconductor die 100.

[0202] Please refer to step 2630 and... Figures 2D to 2F A second semiconductor die 300, including a second bonding pad 388, can be attached to a first semiconductor die 100 by performing a bonding process, wherein the bonding process bonds the second bonding pad 388 to the first bonding pad 228 by metal-to-metal bonding, such that a first subset of the dummy pad 238 has regional overlap with the second semiconductor die 300 when viewed from above.

[0203] In some embodiments, the second semiconductor die 300 may include an edge sealing ring structure 370 extending continuously along all sidewalls of the second semiconductor die 300. Furthermore, some embodiments of the method include positioning the second semiconductor die 300 above the first semiconductor die 100 during a bonding process such that, in top view, at least one dummy pad 238 of a first subset of dummy pads 238 overlaps with the edge sealing ring structure 370. In some embodiments, the second semiconductor die 300 may include an edge sealing ring structure 370 extending continuously along all sidewalls of the second semiconductor die 300. Furthermore, some embodiments of the method include positioning the second semiconductor die 300 above the first semiconductor die 100 during a bonding process such that, in top view, at least one dummy pad 238 of a first subset of dummy pads 238 is at least partially within the region surrounded by the edge sealing ring structure 370. In some embodiments, the second semiconductor die 300 may include an edge sealing ring structure 370 extending continuously along all sidewalls of the second semiconductor die 300. Furthermore, some embodiments of the method include positioning the second semiconductor die 300 above the first semiconductor die 100 during the bonding process, such that at least one dummy pad 238 of a first subset of dummy pads 238 is at least partially located within a frame-shaped region between the outer edge of the edge sealing ring structure 370 and the sidewall of the second semiconductor die 300. In some embodiments, the dummy pads 238 can be formed by depositing and patterning a first filler material within a first subset of at least one bonding-level dielectric layer 220, and the first bonding pads 228 can be formed by depositing and patterning a second filler material within at least one bonding-level dielectric layer 220, such that each first bonding pad 228 extends vertically from the bottom surface of at least one bonding-level dielectric layer 220 to the top surface of at least one bonding-level dielectric layer 220.

[0204] In some embodiments, a first filler material is deposited by a first deposition process and planarized by a first planarization process to form a dummy pad 238; a second filler material is deposited by a second deposition process and planarized by a second planarization process to form a first bonding pad 228, wherein the second deposition process is different from the first deposition process. In some embodiments, the method further includes depositing a second subset of at least one bonding-level dielectric layer 220 over the dummy pad 238 and forming a bonding pad cavity 227 that extends through the second subset and through the first subset, wherein the first bonding pad 228 is formed in the bonding pad cavity 227.

[0205] Figure 27 This is a second flowchart illustrating the steps for forming a semiconductor structure according to some embodiments of the present invention.

[0206] Please refer to step 2710 and... Figure 1 , Figure 2A , Figure 2B A first molding compound matrix 260 can be formed around the first semiconductor die 100, such that the top surface of the first molding compound matrix 260 is coplanar with the top dielectric surface of the first semiconductor die 100.

[0207] Please refer to step 2720 and... Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12C , Figure 12D , Figure 13A , Figure 13C , Figure 13D , Figure 14A , Figure 14C , Figure 14D , Figure 15A , Figure 15D , Figure 16A , Figure 16B , Figure 17A , Figure 17C , Figure 18A , Figure 18C , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 22A , Figure 22B , Figure 23A , Figure 23B The dummy pad cavity 237 can be formed as a first subset passing through at least one bonding level dielectric layer 220.

[0208] Please refer to step 2730 and... Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8C , Figure 9D , Figure 10C , Figure 11C , Figure 12B , Figure 12E , Figure 13B , Figure 13E , Figure 14B , Figure 14F , Figure 15B , Figure 15F , Figure 16C , Figure 17B , Figure 17F , Figure 18B , Figure 18E , Figure 19D , Figure 20C , Figure 22C , Figure 23C The dummy pad 238 can be formed by depositing a first filling material in the dummy pad cavity 237.

[0209] Please refer to step 2740 and... Figure 4C , Figure 4D , Figure 5C , Figure 5D , Figure 6C , Figure 6D , Figure 7C , Figure 7D , Figure 8D , Figure 9C , Figure 10D , Figure 11A , Figure 11B , Figure 12F , Figure 13F , Figure 14E , Figure 15D , Figure 16D , Figure 17D , Figure 18D , Figure 19C , Figure 20D , Figure 22D , Figure 23D The bonding pad cavity 227 can be formed through each layer of at least one bonding level dielectric layer 220.

[0210] Please refer to step 2750 and... Figure 2C , Figure 4E , Figure 5E , Figure 6E , Figure 7E , Figure 8F , Figure 9D , Figure 10E , Figure 11C , Figure 12G , Figure 13G , Figure 14F , Figure 15F , Figure 16E , Figure 17E , Figure 18E , Figure 19D , Figure 20E , Figure 22E , Figure 23E The first bonding pad 228 can be formed by depositing a second filling material in the bonding pad cavity 227, wherein each first bonding pad 228 is formed directly on a corresponding conductive structure (e.g., substrate via structure 114) within the first semiconductor die 100.

[0211] Please refer to step 2760 and... Figures 2D to 2F , Figure 3 , Figure 5F , Figure 6F , Figure 7F , Figure 8F , Figure 9E , Figure 10F , Figure 11D , Figure 12H , Figure 13H , Figure 14G , Figure 15G , Figure 16F , Figure 17F , Figure 18F , Figure 19E , Figures 21A to 21C , Figure 22F , Figure 23F , Figure 24 , Figures 25A to 25D A second semiconductor die 300, including a second bonding pad 388, can be attached to a first semiconductor die 100 by performing a bonding process, wherein the bonding process bonds the second bonding pad 388 to the first bonding pad 228 by metal-to-metal bonding, such that a first subset of the dummy pad 238 has regional overlap with the second semiconductor die 300 when viewed from above.

[0212] In some embodiments, the dummy pad cavity 237 may be formed to have a first depth, and the dummy pad cavity 237 may be formed to have a second depth, wherein the second depth is greater than the first depth. In some embodiments, the method may further include performing a first planarization process that removes excess portions of the first filler material from a horizontal plane above the top surface of a first subset including at least one bonding level dielectric layer 220. In some embodiments, the bonding pad cavity may be formed after performing the first planarization process. In some embodiments, the method further includes performing a second planarization process that removes excess portions of the second filler material from a horizontal plane above the top surface of the at least one bonding level dielectric layer 220, wherein after the second planarization process, the first bonding pad 228 includes residual portions of the second filler material. In some embodiments, the first filler material has a first material composition and is deposited by performing a first deposition process, and the second filler material has a second material composition, wherein the second material composition is different from the first material composition, and is deposited by performing a second deposition process, wherein the second deposition process is different from the first deposition process. In some embodiments, a first subset of at least one bonding layer 220 is smaller than the entirety of at least one bonding layer 220, and the method includes depositing a second subset of at least one bonding layer 220 over the first subset of at least one bonding layer 220.

[0213] Some embodiments of this invention provide metal-to-metal bonding with enhanced stress relief around the bonding region by disposing a dummy pad 238 below and around the peripheral region of the upper semiconductor die (i.e., the second semiconductor die 300). The dummy pad 238 in some embodiments of this invention can reduce the formation of cracks in the gap filler material applied around the upper semiconductor die, and can also improve bonding yield and enhance the reliability of the composite die 900, which includes bonding assemblies of semiconductor dies bonded together by metal-to-metal bonding or hybrid bonding.

[0214] Some embodiments of this utility model provide a method for forming a semiconductor structure. The method includes forming a first molding compound around a first semiconductor die, such that a top surface of the first molding compound is coplanar with a top dielectric surface of the first semiconductor die, and forming a combination of at least one bonding-level dielectric layer, a plurality of first bonding pads, and a plurality of dummy pads above the first semiconductor die and the first molding compound, wherein each of the first bonding pads is directly formed on a corresponding conductive structure within the first semiconductor die. The method also includes attaching a second semiconductor die, including a plurality of second bonding pads, to the first semiconductor die by performing a bonding process, wherein the bonding process bonds the second bonding pads to the first bonding pads via metal-to-metal bonding, such that a first subset of the dummy pads overlaps with the second semiconductor die in a top view.

[0215] In some embodiments, the second semiconductor die includes an edge sealing ring structure that extends continuously along all sidewalls of the second semiconductor die. The method includes positioning the second semiconductor die above the first semiconductor die during a bonding process such that at least one dummy pad in a first subset of dummy pads overlaps with the edge sealing ring structure when viewed from above.

[0216] In some embodiments, the second semiconductor die includes an edge sealing ring structure that extends continuously along all sidewalls of the second semiconductor die. The method includes positioning the second semiconductor die above the first semiconductor die during a bonding process such that, when viewed from above, at least one dummy pad in a first subset of dummy pads is at least partially located within a region surrounded by the edge sealing ring structure.

[0217] In some embodiments, the second semiconductor die includes an edge sealing ring structure that extends continuously along all sidewalls of the second semiconductor die. The method includes positioning the second semiconductor die above a first semiconductor die during a bonding process such that, in top view, at least one dummy pad in a first subset of dummy pads is at least partially located within a frame-shaped region between an outer edge of the edge sealing ring structure and a plurality of sidewalls of the second semiconductor die.

[0218] In some embodiments, the method forms dummy pads by depositing and patterning a first filler material within a first subset of at least one bonding level dielectric layer, and forms first bonding pads by depositing and patterning a second filler material within at least one bonding level dielectric layer, such that each of the first bonding pads extends vertically from a bottom surface of at least one bonding level dielectric layer to a top surface of at least one bonding level dielectric layer.

[0219] In some embodiments, a first filler material is deposited and planarized using a first deposition process and a first planarization process to form a dummy pad, and a second filler material is deposited and planarized using a second deposition process and a second planarization process to form a first bonding pad, wherein the second deposition process differs from the first deposition process. In some embodiments, the method further includes depositing a second subset of at least one bonding-level dielectric layer over the dummy pad and forming a plurality of bonding pad cavities that pass through the second subset and through the first subset, wherein the first bonding pad is formed in the bonding pad cavity.

[0220] Some embodiments of this invention provide a method for forming a semiconductor structure. The method includes forming a first molding compound around a first semiconductor die such that a top surface of the first molding compound is coplanar with a top dielectric surface of the first semiconductor die, and forming a plurality of dummy pad cavities as a first subset passing through at least one bonding-level dielectric layer above the first molding compound. The method also includes forming a plurality of dummy pads by depositing a first filler material in the dummy pad cavities, and forming a plurality of bonding pad cavities passing through each of at least one bonding-level dielectric layer. The method further includes forming a plurality of first bonding pads by depositing a second filler material in the bonding pad cavities, wherein each of the first bonding pads is formed directly on a corresponding conductive structure within the first semiconductor die, wherein the first bonding pads are formed before or after the formation of the dummy pads. The method further includes attaching a second semiconductor die, including a plurality of second bonding pads, to the first semiconductor die by performing a bonding process, wherein the bonding process bonds the second bonding pads to the first bonding pads by metal-to-metal bonding.

[0221] In some embodiments, a dummy pad cavity is formed having a first depth, and a bonding pad cavity is formed having a second depth greater than the first depth. In some embodiments, the method further includes performing a first planarization process that removes multiple excess portions of a first filler material from a horizontal plane above a top surface of a first subset including at least one bonding-level dielectric layer. In some embodiments, the bonding pad cavity is formed after performing the first planarization process. In some embodiments, the method further includes performing a second planarization process that removes multiple excess portions of a second filler material from a horizontal plane above a top surface of a first bonding-level dielectric layer, wherein after the second planarization process, the first bonding pad includes multiple residual portions of the second filler material.

[0222] In some embodiments, a first filler material has a first material composition and is deposited by performing a first deposition process; a second filler material has a second material composition different from the first material composition and is deposited by performing a second deposition process different from the first deposition process. In some embodiments, a first subset of at least one bonding-level dielectric layer is smaller than the entirety of at least one bonding-level dielectric layer. The method includes depositing a second subset of at least one bonding-level dielectric layer over the first subset of at least one bonding-level dielectric layer.

[0223] Some embodiments of this utility model provide a semiconductor structure. The semiconductor structure includes a molding compound, at least one bonding-level dielectric layer, and a second semiconductor die. The molding compound laterally surrounds a first semiconductor die and has a top surface coplanar with a top dielectric surface of the first semiconductor die. The at least one bonding-level dielectric layer has a plurality of first bonding pads and a plurality of dummy pads formed therein, and is located above the first semiconductor die and the molding compound, wherein each of the first bonding pads is electrically connected to a corresponding conductive structure within the first semiconductor die. The second semiconductor die includes a plurality of second bonding pads bonded to the first bonding pads by metal-to-metal bonding, wherein a first subset of the dummy pads overlaps with the second semiconductor die in a top view.

[0224] In some embodiments, the second semiconductor die includes an edge sealing ring structure that extends continuously along all sidewalls of the second semiconductor die. In top view, at least one dummy pad in a first subset of the dummy pads overlaps with the edge sealing ring structure. In some embodiments, one of the dummy pads has a different material composition than the bonding pad.

[0225] In some embodiments, one of the dummy pads has a top surface that is vertically offset from a horizontal plane including a plurality of top surfaces of the bonding pads. In some embodiments, one of the dummy pads has a bottom surface that is vertically offset from a first horizontal plane including a plurality of bottom surfaces of the bonding pads. In some embodiments, an additional dummy pad includes a via portion that extends to the first horizontal plane and contacts an additional conductive structure within a first semiconductor die, and the additional dummy pad is spaced apart from any conductive structure located on or within a second semiconductor die.

[0226] The foregoing summary of features of several embodiments enables those skilled in the art to better understand various aspects of the present invention. Unless otherwise stated in this specification, each embodiment described using the term "comprises" also implicitly discloses additional embodiments replaced by the terms "consists essentially of" or "consists of". Whenever two or more interchangeable elements are listed in the same or different paragraphs, the Markush group comprising the listed two or more elements is also implicitly disclosed. Whenever the term "may" is used in this invention to describe the formation of an element or the execution of a process step, it is expressly contemplated that embodiments in which the described element is not formed or the described process step is performed may still produce equivalent equipment or apparatus. Therefore, whenever omitting the formation of a described element or the execution of a described process step still provides the same or equivalent results, "may" describing the formation of an element or the performance of a process step should be interpreted as "may" or "may or may not," where equivalent results include slightly better or worse results. Those skilled in the art should understand that this invention can be readily used as the basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described in this specification. Those skilled in the art should also understand that such equivalent configurations do not depart from the spirit and scope of this invention, and that various changes, substitutions, and modifications can be made to this invention without departing from its spirit and scope.

Claims

1. A semiconductor structure, characterized in that, include: A molding compound laterally surrounds a first semiconductor grain and has a top surface coplanar with a top dielectric surface of the first semiconductor grain; At least one bonding-level dielectric layer, wherein a plurality of first bonding pads and a plurality of dummy pads are formed and located above the first semiconductor die and the molding compound, wherein each of the plurality of first bonding pads is electrically connected to a corresponding conductive structure within the first semiconductor die; as well as A second semiconductor die includes a plurality of second bonding pads bonded to a plurality of first bonding pads by metal-to-metal bonding, wherein a first subset of the plurality of dummy pads overlaps with the second semiconductor die when viewed from above.

2. The semiconductor structure as described in claim 1, characterized in that, The second semiconductor die includes an edge sealing ring structure that extends continuously along all sidewalls of the second semiconductor die. as well as When viewed from above, at least one dummy pad in the first subset of the plurality of dummy pads overlaps with the edge sealing ring structure.

3. The semiconductor structure as described in claim 1, characterized in that, The second semiconductor die includes an edge sealing ring structure that extends continuously along all sidewalls of the second semiconductor die. as well as When viewed from above, at least one dummy pad in the first subset of the plurality of dummy pads is at least partially located within a region surrounded by the edge sealing ring structure.

4. The semiconductor structure as described in claim 1, characterized in that, The second semiconductor die includes an edge sealing ring structure that extends continuously along all sidewalls of the second semiconductor die. as well as When viewed from above, at least one dummy pad in the first subset of the plurality of dummy pads is at least partially located within a frame-shaped region between an outer edge of the edge sealing ring structure and a plurality of sidewalls of the second semiconductor die.

5. The semiconductor structure as described in claim 1, characterized in that, The material composition of one of the plurality of dummy pads is different from the material composition of the plurality of first bonding pads.

6. The semiconductor structure as described in claim 1, characterized in that, One of the plurality of dummy pads has a top surface that is vertically offset from a horizontal plane comprising a plurality of top surfaces of the plurality of first bonding pads.

7. The semiconductor structure as described in claim 1, characterized in that, One of the plurality of dummy pads has a bottom surface that is vertically offset from a first horizontal plane comprising the plurality of bottom surfaces of the plurality of first engagement pads.

8. The semiconductor structure as described in claim 7, characterized in that, One of the plurality of dummy pads includes a via portion that extends to the first horizontal plane and contacts an additional conductive structure within the first semiconductor die, and the additional dummy pad is spaced apart from any conductive structure located on or within the second semiconductor die.

9. The semiconductor structure as described in claim 1, characterized in that, The at least one bonding layer includes a first subset and a second subset located above the first subset of the at least one bonding layer, a plurality of said dummy pads are formed in the first subset of the bonding layer, and the plurality of the first bonding pads are formed to pass through the first subset of the bonding layer and through the second subset of the bonding layer.

10. The semiconductor structure as claimed in claim 1, characterized in that, The thickness of any one of the plurality of dummy pads is less than or equal to the thickness of the at least one bonding layer dielectric layer.

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