A low-power cut-off foldback linear voltage regulator circuit

Abstract

The utility model relates to linear voltage stabilizer field provides a kind of low-power consumption turn-back type linear voltage stabilizing circuit that can be off, including LDO circuit, turn-back type current limiting circuit and shutdown circuit, the output end of LDO circuit connects voltage regulator output port, to connect load, provides output power supply to load, the turn-back type current limiting circuit is connected with the LDO circuit, for when load current is too high, limit load current, the controlled end of shutdown circuit is connected with voltage regulator enable port, control end connects the LDO circuit, to reduce internal power consumption when voltage regulator stops;The utility model can limit current to reduce power consumption when load short circuit, further reduce power consumption simultaneously when off.

Description

Technical Field

[0001] This utility model relates to the field of linear voltage regulators, and more specifically, to a turn-off low-power foldback linear voltage regulator circuit. Background Technology

[0002] A low-dropout regulator (LDO), also known as a voltage linear regulator, is characterized by its ability to stabilize the output voltage, ensuring that the output voltage remains constant under different load or input power supply voltage conditions. A traditional linear regulator typically includes a reference voltage source, an error amplifier, and a power transistor. The reference voltage source generates a stable and accurate reference voltage. The error amplifier compares the output voltage with the reference voltage and generates an error signal. The power transistor adjusts its conduction based on the output signal from the error amplifier. In this way, when the input voltage or load changes, the power transistor can automatically adjust its operating state to ensure the stability of the output voltage.

[0003] With the development of technology, the application scenarios of LDOs have increased, placing certain demands on circuit power consumption. This has made extremely low power consumption and turn-off capability essential requirements. However, controlling power consumption requires reducing the size of the circuit and improving it while still meeting functional requirements. When the load current suddenly increases or the load is short-circuited, traditional current limiting methods still limit the current, resulting in insufficient power consumption. In some cases, it is necessary to turn off the circuit to meet low power requirements, but leakage current can affect subsequent circuit stages, potentially impacting their performance. Utility Model Content

[0004] The problem solved by this invention is how to provide a turn-off low-power foldback linear regulator circuit that can limit current and reduce power consumption when the load is short-circuited, and further reduce power consumption when turned off.

[0005] To address the aforementioned problems, this utility model provides a turn-off low-power foldback linear regulator circuit, comprising: an LDO circuit, a foldback current limiting circuit, and a shutdown circuit. The output terminal of the LDO circuit is connected to the output port of the regulator to connect to the load and provide output power to the load. The foldback current limiting circuit is connected to the LDO circuit and is used to limit the load current when the load current is too high. The controlled terminal of the shutdown circuit is connected to the enable port of the regulator, and the control terminal is connected to the LDO circuit to reduce internal power consumption when the regulator stops.

[0006] Furthermore, the LDO circuit includes a first error amplifier, a first MOS transistor, and a feedback network. The first MOS transistor is a power transistor and is a PMOS transistor. The inverting input terminal of the first error amplifier is connected to a reference voltage, and the output terminal is connected to the gate of the first MOS transistor. The source of the first MOS transistor is connected to the input power supply, and the drain is connected to the output power supply. The feedback network is connected to the drain of the first MOS transistor.

[0007] Furthermore, the feedback network includes a first resistor and a second resistor connected in series. The first end of the first resistor is connected to the drain of the first MOSFET, and the second end is connected to the non-inverting input of the first error amplifier. The first end of the second resistor is connected to the second end of the first resistor, and the second end is grounded.

[0008] Furthermore, the foldback current limiting circuit includes five MOSFETs and two resistors. The source of the second MOSFET is connected to the input power supply, and its drain is connected to the output of the first error amplifier. The gate of the second MOSFET is connected to the first end of the fourth resistor and the drain of the sixth MOSFET. The second end of the fourth resistor is connected to the input power supply. The gate of the third MOSFET is connected to the output of the first error amplifier, its source is connected to the input power supply, and its drain is connected to the source of the fourth MOSFET. The gate of the fourth MOSFET is connected to the output power supply, and its drain is connected to the drain and gate of the fifth MOSFET. The source of the fifth MOSFET is grounded through the third resistor, and its gate is connected to the gate of the sixth MOSFET. The source of the sixth MOSFET is connected to the output power supply.

[0009] Furthermore, the second, third, and fourth MOS transistors are PMOS transistors, while the fifth and sixth MOS transistors are NMOS transistors.

[0010] Furthermore, the shutdown circuit includes a seventh MOS transistor, an eighth MOS transistor, and a first inverter. The gate of the seventh MOS transistor is connected to an enable signal, the drain is connected to the output power supply, and the source is grounded. The input terminal of the first inverter is connected to an enable signal, and the output terminal is connected to the gate of the eighth MOS transistor. The source of the eighth MOS transistor is connected to the input power supply, and the drain is connected to the output terminal of the first error amplifier.

[0011] Furthermore, the seventh and eighth MOS transistors are NMOS transistors.

[0012] Compared with the prior art, the beneficial effects of this utility model are:

[0013] The foldback current limiting circuit of this invention can limit the current when the output load current of the LDO circuit is too large or the load is short-circuited, thereby reducing power consumption and preventing chip damage caused by excessive current. The presence of the shutdown circuit can further reduce power consumption when the circuit is not in use, greatly increasing the application scenarios. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the overall principle structure of an embodiment of the present utility model. Detailed Implementation

[0015] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings.

[0016] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0017] In the description of this specification, references to terms such as "embodiment," "one embodiment," and "one implementation" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or implementation is included in at least one embodiment or illustrative embodiment of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or implementation. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or implementations.

[0018] like Figure 1 As shown, this utility model provides a turn-off low-power foldback linear regulator circuit, including: an LDO circuit, a foldback current limiting circuit, and a turn-off circuit. Generally, existing voltage regulator chips have multiple external connection ports, such as the input pin VDD, which connects to the input voltage source to power the internal voltage regulator chip; the output pin VOUT, which outputs a stable voltage for the load; the ground pin GND, which provides a reference ground; and the enable pin EN / CE, which controls the operating state of the voltage regulator chip. Figure 1 In the diagram, VDD is the input power supply, VOUT is the output power supply and is connected to the output pin, CE is the enable signal input to the enable terminal; EA is the first error amplifier, INV1 is the first inverter, M1-M8 are the first to eighth MOS transistors, and R1-R4 are the first to fourth resistors.

[0019] Under normal operating conditions, the voltage regulator outputs a VREF reference voltage to the error amplifier EA. Due to the presence of the feedback loop, the output voltage VOUT can be adjusted through the feedback network. Furthermore, due to the presence of the negative feedback network, the output can be stabilized by adjusting the gate voltage of the power transistor (PMOS) M1. MOS transistors M2 to M6 and resistors R3 and R4 form a foldback current limiting circuit. MOS transistors M7 and M8 and inverter INV1 form an enable circuit.

[0020] When the circuit is operating normally, the load current is below the set value. The error amplifier EA outputs voltage to (PMOS)M1 and (PMOS)M3, and the error amplifier output (EA_OUT) is relatively high. This results in a low difference between the gate-source voltage and the threshold voltage of (PMOS)M3, so (PMOS)M3 is in a fully conducting state. The gate of (PMOS)M4 is at the output voltage VOUT, and the conduction of (PMOS)M3 causes the source of (PMOS)M4 to be at a relatively high potential, thus it is also in the saturation region. In the same branch, (NMOS)M5 is also in a conducting state, so a certain amount of current flows into resistor R3. Since the source voltage of (NMOS)M6 is VOUT, the threshold voltage of (NMOS)M6 is relatively high, and the difference between the gate voltage and the source voltage is lower than the threshold voltage, so it cannot conduct. Therefore, the gate of (PMOS)M2 is relatively high and in a turn-off state. The CE terminal is in an on state and has no effect on the circuit. Therefore, under normal operating conditions, the foldback current limiting circuit and the turn-off circuit have no effect on the LDO circuit.

[0021] When the load exceeds the set value, the gate-source and drain-source voltages of PMOS (M3) are relatively close when the load current has not reached the set value. When VOUT decreases due to the increased load, the output voltage of the error amplifier (EA_OUT) decreases, and the gate-source voltage of PMOS (M3) increases, causing PMOS (M3) to operate in the linear region. Because VOUT decreases, the source voltage of PMOS (M4) increases, and the current flowing through resistor R3 increases. At this time, the gate voltage of NMOS (M5) increases, so NMOS (M5) consistently operates in the saturation region throughout the process. However, due to the decrease in VOUT, the threshold voltage of NMOS (M6) increases. The change causes (NMOS)M6 to conduct, and (NMOS)M6 mirrors the current of (NMOS)M5. The current flowing through resistor R4 generates a voltage drop, which lowers the gate voltage of (PMOS)M2. Therefore, it pulls up the output (EA_OUT) of the error amplifier, thereby limiting the load current. Throughout the process, as the output (EA_OUT) of the error amplifier increases, the gate-source voltage of (PMOS)M1 decreases. As the internal resistance increases, the current decreases, causing the output current and output voltage to decrease synchronously. Moreover, as the load increases, VOUT and the load decrease due to the foldback current limiting protection circuit, thereby reducing power consumption and protecting the circuit.

[0022] When enabled and disabled, when the CE terminal is turned off, the (NMOS)M7 turns on to conduct the weak leakage current generated when other devices are turned off, avoiding its influence on the downstream circuit. The CE signal outputs the signal CE_N through the inverter INV1 to the gate of the (PMOS)M8 to pull the potential of the error amplifier high, thereby turning off the power device, which greatly reduces power consumption.

[0023] Although the disclosure is as stated above, the scope of protection of this disclosure is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of this disclosure, and all such changes and modifications will fall within the protection scope of this utility model.

Claims

1. A turn-off low-power foldback linear voltage regulator circuit, characterized in that, include: The circuit comprises an LDO circuit, a foldback current limiting circuit, and a shutdown circuit. The output of the LDO circuit is connected to the output port of the voltage regulator to connect to the load and provide output power to the load. The foldback current limiting circuit is connected to the LDO circuit to limit the load current when the load current is too high. The controlled terminal of the shutdown circuit is connected to the enable port of the voltage regulator, and the control terminal is connected to the LDO circuit to reduce internal power consumption when the voltage regulator stops.

2. The turn-off low-power foldback linear regulator circuit according to claim 1, characterized in that, The LDO circuit includes a first error amplifier, a first MOSFET, and a feedback network. The first MOSFET is a power transistor and is a PMOS transistor. The inverting input terminal of the first error amplifier is connected to a reference voltage, and the output terminal is connected to the gate of the first MOSFET. The source of the first MOSFET is connected to the input power supply, and the drain is connected to the output power supply. The feedback network is connected to the drain of the first MOSFET.

3. The turn-off low-power foldback linear regulator circuit according to claim 2, characterized in that, The feedback network includes a first resistor and a second resistor connected in series. The first end of the first resistor is connected to the drain of the first MOSFET, and the second end is connected to the non-inverting input of the first error amplifier. The first end of the second resistor is connected to the second end of the first resistor, and the second end is grounded.

4. The turn-off low-power foldback linear regulator circuit according to claim 3, characterized in that, The foldback current limiting circuit includes five MOSFETs and two resistors. The source of the second MOSFET is connected to the input power supply, and its drain is connected to the output of the first error amplifier. The gate of the second MOSFET is connected to the first terminal of the fourth resistor and the drain of the sixth MOSFET. The second terminal of the fourth resistor is connected to the input power supply. The gate of the third MOSFET is connected to the output of the first error amplifier, its source is connected to the input power supply, and its drain is connected to the source of the fourth MOSFET. The gate of the fourth MOSFET is connected to the output power supply. Its drain is connected to the drain and gate of the fifth MOSFET. The source of the fifth MOSFET is grounded through the third resistor, and its gate is connected to the gate of the sixth MOSFET. The source of the sixth MOSFET is connected to the output power supply.

5. The turn-off low-power foldback linear regulator circuit according to claim 4, characterized in that, The second, third, and fourth MOS transistors are PMOS transistors, while the fifth and sixth MOS transistors are NMOS transistors.

6. The turn-off low-power foldback linear regulator circuit according to claim 5, characterized in that, The shutdown circuit includes a seventh MOS transistor, an eighth MOS transistor, and a first inverter. The gate of the seventh MOS transistor is connected to an enable signal, the drain is connected to the output power supply, and the source is grounded. The input terminal of the first inverter is connected to an enable signal, and the output terminal is connected to the gate of the eighth MOS transistor. The source of the eighth MOS transistor is connected to the input power supply, and the drain is connected to the output terminal of the first error amplifier.

7. The turn-off low-power foldback linear regulator circuit according to claim 6, characterized in that, The seventh and eighth MOS transistors are NMOS transistors.

Images