Board card, case, clock distribution circuit and system applied to quantum computing

Abstract

A kind of board card, cabinet, clock distribution circuit and system applied to quantum computing belong to quantum computing technical field;High-precision clock source is used to synchronize output high-speed clock signal and low-speed clock signal, ensure the synchronization of low-speed reference clock and high-speed sampling clock of multiple cabinets, multiple board cards;Independent clock distribution board card is used, high-speed clock electrical signal is converted into high-speed clock optical signal by microwave modulation light source, after optical power amplification, optical beam splitter, it is distributed to the clock distribution board card of each cabinet by optical fiber, low-speed clock electrical signal is connected to the clock distribution board card of each cabinet by radio frequency cable;High-speed clock optical signal, low-speed clock electrical signal are input to clock distribution board card, then by clock distribution board card distribution to each control board card, reduce the number of PD detector, Buffer, PLL and amplification filtering module on clock signal transmission path, reduce cabinet space use pressure and cost.

Description

Technical Field

[0001] This utility model belongs to the field of quantum computing technology, and relates to a board, chassis, clock distribution circuit and system for quantum computing. Background Technology

[0002] The synchronous clock distribution of chassis and boards is a key technology to ensure high-precision time synchronization among boards in a distributed system, especially crucial in fields such as quantum computing, quantum communication, lidar, and industrial automation. For example, in the field of quantum computing, when conducting large-scale qubit experiments, multiple control signals must be manipulated simultaneously, and any asynchrony in any control signal will affect the accuracy of the experiment.

[0003] like Figure 7 As shown, when multiple chassis are networked, the existing technology typically uses a high-precision clock source, which is cascaded from the top-level chassis (e.g., chassis 1) to the lower-level chassis (e.g., chassis 2 to chassis N) via RF cables, outputting the clock signal to the clock board input interface of the lower-level chassis. Specifically, Buffer 1 (Buffer means clock buffer) on the clock board of chassis 1 divides the clock signal into N paths. The first path of the clock signal is sent to Buffer 2 on the clock board of chassis 1 and then sent to each control board in chassis 1 through the backplane. The second to Nth paths of the clock signal are respectively sent to Buffer 2 on the clock boards of chassis 2 to chassis N as external reference clocks. In each control board of each chassis, the frequency is multiplied by a PLL phase-locked loop and then sampled by a frequency divider chip (such as FPGA, DAC, or other IC devices).

[0004] Existing solutions rely on cascaded RF cables for clock distribution between chassis boards, which has the following drawbacks: long-distance RF cables significantly exacerbate signal loss, latency, phase shift, and impedance mismatch; temperature changes and mechanical vibrations further degrade signal transmission quality, and existing phase-stable cables are only effective within a limited temperature range; multiple control boards use independent PLL (phase-locked loop) frequency multiplication clocks, and due to the closed-loop feedback mechanism of the PLL, if the error in the output oscillation frequency reaches a certain range, the PLL output frequency will be considered successfully locked. Therefore, the PLL output clock has inherent phase instability, and the phase synchronization of the clocks output between multiple PLLs is even worse. These drawbacks lead to the loss of synchronization of multiple control signals in large-scale quantum bit experiments, reducing the accuracy of the experiments. Utility Model Content

[0005] The technical solution of this utility model is used to solve the problems of how to improve the synchronization of control signals and reduce costs.

[0006] This utility model solves the above-mentioned technical problems through the following technical solution: This invention provides a clock distribution board for quantum computing, comprising a first clock buffer, a phase-locked loop (PLL), a PD detector, an amplification and filtering module, and a first power divider. The input terminal of the first clock buffer serves as the low-speed clock signal input interface of the clock distribution board, and the output terminal of the first clock buffer is connected to the input terminal of the PLL, which serves as the low-speed clock signal output interface of the clock distribution board. The input terminal of the PD detector serves as the high-speed clock optical signal input interface of the clock distribution board, and the output terminal of the PD detector is connected to the input terminal of the amplification and filtering module. The output terminal of the amplification and filtering module is connected to the input terminal of the first power divider, which serves as the high-speed clock signal output interface of the clock distribution board.

[0007] Furthermore, the output of the first clock buffer is connected to the input of the phase-locked loop via PCB traces, the output of the PD detector is connected to the input of the amplification and filtering module via PCB traces, and the output of the amplification and filtering module is connected to the input of the first power divider via PCB traces.

[0008] This invention provides a multi-channel clock distribution circuit for quantum computing, comprising a high-precision clock source, a microwave modulation light source, an optical power amplifier, an optical beam splitter, and multiple clock distribution boards; the multiple clock distribution boards are arranged in parallel; the first output terminal of the high-precision clock source is connected to the input terminal of the microwave modulation light source, the output terminal of the microwave modulation light source is connected to the input terminal of the optical power amplifier, the output terminal of the optical power amplifier is connected to the input terminal of the optical beam splitter, the output terminal of the optical beam splitter is divided into multiple paths, each corresponding to a high-speed clock optical signal input interface of one of the multiple clock distribution boards; the second output terminal of the high-precision clock source is divided into multiple paths, each corresponding to a low-speed clock electrical signal input interface of one of the multiple clock distribution boards.

[0009] Furthermore, the first output terminal of the high-precision clock source is connected to the input terminal of the microwave modulation light source via an RF cable.

[0010] Furthermore, the output end of the microwave modulated light source is connected to the input end of the optical power amplifier via an optical fiber, and the output end of the optical power amplifier is connected to the input end of the optical beam splitter via an optical fiber.

[0011] Furthermore, the output end of the optical beam splitter is connected to the high-speed clock optical signal input interface of multiple clock distribution boards via optical fiber; the second output end of the high-precision clock source is connected to the low-speed clock electrical signal input interface of multiple clock distribution boards via radio frequency cable.

[0012] This invention provides a chassis for quantum computing, comprising one clock distribution board and multiple control boards installed within the chassis housing, wherein the multiple control boards are arranged in parallel; the low-speed clock signal output interface of the clock distribution board is connected to the low-speed clock signal input interface of the multiple control boards respectively; the high-speed clock signal output interface of the clock distribution board is connected to the high-speed clock signal input interface of the multiple control boards respectively; the low-speed clock signal input interface of the clock distribution board serves as the low-speed clock signal input interface of the chassis, and the high-speed clock optical signal input interface of the clock distribution board serves as the high-speed clock optical signal input interface of the chassis.

[0013] Furthermore, the control board includes a second clock buffer, a second power divider, an FPGA, and multiple DACs; the input terminal of the second clock buffer serves as the low-speed clock signal input interface of the control board, and the output terminal of the second clock buffer is connected to the input terminals of the FPGA and multiple DACs respectively; the input terminal of the second power divider serves as the high-speed clock signal input interface of the control board, and the output terminal of the second power divider is connected to the input terminals of multiple DACs respectively.

[0014] Furthermore, the output of the second clock buffer is connected to the input of the FPGA and multiple DACs via PCB traces; the output of the second power divider is connected to the input of multiple DACs via PCB traces.

[0015] This invention provides a multi-channel clock distribution system for quantum computing, comprising a high-precision clock source, a microwave modulation light source, an optical power amplifier, an optical beam splitter, and multiple chassis as described above, arranged in parallel. The first output terminal of the high-precision clock source is connected to the input terminal of the microwave modulation light source, the output terminal of the microwave modulation light source is connected to the input terminal of the optical power amplifier, the output terminal of the optical power amplifier is connected to the input terminal of the optical beam splitter, and the output terminal of the optical beam splitter is divided into multiple paths, each corresponding to a high-speed clock optical signal input interface of one of the multiple chassis. The second output terminal of the high-precision clock source is also divided into multiple paths, each corresponding to a low-speed clock electrical signal input interface of one of the multiple chassis. Attached Figure Description

[0016] Figure 1 This is a structural diagram of a clock distribution board for quantum computing according to Embodiment 1 of this utility model; Figure 2 This is a structural diagram of a multi-channel clock distribution circuit for quantum computing according to Embodiment 2 of this utility model; Figure 3 This is a structural diagram of the control board for quantum computing according to Embodiment 3 of this utility model; Figure 4This is a structural diagram of the chassis for quantum computing according to Embodiment 4 of this utility model; Figure 5 This is a structural diagram of the chassis networking system for quantum computing according to Embodiment 4 of this utility model; Figure 6 This is a structural diagram of the multi-channel clock distribution system for quantum computing according to Embodiment 5 of this utility model; Figure 7 This is a structural diagram of a current multi-channel clock distribution system. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below in conjunction with the embodiments of this utility model. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0018] The technical solution of this utility model will be further described below with reference to the accompanying drawings and specific embodiments: Example 1 like Figure 1 As shown, this embodiment provides a clock distribution board for quantum computing. The clock distribution board includes a first clock buffer (Buffer 1), a phase-locked loop (PLL), a PD detector, an amplification and filtering module, and a first power divider (Power Divider 1).

[0019] The input terminal of the first clock buffer serves as the low-speed clock signal input interface of the clock distribution board. The output terminal of the first clock buffer is connected to the input terminal of the phase-locked loop (PLL) via PCB traces. The output terminal of the PLL serves as the low-speed clock signal output interface of the clock distribution board, outputting a low-speed clock signal via an RF cable. The input terminal of the PD detector serves as the high-speed clock optical signal input interface of the clock distribution board. The output terminal of the PD detector is connected to the input terminal of the amplification and filtering module via PCB traces. The output terminal of the amplification and filtering module is connected to the input terminal of the first power divider via PCB traces. The output terminal of the first power divider serves as the high-speed clock signal output interface of the clock distribution board, outputting a high-speed clock signal via an RF cable.

[0020] The workflow of the clock distribution board in this embodiment is as follows: The input terminal of the first clock buffer receives a low-speed clock signal, which is then distributed, multiplied, or divided by a phase-locked loop before being output. The input terminal of the PD detector receives a high-speed clock optical signal. The PD detector, acting as a photoelectric conversion module, converts the input high-speed clock optical signal into a high-speed clock electrical signal. After being amplified and filtered by an amplification and filtering module, the high-speed clock electrical signal is distributed into multiple high-speed clock electrical signals by the first power divider before being output.

[0021] This embodiment designs an independent clock distribution board. The input high-speed clock optical signal is first converted into a high-speed clock electrical signal by a PD detector, then distributed into multiple high-speed clock electrical signals by a first power divider, and finally transmitted to the corresponding multiple control boards via RF cables. The input low-speed clock electrical signal is distributed, multiplied, or divided by a first clock buffer and a phase-locked loop (PLL), and finally transmitted to the corresponding multiple control boards via RF cables. This independent clock distribution board design uses only one clock buffer and PLL on the low-speed clock electrical signal transmission path to achieve signal distribution, multiplication, or division; and only one PD detector and amplification / filtering module on the high-speed clock optical signal transmission path to convert the high-speed clock optical signal into a high-speed clock electrical signal for subsequent distribution. This reduces the number of clock buffers, PLLs, PD detectors, and amplification / filtering modules on the clock transmission path, thus reducing the space requirements and cost of the control boards in the chassis.

[0022] Example 2 like Figure 2 As shown, this embodiment provides a multi-channel clock distribution circuit for quantum computing. The multi-channel clock distribution circuit includes a high-precision clock source, a microwave modulation light source, an optical power amplifier, an optical beam splitter, and N (N is an integer greater than or equal to 2) clock distribution boards as described in Embodiment 1; wherein, the N clock distribution boards are arranged in parallel. The first output terminal of the high-precision clock source outputs a high-speed clock signal, and the second output terminal of the high-precision clock source outputs a low-speed clock signal. The first output terminal of the high-precision clock source is connected to the input terminal of the microwave modulation light source via an RF cable. The output terminal of the microwave modulation light source is connected to the input terminal of the optical power amplifier via an optical fiber. The output terminal of the optical power amplifier is connected to the input terminal of the optical beam splitter via an optical fiber. The output terminal of the optical beam splitter is divided into N paths, which are respectively connected to the high-speed clock optical signal input interfaces of the N clock distribution boards via optical fibers. The second output terminal of the high-precision clock source is divided into N paths, which are respectively connected to the low-speed clock electrical signal input interfaces of the N clock distribution boards via RF cables.

[0023] The workflow of the multi-channel clock distribution circuit in this embodiment is as follows: The high-precision clock source outputs both high-speed clock electrical signals (1GHz~12GHz) and low-speed clock electrical signals (10MHz~300MHz). The microwave modulation light source acts as a photoelectric conversion module, converting the high-speed clock electrical signals into high-speed clock optical signals. The high-speed clock optical signals are amplified and distributed into multiple paths by an optical power amplifier and an optical beam splitter, and then input to N clock distribution boards through optical fibers. The N independent clock distribution boards detect and convert the high-speed clock optical signals and further distribute them. The low-speed clock electrical signals are input to the N clock distribution boards through RF cables, and the N independent clock distribution boards further distribute the low-speed clock electrical signals.

[0024] The high precision of the high-precision clock source in this embodiment can be high synchronization precision (e.g., synchronization precision requirement: ≤20ns) or high frequency precision (usually reflected in phase noise, for example, low frequency phase noise requirement: 50MHz≤-160dBc / Hz@1kHz, 250MHz≤-143dBc / Hz@1kHz; high frequency phase noise requirement: 1GHz≤-140dBc / Hz@1kHz, 10GHz≤-122dBc / Hz@1kHz, 20GHz≤-116dBc / Hz@1kHz). Those skilled in the art can select the device according to actual needs.

[0025] The multi-channel clock distribution circuit in this embodiment outputs both high-speed and low-speed clock signals from a high-precision clock source, ensuring the synchronization of low-speed reference clocks and high-speed sampling clocks across multiple boards. A microwave-modulated light source converts the high-speed clock signal from the high-precision clock source into a high-speed optical clock signal for transmission, which is then input to each clock distribution board. Fiber optic transmission eliminates the losses, delays, phase shifts, impedance mismatches, and noise interference associated with RF cable transmission. Furthermore, fiber optic transmission is less sensitive to temperature changes and mechanical vibrations, ensuring precise clock synchronization among multiple boards and meeting the phase stability requirements of quantum control output. Distributing the high-speed optical clock signal and the low-speed clock signal to the clock distribution boards, and then further distributing them, reduces the number of PD detectors, PLLs, and amplification / filtering modules along the clock signal transmission path, thus reducing space requirements and cost. This approach is suitable for applications with high phase stability requirements and a large number of boards.

[0026] Example 3 like Figure 3As shown, this embodiment provides a control board for quantum computing. The control board includes a second clock buffer (Buffer 2), a second power divider (Power Divider 2), an FPGA, and multiple DACs. The input terminal of the second clock buffer serves as the low-speed clock signal input interface of the control board, inputting a low-speed clock signal via an RF cable. The output terminal of the second clock buffer is connected to the input terminals of the FPGA and multiple DACs in the control board via PCB traces. The input terminal of the second power divider serves as the high-speed clock signal input interface of the control board, inputting a high-speed clock signal via an RF cable. The output terminal of the second power divider is connected to the input terminals of multiple DACs in the control board via PCB traces.

[0027] Example 4 like Figure 4 As shown, this embodiment provides a chassis for quantum computing. The chassis includes one clock distribution board as described in Embodiment 1 and n control boards as described in Embodiment 3. Both the clock distribution board and the n control boards are installed inside the chassis housing, with the n control boards arranged in parallel. The low-speed clock signal output interface of the clock distribution board is connected to the low-speed clock signal input interfaces of the n control boards via radio frequency cables. The high-speed clock signal output interface of the clock distribution board is connected to the high-speed clock signal input interfaces of the n control boards via radio frequency cables. n is an integer greater than or equal to 2. The low-speed clock signal input interface of the clock distribution board serves as the low-speed clock signal input interface of the chassis, and the high-speed clock optical signal input interface of the clock distribution board serves as the high-speed clock optical signal input interface of the chassis.

[0028] like Figure 5 As shown, this embodiment also provides a chassis networking system, which includes N chassis as described in Embodiment 4. The N chassis are arranged in parallel, and N is an integer greater than or equal to 2.

[0029] Example 5 like Figure 6As shown, this embodiment provides a multi-channel clock distribution system for quantum computing. The multi-channel clock distribution system includes a high-precision clock source, a microwave modulation light source, an optical power amplifier, an optical beam splitter, and N (N is an integer greater than or equal to 2) parallel-configured chassis, namely chassis 1, chassis 2... chassis N. Each chassis contains one clock distribution board and n (n is an integer greater than or equal to 2) parallel-configured control boards, namely control board 1, control board 2... control board n. The clock distribution board includes a first clock buffer (Buffer 1), a phase-locked loop (PLL), a PD detector, an amplification and filtering module, and a first power divider (power divider 1). Each control board contains a second clock buffer (Buffer 2), a second power divider (power divider 2), an FPGA, and multiple DACs.

[0030] The high-precision clock source outputs a high-speed clock signal at its first output terminal and a low-speed clock signal at its second output terminal. The first output terminal of the high-precision clock source is connected to the input terminal of a microwave modulation light source via an RF cable. The output terminal of the microwave modulation light source is connected to the input terminal of an optical power amplifier via an optical fiber. The output terminal of the optical power amplifier is connected to the input terminal of an optical beam splitter via an optical fiber. The output terminal of the optical beam splitter is divided into N paths, each connected to the input terminal of a PD detector in one of the N chassis via an optical fiber. The input terminal of the PD detector serves as the high-speed clock optical signal input interface for the clock distribution board within the chassis. The second output terminal of the high-precision clock source is also divided into N paths, each connected to the input terminal of a first clock buffer in one of the N chassis via an RF cable. The input terminal of the first clock buffer serves as the low-speed clock signal input interface for the clock distribution board within the chassis.

[0031] The output of the first clock buffer is connected to the input of the phase-locked loop via PCB traces. The output of the phase-locked loop is connected to the input of the second clock buffer in each of the n control boards via RF cables. The output of the second clock buffer is connected to the input of the FPGA and multiple DACs in the control boards via PCB traces.

[0032] The output of the PD detector is connected to the input of the amplification and filtering module via PCB traces. The output of the amplification and filtering module is connected to the input of the first power divider via PCB traces. The output of the first power divider is connected to the input of the second power divider in the n control boards via RF cables. The output of the second power divider is connected to the input of multiple DACs in the control boards via PCB traces.

[0033] The functions of each module in the multi-channel clock distribution system of this embodiment are as follows: 1) The high-precision clock source outputs a high-speed clock signal (1GHz~12GHz) and a low-speed clock signal (10MHz~300MHz) from the same source. The high-speed clock signal is used as the sampling clock for the DAC, meeting the performance requirements of low phase noise and low jitter, and ensuring the phase stability of the DAC output. The low-speed clock signal is used for digital signal communication data acquisition, which can achieve the performance requirements of lower phase noise and jitter, and ensure error-free transmission. The same source output can ensure the clock synchronization of the high-speed clock signal and the low-speed clock signal. 2) The microwave modulation light source, as a photoelectric conversion module, can convert the high-speed clock electrical signal generated by the high-precision clock source into a high-speed clock optical signal; 3) The optical power amplifier is used to amplify the converted high-speed clock optical signal. The amplified high-speed clock optical signal is then connected to the optical beam splitter. The amplification power is flexibly determined according to the number of chassis and the number of clock distribution boards. 4) The optical beam splitter is used to distribute the high-speed clock optical signal into multiple paths, which are then connected to the PD detectors on each clock distribution board in each chassis. The number of distributions is flexibly determined according to the number of chassis and the number of clock distribution boards. 5) The PD detector, as a photoelectric conversion module, converts high-speed clock optical signals into high-speed clock electrical signals; 6) The amplification and filtering module is used to amplify and filter the high-speed clock signal. The amplification factor is flexibly determined according to the number of DACs. 7) The first and second power dividers are used to distribute high-speed clock signals. The output signal of the second power divider is connected to the DAC. The number of power dividers distributed is flexibly determined according to the number of DACs. 8) The first clock buffer is used to distribute the low-speed clock signal generated by the high-precision clock source; 9) Phase-locked loops (PLLs) are used to distribute, multiply, or divide low-speed clock signals. The number of PLLs is determined by the number of low-speed clock signals required by the integrated circuit devices (FPGA, DAC) on the control board. 10) The second clock buffer is used to distribute the low-speed clock signal distributed, multiplied, or divided by the phase-locked loop. The output signal is connected to the FPGA and multiple DACs respectively, and is used for synchronous communication between the FPGA and the DACs. 11) DAC is a digital-to-analog converter, used to convert digital signals into analog signals and output multiple analog signals. The control board in this embodiment is equipped with multiple DACs.

[0034] The workflow of the multi-channel clock distribution system in this embodiment is as follows: The high-precision clock source outputs both a high-speed clock electrical signal (1GHz~12GHz) and a low-speed clock electrical signal (10MHz~300MHz). A microwave modulation light source, acting as a photoelectric conversion module, converts the high-speed clock electrical signal into a high-speed clock optical signal. This high-speed clock optical signal is amplified and distributed into multiple paths via optical power amplifiers and beam splitters, then input through optical fibers to the clock distribution boards of N chassis. Each clock distribution board's PD detector converts the signal into a high-speed clock electrical signal, which is then amplified, filtered, and divided by a first power divider before being input to the second power dividers of n control boards. The second power dividers then distribute the signal into multiple paths, which are correspondingly input to multiple DACs for use as high-speed sampling clocks. The low-speed clock electrical signal output from the high-precision clock source is input via RF cables to the clock distribution boards of N chassis. After passing through the first clock buffer and phase-locked loop in each clock distribution board, it is input to the second clock buffers of the n control boards. The second clock buffers then distribute the signal to the FPGA and multiple DACs for use as synchronous communication clocks.

[0035] This embodiment of the multi-channel clock distribution system outputs both high-speed and low-speed clock signals from a high-precision clock source, ensuring that low-speed reference clocks and high-speed sampling clocks from multiple chassis and boards share the same clock synchronization circuit. A microwave-modulated light source is used to convert the high-speed clock signal output from the high-precision clock source into a high-speed clock optical signal for transmission, which is then input to each clock distribution board in each chassis. Fiber optic transmission eliminates the losses, delays, phase shifts, impedance mismatches, and noise interference associated with RF cable transmission. Furthermore, fiber optic transmission is less sensitive to temperature changes and mechanical vibrations, ensuring precise clock synchronization between multiple chassis and boards, guaranteeing high stability of the DAC output phase and meeting the phase stability requirements of quantum control output. The high-speed clock optical signal and low-speed clock signal are distributed to the clock distribution boards, which then distribute them to the various control boards. This reduces the number of PD detectors, buffers, PLLs, and amplification / filtering modules along the clock signal transmission path, lowering the space requirements and cost of the chassis control boards. It is suitable for applications with high phase stability requirements and a large number of chassis boards.

[0036] The above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims

1. A clock distribution board for quantum computing, characterized in that, It includes a first clock buffer, a phase-locked loop, a PD detector, an amplification and filtering module, and a first power divider; the input terminal of the first clock buffer serves as the low-speed clock signal input interface of the clock distribution board, and the output terminal of the first clock buffer is connected to the input terminal of the phase-locked loop, and the output terminal of the phase-locked loop serves as the low-speed clock signal output interface of the clock distribution board. The input terminal of the PD detector serves as the high-speed clock optical signal input interface of the clock distribution board. The output terminal of the PD detector is connected to the input terminal of the amplification and filtering module. The output terminal of the amplification and filtering module is connected to the input terminal of the first power divider. The output terminal of the first power divider serves as the high-speed clock electrical signal output interface of the clock distribution board.

2. The clock distribution board according to claim 1, characterized in that, The output of the first clock buffer is connected to the input of the phase-locked loop via PCB traces, the output of the PD detector is connected to the input of the amplification and filtering module via PCB traces, and the output of the amplification and filtering module is connected to the input of the first power divider via PCB traces.

3. A multi-channel clock distribution circuit for quantum computing, characterized in that, It includes a high-precision clock source, a microwave modulation light source, an optical power amplifier, an optical beam splitter, and multiple clock distribution boards as described in claim 1 or 2; the multiple clock distribution boards are arranged in parallel; the first output terminal of the high-precision clock source is connected to the input terminal of the microwave modulation light source, the output terminal of the microwave modulation light source is connected to the input terminal of the optical power amplifier, the output terminal of the optical power amplifier is connected to the input terminal of the optical beam splitter, and the output terminal of the optical beam splitter is divided into multiple paths, which are respectively connected to the high-speed clock optical signal input interfaces of the multiple clock distribution boards; The second output of the high-precision clock source is divided into multiple channels, which are respectively connected to the low-speed clock electrical signal input interfaces of multiple clock distribution boards.

4. The clock distribution circuit according to claim 3, characterized in that, The first output terminal of the high-precision clock source is connected to the input terminal of the microwave modulation light source via an RF cable.

5. The clock distribution circuit according to claim 3, characterized in that, The output of the microwave modulated light source is connected to the input of the optical power amplifier via an optical fiber, and the output of the optical power amplifier is connected to the input of the optical beam splitter via an optical fiber.

6. The clock distribution circuit according to claim 3, characterized in that, The output of the optical beam splitter is connected to the high-speed clock optical signal input interface of multiple clock distribution boards via optical fiber; the second output of the high-precision clock source is connected to the low-speed clock electrical signal input interface of multiple clock distribution boards via radio frequency cable.

7. A chassis for quantum computing, characterized in that, It includes a clock distribution board as described in claim 1 or 2, installed inside a chassis housing, and multiple control boards, wherein the multiple control boards are arranged in parallel; the low-speed clock electrical signal output interface of the clock distribution board is connected to the low-speed clock electrical signal input interface of the multiple control boards respectively. The high-speed clock signal output interface of the clock distribution board is connected to the high-speed clock signal input interface of multiple control boards. The low-speed clock electrical signal input interface of the clock distribution board serves as the low-speed clock electrical signal input interface of the chassis, and the high-speed clock optical signal input interface of the clock distribution board serves as the high-speed clock optical signal input interface of the chassis.

8. The chassis according to claim 7, characterized in that, The control board includes a second clock buffer, a second power divider, an FPGA, and multiple DACs; The input terminal of the second clock buffer serves as the low-speed clock signal input interface of the control board, and the output terminal of the second clock buffer is connected to the input terminals of the FPGA and multiple DACs respectively. The input terminal of the second power divider serves as the high-speed clock signal input interface of the control board, and the output terminal of the second power divider is connected to the input terminals of multiple DACs respectively.

9. The chassis according to claim 8, characterized in that, The output of the second clock buffer is connected to the input of the FPGA and multiple DACs via PCB traces; the output of the second power divider is connected to the input of multiple DACs via PCB traces.

10. A multi-channel clock distribution system for quantum computing, characterized in that, The device includes a high-precision clock source, a microwave modulation light source, an optical power amplifier, an optical beam splitter, and multiple chassis as described in any one of claims 7 to 9, wherein the multiple chassis are arranged in parallel; the first output terminal of the high-precision clock source is connected to the input terminal of the microwave modulation light source, the output terminal of the microwave modulation light source is connected to the input terminal of the optical power amplifier, the output terminal of the optical power amplifier is connected to the input terminal of the optical beam splitter, and the output terminal of the optical beam splitter is divided into multiple paths, which are respectively connected to the high-speed clock optical signal input interfaces of the multiple chassis; The second output of the high-precision clock source is divided into multiple channels, which are respectively connected to the low-speed clock signal input interfaces of multiple chassis.

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