Global shutter pixel readout circuit
Patent Information
- Application Number
- CN202522082732.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-26
- Publication Date
- 2026-08-28
- Estimated Expiration
- 2035-09-26
AI Technical Summary
[0003]但是全局快门像素电路，由于保持电容的引入，积分节点的积分信号传输至保持节点时摆幅会降低，其输出的信噪比越小，降低了输出信号质量
[0023] The global shutter pixel readout circuit provided by this utility model includes an integrating circuit for generating an integrating signal, the integrating circuit including an integrating node; a storage and holding circuit including a holding node; and a transmission circuit connecting the integrating node and the holding node, the transmission circuit being used to transmit the integrating signal to the holding node. The transmission circuit can improve the storage and holding performance, output swing, and output signal-to-noise ratio of the global shutter pixel circuit.
Smart Images
Figure CN224697819U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of integrated circuit technology, and specifically relates to a global shutter pixel readout circuit. Background Technology
[0002] In the readout circuit framework of a CMOS image sensor, the pixel circuit, as the most direct processing unit for photoelectric signal input, directly impacts image quality. Pixel circuits are categorized into two types based on shutter type: rolling shutters and global shutters. Rolling shutters integrate pixels in each row sequentially with a fixed delay, resulting in a simple structure. However, they suffer from rolling shutter distortion when imaging rotating objects, leading to image distortion. Global shutters integrate all pixels simultaneously, store the data, and then read it out sequentially, effectively avoiding the rolling shutter effect and offering significant advantages in imaging moving objects. The moving imaging advantages of global shutters have led to their widespread application in industrial inspection, machine vision, and scientific imaging.
[0003] However, in the global shutter pixel circuit, due to the introduction of the holding capacitor, the swing of the integral signal from the integral node is reduced when it is transmitted to the holding node, resulting in a smaller signal-to-noise ratio and reduced output signal quality. Utility Model Content
[0004] To solve the above-mentioned technical problems, this utility model provides a global shutter pixel readout circuit, which can improve signal quality.
[0005] In a first aspect, this utility model provides a global shutter pixel readout circuit, comprising:
[0006] An integrating circuit for generating an integrating signal, the integrating circuit including an integrating node;
[0007] A storage retention circuit, the storage retention circuit including a retention node;
[0008] A transmission circuit is provided, which connects the integrator node and the hold node, and is used to transmit the integral signal to the hold node.
[0009] In one embodiment, the system further includes an input circuit comprising a first transistor, wherein the source terminal of the first transistor is connected to the photodetector via hybrid bonding, the drain terminal of the first transistor is connected to the integrating node, and the gate terminal of the first transistor receives a first control signal.
[0010] In one embodiment, the integrating circuit includes: a second transistor and an integrating capacitor;
[0011] The drain of the second transistor is connected to the reset voltage, the gate of the second transistor receives the integration control signal, the source of the second transistor is connected to the integration node, the first end of the integration capacitor is connected to the integration node, and the second end of the integration capacitor is grounded.
[0012] In one embodiment, the transmission circuit includes: a third transistor and a buffer operational amplifier unit;
[0013] The positive terminal of the buffer operational amplifier unit is connected to the integration node, the negative terminal of the buffer operational amplifier unit is connected to the output terminal of the buffer operational amplifier unit, the source terminal of the third transistor is connected to the output terminal of the buffer operational amplifier unit, the gate terminal of the third transistor is connected to the transmission control signal, and the source terminal of the third transistor is connected to the holding node.
[0014] In one embodiment, the low-level period of the integral control signal partially overlaps with the low-level period of the transmission control signal.
[0015] In one embodiment, the storage holding circuit includes: a holding capacitor and a fourth transistor;
[0016] The drain of the fourth transistor is connected to the reset voltage, and the gate of the fourth transistor is connected to the second control signal; the source of the fourth transistor is connected to the holding node, the first end of the holding capacitor is connected to the holding node, and the second end of the holding capacitor is grounded.
[0017] In one embodiment, the low-level period of the second control signal partially overlaps with the low-level period of the transmission control signal.
[0018] In one embodiment, the end of the low-level period of the integral control signal overlaps with the low-level period of the transmission control signal; and the beginning of the low-level period of the second control signal overlaps with the low-level period of the transmission control signal.
[0019] In one embodiment, it further includes: an output circuit, the output circuit including a fifth transistor and a sixth transistor;
[0020] The gate of the fifth transistor is connected to the holding node, the drain of the fifth transistor is connected to the power supply voltage, and the source of the fifth transistor is connected to the drain of the sixth transistor; the source of the sixth transistor is the output port, and the gate of the sixth transistor is connected to the third control signal.
[0021] In one embodiment, the output circuit further includes a fifth transistor, a sixth transistor, and a seventh transistor;
[0022] The gate of the fifth transistor is connected to the holding node, the drain of the fifth transistor is connected to the power supply voltage, and the source of the fifth transistor is connected to the drain of the sixth transistor. The source of the sixth transistor is an output port, the gate of the sixth transistor is connected to a third control signal, the drain of the seventh transistor is connected to the source of the fifth transistor, the source of the seventh transistor is grounded, and the gate of the seventh transistor receives a bias voltage.
[0023] The global shutter pixel readout circuit provided by this utility model includes an integrating circuit for generating an integrating signal, the integrating circuit including an integrating node; a storage and holding circuit including a holding node; and a transmission circuit connecting the integrating node and the holding node, the transmission circuit being used to transmit the integrating signal to the holding node. The transmission circuit can improve the storage and holding performance, output swing, and output signal-to-noise ratio of the global shutter pixel circuit. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This is a schematic diagram of the structure of the first embodiment of the global shutter pixel readout circuit of this utility model;
[0026] Figure 2 This is a schematic diagram of the structure of an embodiment of the buffer operational amplifier unit of this utility model;
[0027] Figure 3 This is a schematic diagram of the working timing of the global shutter pixel readout circuit of this utility model;
[0028] Figure 4 This is a schematic diagram of the second embodiment of the global shutter pixel readout circuit of this utility model. Detailed Implementation
[0029] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.
[0030] To make the technical problem to be solved, the technical solution, and the beneficial effects of this utility model clearer and more understandable, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this utility model and are not intended to limit this utility model.
[0031] See Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the global shutter pixel readout circuit of this utility model, which specifically includes: an integration circuit 12, a transmission circuit 13, and a storage and holding circuit 14.
[0032] An integrating circuit 12 is used to generate an integrating signal VSIG, and the integrating circuit 12 includes an integrating node Vint; a storage and holding circuit 14 includes a holding node VFD; a transmission circuit 13 connects the integrating node Vint and the holding node VFD, and the transmission circuit 13 is used to transmit the integrating signal VSIG to the holding node VFD.
[0033] In one embodiment, the global shutter pixel readout circuit further includes an input circuit 11, which includes a first transistor M1. The source terminal of the first transistor M1 is connected to the photodetector PD via hybrid bonding, the drain terminal of the first transistor M1 is connected to the integrating node Vint, and the gate terminal of the first transistor M1 receives a first control signal GPOL. When the photodetector detects a photoelectric signal, a photocurrent Iph is generated and flows into the integrating circuit 12 through the input circuit 11.
[0034] The integrating circuit 12 includes a second transistor M2 and an integrating capacitor Cint. The drain of the second transistor M2 is connected to the reset voltage VRST, the gate of the second transistor M2 receives the integrating control signal SW1, the source of the second transistor M2 is connected to the integrating node Vint, the first terminal of the integrating capacitor Cint is connected to the integrating node Vint, and the second terminal of the integrating capacitor is grounded to GND. When the integrating control signal SW1 is high, it controls the second transistor M2 to turn on, and the upper-level board potential of the integrating capacitor Cint is reset to the VRST voltage; when SW1 is low, it controls the second transistor M2 to turn off, and Cint integrates under the action of the photocurrent Iph to generate the VSIG signal voltage.
[0035] The transmission circuit 13 includes a third transistor M3 and a buffer operational amplifier unit AMP. The positive terminal of the buffer operational amplifier unit AMP is connected to the integration node, the negative terminal of the buffer operational amplifier unit AMP is connected to the output terminal of the buffer operational amplifier unit AMP, and the source terminal of the third transistor M3 is connected to the output terminal of the buffer operational amplifier unit AMP. The gate terminal of the third transistor M3 is connected to the transmission control signal SW2, and the source terminal of the third transistor M3 is connected to the holding node VFD. The buffer operational amplifier unit AMP forms negative feedback. When the transmission control signal SW2 is low and the third transistor M3 is turned on, the transmission circuit 13 transmits the integration signal VSIG to the storage and holding circuit 14 for storage and holding.
[0036] Buffered operational amplifier unit (AMP) such as Figure 2 As shown, it consists of five transistors, M7 to M11. M7 serves as the op-amp's wake transistor, providing the wake source. The gate of M7 is connected to the bias voltage Vb, and the source of M7 is grounded. The drain of M7 is connected to the source of M8 and M9. M8 and M9 are the input pair. The drain of M8 is connected to the gate and drain of M10 and the gate of M11. The gate of M8 is the positive input terminal A of the op-amp. The drain of M9 is connected to the drain of M11 and serves as the output terminal C of the op-amp. The gate of M9 is the inverting input terminal B of the op-amp. M10 and M11 are the mirror pair. The sources of both M10 and M11 are connected to the power supply voltage VCC. It should be noted that the op-amp structure described is only one embodiment of this utility model and is not intended to limit the architecture of buffered op-amps.
[0037] The storage and holding circuit 14 includes a holding capacitor C1 and a fourth transistor M4. The drain of the fourth transistor M4 is connected to the reset voltage VRST, and the gate of the fourth transistor M4 is connected to the second control signal SW3. The source of the fourth transistor M4 is connected to the holding node VFD, the first end of the holding capacitor C1 is connected to the holding node VFD, and the second end of the holding capacitor C1 is grounded to GND. When the second control signal SW3 is low, the fourth transistor M4 is turned off, and the upper plate of the holding capacitor C1 maintains the voltage of the integral signal VSIG, waiting for the output circuit (15) to read it out. When the second control signal SW3 is high, the fourth transistor M4 is turned on, and the upper plate of the holding capacitor C1 is at the reset voltage VRST.
[0038] In one embodiment, the global shutter pixel readout circuit further includes an output circuit 15, which includes a fifth transistor M5 and a sixth transistor M6. The gate of the fifth transistor M5 is connected to the holding node, the drain of the fifth transistor M5 is connected to the power supply voltage VCC, and the source of the fifth transistor M5 is connected to the drain of the sixth transistor M6. The source of the sixth transistor M6 is the output port VOUT, and the gate of the sixth transistor M6 is connected to a third control signal SW4. When the third control signal SW4 is low and controls M6 to turn off, the voltage VFD of the holding node is not read out. When the third control signal SW4 is high and controls the sixth transistor M6 to turn on, the fifth transistor M5, as a source follower, transmits the signal on the holding node VFD to the output port for processing by subsequent circuits.
[0039] This invention introduces a buffer operational amplifier unit (AMP) into the transmission circuit 13, transforming signal transmission from capacitive voltage division to voltage following, fundamentally avoiding signal amplitude reduction. This invention eliminates the signal amplitude reduction caused by the introduction of a hold capacitor in traditional global shutter pixel circuits; effectively increases the output signal amplitude, improving the output signal-to-noise ratio of the pixel circuit; and solves the problem of hold capacitors being limited by signal amplitude, allowing the hold capacitor size to be set as needed, improving the hold performance of the storage node and reducing noise interference.
[0040] To describe the operation of the circuit more clearly and understandably, the following will be combined with... Figure 3 The workflow of this utility model embodiment will be described in detail below:
[0041] The operation of this utility model embodiment is divided into four stages: initialization stage, exposure integration stage, storage and transmission stage, storage and retention stage, and readout stage.
[0042] The initial stage is the initialization before the circuit works. By pulling up the control voltage SW1 of the second transistor M2 in the integrator circuit, the voltage of the integrator node Vint is reset to the reset voltage VRST. By pulling up the gate control signal SW2 of the third transistor M3 in the transmission circuit, the third transistor M3 is turned off, and signal transmission is stopped. By pulling up the gate control signal SW3 of the fourth transistor M4 in the storage and holding circuit, the voltage of the holding node VFD is reset to the reset voltage VRST. By pulling down the gate control signal SW4 of the sixth transistor M6 in the output circuit, pixel readout is stopped.
[0043] The exposure integration stage is the generation stage of the integration signal VSIG. During this stage, the gate control signal SW1 of the second transistor M2 in the integration circuit remains low, allowing the photocurrent Iph to accumulate on the integration capacitor Cint; the gate control signal SW2 of the third transistor M3 in the transmission circuit remains high; the gate control signal SW3 of the transistor M4 in the storage and holding circuit remains high, allowing the storage node VFD to maintain the reset voltage VRST; and the gate control signal SW4 of the transistor M6 in the output circuit remains low, disabling readout.
[0044] In the storage and transmission phase and the storage and holding phase, the integrated signal is transmitted and stored. In the storage and transmission phase, the gate control signal SW1 of the second transistor M2 in the integration circuit is first held at a low level, and then held at a high level after the transmission is completed. In the transmission circuit, the gate control signal SW2 of the transistor M3 is held at a low level, and the integrated signal VSIG is transmitted to the holding capacitor C1 for storage and holding. In the storage and holding phase, the gate control signal SW3 of the transistor M4 in the storage and holding circuit is held at a low level, so that the holding capacitor C1 has no discharge circuit, and the integrated signal is stored and held; in (15), the gate control signal SW4 of the transistor M6 is held at a low level, and reading is prohibited.
[0045] It should be noted that the low-level period of the integral control signal partially overlaps with the low-level period of the transmission control signal. The low-level period of the second control signal also partially overlaps with the low-level period of the transmission control signal. Specifically, the end of the low-level period of the integral control signal overlaps with the low-level period of the transmission control signal; and the beginning of the low-level period of the second control signal overlaps with the low-level period of the transmission control signal. Please refer to [link to details]. Figure 3 .
[0046] The readout phase reads the integral signal on the holding node. In this phase, the gate control signal SW1 of transistor M2 in the integration circuit is kept high, and the integration node VPD is kept at the reset voltage VRST. In the transmission circuit, the gate control signal SW2 of transistor M3 is kept high, disabling transmission. In the storage and holding circuit, the gate control signal SW3 of transistor M4 is first kept low to read the integral signal VSIG, and then kept high to reset the storage node VFD to VRST, reading the reset voltage. In the output circuit, the gate control signal SW4 of transistor M6 is kept high for signal readout.
[0047] See Figure 4 , Figure 4 This is a schematic diagram of the second embodiment of the global shutter pixel readout circuit of this utility model, which is similar to the one described above. Figure 1The difference in the illustrated embodiment is that the output circuit of the global shutter pixel readout circuit in this embodiment includes a fifth transistor M5, a sixth transistor M6, and a seventh transistor M12. The gate of the fifth transistor M5 is connected to the holding node, the drain of the fifth transistor M5 is connected to the power supply voltage, and the source of the fifth transistor M5 is connected to the drain of the sixth transistor. The source of the sixth transistor M6 is the output port, the gate of the sixth transistor M6 is connected to the third control signal, the drain of the seventh transistor M12 is connected to the source of the fifth transistor, the source of the seventh transistor M12 is grounded, and the gate of the seventh transistor M12 receives the bias voltage. This embodiment provides a stable current to the fifth transistor M5 under the bias voltage Vb_SF by introducing a wake transistor, i.e., the seventh transistor M12.
[0048] The above-disclosed embodiments are merely preferred embodiments of the present utility model and should not be construed as limiting the scope of the present utility model. Those skilled in the art can understand that implementing all or part of the above-described embodiments and making equivalent changes in accordance with the claims of the present utility model are still within the scope of the utility model.
Claims
1. A global shutter pixel readout circuit, characterized in that, include: An integrating circuit for generating an integrating signal, the integrating circuit including an integrating node; A storage retention circuit, the storage retention circuit including a retention node; A transmission circuit is provided, which connects the integrator node and the hold node, and is used to transmit the integral signal to the hold node.
2. The global shutter pixel readout circuit according to claim 1, characterized in that, Also includes: The input circuit includes: a first transistor, the source terminal of which is connected to a photodetector via hybrid bonding, the drain terminal of which is connected to the integrating node, and the gate terminal of which receives a first control signal.
3. The global shutter pixel readout circuit according to claim 1, characterized in that, The integrating circuit includes: a second transistor and an integrating capacitor; The drain of the second transistor is connected to the reset voltage, the gate of the second transistor receives the integration control signal, the source of the second transistor is connected to the integration node, the first end of the integration capacitor is connected to the integration node, and the second end of the integration capacitor is grounded.
4. The global shutter pixel readout circuit according to claim 3, characterized in that, The transmission circuit includes: a third transistor and a buffer operational amplifier unit; The positive terminal of the buffer operational amplifier unit is connected to the integration node, the negative terminal of the buffer operational amplifier unit is connected to the output terminal of the buffer operational amplifier unit, the source terminal of the third transistor is connected to the output terminal of the buffer operational amplifier unit, the gate terminal of the third transistor is connected to the transmission control signal, and the source terminal of the third transistor is connected to the holding node.
5. The global shutter pixel readout circuit according to claim 4, characterized in that, The low-level period of the integral control signal partially overlaps with the low-level period of the transmission control signal.
6. The global shutter pixel readout circuit according to claim 5, characterized in that, The storage retention circuit includes: a retention capacitor and a fourth transistor; The drain of the fourth transistor is connected to the reset voltage, and the gate of the fourth transistor is connected to the second control signal; the source of the fourth transistor is connected to the holding node, the first end of the holding capacitor is connected to the holding node, and the second end of the holding capacitor is grounded.
7. The global shutter pixel readout circuit according to claim 6, characterized in that, The low-level period of the second control signal partially overlaps with the low-level period of the transmission control signal.
8. The global shutter pixel readout circuit according to claim 7, characterized in that, The end of the low-level period of the integral control signal overlaps with the low-level period of the transmission control signal; and the beginning of the low-level period of the second control signal overlaps with the low-level period of the transmission control signal.
9. The global shutter pixel readout circuit according to claim 1, characterized in that, Also includes: The output circuit includes a fifth transistor and a sixth transistor; The gate of the fifth transistor is connected to the holding node, the drain of the fifth transistor is connected to the power supply voltage, and the source of the fifth transistor is connected to the drain of the sixth transistor; the source of the sixth transistor is the output port, and the gate of the sixth transistor is connected to the third control signal.
10. The global shutter pixel readout circuit according to claim 1, characterized in that, Also includes: An output circuit, comprising a fifth transistor, a sixth transistor, and a seventh transistor; The gate of the fifth transistor is connected to the holding node, the drain of the fifth transistor is connected to the power supply voltage, and the source of the fifth transistor is connected to the drain of the sixth transistor. The source of the sixth transistor is an output port, the gate of the sixth transistor is connected to a third control signal, the drain of the seventh transistor is connected to the source of the fifth transistor, the source of the seventh transistor is grounded, and the gate of the seventh transistor receives a bias voltage.