Semiconductor device

Abstract

A semiconductor device includes a plurality of memory structures in a plurality of wiring layers in a first region of a substrate, the memory structures including a plurality of storage elements in the wiring layers, a peripheral circuit in a second region of the substrate, and a plurality of dummy memory structures in the wiring layers in the second region and vertically overlapping the peripheral circuit.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] The semiconductor device industry has produced a wide variety of devices to solve problems in many different fields. Some of these devices include structures for storing data. As semiconductor devices become increasingly complex, vertical integration is becoming more and more attractive for shrinking die size. Utility Model Content

[0003] In some embodiments, a semiconductor device includes a plurality of memory structures, peripheral circuitry, and a plurality of virtual memory structures. The memory structures are located in a plurality of wiring layers in a first region of a substrate, and these memory structures include a plurality of storage elements within these wiring layers. The peripheral circuitry is located in a second region of the substrate. The virtual memory structures are located in these wiring layers in the second region and vertically overlap with the peripheral circuitry.

[0004] In some embodiments, a semiconductor device includes peripheral circuitry, a plurality of memory structures, and a plurality of virtual memory structures. The peripheral circuitry is located in an active layer of a substrate and includes a plurality of elements. The memory structures are located in a plurality of wiring layers in a first region of the substrate and include a plurality of storage elements within the wiring layers. The virtual memory structures are located in wiring layers in a second region of the substrate and vertically overlap with the peripheral circuitry, wherein each virtual memory structure includes a virtual storage element within the wiring layers of the second region.

[0005] In some embodiments, a semiconductor device includes a plurality of memory cells, peripheral circuitry, and a plurality of resistors. The memory cells are located in a first region of a substrate, and these memory cells include a plurality of magnetic tunneling junction storage elements in a plurality of wiring layers within the first region of the substrate. The peripheral circuitry is located in a second region of the substrate. The resistors are located in the second region of the substrate, and these resistors include a plurality of magnetic tunneling junction resistor elements in these wiring layers within the second region and are perpendicularly overlapped with the peripheral circuitry. Attached Figure Description

[0006] The nature of this disclosure is best understood by reading it in conjunction with the accompanying drawings from the following detailed description. Please note that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1A This is a front view of a semiconductor device according to one embodiment, and Figure 1B It corresponds Figure 1A Cross-sectional view;

[0008] Figure 2A This is a front view of a semiconductor device according to one embodiment, and Figure 2B It corresponds Figure 2A Cross-sectional view;

[0009] Figure 3A This is a front view of a semiconductor device according to one embodiment, and Figure 3B It corresponds Figure 3A Cross-sectional view;

[0010] Figure 4 This is a front view of conductors in wiring layers in various regions of a semiconductor device according to one embodiment;

[0011] Figure 5 It is a front view of a conductor pattern in a semiconductor device according to some embodiments;

[0012] Figures 6 to 17 This is a front view of the arrangement of the array region and peripheral circuit region in a semiconductor device according to some embodiments;

[0013] Figure 18 This is a front view of a semiconductor device according to one embodiment;

[0014] Figure 19A This is a cross-sectional schematic diagram of a resistor structure according to some implementation methods;

[0015] Figure 19B This is a cross-sectional schematic diagram of a resistor structure according to some implementation methods;

[0016] Figure 20 This is a flowchart of a method for generating a layout according to some implementation methods and using this layout to manufacture a semiconductor device;

[0017] Figure 21 This is a flowchart of a method for generating a layout according to one embodiment;

[0018] Figure 22 This is a flowchart of a method for manufacturing one or more elements of a semiconductor device according to one embodiment;

[0019] Figure 23 This is a block diagram of a semiconductor device according to one embodiment;

[0020] Figure 24 This is a block diagram of an electronic design automation (EDA) system according to some implementation methods;

[0021] Figure 25It is a block diagram of an integrated circuit (IC) manufacturing system and a related semiconductor device manufacturing process according to some implementation methods.

[0022] [Symbol Explanation]

[0023] 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 2300: Semiconductor devices

[0024] 110:Substrate

[0025] 115, 415, 515: First Zone

[0026] 116, 216, 316, 416, 516: Second Zone

[0027] 117: Memory Cell Array

[0028] 117a: First Memory Cell Array

[0029] 117b: Second Memory Cell Array

[0030] 117c: Third Memory Cell Array

[0031] 117d: Fourth Memory Cell Array

[0032] 117e: Fifth Memory Cell Array

[0033] 117f: Sixth Memory Cell Array

[0034] 117g: Seventh Memory Cell Array

[0035] 117h: Eighth Memory Cell Array

[0036] 118: Peripheral Circuits

[0037] 120: Storage element

[0038] 120a: First electrode

[0039] 120b: Second electrode

[0040] 120c: Dielectric segment

[0041] 125: Appendix Labels

[0042] 126: Peripheral circuit transistors

[0043] 127: Grassroots

[0044] 128, 132, 142, 144, 150, 1942, 1944, SEC_Mx, SEC_Mx-1, DSEC_Mx, DSEC_Mx-1: Conductor

[0045] 129: Conductive Contact

[0046] 130: Top through hole

[0047] 131, 145, 153, 1961, 1963: Through holes

[0048] 140: Virtual storage element

[0049] 148: Dashed area

[0050] 216a, 316a, 416a, 516a: First sub-region

[0051] 216b, 316b, 416b, 516b: Second sub-region

[0052] 1802, 1860: Corner Area

[0053] 1804, 1808, 1812, 1816: First marginal region

[0054] 1806, 1564: LIO edge region

[0055] 1810, 1838, 1870: MCTRL circuit region

[0056] 1814, 1874: LCTRL edge region

[0057] 1818, 1878: GIO edge region

[0058] 1820: Second Edge Region

[0059] 1822, 1826, 1850, 1856: LIO circuit region

[0060] 1824, 1852: MIO circuit region

[0061] 1828, 1858: GIO circuit region

[0062] 1830: WLDRV edge region

[0063] 1832, 1836, 1840, 1844: WLDRV circuit region

[0064] 1834, 1842: LCTRL circuit region

[0065] 1846: GCTRL circuit region

[0066] 1862, 1868, 1872, 1876: Third marginal region

[0067] 1900A, 1900B, 1900C, 1900D: Resistor Structure

[0068] 1960: Resistor element

[0069] 1960A: First MTJ Resistor Component

[0070] 1960B: Second MTJ Resistor Element

[0071] 2000, 2100, 2200: Methods; 2002, 2004, 2102, 2104, 2202, 2204, 2206: Operations; 2302: Macro.

[0072] 2304: Area

[0073] 2400: EDA System

[0074] 2402: Processor

[0075] 2404: Computer-readable storage media

[0076] 2406: Computer Program Code

[0077] 2407: Standard Unit Library

[0078] 2408: Bus

[0079] 2410: I / O Interface

[0080] 2412: Network Interface

[0081] 2414: Network

[0082] 2442: User Interface

[0083] 2500: IC Manufacturing System

[0084] 2520: Design Company

[0085] 2522: IC Design Layout

[0086] 2530: Mask Producer

[0087] 2532: Masking Data Preparation

[0088] 2544: Mask Manufacturing

[0089] 2545: Mask

[0090] 2550: IC wafer fab

[0091] 2552: Crafting Tools

[0092] 2553: Semiconductor wafer

[0093] 2560: IC device

[0094] I-I': line

[0095] Mx, Mx-1, M0, M1, M2, M3, M4, M5: Wiring layers

[0096] Vx-1, Vx-2: Through-hole layer

[0097] a: First conductor pattern

[0098] b: Second conductor pattern

[0099] c: Third conductor pattern

[0100] d: Fourth conductor pattern

[0101] e: Fifth conductor pattern

[0102] f: Sixth conductor pattern Detailed Implementation

[0103] The following disclosure provides numerous different implementations or examples for carrying out various features of the provided object. Specific examples of elements, materials, values, steps, and configurations are described below to simplify this disclosure. Of course, these elements, materials, values, steps, and configurations are merely examples and are not intended to be limiting. Other elements, materials, values, steps, and configurations may be considered. For example, in the following description, the formation of a first feature above or on a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where an additional feature may be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various implementations and / or configurations discussed.

[0104] Additionally, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms may be used herein for ease of description to describe the relationship between one element or feature and another, as illustrated in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. Source / drain may refer individually or jointly to the source or drain, depending on the context.

[0105] Semiconductor devices include multiple transistors in an active region of a substrate and multiple interconnect layers above the active region to interconnect the transistors. In some semiconductor devices, multiple memory elements of multiple memory cells are provided in the interconnect layers instead of in the substrate to reduce the overall die area. In the interconnect layers, conductive structures, such as metal conductors, forming portions of the memory cells can have a different layout than conductive structures used for other purposes, such as interconnects or other wiring. This difference in layout can result in different region densities (pattern densities) of conductive structures, such as metal conductors, in the interconnect layers. Different region densities can be challenging during planarization operations such as chemical-mechanical polishing (CMP) because different region densities on the wafer surface lead to variations in material removal. Possible loading effects include pitting, etching, uneven features, non-uniform feature thickness, and similar conditions. Loading effects from different region densities can have adverse consequences such as reduced process control, lower yields, design limitations, and similar situations.

[0106] Figure 1A This is a front view of a semiconductor device 100 according to some embodiments, and Figure 1B yes Figure 1A A cross-sectional view along line I-I'.

[0107] Semiconductor device 100 includes a substrate 110 having a first region 115 for a memory cell array 117 and a second region 116 for peripheral circuitry 118. The memory cell array has a plurality of memory structures, each memory structure including a storage element 120. The first region 115 may be referred to as an array region. In some embodiments, the memory cell array 117 is embedded memory.

[0108] exist Figures 1A to 1B In this embodiment, there are two array regions (first region 115), each array region having a memory cell array 117. In other embodiments, there is only a single array region (first region 115). Figures 1A to 1B In one embodiment, peripheral circuitry 118 is located between two array regions (first region 115). In other embodiments, peripheral circuitry 118 is adjacent to only one memory cell array 117, for example, when peripheral circuitry 118 is located at the edge or outer region of semiconductor device 100. In other embodiments, peripheral circuitry 118 has memory cell array 117 on three or four sides. In other embodiments, memory cell array 117 has peripheral circuitry 118 on two, three, or four sides. Additional arrangements are possible, some of which are described below. Figure 18 Describe it.

[0109] Storage element 120 is located in a wiring layer above substrate 110. Storage element 120 and wiring layer are formed by multiple manufacturing operations of the back-end ofline (BEOL). The storage element 120 and wiring layer formed during the BEOL operation may be referred to as multiple BEOL structures. During the BEOL operation, front-end ofline (FEOL) structures (e.g., transistors and similar elements) in substrate 110 are also provided with interconnects, power and ground connections, connections to other substrates, or the like.

[0110] The BEOL structure includes a wiring layer Mx and a wiring layer Mx-1 located below the wiring layer Mx (i.e., between the wiring layer Mx and the substrate 110). In some embodiments, the wiring layers Mx and Mx-1 are metal layers. The storage element 120 is located in... Figure 1B Between wiring layer Mx and wiring layer Mx-1. In some embodiments, one or more wiring layers are below wiring layer Mx-1, that is, between wiring layer Mx-1 and substrate 110. In some embodiments, one or more wiring layers M0, M1, M2, M3 and similar layers are below wiring layer Mx-1, wherein wiring layer M0 is the first wiring layer above the substrate. In some embodiments, wiring layer Mx-1 is wiring layer M4 and wiring layer Mx is wiring layer M5. In some embodiments, one or more wiring layers are present above wiring layer Mx.

[0111] For ease of explanation, Figure 1B Three storage elements 120 are shown in each array region (first region 115), but it should be understood that in various embodiments, the memory cell array 117 includes any suitable number of storage elements 120.

[0112] In the substrate 110 of the array region (first region 115), one or more transistors are provided for, for example, controlling or accessing storage elements 120. In some embodiments, each memory cell of the memory cell array 117 includes (i) at least one storage element 120 in a wiring layer in the array region (first region 115) and (ii) at least one transistor in the substrate 110 of the array region (first region 115). The transistor of the memory cell may be referred to as an access transistor and is composed of... Figure 1B The figures in the accompanying drawings are commonly identified by reference numeral 125. Figure 1BIn this configuration, the access transistor (reference numeral 125) is located in an array region (first region 115) and thus overlaps perpendicularly with the storage element 120. The first element or region is considered to overlap perpendicularly with the second element or region when an imaginary line parallel to the Z-axis intersects both the first element or region and the second element or region. In some embodiments, the Z-axis is considered to be perpendicular to the principal surface of the substrate 110.

[0113] An example of the storage element 120 is a metal-insulator-metal (MIM) capacitor, wherein a dielectric segment 120c is inserted between the first electrode 120a and the second electrode 120b.

[0114] In some embodiments, fabricating the storage element 120 includes forming a base layer 127, such as an etch stop layer or the like, on a wiring layer Mx-1; patterning the base layer 127 to form openings in the base layer that perpendicularly overlap with a plurality of conductors 128 in the wiring layer Mx-1; and forming a plurality of conductive contacts 129 in the openings. To fabricate the storage element as a MIM capacitor, a metal layer corresponding to the second electrode 120b, a dielectric layer corresponding to the dielectric segment 120c, and another metal layer corresponding to the first electrode 120a are sequentially stacked. The stacked layers are then patterned (e.g., using the base layer 127 as an etch stop layer) to form individual storage elements 120 above the wiring layer Mx-1 that perpendicularly overlap with the conductive contacts 129. To provide connectivity to the MIM capacitor, a plurality of upper vias 130 are formed in the via layer Vx-1 to perpendicularly overlap with the first electrode 120a, and a plurality of conductors 132 are formed in the wiring layer Mx to perpendicularly overlap with the upper vias 130.

[0115] In some embodiments, the metal layers used for the MIM capacitor, namely the first electrode 120a and the second electrode 120b, include one or more of the following materials: aluminum, titanium, titanium nitride, tantalum nitride, cobalt, silver, gold, copper, nickel, chromium, hafnium, ruthenium, tungsten, platinum, or similar materials. In some embodiments, the dielectric layer, namely the dielectric segment 120c, includes aluminum oxide, barium oxide, bismuthstrontium tantalite (BST), calcium oxide, copper oxide (I), hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, and Hf. 1-x Zr xOne or more of the following materials: O2 (HZO), lanthanum oxide, lead zirconate titanate (PZT), magnesium oxide, niobium oxide (V), nickel oxide (II), silicon carbide, silicon nitride, strontium bismuth tantalite (SBT), strontium oxide, strontium tantalate (ST), tantalum oxide, tantalum oxynitride, titanium oxide, yttrium oxide, zirconium oxide, or similar materials.

[0116] The structure, materials, and manufacturing process of MIM memory cells are also disclosed in U.S. Patent Nos. 11,581,368 and 10,553,672, the entire contents of which are incorporated herein by reference.

[0117] exist Figure 1B In this embodiment, each storage element 120 is a MIM capacitor, but in other embodiments, the storage element is another type of capacitor, variable resistor device, or the like. For example, in some embodiments, the storage element 120 is a resistive random-access memory (RRAM), a magnetoresistive random-access memory (MRAM), a phase-change memory (PCM), or another BEOL-compatible storage element.

[0118] In some implementations, the memory cell is an RRAM cell comprising a resistive material layer with variable resistance, for example, to represent logic "0" or logic "1". An example of an RRAM structure includes a first electrode, a resistive material layer, and a second electrode, the resistive material layer being between and in contact with the first and second electrodes. The RRAM structure can vary between at least two states, each with different resistance values ​​corresponding to different logic values. By applying a predetermined voltage or current between the electrodes of the RRAM structure, the RRAM structure switches from one state to another (e.g., switching between a relatively high resistance state and a relatively low resistance state).

[0119] In some embodiments, the first and second electrodes of the RRAM cell comprise one or more of aluminum, copper, gold, iridium, platinum, ruthenium, tantalum, titanium, tungsten, or similar materials, or their borides, carbides, fluorides, nitrides, oxides, or silicides or similar materials. Specific examples include TaN, TiAlN, TiN, TiW, indium tin oxide (ITO), and iridium-tantalum alloys. In some embodiments, the resistive material layer comprises one or more of aluminum, cobalt, chromium, copper, iron, hafnium, molybdenum, nickel, ruthenium, silver, tin, tantalum, titanium, tungsten, zinc, zirconium, or similar materials, or composites thereof with silicon. Specific examples include aluminum oxide, copper oxide, hafnium oxide, molybdenum oxide, nickel oxide, tantalum oxide, titanium oxide, tungsten oxide, zinc oxide, and zirconium oxide.

[0120] The structure, materials, and manufacturing process of RRAM memory cells are also disclosed in U.S. Patent Nos. 10,950,303, 9,431,604, and 9,299,927, the entire contents of which are incorporated herein by reference.

[0121] In some embodiments, the memory cell is an MRAM cell that includes a magnetic tunnel junction (MTJ) structure as storage element 120. An example of an MTJ structure includes a lower MTJ layer, an upper MTJ layer, and a non-magnetic tunnel barrier layer between the lower and upper MTJ layers. The non-magnetic tunnel barrier layer is formed to have a thickness that allows electrons to tunnel through it. One of the lower and upper MTJ layers may include a reference layer with a fixed magnetization direction. The other of the lower and upper MTJ layers may include a free layer. The free layer can exist in two stable magnetization directions, parallel and antiparallel to the magnetization direction of the reference layer, respectively. The resistance of storage element 120 varies depending on the relative magnetic moments of the free layer and the reference layer, and the magnetization direction of the free layer relative to the fixed magnetization direction of the reference layer. When the magnetization direction of the free layer is parallel to the fixed magnetization direction of the reference layer, storage element 120 exhibits relatively low resistance. When the magnetization direction of the free layer is antiparallel to the fixed magnetization direction of the reference layer, the storage element exhibits relatively high resistance.

[0122] In some embodiments, the storage element 120 having an MTJ structure includes one or more additional layers, such as a seed layer, a hard ferromagnetic layer, an antiferromagnetic coupling layer, a capping layer, or a similar layer. For example, in some embodiments, the lower layer of the MTJ includes one or more of a seed layer, a hard ferromagnetic layer, an antiferromagnetic coupling layer, and a reference layer, and the upper layer of the MTJ includes a capping layer and a free layer. In other embodiments, the lower layer of the MTJ includes one or more of a capping layer and a free layer, and the upper layer of the MTJ includes one or more of an antiferromagnetic coupling layer, a hard ferromagnetic layer, and a reference layer.

[0123] In some embodiments, the nonmagnetic tunneling barrier layer comprises one or more of aluminum nitride, aluminum oxide, aluminum oxynitride, hafnium oxide, magnesium oxide, zirconium oxide, or similar materials. In some embodiments, the reference layer comprises a ferromagnetic material providing a fixed magnetization direction, such as one or more of cobalt, CoFe, CoFeB, CoFeNi, CoFeTa, CoPt, iron, FeB, molybdenum, NiFe, tantalum, tungsten, or similar materials. In some embodiments, the free layer comprises a ferromagnetic material, such as one or more of Co, CoFe, CoFeB, CoFeNi, CoFeTa, CoPt, Fe, FeB, NiFe, or similar materials. In some embodiments, the seed layer comprises a polycrystalline nonmagnetic metallic material, such as a CoFeB alloy, a NiFe alloy, ruthenium, titanium, or similar materials. In some embodiments, the hard ferromagnetic layer comprises one or more of the following: cobalt, CoFe, CoNi, CoPd, CoPt, FeMn, iridium, IrMn, nickel, OsMn, palladium, platinum, PtMn, RhMn, ruthenium, or similar materials, and / or a double-layer stack of Co / Pt, Co / Pd, Co / Ni, or similar materials. In some embodiments, the antiferromagnetic coupling layer comprises one or more of the following: chromium, iridium, ruthenium, or similar materials. In some embodiments, the capping layer comprises one or more of the following: aluminum, aluminum nitride, aluminum oxide, aluminum oxynitride, chromium, copper, germanium, hafnium oxide, magnesium, magnesium oxide, molybdenum, molybdenum nitride, niobium, platinum, ruthenium, tantalum, titanium, titanium nitride, tungsten, zirconium, zirconium nitride, zirconium oxide, or similar materials. In some embodiments, the electrodes disposed on opposite sides of the MTJ structure comprise one or more non-magnetic metallic materials, such as aluminum, cobalt, copper, molybdenum, platinum, ruthenium, tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, or similar materials.

[0124] The structure, materials, and manufacturing process of MRAM memory cells are also disclosed in U.S. Patent Nos. 11,997,931 and 10,553,785, the entire contents of which are incorporated herein by reference.

[0125] In some embodiments, the storage element 120 having a PCM structure includes a first electrode, a second electrode, and one or more layers of PCM material between and in contact with the first and second electrodes. In some embodiments, a heating structure for heating the PCM material layer is located between or adjacent to the first and / or second electrodes. During memory operation, current flows through the PCM material based on an applied voltage, and the resistance of the PCM structure is measured based on the values ​​of the applied voltage and current. Moreover, for a sufficiently large applied voltage value, the current flowing through the PCM material and the heating structure (if present) causes self-heating, thereby causing a temperature rise to affect the phase transition in the PCM material. In some embodiments, a given phase configuration corresponds to a ratio of (i) one or more volumes of the PCM material layer in the crystalline phase to (ii) one or more volumes of the PCM material layer in the amorphous phase. In some embodiments, the lowest value of this ratio corresponds to the minimum volume of the crystalline phase, thereby corresponding to the lowest electrical conductivity of the PCM structure, and the highest value of this ratio corresponds to the maximum volume of the crystalline phase, thereby corresponding to the highest electrical conductivity of the PCM structure. In some embodiments, the lowest ratio and conductivity value correspond to a fully amorphous PCM material layer, and the highest ratio and conductivity value correspond to a fully crystalline PCM material layer. In some embodiments, the lowest ratio and conductivity value correspond to at least a portion of the PCM material layer being in a crystalline phase, and / or the highest ratio and conductivity value correspond to at least a portion of the PCM material layer being in an amorphous phase. The PCM material layer transitions between a low-resistivity crystalline phase and a high-resistivity amorphous phase based at least in part on one or more temperature values ​​within a temperature range controlled by the applied voltage.

[0126] In some embodiments, the first and second electrodes of the PCM structure comprise one or more of aluminum, copper, tungsten, or similar materials. In some embodiments, the resistive material layer comprises one or more chalcogenide materials, such as germanium antimony tellurium (GeSbTe or GST), GeTe, GeSb, Sb2Te3, or similar materials, which in some embodiments are doped with one or more of arsenic, carbon, gallium, indium, nitrogen, oxygen, selenium, silicon, tin, or similar materials.

[0127] The structure, materials, and manufacturing process of PCM memory cells are also disclosed in U.S. Patent No. 10,971,223, the entire contents of which are incorporated herein by reference.

[0128] Additionally, the embedded memory can be implemented as a memory cell array 117, for example, using charge-based memory, such as flash memory.

[0129] In semiconductor device 100, a second region 116 of substrate 110 includes circuitry distinct from the circuitry of memory cell array 117. In some embodiments, the circuitry in the second region 116 is or includes peripheral circuitry 118. In some embodiments, peripheral circuitry 118 is configured to operate memory cell array 117, such as writing or reading data from memory cell array 117, or to provide other functions such as input / output (I / O) associated with memory cell array 117. Examples of peripheral circuitry 118 include word line drivers, local I / O circuitry, main I / O circuitry, global I / O circuitry, local control circuitry, main control circuitry, or the like. In other embodiments, peripheral circuitry 118 is circuitry adjacent to memory cell array 117 but provides functions independent of memory cell array 117.

[0130] In the second region 116, the peripheral circuitry 118 includes a plurality of peripheral circuitry transistors 126 in the substrate 110. Also in the second region 116, interconnect wiring for the peripheral circuitry transistors 126 is perpendicularly overlapped with the peripheral circuitry transistors 126 (e.g., in a wiring layer between wiring layer Mx-1 and substrate 110) to couple power, ground, signal, or the like to the peripheral circuitry transistors 126.

[0131] As described above, in the first region 115, Figure 1B Storage element 120 has conductor 128 in wiring layer Mx-1 and conductor 132 in wiring layer Mx. The multiple storage element conductors (SECs) in wiring layer Mx, collectively referred to as conductor 132, will be called conductor SEC_Mx. The SECs in wiring layer Mx-1, collectively referred to as conductor 128, will be called conductor SEC_Mx-1.

[0132] The difference in conductor density in wiring layer Mx between first region 115 and second region 116, and / or the difference in conductor density in wiring layer Mx-1 between first region 115 and second region 116, may cause loading effects in planarization operations such as chemical mechanical polishing (CMP). Therefore, manufacturing defects may increase and yield may decrease. For example, uneven removal of metal layers on the wafer may lead to over-removal of metal features, resulting in, for example, open circuits or high resistance, or may result in metal residues between adjacent conductors, leading to, for example, short circuits.

[0133] In some embodiments, one or more elements (e.g., storage element 120 and / or conductor 128, conductor 132) of the memory cells formed in the memory cell array 117 in the first region 115, along with vias 131, are also formed in the virtual memory cells in the second region 116. Figure 1B In the second region 116, the virtual storage element 140 corresponds to the storage element 120 in the first region 115, the conductor 142 in the second region 116 corresponds to the conductor 128 in the first region 115, the conductor 144 in the second region 116 corresponds to the conductor 132 in the first region 115, and the via 145 in the second region 116 corresponds to the via 131 in the first region 115.

[0134] Including elements such as virtual storage element 140 and / or conductors 142 and 144 in the second region 116 allows adjustment of the region density difference between the first region 115 and the second region 116 to reduce or mitigate load effects, avoiding the use of additional photomasks or incurring additional process costs. In the semiconductor device 100, such elements are included among other elements of the peripheral circuitry 118, i.e., such elements, in addition to the elements, wiring, or the like of the peripheral circuitry 118, reduce or mitigate load effects while retaining the elements, wiring, or the like of the peripheral circuitry 118.

[0135] exist Figure 1B In the second region 116, there are virtual storage elements 140, corresponding conductors 142 that are vertically overlapping and below the virtual storage elements 140 in the wiring layer Mx-1, a plurality of vias 145 that are below the conductors 142 in the via layer Vx-2, and corresponding conductors 144 that are vertically overlapping and above the virtual storage elements 140 in the wiring layer Mx. Therefore, each virtual memory cell in the second region 116 includes a virtual storage element 140 between the conductors 144 in the wiring layer Mx and the conductors 142 in the wiring layer Mx-1.

[0136] The multiple dummy memory storage element conductors (DSECs) in routing layer Mx, collectively referred to as conductor 144, will be called conductor DSEC_Mx. The DSECs in routing layer Mx-1, collectively referred to as conductor 142, will be called conductor DSEC_Mx-1.

[0137] The virtual memory cells including virtual storage elements 140 and conductors 142 and 144 in the second region 116 effectively mimic the memory cells including storage elements 120 and conductors 128 and 132 in the first region 115, and allow control over the relative metal region density in the second region 116 relative to the first region 115. Control over the relative region density allows the layout to reduce or mitigate load effects.

[0138] More specifically, the inclusion of virtual memory cells, and more specifically, the inclusion of conductors DSEC_Mx and DSEC_Mx-1, alters the relative region density of conductors in wiring layers Mx and Mx-1 within the second region 116. In some embodiments, controlling the number of virtual memory cells, and thus controlling the number of conductors DSEC_Mx and DSEC_Mx-1 in the second region 116, adjusts the relative region density of conductors in wiring layers Mx and Mx-1 between the first region 115 and the second region 116, which can reduce or mitigate load effects.

[0139] In some embodiments, the conductor DSEC_Mx is included in a quantity sufficient to adjust or balance the relative region densities of the conductors in the wiring layer Mx between the first region 115 and the second region 116. In other words, in some embodiments, the conductor DSEC_Mx is included in a quantity such that the region density of conductor DSEC_Mx is adjusted or balanced with the region density of conductor SEC_Mx. That is, the combined region density of conductor 144 is adjusted or balanced with the region density of conductor 132.

[0140] Similarly, in some embodiments, the conductor DSEC_Mx-1 is included in sufficient quantity to adjust or balance the relative region density of the conductors in the wiring layer Mx-1 between the first region 115 and the second region 116. In other words, in some embodiments, the conductor DSEC_Mx-1 is included in such quantity that the region density of conductor DSEC_Mx-1 is adjusted or balanced with the region density of conductor SEC_Mx-1. That is, the region density of conductor 142 is adjusted or balanced with the region density of conductor 128.

[0141] In some embodiments, the conductor DSEC_Mx includes a quantity such that the region density of conductor DSEC_Mx is equal to or approximately equal to the region density of conductor SEC_Mx, and / or the conductor DSEC_Mx-1 includes a quantity such that the region density of conductor DSEC_Mx-1 is equal to or approximately equal to the region density of conductor SEC_Mx-1.

[0142] In some embodiments, the number of conductors DSEC_Mx is such that the region density of conductor DSEC_Mx is less than the region density of conductor SEC_Mx, and / or the number of conductors DSEC_Mx-1 is such that the region density of conductor DSEC_Mx-1 is less than the region density of conductor SEC_Mx-1.

[0143] In some embodiments, the number of conductors DSEC_Mx is such that the region density of conductor DSEC_Mx is greater than the region density of conductor SEC_Mx, and / or the number of conductors DSEC_Mx-1 is such that the region density of conductor DSEC_Mx-1 is greater than the region density of conductor SEC_Mx-1.

[0144] In the memory cell array 117 (first region 115), a top via 130 provides a connection to the storage element 120. However, as Figure 1B As shown in the multiple dashed areas 148, such vias are omitted in the virtual memory cells of the peripheral circuit 118 (second area 116). Therefore, the virtual storage element 140 is not connected to the conductor 144, thus the virtual storage element 140 cannot be used as memory (and is therefore a "virtual" memory cell).

[0145] Similarly, in the memory cell array 117 (first region 115), conductive contacts 129 provide connections to the storage element 120. However, such contacts are omitted in the virtual memory cells in the peripheral circuitry 118 (second region 116). Therefore, the virtual storage element 140 is not connected to the conductor 142, thus rendering the virtual storage element 140 unusable as memory (hence, it is a "virtual" memory cell).

[0146] In some embodiments, conductors 142 and / or 144 not connected to the virtual storage element 140 are used for routing or wiring of other elements of the semiconductor device 100, such as peripheral circuitry 118 or similar elements. In some embodiments, conductors 142 and / or 144 not connected to the virtual storage element 140 are used to provide power, ground, signal, or the like. In some embodiments, conductors 142 and / or 144 form portions of a structure other than the memory cell, such as resistors or similar elements.

[0147] although Figure 1BThe semiconductor device 100 is shown as having no vias between the virtual storage element 140 and the conductor 144 (in region 148) and no contacts between the virtual storage element 140 and the conductor 142. However, in other embodiments, such vias and / or contacts are present to connect the virtual storage element 140, and alternatively, other vias, conductors, or elements are omitted or not connected so that the virtual storage element 140 is not functional.

[0148] exist Figure 1B In the diagram, three storage elements 120 are shown in each first region 115, and two virtual storage elements 140 are shown in a second region 116. However, each first region 115 may include an appropriate number of storage elements 120, i.e., any appropriate number of memory cells, and the second region may include any appropriate number of virtual storage elements 140, i.e., any appropriate number of virtual memory cells.

[0149] Figure 2A This is a front view of a semiconductor device 200 according to one embodiment, and Figure 2B yes Figure 2A A cross-sectional view along line I-I'.

[0150] Semiconductor device 200 is similar to semiconductor device 100, except that semiconductor device 200 has a second region 216, wherein a first sub-region 216a has peripheral circuitry 118 and a plurality of virtual memory cells, and a plurality of second sub-regions 216b have peripheral circuitry 118 but no plurality of virtual memory cells. In other words, while Figures 1A to 1B The second region 116 includes peripheral circuitry 118 having virtual memory cells arranged anywhere within the second region 116. Figures 2A to 2B The second region 216 includes peripheral circuitry 118 in the first sub-region 216a and the second sub-region 216b, and also includes virtual memory cells arranged at any position in the first sub-region 216a but not in the second sub-region 216b. Therefore, the peripheral circuitry 118 has virtual memory cells that are vertically overlapped with the peripheral circuitry transistor 126 in the first sub-region 216a, but does not have virtual memory cells that are vertically overlapped with the peripheral circuitry transistor 126 in the second sub-region 216b.

[0151] exist Figures 2A to 2B In this embodiment, the virtual storage element 140 and conductor 144 in the wiring layer Mx are omitted in the second sub-region 216b. Therefore, the region density of the conductors in the wiring layer Mx in the second sub-region 216b is less than the region density of the conductors in the first region 115 and the first sub-region 216a.

[0152] The second sub-region 216b includes conductors 150 in wiring layer Mx-1 and a plurality of vias 153 in via layer Vx-2. The region density of conductors 150 in wiring layer Mx-1 is controlled to reduce or mitigate the load effect when planarizing wiring layer Mx-1. In various embodiments, the region density of conductors 150 in wiring layer Mx-1 is equal to, less than, or greater than the region density of conductors 128 in first region 115 and / or the region density of conductors 142 in first sub-region 216a.

[0153] Although the semiconductor device 200 includes conductor 150 in wiring layer Mx-1 in the second sub-region 216b but does not include conductor in wiring layer Mx, in other embodiments, wiring layer Mx in the second sub-region 216b also includes conductor. In still other embodiments, wiring layer Mx in the second sub-region 216b includes conductor, while wiring layer Mx-1 in the second sub-region 216b omits conductor 150.

[0154] In a specific example where the peripheral circuitry is the word line driver of the memory cell array 117, the word line driver circuitry (including the peripheral circuitry transistors 126 in the substrate 110 of the second region 216 and multiple interconnections in the wiring layer above the substrate 110 in the second region 216) is arranged throughout the second region 216. In the first sub-region 216a, the word line driver circuitry is vertically overlapped by virtual memory cells including virtual storage elements 140, by corresponding conductors 142 below and vertically overlapped with virtual storage elements 140 in wiring layer Mx-1, and by corresponding conductors 144 above and vertically overlapped with virtual storage elements 140 in wiring layer Mx. In the second sub-region 216b, the word line driver circuitry is not overlapped by virtual storage elements 140 or conductors 144.

[0155] The semiconductor device 200, including the second sub-region 216b, allows for additional control over the density of metal regions. The size, number, and arrangement of the second sub-region 216b relative to the size, number, and arrangement of the first region 115 and the first sub-region 216a can be controlled to provide a step arrangement in which peripheral circuitry regions of non-virtual memory cells (e.g., the second sub-region 216b) are mixed with memory cell array regions (e.g., the first region 115) and peripheral circuitry regions containing virtual memory cells (e.g., the first sub-region 216a), thereby controlling the relative region density in layers, such as wiring layers Mx and Mx-1 of the semiconductor device 200. This allows the layout to reduce or mitigate load effects.

[0156] exist Figures 2A to 2B In the diagram, a first subregion 216a lies between two second subregions 216b relative to the X-axis. (See the following text regarding...) Figures 5 to 16 In other embodiments, the multiple sub-regions are arranged in other ways.

[0157] Figure 3A This is a front view of a semiconductor device 300 according to one embodiment, and Figure 3B It is along Figure 3A A cross-sectional view of line I-I'.

[0158] Semiconductor device 300 is similar to semiconductor device 200, except that semiconductor device 300 has a second region 316, wherein two first sub-regions 316a have peripheral circuitry 118 and virtual memory cells, and the second sub-region 316b has peripheral circuitry 118 but no virtual memory cells. Figures 3A to 3B In the middle, the second sub-region 316b lies between the two first sub-regions 316a relative to the X-axis.

[0159] exist Figures 3A to 3B In the second region 316, peripheral circuitry 118 is included in the first sub-region 316a and the second sub-region 316b, and virtual memory cells are also included at any location within the first sub-region 316a but not within the second sub-region 316b. Therefore, the peripheral circuitry 118 has virtual memory cells in the first sub-region 316a that are perpendicularly overlapped with the peripheral circuitry transistor 126, but does not have virtual memory cells in the second sub-region 316b that are perpendicularly overlapped with the peripheral circuitry transistor 126.

[0160] exist Figure 3A and Figure 3B In this embodiment, the virtual storage element 140 and conductor 144 in the wiring layer Mx are omitted in the second sub-region 316b. Therefore, the region density of the conductors in the wiring layer Mx in the second sub-region 316b is less than the region density of the conductor 132 in the first region 115 and less than the region density of the conductor 144 in the first sub-region 316a. In the wiring layer Mx-1, the region density of the conductor 150 can be controlled to be the same as, greater than, or less than the region density of the conductor 128 in the first region 115 and / or the region density of the conductor 142 in the first sub-region 316a.

[0161] Semiconductor device 300 provides a stepped arrangement in which peripheral circuit regions of non-virtual memory cells (e.g., second sub-region 316b) are mixed with memory cell array regions (e.g., first region 115) and peripheral circuit regions containing virtual memory cells (e.g., first sub-region 316a), thereby controlling the relative region density in layers of semiconductor device 300 such as wiring layer Mx, wiring layer Mx-1. This allows the layout to reduce or mitigate load effects.

[0162] Figure 4This is a front view of conductors in wiring layers in various regions of a semiconductor device 400 according to one embodiment.

[0163] exist Figure 4 In this design, the array region, the peripheral circuit region containing virtual memory cells, and the peripheral circuit region without virtual cells each have different conductor patterns. The array region, denoted as first region 415, corresponds to first region 115 and includes the memory cell array 117. The peripheral circuit region containing virtual memory cells, denoted as first sub-region 416a, corresponds to first sub-regions 216a and 316a. The peripheral circuit region without virtual cells, denoted as second sub-region 416b, corresponds to second sub-regions 216b and 316b. First sub-region 416a and second sub-region 416b together include peripheral circuitry 118.

[0164] exist Figure 4 In the memory cell array 117, there is a regular array of four rows and four columns of conductors. The memory cell array 117 consists of conductors 132 in wiring layer Mx and / or conductors 128 in wiring layer Mx-1. The four rows and four columns are merely examples, and in other embodiments, any suitable number of rows and / or columns of conductors may be included. The first region 115 has a first region density of conductors 132 and conductors 128 in wiring layers Mx and Mx-1.

[0165] In the first sub-region 416a, conductors 142 and / or 144 have a pattern similar to the four-row, four-column pattern of the memory cell array 117, except that the patterns of two adjacent columns in the second row are connected together in a stripe shape, and the third row includes a pattern that is longer than the conductors 132 and 128 of the memory cell array 117 in the X-axis direction. The first sub-region 416a has a second region density of conductors 132 and 128 in wiring layers Mx and Mx-1.

[0166] In the second sub-region 416b, conductors 150 are typically row-shaped, extending parallel to the X-axis and shorter in the Y-axis direction, resulting in seven rows of conductors 150 compared to the four rows of conductors 132 and 128 in the memory cell array 117. The second sub-region 416b has a third region density of conductors 150 in the wiring layer Mx-1. The region density of conductors 150 in the wiring layer Mx-1 in the second sub-region 416b can be controlled to be equal to, greater than, or less than the region density of conductors 128 in the first region 115 and / or the region density of conductors 142 in the first sub-region 416a.

[0167] Figure 5 This is a front view of the conductor pattern in the semiconductor device 500 according to the embodiment.

[0168] The semiconductor device 500 includes a first region 515 corresponding to the first region 115 and the first region 415, and includes a memory cell array 117. Two first sub-regions 516a and a second sub-region 516b (forming a second region 516) together include peripheral circuitry 118.

[0169] The first sub-region 516a corresponds to the first sub-regions 216a, 316a, and 416a, and includes virtual memory cells. Therefore, the virtual storage element 140, the conductor 144 in the wiring layer Mx, and the conductor 142 in the wiring layer Mx-1 are vertically overlapped with the peripheral circuit transistor 126 of the peripheral circuit 118 in the first sub-region 516a.

[0170] The second sub-region 516b corresponds to the second sub-regions 216b, 316b, and 416b, and does not include virtual memory cells. In some embodiments, the second sub-region 516b includes conductors 150 in wiring layer Mx-1 and vias 153 in via layer Vx-2, but does not include virtual storage elements 140 or conductors 144 in wiring layer Mx.

[0171] exist Figure 5 In this context, six different conductor patterns (first conductor pattern a, second conductor pattern b, third conductor pattern c, fourth conductor pattern d, fifth conductor pattern e, and sixth conductor pattern f) are some examples of conductor patterns used for wiring layers in the first sub-region 516a, such as conductor 144 in wiring layer Mx and / or conductor 142 in wiring layer Mx-1. Various conductor patterns can be used for wiring or the like, in addition to existing wiring in the first sub-region 516a dedicated to peripheral circuitry 118, or in addition to existing wiring in the first sub-region 516a dedicated to peripheral circuitry 118. Therefore, the six conductor patterns (first conductor patterns a through sixth conductor patterns f) are some examples of wiring shapes that can be used for wiring device elements decoupled from memory cell array 117, thereby providing additional functionality or wiring flexibility in semiconductor device 500 relative to semiconductor devices that do not include virtual memory cells in peripheral circuitry 118.

[0172] The first conductor pattern a used for conductors 142 and / or 144 is the same as the pattern used for conductors 128 and / or 132 in the memory cells of the memory cell array 117.

[0173] The second conductor pattern b is composed of conductors 128 and / or 132 in the memory cells of the memory cell array 117, having the same XY area, but arranged at a different pitch in one direction. Figure 5In the second conductor pattern b, the pitch of conductors 142 and 144 in the Y-axis direction is greater than the pitch of conductors 128 and 132 in the memory cell array 117 in the Y-axis direction. In some embodiments, the pitch of conductors 142 and 144 in the second conductor pattern b in the X-axis direction is also greater than the pitch of conductors 128 and 132 in the X-axis direction.

[0174] The third conductor pattern c consists of conductors 142 and / or 144 having the same XY area as conductors 128 and / or 132, and arranged with random pitch in the Y-axis direction. In other embodiments, the pitch of conductors 142 and 144 in the third conductor pattern c is also random in the X-axis direction.

[0175] The fourth conductor pattern d is composed of conductors 142 and / or 144 having the same X-axis dimensions as conductors 128 and / or 132, while having extended slot-like (or strip-like) shapes relative to conductors 128 and 132 in the Y-axis direction. In some embodiments, the X-axis dimensions of conductors 142 and / or 144 are larger or smaller than the X-axis dimensions of conductors 128 and 132.

[0176] The fifth conductor pattern e consists of conductors 142 and / or 144 having the same Y-axis dimensions as conductors 128 and / or 132, while having an extended row shape (or stripe) on the Y-axis. In some embodiments, the Y-axis dimensions of conductors 142 and / or 144 are greater than or less than the Y-axis dimensions of conductors 128 and 132.

[0177] The sixth conductor pattern f can be composed of any combination of the first conductor patterns a to the fifth conductor patterns e. Various combinations of conductor patterns can be used to provide adaptive wiring layouts with wiring flexibility in the semiconductor device 500, while reducing or mitigating load effects.

[0178] Figures 6 to 17 This is a front view of the arrangement of the array region and the peripheral circuit region in semiconductor devices 600 to 1700 according to the embodiments.

[0179] Figure 6 and Figure 7 This is an example of a strip-shaped arrangement in the peripheral circuit area. Figure 6 and Figure 7 The layout examples illustrate how peripheral circuitry areas with virtual memory cells and those without virtual memory cells can be mixed to provide wiring flexibility while reducing or mitigating load effects.

[0180] exist Figure 6In the semiconductor device 600, a peripheral circuit region is located between two array regions relative to the X-axis direction. Within the peripheral circuit region, peripheral circuitry 118 is composed of two sub-regions containing virtual memory cells (corresponding to...). Figures 2A to 5 The first subregion 216a, the first subregion 316a, the first subregion 416a, and the first subregion 516a) and the three subregions in which virtual memory units have not been formed (corresponding to Figures 2A to 5 The semiconductor device 600 comprises a second sub-region 216b, a second sub-region 316b, a second sub-region 416b, and a second sub-region 516b. The sub-regions extend along the Y-axis and alternate along the X-axis. The semiconductor device 600 is mirror-symmetric with respect to an imaginary line parallel to the Y-axis and located at the center of the semiconductor device 600 relative to the X-axis. The semiconductor device 600 is also mirror-symmetric with respect to an imaginary line parallel to the X-axis and located at the center of the semiconductor device 600 relative to the Y-axis.

[0181] exist Figure 7 In the semiconductor device 700, a peripheral circuit region is located between two array regions relative to the X-axis direction. Within the peripheral circuit region, peripheral circuitry 118 comprises three sub-regions containing virtual memory cells (corresponding to…). Figures 2A to 5 The first subregion 216a, the first subregion 316a, the first subregion 416a, and the first subregion 516a) and the three subregions in which virtual memory units have not been formed (corresponding to Figures 2A to 5 The semiconductor device 700 is composed of a second sub-region 216b, a second sub-region 316b, a second sub-region 416b, and a second sub-region 516b. The sub-regions extend in the X-axis direction and alternate in the Y-axis direction. The semiconductor device 700 is mirror symmetrical with respect to an imaginary line parallel to the Y-axis and located at the center of the semiconductor device 700 with respect to the X-axis.

[0182] Figure 8 and Figure 9 This is an example of a square layout in the surrounding circuit area. Figure 8 and Figure 9 The layout examples illustrate how peripheral circuitry areas with virtual memory cells and those without virtual memory cells can be mixed to provide wiring flexibility while reducing or mitigating load effects.

[0183] exist Figure 8 In the semiconductor device 800, a peripheral circuit region is located between two array regions relative to the X-axis direction. Within the peripheral circuit region, peripheral circuitry 118 is composed of twelve sub-regions containing virtual memory units (corresponding to…). Figures 2A to 5 The first subregion 216a, the first subregion 316a, the first subregion 416a, the first subregion 516a) and the thirteen subregions in which virtual memory units have not been formed (corresponding to Figures 2A to 5The device comprises second sub-regions 216b, 316b, 416b, and 516b. Each sub-region is longer in the Y-axis direction than in the X-axis direction. The sub-regions are arranged in a 5x5 pattern and alternate between the X and Y axes. The semiconductor device 800 is mirror-symmetric with respect to an imaginary line parallel to the Y-axis and located at the center of the semiconductor device 800 relative to the X-axis. The semiconductor device 800 is also mirror-symmetric with respect to an imaginary line parallel to the X-axis and located at the center of the semiconductor device 800 relative to the Y-axis.

[0184] exist Figure 9 In the semiconductor device 900, a peripheral circuit region is located between two array regions relative to the X-axis direction. Within the peripheral circuit region, peripheral circuitry 118 is formed by virtual memory cells distributed therein (corresponding to...). Figures 2A to 5 The seven subregions containing virtual memory units in the subregions of the second subregion 216b, the second subregion 316b, the second subregion 416b, and the second subregion 516b (corresponding to) Figures 2A to 5 The device comprises first subregions 216a, 316a, 416a, and 516a. The subregions containing virtual memory units are longer in the Y-axis direction than in the X-axis direction, and are arranged in alternating rows (in the X-axis direction) with one or two subregions containing virtual memory units. The semiconductor device 900 is mirror-symmetrical with respect to an imaginary line parallel to the X-axis and located at the center of the semiconductor device 900 relative to the Y-axis.

[0185] The above about Figure 8 and Figure 9 The described arrangement examples illustrate how peripheral circuit regions containing virtual memory units and those without virtual memory units can be arranged into square patterns. Figure 8 In the first row, there are five peripheral circuit regions: two pairs of peripheral circuit regions with virtual memory units and peripheral circuit regions without virtual memory units, each pair arranged in a square pattern, and a single peripheral circuit region without virtual memory units. Figure 8 The second row in the image flips the pattern of the first row. Figure 9 In, relative to Figure 8 In the second and third lines, the peripheral circuits containing virtual memory units are changed to peripheral circuit regions without virtual memory units.

[0186] Figure 10 and Figure 11 It is an example of a chessboard or chessboard-shaped layout in the surrounding circuit area. Figure 10 and Figure 11The example layout illustrates how peripheral circuitry areas containing virtual memory cells and those without virtual memory cells can be mixed to provide wiring flexibility while reducing or mitigating load effects.

[0187] exist Figure 10 In the semiconductor device 1000, a peripheral circuit region is included between two array regions relative to the X-axis direction. Within the peripheral circuit region, peripheral circuitry 118 is composed of ten sub-regions containing virtual memory units (corresponding to...). Figures 2A to 5 The first subregion 216a, the first subregion 316a, the first subregion 416a, and the first subregion 516a) and the ten subregions within which virtual memory units have not yet been formed (corresponding to Figures 2A to 5 The semiconductor device 1000 consists of two sub-regions: 216b, 316b, 416b, and 516b. Each sub-region is longer along the Y-axis than along the X-axis. The sub-regions are arranged in a 5x4 pattern (five rows (in the X-axis direction) and four columns (in the Y-axis direction), alternating between the X and Y axes. The semiconductor device 1000 is mirror-symmetric with respect to an imaginary line parallel to the Y-axis and located at the center of the semiconductor device 1000 relative to the X-axis. The semiconductor device 1000 is arranged in a chessboard-like or checkerboard-like layout.

[0188] exist Figure 11 In the semiconductor device 1100, a peripheral circuit region is located between two array regions relative to the X-axis direction. Within the peripheral circuit region, the peripheral circuitry 118 comprises sixteen sub-regions containing virtual memory cells (corresponding to…). Figures 2A to 5 The first subregion 216a, the first subregion 316a, the first subregion 416a, and the first subregion 516a) and the sixteen subregions within which virtual memory units have not yet been formed (corresponding to Figures 2A to 5 The device comprises two sub-regions: 216b, 316b, 416b, and 516b. Each sub-region is longer along the Y-axis than along the X-axis. The sub-regions are arranged in an 8x4 pattern (eight rows (in the X-axis direction) and four columns (in the Y-axis direction), alternating between the X and Y axes. The semiconductor device 1100 is arranged in a chessboard-like or checkerboard-like layout.

[0189] The above about Figure 10 and Figure 11 The described arrangement examples illustrate how peripheral circuit regions containing virtual memory cells and peripheral circuit regions without virtual memory cells are arranged in a checkerboard or checkerboard-shaped pattern. Figure 11 In, relative to Figure 10 Each peripheral circuit region is further subdivided into peripheral circuit regions containing virtual memory units and peripheral circuit regions without virtual memory units.

[0190] Figure 12 and Figure 13 This is an example of a surrounding circuit layout. Figure 12 and Figure 13 The example layout illustrates how peripheral circuitry areas containing virtual memory cells and those without virtual memory cells can be mixed to provide wiring flexibility while reducing or mitigating load effects.

[0191] exist Figure 12 In the semiconductor device 1200, a peripheral circuit region is included between two array regions relative to the X-axis direction. Within the peripheral circuit region, peripheral circuitry 118 is formed by a sub-region surrounding a virtual memory cell (corresponding to...) Figures 2A to 5 The subregions containing virtual memory units (corresponding to the second subregions 216b, 316b, 416b, and 516b) Figures 2A to 5 The system comprises three subregions: 216a, 316a, 416a, and 516a. Each subregion containing virtual memory units is surrounded by another subregion in which virtual memory units are not formed. Therefore, the three subregions are arranged in a surrounding configuration, where the subregion containing virtual memory units surrounds a subregion in which virtual memory units are not formed, and the subregion containing virtual memory units is simultaneously surrounded by another subregion in which virtual memory units are not formed. The subregions are longer in the Y-axis direction than in the X-axis direction.

[0192] exist Figure 13 In the semiconductor device 1300, a peripheral circuit region is included between two array regions relative to the X-axis direction. Within the peripheral circuit region, peripheral circuitry 118 is formed by continuous sub-regions spaced apart in the Y-axis direction and in which virtual memory cells are not formed (corresponding to...). Figures 2A to 5 The three subregions containing virtual memory units (corresponding to the second subregion 216b, the second subregion 316b, the second subregion 416b, and the second subregion 516b) are surrounded by the second subregion 216b, the second subregion 316b, the second subregion 416b, and the second subregion 516b. Figures 2A to 5 The semiconductor device 1300 is composed of first sub-regions 216a, 316a, 416a, and 516a. The semiconductor device 1300 is mirror-symmetric with respect to an imaginary line parallel to the Y-axis and located at the center of the semiconductor device 1300 relative to the X-axis. The semiconductor device 1300 is also mirror-symmetric with respect to an imaginary line parallel to the X-axis and located at the center of the semiconductor device 1300 relative to the Y-axis.

[0193] Figure 14 and Figure 15 This is an example of a symmetrical arrangement in the surrounding circuit area. Figure 14 and Figure 15Examples of layouts illustrate how peripheral circuitry areas containing virtual memory cells and those without virtual memory cells can be mixed to provide wiring flexibility while reducing or mitigating load effects.

[0194] exist Figure 14 In the semiconductor device 1400, a peripheral circuit region is located between two array regions relative to the X-axis direction. Within the peripheral circuit region, peripheral circuitry 118 is composed of three sub-regions containing virtual memory cells (corresponding to…). Figures 2A to 5 The first subregion 216a, the first subregion 316a, the first subregion 416a, and the first subregion 516a) and the three subregions in which virtual memory units have not been formed (corresponding to Figures 2A to 5 The semiconductor device 1400 is composed of a second sub-region 216b, a second sub-region 316b, a second sub-region 416b, and a second sub-region 516b. The semiconductor device 1400 is mirror symmetrical with respect to an imaginary line parallel to the X-axis and located at the center of the semiconductor device 1400 with respect to the Y-axis.

[0195] exist Figure 15 In the semiconductor device 1500, a peripheral circuit region is located between two array regions relative to the X-axis direction. Within the peripheral circuit region, peripheral circuitry 118 is comprised of four sub-regions containing virtual memory cells (corresponding to…). Figures 2A to 5 The first subregion 216a, the first subregion 316a, the first subregion 416a, and the first subregion 516a) and the four subregions in which virtual memory units have not been formed (corresponding to Figures 2A to 5 It consists of a second sub-region 216b, a second sub-region 316b, a second sub-region 416b, and a second sub-region 516b. Compared to semiconductor device 1400, semiconductor device 1500 has antisymmetry with respect to an imaginary line parallel to the X-axis and located at the center of semiconductor device 1500 with respect to the Y-axis.

[0196] Figure 16 and Figure 17 This is an example of an asymmetrical layout in the surrounding circuit area. Figure 16 and Figure 17 Examples of layouts illustrate how peripheral circuitry areas containing virtual memory cells and those without virtual memory cells can be mixed to provide wiring flexibility while reducing or mitigating load effects.

[0197] exist Figure 16 In the semiconductor device 1600, a peripheral circuit region is located between two array regions relative to the X-axis direction. Within the peripheral circuit region, peripheral circuitry 118 is comprised of four sub-regions containing virtual memory cells (corresponding to…). Figures 2A to 5The first subregion 216a, the first subregion 316a, the first subregion 416a, the first subregion 516a) and a subregion in which virtual memory units have not been formed (corresponding to Figures 2A to 5 It consists of the second subregion 216b, the second subregion 316b, the second subregion 416b, and the second subregion 516b. The subregions are arranged asymmetrically.

[0198] exist Figure 17 In the semiconductor device 1700, a peripheral circuit region is included between two array regions relative to the X-axis direction. Within the peripheral circuit region, peripheral circuitry 118 is composed of two sub-regions containing virtual memory cells (corresponding to...). Figures 2A to 5 The first subregion 216a, the first subregion 316a, the first subregion 416a, and the first subregion 516a) and the two subregions in which virtual memory units have not been formed (corresponding to Figures 2A to 5 It consists of the second subregion 216b, the second subregion 316b, the second subregion 416b, and the second subregion 516b. The subregions are arranged asymmetrically.

[0199] exist Figures 6 to 17 In this embodiment, peripheral circuitry 118 is positioned between two memory cell arrays 117 relative to the X-axis direction. In other embodiments, the number of memory cell arrays 117 in the semiconductor device is less than two or more than two. In various embodiments, the memory cell arrays 117 are defined on one, two, three, or four sides by one or more peripheral circuits 118. In some embodiments, peripheral circuitry 118 is defined on one, two, three, or four sides by one or more memory cell arrays 117.

[0200] The above is about Figures 1A to 17 As described, the memory cell array 117 is formed in a first region such as first region 115, first region 415, and first region 515, and the peripheral circuitry 118 is formed in a second region such as second region 116, second region 216, second region 316, second region 416, and second region 516. In some embodiments, the second region includes a first sub-region such as first sub-region 216a, first sub-region 316a, first sub-region 416a, and first sub-region 516a, wherein virtual memory cells are formed together with the peripheral circuitry, and the second region includes a second sub-region such as second sub-region 216b, second sub-region 316b, second sub-region 416b, and second sub-region 516b, wherein no virtual memory cells are formed. The area ratio of the first sub-region to the second sub-region is selected to adjust the layout of the semiconductor device. The area ratio is selected to change or adjust the relative areas of the sub-regions of the peripheral circuitry 118. The area ratio can be from 100:0 to 0:100.

[0201] For example, in semiconductor device 200, the area of ​​the first sub-region 216a (in the front view, i.e., in the XY plane) is approximately equal to the area of ​​the second sub-region 216b (i.e., the combined or total area of ​​the second sub-regions), meaning the area ratio of the first sub-region 216a to the second sub-region 216b is approximately 50:50. In other embodiments, the area ratio can be increased to 100:0, such that the peripheral circuitry 118 completely contains the virtual memory cells, or decreased to 0:100, such that the peripheral circuitry 118 has no virtual memory cells at all. In the former, the characteristics of the conductor layer are also similar to those of an array, i.e., the planarization characteristics of the second region are also similar to those of the memory cell array 117. In the latter, the characteristics of the conductor layer are also similar to those of logic, i.e., the planarization characteristics of the second region are also similar to those of a logic circuit region.

[0202] Generally, the former tends to simplify or improve planarization, for example, by producing a more uniform CMP, while the latter tends to simplify or improve wiring by allowing greater flexibility in the layout of conductors in the wiring layer. Therefore, the semiconductor device according to the embodiment achieves a flexible design approach by allowing adjustment of the area ratio of the peripheral circuit region containing virtual memory cells to the peripheral circuit region containing non-virtual memory cells.

[0203] Furthermore, the relative number, size, shape, and arrangement of the first and second sub-regions (e.g., ...) Figure 6 and Figure 17 (As shown in the examples) can be freely and extensively varied in order to provide the expected adjustments or balances of flattening characteristics relative to layout or wiring flexibility (to reduce or mitigate load effects).

[0204] Figure 18 This is a front view of a semiconductor device 1800 according to one embodiment.

[0205] Semiconductor device 1800 includes eight array regions, each comprising a plurality of memory cell arrays (first memory cell array 117a to eighth memory cell array 117h) arranged in a 4x2 configuration and surrounded by peripheral circuitry 118. Peripheral circuitry 118 includes word line drivers (WLDRV), local input / output (LIO) circuitry, main I / O (MIO) circuitry, global I / O (GIO) circuitry, local control (LCTRL) circuitry, global control (GCTRL) circuitry, and main control (MCTRL) circuitry.

[0206] Any one or more of the peripheral circuits 118 of the semiconductor device 1800 can be configured as follows Figures 1A to 17 Peripheral circuitry 118. Any one or more peripheral circuits 118 of the semiconductor device 1800 may also include a first sub-region, the first sub-region including virtual memory cells (corresponding to...). Figures 2A to 5 The first subregion 216a, the first subregion 316a, the first subregion 416a, the first subregion 516a) and the second subregion (corresponding to) in which no virtual memory units are formed Figures 2A to 5 The second sub-regions 216b, 316b, 416b, and 516b). The first and second sub-regions of the peripheral circuit 118 can be as follows: Figures 2A to 17 The arrangement is shown.

[0207] In the semiconductor device 1800, the first memory cell array 117a is surrounded by a corner region 1802, a first edge region 1804, an LIO edge region 1806, an LIO circuit region 1822, an LCTRL circuit region 1834, a WLDRV circuit region 1832, a WLDRV edge region 1830, and a second edge region 1820.

[0208] The second memory cell array 117b is surrounded by the LIO edge region 1806, the first edge region 1808, the MCTRL circuit region 1810, the MIO circuit region 1824, the MCTRL circuit region 1838, the WLDRV circuit region 1836, the LCTRL circuit region 1834, and the LIO circuit region 1822. The second memory cell array 117b is aligned with the first memory cell array 117a along the X-axis.

[0209] The third memory cell array 117c is surrounded by MCTRL circuit region 1810, first edge region 1812, LCTRL edge region 1814, LIO circuit region 1826, LCTRL circuit region 1842, WLDRV circuit region 1840, MCTRL circuit region 1838, and MIO circuit region 1824. The third memory cell array 117c is aligned with the first memory cell array 117a along the X-axis direction.

[0210] The fourth memory cell array 117d is surrounded by the LCTRL edge region 1814, the first edge region 1816, the GIO edge region 1818, the GIO circuit region 1828, the GCTRL circuit region 1846, the WLDRV circuit region 1844, the LCTRL circuit region 1842, and the LIO circuit region 1826. The fourth memory cell array 117d is aligned with the first memory cell array 117a along the X-axis.

[0211] The fifth memory cell array 117e is surrounded by the WLDRV edge region 1830, the WLDRV circuit region 1832, the LCTRL circuit region 1834, the LIO circuit region 1850, the LIO edge region 1864, the third edge region 1862, the corner region 1860, and the second edge region 1848. The fifth memory cell array 117e is aligned with the first memory cell array 117a along the Y-axis.

[0212] The sixth memory cell array 117f is surrounded by LCTRL circuit region 1834, WLDRV circuit region 1836, MCTRL circuit region 1838, MIO circuit region 1852, MCTRL circuit region 1870, third edge region 1868, LIO edge region 1864, and LIO circuit region 1850. The sixth memory cell array 117f is aligned with the second memory cell array 117b along the Y-axis and with the fifth memory cell array 117e along the X-axis.

[0213] The seventh memory cell array 117g is surrounded by MCTRL circuit region 1838, WLDRV circuit region 1840, LCTRL circuit region 1842, LIO circuit region 1856, LCTRL edge region 1874, third edge region 1872, MCTRL circuit region 1870, and MIO circuit region 1852. The seventh memory cell array 117g is aligned with the third memory cell array 117c along the Y-axis and with the fifth memory cell array 117e along the X-axis.

[0214] The eighth memory cell array 117h is surrounded by LCTRL circuit region 1842, WLDRV circuit region 1844, GCTRL circuit region 1846, GIO circuit region 1858, GIO edge region 1878, third edge region 1876, LCTRL edge region 1874, and LIO circuit region 1856. The eighth memory cell array 117h is aligned with the fourth memory cell array 117d along the Y-axis and with the fifth memory cell array 117e along the X-axis.

[0215] In some implementations, virtual memory cells in the BEOL layer containing virtual memory cell regions are used to implement one or more peripheral circuit regions surrounding each memory cell array (first memory cell array 117a to eighth memory cell array 117h) to help adjust or balance CMP loads in the array and surrounding peripheral circuits and / or to provide wiring flexibility using conductors associated with the virtual memory cells (e.g., virtual memory cell conductors in wiring layer Mx, wiring layer Mx-1).

[0216] Figure 19A These are cross-sectional schematic diagrams of resistor structures 1900A and 1900B according to some embodiments.

[0217] As mentioned above Figure 1B , Figure 2B and Figure 3B The semiconductor device described, according to some embodiments, includes a peripheral circuit region in which virtual memory cells are formed, the virtual memory cells including virtual storage elements 140 and conductors 142 and 144. In some embodiments, the virtual storage element 140 forms a portion of a resistor structure in a BEOL layer.

[0218] For example, in resistor structure 1900A, resistor element 1960 corresponds to virtual storage element 140, and conductor 1944 corresponds to... Figure 1B , Figure 2B and Figure 3B Conductor 144, and conductor 1942 corresponding to Figure 1B , Figure 2B and Figure 3B Conductor 142. Resistor element 1960 is disposed between conductor 1942 and conductor 1944. One or more through holes 1961 (or contacts) connect resistor element 1960 to conductor 1942. One or more through holes 1963 (or contacts) connect resistor element 1960 to conductor 1944. Additional wiring ( Figure 19A (Not shown) Connect conductors 142 and 144 to other circuit elements in the semiconductor device.

[0219] Resistor element 1960 is formed of a resistive material having a conductivity lower than that of conductors 1942 and 1944. Examples of materials used for resistor element 1960 include resistive materials compatible with BEOL processes. In some embodiments, the storage elements 120 of memory cell array 117 include resistive material, and the same resistive material is also used to form resistor element 1960.

[0220] In a specific example, resistor element 1960 is an MTJ structure as described above with respect to storage element 120. In some embodiments, a reference layer and a free layer of the MTJ structure are formed to provide an MTJ structure, i.e., resistor element 1960 having a given resistivity such as per unit length, thickness, area, or the like. Resistor element 1960 has a resistance at least in part determined by the total length, thickness, area, or the like of resistor element 1960. In some embodiments, resistor element 1960 is manufactured to have a fixed and / or predetermined resistance.

[0221] In some embodiments, the total resistance of resistor structure 1900A is determined by a combination of factors including the resistivity of resistor element 1960, the size of resistor element 1960, and the number and location of vias 1961 and 1963. Increasing the via ratio (e.g., increasing the number of vias for connection to the top and bottom sides of resistor element 1960) reduces the total resistance by enhancing conductivity. Reducing the top-to-bottom via spacing reduces the total resistance by shortening the path through resistor element 1960.

[0222] For example, Figure 19A The total resistance of resistor structure 1900A is partly dependent on the presence of three vias 1961 and three vias 1963. In contrast, resistor structure 1900B has only two vias 1961 and two vias 1963, and the distance between vias 1961 and 1963 in resistor structure 1900B is greater than the distance between vias 1961 and 1963 in resistor structure 1900A. Therefore, assuming the same resistor element 1960 is used in each of resistor structures 1900A and 1900B, the relatively larger number and closer spacing of vias 1961 and 1963 in resistor structure 1900A results in a lower total resistance for resistor structure 1900A compared to resistor structure 1900B.

[0223] Therefore, the semiconductor device according to the embodiment can be configured to have resistor structures 1900A and 1900B, which have a total resistance. This total resistance can be set or adjusted not only by the resistance of resistor element 1960 but also by the layout of conductors in various wiring layers, such as conductor 1944 in wiring layer Mx, conductor 1942 in wiring layer Mx-1, and vias. Furthermore, conductors 1942 and 1944 serve a dual purpose: to mitigate the load effect by adjusting the regional density of conductors in peripheral circuit 118 relative to conductors in memory cell array 117, and to allow the resistor structure to be integrated into the BEOL layer.

[0224] Figure 19B These are cross-sectional schematic diagrams of resistor structures 1900C and 1900D according to some embodiments.

[0225] Resistor structure 1900C includes a first MTJ resistor element 1960A, and resistor structure 1900D includes a second MTJ resistor element 1960B. The reference layer and free layer in the first MTJ resistor element 1960A have a first parallel magnetic moment, and the reference layer and free layer in the second MTJ resistor element 1960B have a second parallel magnetic moment weaker than the first parallel magnetic moment. The stronger parallel magnetic moment of the first MTJ resistor element 1960A results in a reduction in resistance in the first MTJ resistor element 1960A relative to the second MTJ resistor element 1960B. Therefore, the semiconductor device according to the embodiment can be configured to have resistor structures 1900C and 1900D, the resistor structures 1900C and 1900D having a total resistance depending on the relative magnetic moments of the reference layer and the free layer. In some embodiments, an MTJ resistor structure including an MTJ resistor element having a first parallel magnetic moment has a lower resistance than an MTJ resistor structure including an MTJ resistor element having a relatively weak second parallel magnetic moment. In some embodiments, an MTJ resistor structure including a through-hole of a first size connecting a conductor to an MTJ resistor element has a lower resistance than an MTJ resistor structure including a through-hole of a relatively small second size. In some embodiments, an MTJ resistor structure including a first number of through-holes connecting a conductor to an MTJ resistor element has a lower resistance than an MTJ resistor structure including a second number of through-holes. In some embodiments, an MTJ resistor structure including through-holes on opposite sides of an MTJ resistor element and spaced apart by a first lateral distance has a lower resistance than an MTJ resistor structure including through-holes spaced apart by a relatively large second lateral distance.

[0226] Figure 20 This is a flowchart of a method 2000 for generating a layout according to some implementations and using this layout to manufacture a semiconductor device.

[0227] Method 2000, for example, uses an electronic design automation (EDA) system (see below for more information). Figure 24 The EDA system 2400 discussed here and semiconductor device manufacturing systems (see below for more information) Figure 25 The IC manufacturing system 2500 discussed is used for implementation. Examples of semiconductor devices manufactured according to method 2000 include the semiconductor devices disclosed herein. Figure 20 In this method 2000, operations 2002 to 2004 are included.

[0228] In operation 2002, a layout is generated. In some embodiments, operation 2002 for generating the layout includes selecting standard cells from a standard cell library, which includes one or more standard cells representing memory elements and one or more standard cells representing peripheral circuit elements having a virtual memory structure. The process proceeds from operation 2002 to operation 2004.

[0229] In operation 2004, based on the layout, at least one of the following is performed: (A) performing one or more photolithography exposures, or (B) fabricating one or more semiconductor photomasks, or (C) fabricating one or more elements in a layer of a semiconductor device.

[0230] Figure 21 This is a flowchart of a layout generation method 2100 according to one embodiment. More specifically, Figure 21 The flowchart shows the demonstration that can be performed in [location]. Figure 20 An additional operation of an instance of the process implemented in Operation 2002. Figure 21 In this context, operation 2002 includes operations 2102 to 2104.

[0231] In operation 2102, this method includes arranging a first unit and a second unit in a layout. The first unit represents a memory element. The second unit represents a peripheral circuit element with a virtual memory structure.

[0232] In operation 2104, this method includes generating wiring connections to the first and second cells. The wiring connections include wiring in a wiring layer above the peripheral circuitry and having non-connected virtual storage elements therein.

[0233] Figure 22 This is a flowchart of a method 2200 for manufacturing one or more elements of a semiconductor device according to one embodiment. More specifically, Figure 22 The flowchart shows the demonstration that can be performed in [location]. Figure 20 An additional operation to an instance of the process implemented in Operation 2004. Figure 22 In this context, Operation 2004 includes Operations 2202 to 2206.

[0234] In operation 2202, components for a peripheral circuit are formed in the active layer of the substrate. This peripheral circuit corresponds to the peripheral circuit 118 discussed above. Examples of peripheral circuits formed in operation 2202 include WLDRV circuits, LIO circuits, MIO circuits, GIO circuits, LCTRL circuits, GCTRL circuits, and MCTRL circuits.

[0235] In operation 2204, a memory structure is formed in a wiring layer in a first region of the substrate. Forming the memory structure includes forming storage elements in the wiring layer. The memory structure corresponds to the memory cells of the memory cell array 117. Examples of memory structures include MIM capacitor structures, RRAM structures, MRAM structures, PCM structures, and other BEOL-compatible storage structures.

[0236] In operation 2206, a virtual memory structure is formed in a wiring layer in a second region of the substrate. The virtual memory structure is formed to vertically overlap with the elements forming peripheral circuitry in operation 2202. The virtual memory structure corresponds to MIM capacitor structures, RRAM structures, MRAM structures, PCM structures, and other BEOL-compatible storage structures. In some embodiments, the virtual memory structure is not connected to one or more vertically overlapping conductors in the wiring layer.

[0237] The described methods include example operations, but they do not necessarily need to be performed in the order shown. Operations may be added, substituted, rearranged, and / or eliminated as appropriate, depending on the spirit and scope of the embodiments described herein. Embodiments combining different features and / or different implementations are within the scope of this disclosure and will be apparent to those skilled in the art upon reading this disclosure.

[0238] In some embodiments, at least one of the methods discussed above is performed wholly or partially by at least one EDA system. In some embodiments, the EDA system may be used as part of a design company for the semiconductor device manufacturing system discussed below.

[0239] Figure 23 This is a block diagram of a semiconductor device 2300 according to one embodiment. Semiconductor device 2300 corresponds to, for example, any one of semiconductor devices 100 to 1800 described above. In some embodiments, the semiconductor device includes one or more of the resistor structures 1900A to 1900D described above.

[0240] exist Figure 23In this embodiment, semiconductor device 2300 includes a macro 2302. In some embodiments, macro 2302 includes one or more memories, power grids, one or more cells, inverters, latches, buffers, peripheral circuitry or components thereof, and / or any other type of circuit arrangement that can be digitally represented in a cell library. In some embodiments, macro 2302 is understood in the context of an architectural hierarchy in modular programming where subprograms / programs are called by a main program (or other subprograms) to perform a given computational function. In this context, semiconductor device 2300 uses macro 2302 to perform one or more given functions. Therefore, in this context and in terms of architectural hierarchy, semiconductor device 2300 is analogous to a main program and macro 2302 is analogous to a subprogram / program. In some embodiments, macro 2302 is a software macro. In some embodiments, macro 2302 is a hardware macro. In some implementations, macro 2302 is a software macro described digitally using register-transferlevel (RTL) codes. In some implementations, macro 2302 has not been composited, positioned, and routed, allowing the software macro to be composited, positioned, and routed for various process nodes. In some implementations, macro 2302 is a hardware macro described digitally using a binary file format (e.g., Graphic Database System II (GDSII) streaming format), wherein the binary file format represents planar geometry, text labels, other information, and similar information about one or more layouts of macro 2302 in a hierarchical manner. In some implementations, macro 2302 has been composited, positioned, and routed, making the hardware macro dedicated to a specific process node.

[0241] exist Figure 23 In the middle, macro 2302 includes region 2304, region 2304 includes a memory structure in a wiring layer in a first region of the substrate, the memory structure including storage elements in the wiring layer, peripheral circuitry in a second region of the substrate, and a virtual memory structure in the wiring layer in the second region and perpendicularly overlapping with the peripheral circuitry.

[0242] In some embodiments, region 2304 corresponds to a circuit formed on a substrate during front-end line (FEOL) manufacturing. In region 2304 above the substrate, various metal layers are stacked with inserted insulating layers during back-end line (BEOL) manufacturing. The BEOL layer provides power networks and / or wiring, and other similar features, for the circuitry of the semiconductor device 2300, which includes macrogroup 2302 and region 2304.

[0243] Figure 24 This is a block diagram of an EDA system 2400 according to some implementation methods.

[0244] In some implementations, the EDA system 2400 includes an automatic placement and routing (APR) system. According to one or more implementations, the design layouts described herein represent conductor layout arrangements that are feasible, for example, using the EDA system 2400 in some implementations.

[0245] In some embodiments, the EDA system 2400 includes a processor 2402 of hardware and a general-purpose computing device with a non-transitory computer-readable storage medium 2404. The computer-readable storage medium 2404 is encoded with (i.e., stored) computer program code 2406 (i.e., an executable instruction set) and other elements. The processor 2402 executes the computer program code 2406 to represent (at least partially) an EDA tool that implements some or all of the methods (hereinafter, the proposed processes and / or methods) described herein according to one or more embodiments.

[0246] Processor 2402 is electrically coupled to computer-readable storage medium 2404 via bus 2408. Processor 2402 is also electrically coupled to I / O interface 2410 via bus 2408. Network interface 2412 is also electrically coupled to processor 2402 via bus 2408. Network interface 2412 is connected to network 2414, enabling processor 2402 and computer-readable storage medium 2404 to be connected to multiple external components via network 2414. Processor 2402 is configured to execute computer program code 2406 encoded in computer-readable storage medium 2404 to enable EDA system 2400 to perform part or all of the proposed process and / or method. In one or more embodiments, processor 2402 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0247] In one or more embodiments, the computer-readable storage medium 2404 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). Examples of the computer-readable storage medium 2404 include semiconductor or solid-state memory, magnetic tape, removable computer floppy disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 2404 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disk.

[0248] In one or more embodiments, computer-readable storage medium 2404 stores computer program code 2406, which is configured to enable EDA system 2400 (where such execution represents (at least partially) EDA tools) to perform part or all of the proposed process and / or method. In one or more embodiments, computer-readable storage medium 2404 also stores information facilitating the performance of part or all of the mentioned process and / or method. In one or more embodiments, computer-readable storage medium 2404 stores a standard cell library 2407 comprising such standard cells disclosed herein.

[0249] EDA system 2400 includes I / O interface 2410. I / O interface 2410 is coupled to external circuitry. In one or more embodiments, I / O interface 2410 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor keys for transmitting information and commands to processor 2402.

[0250] EDA system 2400 also includes a network interface 2412 coupled to processor 2402. Network interface 2412 allows EDA system 2400 to communicate with network 2414, which is connected to one or more other computer systems. Network interface 2412 includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, and WCDMA, or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more EDA systems 2400.

[0251] EDA system 2400 is configured to receive information via I / O interface 2410. The information received via I / O interface 2410 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters processed by processor 2402. This information is transmitted to processor 2402 via bus 2408. EDA system 2400 is also configured to receive information related to the user interface (UI) via I / O interface 2410. This information is stored as user interface 2442 in computer-readable storage medium 2404.

[0252] In some embodiments, some or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application used by the EDA system 2400. In some embodiments, methods such as those available from Cadence Design Systems, Inc. are used. Use tools or other suitable layout generation tools to generate layouts that include standard cells.

[0253] In some implementations, the process is achieved by using the functionality of a non-transitory computer-readable program stored in the recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memory (e.g., ROM, RAM), memory cards, and one or more similar units.

[0254] Figure 25 This is a block diagram of an IC manufacturing system 2500 and a semiconductor device manufacturing process associated therewith, according to some embodiments. In some embodiments, based on layout, the IC manufacturing system 2500 is used to manufacture at least one of the following: (A) one or more semiconductor photomasks or (B) at least one element in a layer of a semiconductor integrated circuit.

[0255] exist Figure 25In this IC manufacturing system 2500, entities such as design company 2520, mask producer 2530, and IC wafer fab 2550 (IC manufacturer / manufacturing plant) interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC device 2560. The entities of IC manufacturing system 2500 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as intranets and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design company 2520, mask producer 2530, and IC wafer fab 2550 are owned by a single larger company. In some embodiments, two or more of design company 2520, mask producer 2530, and IC wafer fab 2550 coexist in a common facility and use common resources.

[0256] Design company 2520 (or design team) generates IC design layout 2522. IC design layout 2522 includes various geometric patterns designed for IC device 2560. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components for manufacturing IC device 2560. Various layers are combined to form various IC features. For example, a portion of IC design layout 2522 includes forming various IC features such as active regions, gates, sources, and drains, metal lines or vias for interlayer interconnects, and multiple openings for multiple bonding pads in a semiconductor substrate (such as a silicon substrate), and setting various material layers on the semiconductor substrate. Design company 2520 implements a formal design flow to form IC design layout 2522. The design flow includes one or more logic design, physical design, or placement and routing operations. IC design layout 2522 is presented in one or more data files containing geometric pattern information. For example, IC design layout 2522 can be expressed in GDSII file format or DFII file format.

[0257] Mask producer 2530 includes mask data preparation 2532 and mask fabrication 2544. Mask producer 2530 uses IC design layout 2522 to fabricate one or more masks 2545, according to the various layers used to fabricate IC device 2560 based on IC design layout 2522. Mask producer 2530 performs mask data preparation 2532, in which IC design layout 2522 is converted into a representative data file (RDF). Mask data preparation 2532 provides the RDF to mask fabrication 2544. Mask fabrication 2544 includes mask writing. Mask writing converts the RDF into an image on a substrate, such as mask 2545 (photomask) or semiconductor wafer 2553. IC design layout 2522 is operated by mask data preparation 2532 to conform to the specific characteristics of mask writing and / or the requirements of IC wafer fab 2550. Figure 25 In this diagram, mask data preparation 2532 and mask manufacturing 2544 are shown as separate elements. In some embodiments, mask data preparation 2532 and mask manufacturing 2544 may be collectively referred to as mask data preparation.

[0258] In some embodiments, mask data preparation 2532 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other process effects. OPC adjusts the IC design layout 2522. In some embodiments, mask data preparation 2532 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shifting masks, other suitable techniques, and similar techniques or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0259] In some implementations, mask data preparation 2532 includes a mask rule checker (MRC) that uses a set of mask creation rules, including geometric and / or connectivity constraints, to check the IC design layout 2522, which has already undergone processes in the OPC, to ensure sufficient margin to account for variability in semiconductor manufacturing processes and similar situations. In some implementations, the MRC modifies the IC design layout 2522 to compensate for constraints during mask fabrication 2544, which can offset some modifications performed by the OPC to meet the mask creation rules.

[0260] In some implementations, mask data preparation 2532 includes lithography process checking (LPC), a simulation of the process to be implemented by IC wafer fab 2550 to manufacture IC device 2560. LPC simulates this process based on IC design layout 2522 to establish a simulated manufacturing apparatus, such as IC device 2560. Process parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar factors or combinations thereof. In some implementations, after establishing the simulated manufacturing apparatus via LPC, if the simulated apparatus is not close enough in shape to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 2522.

[0261] It should be understood that the above description of mask data preparation 2532 has been simplified for clarity. In some embodiments, mask data preparation 2532 includes additional features such as logic operations (LOPs) to modify the IC design layout 2522 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 2522 during mask data preparation 2532 can be performed in various different sequences.

[0262] After mask data preparation 2532 and during mask fabrication 2544, a mask 2545 or a set of masks 2545 is fabricated based on a modified IC design layout 2522. In some embodiments, mask fabrication 2544 includes performing one or more lithography exposures based on the IC design layout 2522. In some embodiments, the mechanism of the electron beam or multiple electron beams is based on the modified IC design layout 2522 to form a pattern on the mask 2545 (photomask or photomask). The mask 2545 can be formed in various techniques. In some embodiments, the mask 2545 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque areas and passes through the transparent areas. In one example, a binary mask version of the mask 2545 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, mask 2545 is formed using a phase-shifting technique. In the phase-shift mask (PSM) version of mask 2545, various features in the pattern formed on the phase-shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shift mask can be an attenuating PSM or an alternating PSM. The mask generated by mask fabrication 2544 is used in a variety of processes. For example, such a mask is used in ion implantation processes to form various doped regions in semiconductor wafer 2553, in etching processes to form various etched regions in semiconductor wafer 2553, and / or for other suitable processes.

[0263] IC wafer fab 2550 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC wafer fab 2550 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (front-end line (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (back-end line (BEOL) manufacturing) for interconnects and packaging of IC products, and a third manufacturing facility can provide other services to the foundry enterprise.

[0264] IC wafer fab 2550 includes manufacturing tools 2552 configured to perform various manufacturing operations on semiconductor wafers 2553, such that IC devices 2560 are manufactured according to a mask (e.g., mask 2545). In various embodiments, manufacturing tools 2552 include wafer steppers, ion implanters, photoresist coaters, processing chambers such as CVD chambers or LPCVD furnaces, CMP systems, plasma etching systems, wafer cleaning systems, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

[0265] IC wafer fab 2550 uses a mask 2545 manufactured by mask producer 2530 to manufacture IC device 2560. Therefore, IC wafer fab 2550 uses IC design layout 2522 at least indirectly to manufacture IC device 2560. In some embodiments, semiconductor wafer 2553 is manufactured by IC wafer fab 2550 using mask 2545 to form IC device 2560. In some embodiments, IC manufacturing includes performing one or more lithography exposures on IC design layout 2522 at least indirectly. Semiconductor wafer 2553 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 2553 also includes one or more of various doped regions, dielectric features, multilayer interconnects, and the like (formed in subsequent manufacturing steps).

[0266] Regarding integrated circuit (IC) manufacturing systems (e.g.) Figure 25 Details of the IC manufacturing system 2500 and its associated IC manufacturing processes can be found, for example, in U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Pre-Grant Publication No. 2015 / 0278429, published October 1, 2015; U.S. Pre-Grant Publication No. 2014 / 0040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, the entire contents of each of which are incorporated herein by reference.

[0267] In some embodiments, the semiconductor device includes a plurality of memory structures in a plurality of wiring layers in a first region of a substrate, the memory structures including a plurality of storage elements in the wiring layers; peripheral circuitry in a second region of the substrate; and a plurality of virtual memory structures in the wiring layers in the second region and perpendicularly overlapping the peripheral circuitry.

[0268] In some embodiments, these virtual memory structures include a plurality of virtual storage elements in the wiring layers of the second region. In some embodiments, the semiconductor device also includes a plurality of first transistors in an active layer of the first region, the storage elements vertically overlapping the first transistors in the first region; and a plurality of second transistors in an active layer of the second region, the virtual memory structures vertically overlapping the second transistors. In some embodiments, each of these virtual memory structures includes a virtual storage element in the wiring layers of the second region; a first conductor in a first wiring layer below the virtual storage element; and a second conductor in a second wiring layer above the virtual storage element. In some embodiments, the virtual storage elements are not electrically connected from at least one first conductor or second conductor. In some embodiments, the semiconductor device also includes a third region between the first and second regions, the third region having neither the storage elements nor the virtual storage elements. In some embodiments, the semiconductor device also includes a third region between the first and second regions. In some embodiments, each of these memory structures includes a first conductor in a first wiring layer and vertically overlapping the storage element; and a second conductor in a second wiring layer and vertically overlapping the storage element. In some embodiments, each of these virtual memory structures includes a virtual storage element in the wiring layers of the second region; a third conductor in the first wiring layer and perpendicularly overlapping the virtual storage element; and a fourth conductor in the second wiring layer and perpendicularly overlapping the virtual storage element. In some embodiments, the third region includes insulating material in the first wiring layer; and a fifth conductor in the second wiring layer. In some embodiments, the first wiring layer has a first region density in the first region, a second region density in the second region, and a third region density in the third region, and the third region density is less than each of the first and second region densities. In some embodiments, the third region lacks multiple conductors in the first wiring layer such that the third region density is zero. In some embodiments, the first region density is equal to or approximately equal to the second region density.

[0269] In some embodiments, a method of manufacturing a semiconductor device includes forming a plurality of elements of peripheral circuitry in an active layer of a substrate; forming a plurality of memory structures in a plurality of wiring layers in a first region of the substrate, the formation of the memory structures including forming a plurality of storage elements in the wiring layers; and forming a plurality of virtual memory structures in the wiring layers in a second region of the substrate, the virtual memory structures being formed to vertically overlap with the elements of the peripheral circuitry.

[0270] In some embodiments, the method further includes forming a plurality of first transistors in an active layer of a first region. In some embodiments, the elements forming the peripheral circuitry include forming a plurality of second transistors in the active layer; forming a plurality of virtual memory structures includes forming a plurality of virtual storage elements in these wiring layers, the storage elements being formed to vertically overlap with the first transistors in the first region, and the virtual storage elements being formed to vertically overlap with the second transistors in the second region. In some embodiments, forming a plurality of virtual memory structures includes forming virtual storage elements in these wiring layers of the second region; forming a first conductor in a first wiring layer below the virtual storage elements; and forming a second conductor in a second wiring layer above the virtual storage elements, and the virtual storage elements being formed to be electrically unconnected from at least one of the first or second conductors. In some embodiments, a third region between the first and second regions is formed without these storage elements and without these virtual storage elements. In some embodiments, forming these memory structures includes forming a first conductor in a first wiring layer and perpendicularly overlapping one of the storage elements; forming a second conductor in a second wiring layer and perpendicularly overlapping one of the storage elements; and forming these virtual memory structures includes forming virtual storage elements in the wiring layers in a second region; forming a third conductor in a first wiring layer and perpendicularly overlapping the virtual storage elements; and forming a fourth conductor in a second wiring layer and perpendicularly overlapping the virtual storage elements. In some embodiments, the method further includes forming a third region, the third region including forming an insulating material in the first wiring layer in the third region; and forming a fifth conductor in the second wiring layer. In some embodiments, the first wiring layer is formed to have a first region density in the first region, a second region density in the second region, and a third region density in the third region, and the third region density is less than each of the first region density and the second region density. In some embodiments, the third region is formed such that there are no multiple conductors in the first wiring layer such that the third region density is zero. In some embodiments, the first region density is formed to be equal to or approximately equal to the second region density.

[0271] In some embodiments, the semiconductor device includes a plurality of memory cells in a first region of a substrate, the memory cells including a plurality of magnetic tunneling junction (MTJ) storage elements in a plurality of wiring layers in the first region of the substrate; peripheral circuitry in a second region of the substrate; and a plurality of resistors in the second region of the substrate, the resistors including a plurality of MTJ resistor elements in the wiring layers in the second region and perpendicularly overlapping the peripheral circuitry.

[0272] In some embodiments, these MTJ resistor elements have a fixed plurality of resistance values. In some embodiments, each of these memory cells includes a first conductor that overlaps perpendicularly to the MTJ storage element in a first wiring layer; and a second conductor that overlaps perpendicularly to the MTJ storage element in a second wiring layer. In some embodiments, each of these resistors includes a third conductor that overlaps perpendicularly to the MTJ resistor element in a first wiring layer; and a fourth conductor that overlaps perpendicularly to the MTJ resistor element in a second wiring layer. In some embodiments, each of these resistors includes a first conductor that contacts and overlaps perpendicularly to the MTJ resistor element; and a second conductor that contacts and overlaps perpendicularly to the MTJ resistor element. These resistors include a first resistor having a first resistance and a second resistor having a second resistance different from the first resistance, the first conductor and the second conductor of the first resistor being spaced apart by a first distance, and the first conductor and the second conductor of the second resistor being spaced apart by a second distance.

[0273] In some embodiments, a semiconductor device includes peripheral circuitry, a plurality of memory structures, and a plurality of virtual memory structures. The peripheral circuitry is located in an active layer of a substrate and includes a plurality of elements. The memory structures are located in a plurality of wiring layers in a first region of the substrate, and each memory structure includes a plurality of storage elements within the wiring layers. The virtual memory structures are located in wiring layers in a second region of the substrate and vertically overlap with the peripheral circuitry, wherein each virtual memory structure includes a virtual storage element within the wiring layers of the second region. In some embodiments, each virtual memory structure further includes a virtual storage element, a first conductor, and a second conductor. The virtual storage element is located in the wiring layers of the second region. The first conductor is located in the first wiring layer below the virtual storage element. The second conductor is located in the second wiring layer above the virtual storage element. The virtual storage element is electrically unconnected from at least one of the first conductors or the second conductor. In some embodiments, the semiconductor device further includes a plurality of first transistors. The first transistors are located in the active layer of the first region, and the storage elements vertically overlap with the first transistors in the first region.

[0274] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be easily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced in various ways without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Multiple memory structures are located in multiple wiring layers in a first region of a substrate, the multiple memory structures including multiple storage elements in the multiple wiring layers; A peripheral circuit is located in a second region of the substrate; as well as Multiple virtual memory structures are located in the multiple wiring layers in the second region and are vertically overlapped with the surrounding circuitry.

2. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A plurality of first transistors, wherein in an active layer in the first region, the plurality of storage elements are vertically overlapped with the plurality of first transistors in the first region; as well as Multiple second transistors, wherein the multiple virtual memory structures vertically overlap the multiple second transistors in the active layer of the second region.

3. The semiconductor device as claimed in claim 1, characterized in that, in: Each of the plurality of virtual memory structures includes: A virtual storage element, within the plurality of wiring layers in the second region; A first conductor, in a first wiring layer beneath the virtual storage element; and A second conductor, in a second wiring layer above the virtual storage element, and The plurality of virtual storage elements are electrically unconnected from at least one of the first conductor or the second conductor.

4. The semiconductor device as claimed in claim 3, characterized in that, It also includes a third region between the first region and the second region, the third region having neither the plurality of storage elements nor the plurality of virtual storage elements.

5. The semiconductor device as claimed in claim 1 or 2, characterized in that, It also includes a third region between the first region and the second region, wherein: Each of the plurality of memory structures includes: A first conductor, in a first wiring layer and perpendicularly overlapping the storage element; and A second conductor, in a second wiring layer and perpendicularly overlapping the storage element, and Each of the plurality of virtual memory structures includes: A virtual storage element, within the plurality of wiring layers in the second region; A third conductor, in the first wiring layer and perpendicularly overlapping the virtual storage element; and A fourth conductor, in the second wiring layer and perpendicularly overlapping the virtual storage element, and This third region includes: A fifth conductor, in the second wiring layer.

6. A semiconductor device, characterized in that, include: A peripheral circuit is located in an active layer of a substrate, wherein the peripheral circuit includes multiple components; Multiple memory structures are located in multiple wiring layers in a first region of the substrate, the multiple memory structures including multiple storage elements in the multiple wiring layers; and Multiple virtual memory structures are located in multiple wiring layers in a second region of the substrate and vertically overlap with the peripheral circuitry, wherein each of the multiple virtual memory structures includes a virtual storage element in the multiple wiring layers in the second region.

7. The semiconductor device as claimed in claim 6, characterized in that, in Each of the plurality of virtual memory structures further includes: A first conductor, in a first wiring layer beneath the virtual storage element; and A second conductor, in a second wiring layer above the virtual storage element, and The plurality of virtual storage elements are electrically unconnected from at least one of the first conductor or the second conductor.

8. The semiconductor device as claimed in claim 6 or 7, characterized in that, Also includes: A plurality of first transistors, wherein in the active layer of the first region, the plurality of storage elements are vertically overlapped with the plurality of first transistors in the first region.

9. A semiconductor device, characterized in that, include: Multiple memory cells are located in a first region of a substrate, the multiple memory cells including multiple magnetic tunneling interface storage elements in multiple wiring layers in the first region of the substrate; A peripheral circuit is located in a second region of the substrate; as well as Multiple resistors, in the second region of the substrate, the multiple resistors include multiple magnetic tunneling junction resistor elements in the multiple wiring layers in the second region and vertically overlap with the peripheral circuitry.

10. The semiconductor device as claimed in claim 9, characterized in that, in: Each of the plurality of memory units includes: A first conductor, in a first wiring layer and perpendicularly overlapping the magnetic tunneling interface storage element; and A second conductor, in a second wiring layer and perpendicularly overlapping the magnetic tunneling interface storage element, and Each of the plurality of resistors includes: A third conductor, in the first wiring layer and perpendicular to the magnetic tunneling junction resistor element; and A fourth conductor, in the second wiring layer, overlaps perpendicularly with the magnetic tunneling junction resistor element.

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