A triode for improving the uniformity of the leakage current distribution
Patent Information
- Application Number
- CN202521832173.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-27
- Publication Date
- 2026-09-08
- Estimated Expiration
- 2035-08-27
AI Technical Summary
[0011] This invention comprises several resistive materials, each located on the top surface of the second heavily doped emitter region; the height of these resistive materials decreases from the center to the sides; several emitter electrodes are provided, each located on the top surface of the resistive materials; by controlling the leakage current and junction temperature to different degrees in the central region, sub-central region, and peripheral region of the transistor, the leakage current in the central region is low and the leakage current in the peripheral region is high, thereby ensuring that the junction temperature in the central region, sub-central region, and peripheral region of the transistor remains consistent. This achieves the purpose of reducing the leakage current of the device and the junction temperature in the weakest region of the transistor. Compared with ordinary transistors, there is no central weak region with the highest junction temperature, so the device can withstand greater current and voltage stress.
Smart Images
Figure CN224734040U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to a transistor that improves the uniformity of leakage current distribution. Background Technology
[0002] In the field of power electronic device technology, transistors are a commonly used semiconductor device, often used in switching circuits and amplifier circuits. As the power density requirements of power electronic device applications become increasingly higher, the current and voltage stress that transistors bear in non-clamped inductive load switching is increasing. Transistors that should be cut off may conduct due to unexpected triggering, causing device failure. This phenomenon is particularly prominent in high-frequency, high-voltage, high dv / dt, or high di / dt scenarios.
[0003] Therefore, how to improve the EAS (single-pulse avalanche energy) capability of transistors and prevent transistors that should be cut off from turning on due to unexpected triggering has always been a core technical challenge for the application of transistors in high-frequency, high-voltage, high-dv / dt or high-di / dt scenarios. Utility Model Content
[0004] This invention addresses the issue of improving the EAS capability of transistors by providing a transistor that reduces leakage current, improves the uniformity of leakage current distribution, and enhances the uniformity of internal junction temperature distribution.
[0005] The technical solution of this utility model is: A transistor for improving the uniformity of leakage current distribution includes a collector electrode, an epitaxial wafer, a first isolation layer, and a second isolation layer arranged sequentially from bottom to top. The epitaxial wafer is provided with: The first doped base regions extend downward from the top surface of the epitaxial wafer; The second doped emitter region is provided in several parts, each extending downward from the top surface of the epitaxial wafer; A first isolation layer is deposited on the top surface of the epitaxial wafer; The base electrode is provided in several parts, which extend downward from the top surface of the first isolation layer and are located on the top surface of the first heavily doped base region (2); The second isolation layer is deposited on the top surface of the first isolation layer; A plurality of resistive materials are provided, each located on the top surface of the second heavily doped emitter region; the height of the plurality of resistive materials decreases from the center to the sides; The emitter electrode is provided in several parts, each located on the top surface of the resistive material.
[0006] Specifically, the height of the resistive material decreases from the middle to the outside.
[0007] Specifically, the resistive material includes polycrystalline silicon, monocrystalline silicon, silicon carbide, or gallium nitride.
[0008] Specifically, the resistive material has a resistance of 1-10000Ω.
[0009] Specifically, the width of the resistive material is equal to the width of the emitter electrode.
[0010] Specifically, the top surfaces of several of the emitter electrodes are in the same plane.
[0011] This invention comprises several resistive materials, each located on the top surface of the second heavily doped emitter region; the height of these resistive materials decreases from the center to the sides; several emitter electrodes are provided, each located on the top surface of the resistive materials; by controlling the leakage current and junction temperature to different degrees in the central region, sub-central region, and peripheral region of the transistor, the leakage current in the central region is low and the leakage current in the peripheral region is high, thereby ensuring that the junction temperature in the central region, sub-central region, and peripheral region of the transistor remains consistent. This achieves the purpose of reducing the leakage current of the device and the junction temperature in the weakest region of the transistor. Compared with ordinary transistors, there is no central weak region with the highest junction temperature, so the device can withstand greater current and voltage stress. Attached Figure Description
[0012] Figure 1 This is a process flow diagram of this utility model; Figure 2 This is a schematic diagram of the cross-sectional structure of the first-fold doped base region; Figure 3 This is a schematic diagram of the cross-sectional structure for fabricating the second-doped emitter region; Figure 4 This is a schematic diagram of the cross-sectional structure of the base electrode. Figure 5 This is a schematic diagram of the cross-sectional structure for preparing resistive materials; Figure 6 This is a schematic diagram of the cross-sectional structure after etching of the resistive material. Figure 7 Schematic diagram of the fabricated emitter electrode cross-sectional structure; Figure 8 This is a schematic diagram of the cross-sectional structure of the current collector electrode; In the figure, 1 is the epitaxial wafer, 2 is the first doped base region, 3 is the second doped emitter region, 4 is the first isolation layer, 5 is the base electrode, 6 is the second isolation layer, 7 is the resistive material, 8 is the emitter electrode, and 9 is the collector electrode. Detailed Implementation
[0013] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.
[0014] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0015] The following is for reference. Figure 1-8 Description of embodiments of this utility model; A method for fabricating a transistor to improve the uniformity of leakage current distribution includes the following steps: Step S100: A first heavily doped base region 2 is prepared within the epitaxial wafer 1, and several second heavily doped emitter regions 3 are prepared at intervals within the first heavily doped base region 2, as shown in the figure. Figure 2-3 As shown; Step S110: Using photolithography, a mask is used to protect the outer region of the first heavily doped base region 2; the first heavily doped base region 2 is formed by diffusion or ion implantation. In step S120, a photolithography process is used to protect the outer region of the second heavily doped emission region 3 using a mask; and a number of spaced second heavily doped emission regions 3 are formed through a diffusion process or an ion implantation process.
[0016] Accordingly, the first and second doped regions are P-regions or N-regions with opposite doping charges. The epitaxial wafer 1 has a thickness of 100-2000 μm, the first heavily doped base region 2 has a thickness of 1-50 μm, the second heavily doped emitter region 3 has a thickness of 0.5-49 μm, a width of 1-50 μm, and a spacing of 1-50 μm. The N-type doping concentration range is 1e. 14 .cm -3 -1e 20 .cm -3 The doping concentration range for P-type doping is 1e. 15 .cm -3 -1e 20 .cm -3 The relevant parameter settings are related to the electrical design of the device; In this embodiment, a silicon epitaxial wafer is used. The first doped region is a P-region, the second doped region is an N-region, and the thickness of epitaxial wafer 1 is 350 μm; the thickness of the first heavily doped base region 2 is 5 μm, and the doping concentration is 1e. 16 .cm -3 The second doped emitter region 3 has a thickness of 3 μm, a width of 20 μm, a spacing width of 10 μm, and a doping concentration of 1e. 19. cm -3 The first heavily doped base region 2 and the second heavily doped emitter region 3 were prepared using ion implantation.
[0017] Step S200: A first isolation layer 4 is prepared on the epitaxial wafer 1, and a window is opened at the first heavily doped base region 2 to prepare several spaced base electrodes 5, as shown in the figure. Figure 4 As shown; In step S210, the first isolation layer 4 is prepared by chemical vapor deposition, and the external area of the base electrode 5 is protected by a mask through photolithography and the window is opened by etching. In step S220, the base electrode 5 is prepared at the window using a stripping or etching process.
[0018] Correspondingly, the first isolation layer 4 plays a protective role. It is made of SiO2 or Si3N4 and the thickness is set to 10-5000nm. It uses ICP dry etching to open the window. The window extends from the top surface of the first isolation layer 4 downward into the interior of the first heavily doped base region 2. The base electrode 5 contacts the first heavily doped base region 2 to form an ohmic contact. The relevant parameter settings are related to the electrical design of the device. In this embodiment, Si3N4 is used as the first isolation layer 4 with a thickness of 200nm. ICP dry etching is used to open the window with a depth of 200nm. A 200nm thick Ti / Al two-layer metal is prepared as the base electrode 5 using a local heavy doping remetallization process and a stripping process.
[0019] Step S300: A second isolation layer 6 is prepared on the epitaxial wafer 1, a window is opened at the second heavily doped emitter region 3, and resistive material 7 is filled in, as per reference. Figure 5 As shown; Step S310: The second isolation layer 6 is prepared by chemical vapor deposition. The external area of the second heavily doped emitter region 3 is protected by a mask through photolithography and the window is opened by etching. In step S320, a resistive material 7 is filled at the opening using a stripping or etching process, and the resistive material 7 contacts the second doped emitter region 3.
[0020] Correspondingly, the second isolation layer 6 plays a protective role. It is made of SiO2 or Si3N4 and the thickness is set to 10-5000nm. It uses ICP dry etching to open the window. The window extends from the top surface of the second isolation layer 6 downward into the interior of the second heavily doped emitter region 3. The resistive material 7 and the second heavily doped emitter region 3 form an ohmic contact. The relevant parameter settings are related to the electrical design of the device. In this embodiment, Si3N4 is used as the second isolation layer 6, with a thickness of 200 nm. ICP dry etching is used to create a window with a depth of 400 nm. A lift-off process is then used to fabricate a 400 nm thick layer with a doping concentration of 1e. 15 .cm -3 Lightly doped polycrystalline silicon is used as resistive material 7 to form an ohmic contact with the heavily doped N-type emitter region.
[0021] Step S400: Etch resistive material 7 so that the resistance value of resistive material 7 at the corresponding second-doped emitter region 3 window reaches the design value, referring to... Figure 6 As shown; Step S410: Etch the resistive material 7 in the middle region so that the resistance value of the resistive material 7 at the window of the second doped emitter region 3 in the middle region reaches the design value. Correspondingly, the number of second-doped emitter regions 3 in the central region is 1-100, and the selection of the number of second-doped emitter regions 3 in the central region is related to the chip design parameters.
[0022] In this embodiment, the number of second-doped emission regions 3 in the middle region is 1, and the resistance value of the resistive material 7 at the window opening of the innermost second-doped emission region 3 has reached the design value, and the etching thickness is 0.
[0023] Step S420: The resistive material 7 in the side region of the central region is etched so that the resistance value of the resistive material 7 at the window of the second doped emitter region 3 at the corresponding position reaches the design value. Step S430: Etch the resistive material 7 in the outer region so that the resistance value of the resistive material 7 at the window of the second doped emitter region 3 in the outer region reaches the design value. Accordingly, the number of second-doped emitter regions 3 in the side region and the outer region is 1-100, and the selection of the number of second-doped emitter regions 3 in each region is related to the chip design parameters. Before the above etching, the resistive material 7 is protected by the mask using photolithography and the resistive material 7 is etched so that the resistance value of the resistive material 7 at the window of the second-doped emitter region 3 in the corresponding region reaches the design value.
[0024] In this embodiment, the number of second heavily doped emission regions 3 in the side region is 2, the number of second heavily doped emission regions 3 in the outer region is 2, the resistive material 7 at the window opening of the second heavily doped emission region 3 in the inner (side region) region is etched by 100nm, and the resistive material 7 at the window opening of the second heavily doped emission region 3 in the outer region is etched by 200nm.
[0025] In step S500, an emitter electrode 8 is prepared on top of the resistive material 7 at the window opening of the second heavily doped emitter region 3, and then planarized. In step S510, an emitter electrode 8 is fabricated on top of the resistive material 7 using a stripping or etching process, and then planarized.
[0026] like Figure 7 As shown, the resistive material 7 and the emitter electrode 8 form an ohmic contact, and the relevant parameter settings are related to the electrical design of the device. In this embodiment, a stripping process is used to prepare a Ti / Al two-layer metal as the emitter electrode 8 and planarize it.
[0027] Step S600: Prepare collector electrode 9 on the back side of the epitaxial wafer.
[0028] like Figure 8 As shown, the epitaxial wafer 1 is thinned to the corresponding thickness by a thinning process, and the collector electrode 9 is prepared on the back side of the epitaxial wafer by sputtering or deposition process. In this embodiment, a thinning process is used to reduce the thickness of the 350µm epitaxial wafer 1 to 180µm, and a deposition process is used to prepare a 1µm thick Ti / Al as the collector electrode 9.
[0029] A high EAS capability transistor includes a collector electrode 9, an epitaxial wafer 1, a first isolation layer 4 and a second isolation layer 6 arranged sequentially from bottom to top; The epitaxial wafer 1 has the following features: The first doped base region 2 extends downward from the top surface of the epitaxial wafer 1; The second doped emitter region 3 is provided with several spaced-apart regions, which extend downward from the top surface of the epitaxial wafer 1 and are disposed inside the first doped base region 2. The first isolation layer 4 is deposited on the top surface of the epitaxial wafer 1; The base electrode 5 has several portions, which extend downward from the top surface of the first isolation layer 4 and are located on the top surface of the first heavily doped base region 2, forming a good ohmic contact with the first heavily doped base region 2; the height of the first isolation layer 4 is equal to the height of the base electrode 5. The second isolation layer 6 is deposited on the top surface of the first isolation layer 4; A plurality of resistive materials 7 are provided, each located on the top surface of the second doped emission region 3, forming a good ohmic contact with the second doped emission region 3; Emitter electrodes 8 are provided in several locations on the top surface of resistive material 7, forming good ohmic contact with resistive material 7. The height of resistive material 7 decreases from the middle to the outside, and its resistance also gradually decreases.
[0030] In this case, resistive material 7 uses a doping concentration of 1e. 15 .cm -3 The lightly doped polycrystalline silicon has a second heavily doped emitter region 3 with a doping concentration of 1e. 19 .cm -3 The N-type doped silicon forms a good ohmic contact with the emitter electrode. The height of the multiple resistive materials 7 decreases from the center to the sides. Due to the presence of the resistive material 7 under the emitter electrode, the leakage current from the collector to the emitter of the device will be reduced. The resistance of the resistive material 7 is the largest in the central region of the device. The leakage current from the collector to the emitter through the path of the resistive material 7 in the central region is reduced the most. This results in the lowest heat generation of the reverse PN junction in the central region of the device. It avoids the temperature rise in the central region of the device being greater than that in the outer region due to the poor heat dissipation capacity. This prevents the central region of the device from entering the parasitic conduction state first and improves the EAS capability of the device.
[0031] This invention addresses the problem of avoiding parasitic conduction in transistors and thus improving their Emergency Easing (EAS) capability. It proposes a method to reduce the overall leakage current of the transistor, improve the uniformity of leakage current distribution, and enhance the uniformity of internal junction temperature distribution. The innovative method involves different degrees of leakage current and junction temperature control in the central, sub-central, and peripheral regions of the transistor. This results in lower leakage current in the central region and higher leakage current in the peripheral region, thereby maintaining a consistent junction temperature across the central (device center), sub-central (near the center), and peripheral (near the outer edge) regions. This simultaneously reduces leakage current and junction temperature in the transistor's weakest areas. Compared to ordinary transistors, there is no central weak area with the highest junction temperature, allowing the transistor to withstand greater current and voltage stress. Under the same process conditions, the high EAS capability transistor prepared by this invention shows a 20%-30% improvement in EAS capability compared to ordinary devices. Furthermore, this invention uses resistive materials with different resistance values in the central, sub-central, and peripheral regions to control leakage current and junction temperature, minimizing the impact of the resistive material introduction on the transistor's current-carrying capacity during turn-on.
[0032] Regarding the information disclosed in this case, the following points need to be clarified: (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design. (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.
Claims
1. A transistor for improving the uniformity of leakage current distribution, characterized in that, It includes a collector electrode (9), an epitaxial wafer (1), a first isolation layer (4), and a second isolation layer (6) arranged sequentially from bottom to top; The epitaxial wafer (1) is provided with: The first doped base region (2) extends downward from the top surface of the epitaxial wafer (1); The second doped emission region (3) is provided in several forms, which extend downward from the top surface of the epitaxial wafer (1); A first isolation layer (4) is deposited on the top surface of the epitaxial wafer (1); The base electrode (5) is provided in several forms, which extend downward from the top surface of the first isolation layer (4) and are located on the top surface of the first heavily doped base region (2); The second isolation layer (6) is deposited on the top surface of the first isolation layer (4); A plurality of resistive materials (7) are provided, each located on the top surface of the second heavily doped emission region (3); the height of the plurality of resistive materials (7) decreases from the middle to the side; The emitter electrode (8) is provided in several places, which are located on the top surface of the resistive material (7).
2. The transistor for improving leakage current distribution uniformity according to claim 1, characterized in that, The height of the resistive material (7) decreases from the middle to the outside.
3. A transistor for improving the uniformity of leakage current distribution according to claim 1, characterized in that, The resistive material (7) includes polycrystalline silicon, monocrystalline silicon, silicon carbide or gallium nitride.
4. A transistor for improving the uniformity of leakage current distribution according to claim 1, characterized in that, The resistive material (7) has a resistance of 1-10000Ω.
5. A transistor for improving the uniformity of leakage current distribution according to claim 1, characterized in that, The width of the resistive material (7) is equal to the width of the emitter electrode (8).
6. A transistor for improving the uniformity of leakage current distribution according to claim 1, characterized in that, The top surfaces of several of the emitter electrodes (8) are in the same plane.