Semiconductor structure and method of forming the same

Abstract

The embodiments of the present disclosure provide a semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: a substrate; memory cells arranged in an array along a first direction and a third direction on a surface of the substrate; the memory cells at least comprise a channel structure and a drain arranged along a second direction; the channel structure comprises a first channel region and a second channel region; an electron mobility of a bulk material of the channel structure is greater than an electron mobility of a bulk material of the drain; the second channel region is connected with the drain, and a size of the second channel region is less than or equal to a size of the first channel region.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and a method for forming the same. Background Technology

[0002] As the size of semiconductor devices continues to shrink, the gate-induced drain leakage (GIDL) of the gate structure becomes larger and larger, resulting in weaker control over the gate structure and worse performance of the semiconductor device. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor structure, including:

[0005] Substrate;

[0006] A memory cell is located on the surface of the substrate and arranged in an array along a first direction and a third direction; the memory cell includes at least a channel structure and a drain arranged along a second direction; the channel structure includes a first channel region and a second channel region; the electron mobility of the bulk material of the channel structure is greater than the electron mobility of the bulk material of the drain.

[0007] The second channel region is connected to the drain electrode, and the size of the second channel region is less than or equal to the size of the first channel region.

[0008] In some embodiments, the memory cell further includes: a first lightly doped region located between the drain and the second channel region, and a gate structure covering the channel structure and the surface of the first lightly doped region;

[0009] The gate structure includes a gate dielectric layer and a gate conductive layer located on the surface of the gate dielectric layer;

[0010] The size of the second channel region decreases in the direction toward the first lightly doped region, and the size of the first lightly doped region is equal to the minimum size of the second channel region.

[0011] In some embodiments, the memory cell further includes a source and a second lightly doped region located between the source and the first channel region;

[0012] The size of the second lightly doped region is equal to the size of the first channel region.

[0013] In some embodiments, the channel structure further includes a third channel region connected to the first channel region; the memory cell further includes a source and a second lightly doped region located between the source and the third channel region;

[0014] The size of the third channel region decreases toward the second lightly doped region, and the electron mobility of the host material of the third channel region is greater than that of the host material of the source electrode; the size of the second lightly doped region is equal to the minimum size of the third channel region.

[0015] In some embodiments, the doping type of the first lightly doped region is the same as the doping type of the second lightly doped region;

[0016] The doping type of the first lightly doped region is opposite to that of the first channel region, or the doping type of the first lightly doped region is the same as that of the first channel region, and the doping concentration of the first lightly doped region is greater than or equal to the doping concentration of the first channel region.

[0017] In some embodiments, the size of the source is equal to the size of the second lightly doped region;

[0018] Furthermore, the size of the drain is equal to the size of the first lightly doped region.

[0019] In some embodiments, the first direction and the second direction are any two directions within the plane where the substrate is located, and the third direction is perpendicular to the plane where the substrate is located.

[0020] The memory cell further includes a bit line structure connected to the source, a word line structure connected to the gate structure, and a capacitor structure connected to the drain and extending along the second direction.

[0021] The bit line structure extends along one of the first direction and the third direction, and the word line structure extends along the other of the first direction and the third direction.

[0022] In a second aspect, embodiments of this disclosure provide a method for forming a semiconductor structure, the method comprising:

[0023] Provide substrate;

[0024] A memory cell array is formed on the surface of the substrate along a first direction and a third direction; the memory cell includes at least a channel structure and a drain arranged along a second direction; the channel structure includes a first channel region and a second channel region; the electron mobility of the bulk material of the channel structure is greater than the electron mobility of the bulk material of the drain.

[0025] The second channel region is connected to the drain electrode, and the size of the second channel region is less than or equal to the size of the first channel region.

[0026] In some embodiments, the memory cell further includes a source electrode; forming memory cells arranged in an array along a first direction and a third direction on the substrate surface includes:

[0027] An initial active stripe is formed on the substrate surface, arranged in an array along the first direction and the third direction, and extending along the second direction;

[0028] An initial channel structure is formed in the initial active strip; the initial channel structure is located between the first and second initial active strips arranged at intervals along the second direction, and the electron mobility of the bulk material of the initial channel structure is greater than the electron mobility of the bulk material of the initial active strip;

[0029] The initial channel structure is processed to form the channel structure;

[0030] The drain and the source are formed in the first initial active strip and the second initial active strip, respectively.

[0031] In some embodiments, processing the initial channel structure to form the channel structure includes:

[0032] A first photoresist layer having a first preset pattern is formed on the surfaces of the initial active strip and the initial channel structure; the first preset pattern exposes the second initial active strip and a portion of the initial channel structure in contact with the second initial active strip;

[0033] The initial channel structure and the second initial active strip exposed by etching correspond to form the second channel region and the second active strip; wherein, the initial channel structure that is not etched constitutes the first channel region; the size of the second channel region decreases in the direction toward the second active strip.

[0034] In some embodiments, the channel structure further includes: a third channel region; the method further includes:

[0035] While forming the second channel region and the second active strip, the first initial active strip and the portion of the initial channel structure in contact with the first initial active strip are etched to form the first active strip and the third channel region.

[0036] The size of the third channel region decreases in the direction toward the first active strip, and the electron mobility of the bulk material of the third channel region is greater than that of the bulk material of the source electrode.

[0037] In some embodiments, the drain and the source are formed in the first initial active strip and the second initial active strip, respectively, including:

[0038] The first initial active strip or the end of the first active strip away from the channel structure along the second direction is subjected to a first heavy doping to form the source electrode;

[0039] The second active strip is subjected to the first heavy doping at the end away from the channel structure along the second direction to form the drain.

[0040] In some embodiments, the method further includes:

[0041] The drain electrode is heat-treated so that the doped ions in the first heavy doping process diffuse to one end of the second active strip near the channel structure to form a first lightly doped region.

[0042] Wherein, the size of the first lightly doped region is equal to the minimum size of the second channel region;

[0043] The source electrode is heat-treated to allow the doped ions from the first heavy doping process to diffuse to the first initial active strip or to one end of the first active strip near the channel structure, forming a second lightly doped region; wherein the size of the second lightly doped region is equal to the size of the first channel region, or the size of the second lightly doped region is equal to the minimum size of the third channel region.

[0044] In some embodiments, prior to forming the source and the drain, the method further includes:

[0045] A gate structure is formed on the surface of the first channel region and the second channel region; or,

[0046] The gate structure is formed on the surfaces of the first channel region, the second channel region, and the third channel region; the gate structure includes a gate dielectric layer and a gate conductive layer located on the surface of the gate dielectric layer.

[0047] In some embodiments, the method further includes:

[0048] The gate structure is formed on the surface of the first lightly doped region.

[0049] In some embodiments, the initial channel structure is formed by the following steps:

[0050] A sacrificial structure is formed in the gap between the plurality of the initial active strips;

[0051] The sacrificial structure and the initial active strip are etched to form an etched groove extending along the first direction; the etched groove divides the initial active strip into a first initial active strip and a second initial active strip; the etched groove exposes the sidewalls of the first initial active strip and the second initial active strip.

[0052] The initial channel structure is formed by extending the sidewall surface exposed by the etched groove.

[0053] In some embodiments, after forming the initial channel structure, the method further includes:

[0054] The initial channel structure is subjected to a second doping; wherein the first doping and the second doping are of the same or opposite doping types.

[0055] In some embodiments, the first direction and the second direction are any two directions within the plane containing the substrate, and the third direction is perpendicular to the plane containing the substrate; the method further includes:

[0056] A bitline structure is formed that is connected to the source electrode;

[0057] A word line structure is formed in connection with the gate structure; wherein the bit line structure extends along one of the first direction and the third direction, and the word line structure extends along the other of the first direction and the third direction;

[0058] A capacitor structure is formed that is connected to the drain and extends along the second direction.

[0059] The semiconductor structure and its formation method provided in this disclosure include a plurality of memory cells, each memory cell including at least a channel structure and a drain. Since the channel structure of the memory cell includes two channel regions of different sizes, and the electron mobility of the bulk material of the channel structure is greater than that of the bulk material of the drain, the gate-induced drain leakage current can be improved, thereby enhancing the electrical performance of the semiconductor structure. Attached Figure Description

[0060] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0061] Figure 1a and Figure 1b This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure;

[0062] Figure 2a and Figure 2b This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

[0063] Figure 3 A schematic flowchart illustrating a semiconductor structure formation method provided in an embodiment of this disclosure;

[0064] Figures 4a to 4j This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure;

[0065] Figures 5a-5e This is another schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure. Detailed Implementation

[0066] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0067] In the following description, numerous details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0068] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0069] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0070] The terminology used herein is intended only to describe particular embodiments and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of said features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0071] Before introducing the embodiments of this disclosure, let's define three directions that may be used in the following embodiments to describe the three-dimensional structure. Taking a Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis, and Z-axis. The substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side. Ignoring the flatness of the top and bottom surfaces, the direction intersecting (e.g., perpendicular) with the top and bottom surfaces of the substrate is defined as the third direction. In the direction of the top and bottom surfaces of the substrate (i.e., the plane in which the substrate is located), two directions that intersect (e.g., perpendicular) with each other are defined. For example, the direction of extension of the channel structure can be defined as the second direction. The planar orientation of the substrate can be determined based on the first and second directions.

[0072] In this embodiment of the disclosure, the first direction, the second direction, and the third direction can be mutually perpendicular; in other embodiments, the first direction, the second direction, and the third direction may not be perpendicular. In this embodiment of the disclosure, the first direction is defined as the X-axis direction, the second direction is defined as the Y-axis direction, and the third direction is defined as the Z-axis direction.

[0073] This disclosure provides a semiconductor structure. Figure 1a and Figure 1b This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure, wherein, Figure 1a The left image is a 3D view, and the right image is an enlarged view of storage unit 100 in the left image. Figure 1b for Figure 1a The right figure is a cross-sectional view along line a-a'. (See figure below.) Figure 1a and Figure 1b As shown, the semiconductor structure 100a includes: a substrate 10; memory cells 100 located on the surface of the substrate 10 and arranged in an array along the X-axis and Z-axis directions; the memory cells 100 include at least a channel structure 101 and a drain 102 arranged along the Y-axis direction; the electron mobility of the bulk material of the channel structure 101 is greater than the electron mobility of the bulk material of the drain 102.

[0074] In this embodiment, the main material of the channel structure 101 can be silicon or silicon-germanium, and the main material of the drain 102 can be silicon. The electron mobility of the main material of the channel structure is greater than that of the main material of the drain, which allows for a greater number of conductive ions in the channel, thereby improving the controllability of the gate structure.

[0075] In some embodiments, please continue to see Figure 1b The channel structure 101 includes a first channel region 101a and a second channel region 101b; wherein the second channel region 101b is close to the drain electrode 102, and the size of the second channel region 101b is less than or equal to the size of the first channel region 101a.

[0076] In this embodiment of the disclosure, the channel structure 101 is horizontal (i.e., extends along the Y-axis direction). In other embodiments, the channel structure 101 may also be vertical (i.e., extends along the Z-axis direction). Therefore, the first channel region 101a and the second channel region 101b may be arranged along the Y-axis direction or along the Z-axis direction.

[0077] In this embodiment of the disclosure, the maximum dimension of the second channel region 101b in the Z-axis (or X-axis) direction is equal to the dimension of the first channel region 101a in the Z-axis (or X-axis) direction, and all dimensions of the second channel region 101b in the Z-axis (or X-axis) direction other than the maximum dimension are smaller than the dimension of the first channel region 101a in the Z-axis (or X-axis) direction. Alternatively, the maximum cross-sectional area of ​​the second channel region 101b along the Z-axis (or X-axis) direction is equal to the cross-sectional area of ​​the first channel region 101a in the Z-axis (or X-axis) direction, and all cross-sectional areas of the second channel region 101b along the Z-axis (or X-axis) direction other than the maximum cross-sectional area are smaller than the cross-sectional area of ​​the first channel region 101a in the Z-axis (or X-axis) direction.

[0078] In other embodiments, the maximum dimension of the second channel region 101b in the X-axis (or Y-axis) direction is equal to the dimension of the first channel region 101a in the X-axis (or Y-axis) direction, and all other dimensions of the second channel region 101b in the X-axis (or Y-axis) direction except for the maximum dimension are smaller than the dimension of the first channel region 101a in the X-axis (or Y-axis) direction. Alternatively, the maximum cross-sectional area of ​​the second channel region 101b in the X-axis (or Y-axis) direction is equal to the cross-sectional area of ​​the first channel region 101a in the X-axis (or Y-axis) direction, and all other cross-sectional areas of the second channel region 101b in the X-axis (or Y-axis) direction except for the maximum cross-sectional area are smaller than the cross-sectional area of ​​the first channel region 101a in the X-axis (or Y-axis) direction.

[0079] In some embodiments, the band-to-band tunneling (BTBT) current typically satisfies the following formula (1):

[0080]

[0081] Among them, J B2B Let q be the inter-band tunneling current, and q be the charge quantity. Where is the effective mass of the density of states, k is the Boltzmann constant, T is the temperature, h is the Planck constant, D is a factor determined by the electron and hole concentrations, W is the effective width, and T pro Let E be the tunneling probability and E be the electron kinetic energy. It can be seen that the interband tunneling current is proportional to the tunneling probability of the charge carriers and the effective width. In this embodiment, the size of the second channel region 101b is smaller than or equal to the size of the first channel region 101a. Therefore, a lower interband tunneling current can be achieved in this embodiment, thereby reducing the gate-induced drain current of the gate structure.

[0082] In some embodiments, please continue to see Figure 1a and Figure 1b The memory cell 100 further includes: a first lightly doped region 103 located between the drain 102 and the second channel region 101b, and a gate structure 104 covering the surface of the channel structure 101 and the first lightly doped region 103. The gate structure 104 includes a gate dielectric layer 104a and a gate conductive layer 104b located on the surface of the gate dielectric layer 104a. The gate structure 104 in this embodiment can be a full-ring gate structure.

[0083] In this embodiment of the present disclosure, the doping type of the first lightly doped region 103 is the same as that of the drain 102, and the doping concentration of the drain 102 is greater than that of the first lightly doped region 103. In this way, leakage current of the semiconductor structure can be reduced.

[0084] In some embodiments, the material of the gate dielectric layer 104a may be silicon oxide or other suitable materials; the material of the gate conductive layer 104b may be any material with good conductivity, such as any one or a combination of titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), and copper (Cu).

[0085] It should be noted that the gate structure 104 in this embodiment may cover part of the first lightly doped region 103 or cover all of the first lightly doped region 103.

[0086] In this embodiment of the disclosure, the first lightly doped region 103 connected to the drain 102 extends into the channel structure, which can reduce the gate-induced drain leakage current of the fully depleted silicon transistor.

[0087] In some embodiments, please continue to see Figure 1a and Figure 1b The size of the second channel region 101b decreases along the direction toward the first lightly doped region 103, and the size of the first lightly doped region 103 is equal to the minimum size of the second channel region 101b.

[0088] In this embodiment of the disclosure, the channel structure 101 extends along the Y-axis direction, the size of the second channel region 101b in the Z-axis (or Y-axis) direction decreases in the direction toward the first lightly doped region 103, and the size of the first lightly doped region 103 in the Z-axis (or Y-axis) direction is equal to the minimum size of the second channel region 101b in the Z-axis (or Y-axis) direction.

[0089] In some embodiments, please continue to see Figure 1a and Figure 1b The memory cell 100 also includes a source 105 and a second lightly doped region 106 located between the source 105 and the first channel region 101a; the size of the second lightly doped region 106 is equal to the size of the first channel region 101a.

[0090] In this embodiment of the disclosure, the channel structure 101 extends along the Y-axis direction, and the size of the second lightly doped region 106 in the Z-axis (or X-axis) direction is equal to the size of the first channel region 101a in the Z-axis (or X-axis) direction, or the cross-sectional area of ​​the second lightly doped region 106 along the Z-axis (or X-axis) direction is equal to the cross-sectional area of ​​the first channel region 101a along the Z-axis (or X-axis) direction.

[0091] In some embodiments, the doping type of the first lightly doped region 103 and the doping type of the second lightly doped region 106 may be the same. For example, both the first lightly doped region 103 and the second lightly doped region 106 may be N-type doped or both may be P-type doped. The doping concentration of the first lightly doped region 103 is greater than or equal to the doping concentration of the first channel region 101a.

[0092] In other embodiments, the doping type of the first lightly doped region 103 may be opposite to that of the second lightly doped region 106. For example, the first lightly doped region 103 may be N-type doped and the second lightly doped region 106 may be P-type doped.

[0093] In some embodiments, when the doping type of the first lightly doped region 103 is the same as that of the second lightly doped region 106, a junctionless transistor is formed; when the doping type of the first lightly doped region 103 is opposite to that of the second lightly doped region 106, a junction transistor is formed. The doping concentration of the source or drain of a junction transistor is lower than that of the source or drain of a junctionless transistor; therefore, the turn-off current of a junctionless transistor is larger than that of a junctionless transistor. Furthermore, the doping concentration of the channel of a junction transistor is greater than that of the channel of a junctionless transistor; therefore, channel control is more difficult in a junction transistor than in a junctionless transistor. Compared to a junction transistor, a junctionless transistor eliminates the concentration gradient distribution between the channel and the source or drain, reducing the thermal budget.

[0094] In some embodiments, please continue to see Figure 1a and Figure 1b The size of the source 105 in the Z-axis (or Y-axis) direction is equal to the size of the second lightly doped region 106 in the Z-axis (or Y-axis) direction; and the size of the drain 102 in the Z-axis (or Y-axis) direction is equal to the size of the first lightly doped region 103 in the Z-axis (or Y-axis) direction.

[0095] In some embodiments, please continue to see Figure 1a and Figure 1b The memory cell 100 also includes a bit line structure 107 connected to the source 105, a word line structure (not shown) connected to the gate structure 104, and a capacitor structure 108 connected to the drain 102 and extending along the Y-axis.

[0096] In some embodiments, the bit line structure 107 material may include tungsten, cobalt, copper, aluminum (Al), titanium nitride, a titanium-containing metal layer, polysilicon, or any combination thereof. The word line structure material may be any one of cobalt, titanium, tantalum (Ta), nickel (Ni), tungsten, platinum, and palladium. The capacitor structure 108 includes a first electrode layer, a dielectric layer, and a second electrode layer. The materials of the first electrode layer and the second electrode layer may include polysilicon, metal nitride, or metal silicide, such as titanium nitride. The dielectric layer material may include a high-k dielectric material, such as lanthanum oxide (La₂O₃), aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), hafnium oxynitride (HfON), or hafnium silicate (HfSiO₂). x One or any combination of zirconium oxide (ZrO2) or zirconium oxide (ZrO2).

[0097] Please continue reading Figure 1a In this embodiment of the disclosure, the bit line structure 107 extends along the X-axis direction. Therefore, the word line structure extends along the Z-axis direction.

[0098] In other embodiments, the bit line structure may extend along the Z-axis, and the word line structure may extend along the X-axis.

[0099] The semiconductor structure provided in this disclosure includes multiple memory cells, each memory cell including at least a channel structure and a drain. Since the channel structure of the memory cell includes a first channel region and a second channel region of different sizes, and the electron mobility of the bulk material of the channel structure is greater than that of the bulk material of the drain, the gate-induced drain leakage current can be improved, thereby enhancing the electrical performance of the semiconductor structure.

[0100] This disclosure also provides a semiconductor structure. Figure 2a and Figure 2b This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure, wherein, Figure 2a For 3D views, Figure 2b for Figure 2a A cross-sectional view along the middle section b-b'. (See attached image.) Figure 2a and Figure 2b As shown, the semiconductor structure includes: a substrate (not shown); and memory cells 100 arranged in an array on the surface of the substrate along the X-axis and Z-axis directions. Figure 2a and Figure 2b(Only one memory cell is shown in the diagram); the memory cell 100 includes at least a source 105, a channel structure 101, and a drain 102 arranged along the Y-axis; the electron mobility of the bulk material of the channel structure 101 is greater than that of the bulk material of the drain 102. The channel structure 101 includes a third channel region 101c, a first channel region 101a, and a second channel region 101b; the first channel region 101a is located between the second channel region 101b and the third channel region 101c, the second channel region 101b is connected to the drain 102, and the third channel region 101c is connected to the source 105.

[0101] In some embodiments, please continue to see Figure 2a and 2b The memory cell 100 further includes a first lightly doped region 103 and a second lightly doped region 106; the size of the second channel region 101b decreases in the direction toward the first lightly doped region 103, and the electron mobility of the host material of the second channel region 101b is greater than the electron mobility of the host material of the drain 102. The size of the third channel region 101c decreases in the direction toward the second lightly doped region 106, and the electron mobility of the host material of the third channel region 101c is greater than the electron mobility of the host material of the source 105.

[0102] In this embodiment of the disclosure, please continue to refer to Figure 2a and 2b The size of the second channel region 101b in the Z-axis (or Y-axis) direction decreases along the direction toward the first lightly doped region 103, and the size of the third channel region 101c in the Z-axis (or Y-axis) direction decreases along the direction toward the second lightly doped region 106.

[0103] In this embodiment of the disclosure, please continue to refer to Figure 2a and 2b The size of the first lightly doped region 103 in the Z-axis (or Y-axis) direction is equal to the minimum size of the second channel region 101b in the Z-axis (or Y-axis) direction, and the size of the second lightly doped region 106 in the Z-axis (or Y-axis) direction is equal to the minimum size of the third channel region 101c in the Z-axis (or Y-axis) direction.

[0104] It should be noted that, in this embodiment of the present disclosure, the minimum size of the second channel region 101b and the minimum size of the third channel region 101c may be equal or unequal.

[0105] In some embodiments, the doping type of the first lightly doped region is the same as that of the second lightly doped region.

[0106] In this embodiment of the disclosure, the doping type of the first lightly doped region (or the second lightly doped region) is opposite to that of the first channel region, for example, both are N-type doped or both are P-type doped.

[0107] In other embodiments, the doping type of the first lightly doped region (or the second lightly doped region) is the same as the doping type of the first channel region, and the doping concentration of the first lightly doped region is greater than or equal to the doping concentration of the first channel region.

[0108] In some embodiments, please continue to see Figure 2a and 2b The memory cell 100 further includes a gate structure 104, which covers the channel structure 101 (i.e., the third channel region 101c, the first channel region 101a, and the second channel region 101b) and a portion of the first lightly doped region 103. The gate structure 104 includes a gate dielectric layer 104a and a gate conductive layer 104b located on the surface of the gate dielectric layer 104a.

[0109] In some embodiments, please continue to see Figure 2a and 2b The memory cell 100 also includes a bit line structure 106 connected to the source, a word line structure (not shown) connected to the gate structure 104, and a capacitor structure 108 connected to the drain 102 and extending along the Y-axis.

[0110] The semiconductor structure provided in this embodiment includes multiple memory cells, each memory cell including at least a channel structure and a drain. Since the channel structure of the memory cell includes a first channel region, a second channel region, and a third channel region of different sizes, and the electron mobility of the bulk material of the channel structure is greater than that of the bulk material of the drain, the gate-induced drain leakage current can be improved, the control capability of the gate structure can be enhanced, and thus the electrical performance of the semiconductor structure can be improved.

[0111] In addition, this disclosure also provides a method for forming a semiconductor structure. Figure 3 This is a schematic flowchart of a semiconductor structure formation method provided in an embodiment of the present disclosure, such as... Figure 3 As shown, the method for forming a semiconductor structure includes the following steps:

[0112] Step S301: Provide a substrate.

[0113] In this embodiment of the disclosure, the substrate may be a silicon substrate, or may include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof.

[0114] Step S302: Memory cells are arrayed along a first direction and a third direction on the substrate surface. Each memory cell includes at least a channel structure and a drain arranged along a second direction; the channel structure includes a first channel region and a second channel region; the electron mobility of the bulk material of the channel structure is greater than the electron mobility of the bulk material of the drain; the second channel region is connected to the drain, and the size of the second channel region is less than or equal to the size of the first channel region.

[0115] In some embodiments, the main material of the channel structure can be silicon-germanium, and the main material of the drain electrode can be silicon.

[0116] The semiconductor structure formed by the semiconductor structure formation method provided in this embodiment has two channel regions of different sizes, and the electron mobility of the main material of the channel structure is greater than that of the main material of the drain. Therefore, it can improve the gate-induced drain leakage current, improve the control capability of the gate structure, and thus improve the electrical performance of the semiconductor structure.

[0117] Figures 4a to 4j This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure. The following is in conjunction with... Figures 4a to 4j The formation process of the semiconductor structure provided in the embodiments of this disclosure will be described.

[0118] In some embodiments, forming memory cells arrayed along a first direction and a third direction on the substrate surface can be achieved through the following steps: forming initial active strips arrayed along the first direction and a third direction and extending along a second direction on the substrate surface; forming an initial channel structure in the initial active strips; the initial channel structure is located between the first initial active strips and the second initial active strips spaced apart along the second direction, and the electron mobility of the bulk material of the initial channel structure is greater than the electron mobility of the bulk material of the initial active strips; processing the initial channel structure to form a channel structure; and forming a drain and a source in the first initial active strip and the second initial active strip, respectively.

[0119] like Figure 4aAs shown, initial active strips 401 are formed in an array along the Y-axis and Z-axis directions on the surface of a substrate (not shown), with the initial active strips 401 extending along the Y-axis direction. The initial active strips can be P-type doped silicon with a doping concentration of 10⁻⁶. 15 atoms per square centimeter (cm) 2 ) to 10 18 atoms / cm 2 .

[0120] It should be noted that, for ease of understanding, Figure 4a Only one initial active strip 401 is shown in the image; subsequent active strips are shown later. Figures 4b-4j The process of forming a memory cell is illustrated using an initial active strip 401 as an example.

[0121] In some embodiments, forming an initial channel structure between initial active strips may include the following steps: forming a sacrificial structure in the gap between a plurality of initial active strips; etching the sacrificial structure and the initial active strips to form an etched groove extending along a first direction; the etched groove dividing the initial active strips into a first initial active strip and a second initial active strip; the etched groove exposing the sidewalls of the first initial active strip and the second initial active strip; and forming an initial channel structure epitaxially on the surface of the sidewalls exposed by the etched groove.

[0122] like Figure 4a and Figure 4b As shown, a sacrificial material is deposited in the gaps between multiple initial active strips 401 to form a sacrificial structure 402; the sacrificial structure 402 and the initial active strips 401 are etched to form an etched groove 403 extending along the X-axis direction, and the etched groove 403 divides the initial active strips 401 into a first initial active strip 401a and a second initial active strip 401b.

[0123] In some embodiments, the sacrificial material may be silicon oxide or silicon oxynitride. It should be noted that the initial active strip in the embodiments of this disclosure may be cubic or cylindrical.

[0124] In this embodiment, the initial active strip 401 can be silicon, and the etched groove 403 exposes the sidewalls of the first initial active strip 401a and the second initial active strip 401b along the Y-axis direction, that is, the etched groove 403 exposes the first initial active strip 401a and the second initial active strip 401b. <100> Crystal facets. For example... Figure 4d As shown, in the first initial active strip 401a and the second initial active strip 401b <100> Silicon-germanium material is epitaxially grown on the crystal plane to form the initial channel structure 404. It should be noted that, for ease of understanding, Figure 4d The sacrificial structure 402 is not shown in the diagram.

[0125] In some embodiments, after forming the initial channel structure 404, the method for forming the semiconductor structure further includes removing the remaining sacrificial structure 402. In embodiments of this disclosure, the remaining sacrificial structure can be removed by a wet etching process or a dry etching process.

[0126] In some embodiments, forming an initial channel structure between initial active strips may further include the following steps: etching the initial active strips to form a first initial active strip, a third initial active strip, and a second initial active strip arranged along a second direction; wherein the size of the third initial active strip is smaller than the size of the first initial active strip; and epitaxially forming an initial channel structure on the surface of the third initial active strip.

[0127] Etching Figure 4a The initial active strip 401 shown forms as follows: Figure 4c The first initial active strip 401a, the third initial active strip 401e, and the second initial active strip 401b are arranged along the Y-axis. The dimension of the third initial active strip 401e in the Z-axis (or X-axis) direction is smaller than the dimension of the first initial active strip 401a in the Z-axis (or X-axis) direction.

[0128] Please continue reading Figure 4d Silicon-germanium material is epitaxially grown on the surface of the third initial active strip 401e to form an initial channel structure 404.

[0129] In some embodiments, the electron mobility of the host material of the initial channel structure 404 is greater than that of the host material of the initial active strip 401.

[0130] In some embodiments, processing the initial channel structure to form the channel structure may include the following steps: forming a first photoresist layer (not shown) having a first preset pattern on the surfaces of the initial active strip 401 (i.e., the first initial active strip 401a and the second initial active strip 401b) and the initial channel structure 404; exposing the second initial active strip 401b and a portion of the initial channel structure 404 in contact with the second initial active strip through the first preset pattern; etching the exposed initial channel structure 404 and the second initial active strip 401b to correspondingly form as shown in the figure. Figure 4e The second channel region 101b and the second active strip 401c are shown; wherein, the unetched initial channel structure 404 constitutes the first channel region 101a; the first channel region 101a and the second channel region 101b together constitute the channel structure 101. The dimension of the second channel region 101b in the Z-axis (or Y-axis) direction decreases in the direction toward the second active strip 401c.

[0131] In this embodiment of the disclosure, the initial channel structure 404 and the second initial active strip 401b exposed by conventional inductively coupled plasma (ICP) such as carbon tetrafluoride (CF4), oxygen or helium can be continuously etched to form the second channel region 101b and the second active strip 401c.

[0132] In other embodiments, pulsed plasma quasi-atomic layer etching can be used to form quasi-atoms, and oxygen self-limiting oxidation, hydrogen fluoride or CF4 gas self-limiting selective etching can be used to form the second channel region 101b and the second active strip 401c.

[0133] In this embodiment, the size of the second channel region decreases along the direction toward the second active strip, which can reduce leakage current on the one hand, and is easier to implement in terms of process on the other hand.

[0134] In some embodiments, after forming the initial channel structure, the method for forming the semiconductor structure further includes: performing a second doping on the initial channel structure.

[0135] In this embodiment, the second doping can be P-type doping, for example, using trivalent impurity elements such as boron, gallium, and indium. In other embodiments, the second doping can also be N-type doping, for example, using pentavalent impurity elements such as phosphorus, antimony, and arsenic.

[0136] In some embodiments, the method for forming a semiconductor structure further includes forming a gate structure on the surface of the first channel region and the second channel region.

[0137] In such Figure 4e The surfaces of the first channel region 101a and the second channel region 101b shown are sequentially deposited with a gate dielectric material and a gate conductive material to form a structure as shown in the figure. Figure 4f The gate dielectric layer 104a and the gate conductive layer 104b located on the surface of the gate dielectric layer 104a are shown.

[0138] In this embodiment of the disclosure, the gate dielectric layer 104a and the gate conductive layer 401b can be formed by any suitable deposition process, such as chemical vapor deposition, physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, coating process, or furnace tube process.

[0139] In this embodiment of the disclosure, the gate dielectric layer may be silicon oxide or other suitable materials; the gate conductive material may be any material with good conductivity, such as any one or a combination of titanium, titanium nitride, tungsten, cobalt, platinum, and copper.

[0140] In some embodiments, forming a drain and a source in the first initial active strip and the second initial active strip respectively includes the following steps: performing a first heavy doping on the end of the first initial active strip away from the channel structure along the second direction to form a source; performing a first heavy doping on the end of the second active strip away from the channel structure along the second direction to form a drain.

[0141] like Figure 4g As shown, the end of the first initial active strip 401a away from the channel structure (or gate structure 104) along the Y-axis is first heavily doped to form the source 105; the end of the second active strip 401c away from the channel structure (or gate structure 104) along the Y-axis is first heavily doped to form the drain 102.

[0142] In this embodiment, the first doping can be either N-type ion doping or P-type ion doping. The first doping and the second doping have the same or opposite doping types. When the first doping and the second doping have the same doping type, a junctionless transistor is formed; when the first doping and the second doping have opposite doping types, a junction transistor is formed.

[0143] In some embodiments, the method for forming a semiconductor structure further includes: heat-treating the drain electrode to allow dopant ions from the first heavy doping process to diffuse to one end of the second active strip near the channel structure, forming a first lightly doped region; and heat-treating the source electrode to allow dopant ions from the first heavy doping process to diffuse to one end of the first initial active strip near the channel structure, forming a second lightly doped region. The size of the first lightly doped region is equal to the minimum size of the second channel region; the size of the second lightly doped region is equal to the size of the first channel region.

[0144] right Figure 4g The source 105 and drain 102 in the semiconductor structure shown are subjected to thermal annealing, which causes the doped ions in the source 105 and drain 102 to diffuse into the undoped first initial active strip 401a and second active strip 401c, respectively, forming a structure as shown. Figure 4h The second lightly doped region 106 and the first lightly doped region 103 are shown.

[0145] In this embodiment of the disclosure, by forming a second lightly doped region connected to the source and a second lightly doped region connected to the drain, the leakage current of the semiconductor structure can be reduced and the performance of the semiconductor structure can be improved.

[0146] In some embodiments, the method of forming a semiconductor structure further includes forming a gate structure on the surface of a first lightly doped region.

[0147] In this embodiment of the present disclosure, forming a gate structure on the surface of the first lightly doped region includes the following two cases: one is to form a gate structure on the surface of a portion of the first lightly doped region; the other is to form a gate structure on the surface of all the first lightly doped regions.

[0148] like Figure 4i As shown, a gate structure 104 is formed on the surface of a portion of the first lightly doped region 103.

[0149] In this embodiment of the present disclosure, forming a gate structure on the surface of the first lightly doped region can also be understood as the first lightly doped region extending into the channel structure. In this way, the overlap between the channel structure and the drain can be increased, thereby reducing the interband tunneling current of the fully depleted silicon transistor.

[0150] In some embodiments, the method for forming a semiconductor structure further includes: forming a bit line structure connected to the source; forming a word line structure connected to the gate structure; wherein the bit line structure extends along one of a first direction and a third direction, and the word line structure extends along the other of the first direction and the third direction.

[0151] In this embodiment of the disclosure, the word line structure and the bit line structure extend in different directions and intersect.

[0152] In some embodiments, the method for forming a semiconductor structure further includes: forming a capacitor structure that is connected to the drain and extends along a second direction.

[0153] like Figure 4j As shown, a bit line structure 107 is formed that is connected to the source 105 and extends along the X-axis; a capacitor structure 108 is formed that is connected to the drain 102 and extends along the Y-axis. The capacitor structure in this embodiment may include a first electrode layer, a dielectric layer, and a second electrode layer.

[0154] Figures 5a-5e This is another schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure, which is described below in conjunction with... Figures 5a-5e The formation process of the semiconductor structure provided in the embodiments of this disclosure will be described.

[0155] In some embodiments, while forming the second channel region and the second active strip, the first initial active strip and the portion of the initial channel structure in contact with the first initial active strip are etched to form the first active strip and the third channel region.

[0156] During implementation, in the formation of such Figure 4dAfter the initial channel structure 404 is shown, the method for forming the semiconductor structure may further include: forming a second photoresist layer (not shown) with a second preset pattern on the surfaces of the initial active strip 401 (i.e., the first initial active strip 401a and the second initial active strip 401b) and the initial channel structure 404; exposing the first initial active strip 401a, the portion of the initial channel structure 404 in contact with the first initial active strip, the second initial active strip 401b, and the portion of the initial channel structure 404 in contact with the second initial active strip; etching the exposed initial channel structure 404, the first initial active strip 401a, and the second initial active strip 401b to correspondingly form as shown. Figure 5a The third channel region 101c, the second channel region 101b, and the second active strip 401c are shown; wherein, the unetched initial channel structure 404 constitutes the first channel region 101a; the first channel region 101a, the second channel region 101b, and the third channel region 101c together constitute the channel structure 101.

[0157] In this embodiment of the disclosure, the size of the second channel region 101b in the Z-axis (or Y-axis) direction decreases along the direction toward the second active strip 401c, and the size of the third channel region 101c in the Z-axis (or Y-axis) direction decreases along the direction toward the first active strip 401d.

[0158] In this embodiment, the main material of the third channel region is silicon-germanium, and the main material of the source is silicon. The electron mobility of the main material of the third channel region is greater than that of the main material of the source, which allows for a greater number of conductive ions in the channel, thereby improving the controllability of the gate structure.

[0159] It should be noted that the etching process for forming the first channel region 101a, the second channel region 101b, and the third channel region 101c in this embodiment is the same as the process for forming the second channel region 101b and the third channel region 101c in the above embodiments. Please refer to the above embodiments for understanding.

[0160] Next, as Figure 5a As shown, gate dielectric material and gate conductive material are sequentially deposited on the surfaces of the third channel region 101c, the first channel region 101a, and the second channel region 101b to form a structure as shown in the figure. Figure 5b The gate dielectric layer 104a and the gate conductive layer 104b located on the surface of the gate dielectric layer 104a are shown.

[0161] In some embodiments, the method for forming a semiconductor structure further includes: performing a first heavy doping on one end of the first active strip away from the channel structure along the second direction to form a source; and performing a first heavy doping on one end of the second active strip away from the channel structure along the second direction to form a drain.

[0162] like Figure 5c As shown, the end of the first active strip 401d away from the channel structure (or gate structure 104) along the Y-axis is first heavily doped to form the source 105; the end of the second active strip 401c away from the channel structure (or gate structure 104) along the Y-axis is first heavily doped to form the drain 102.

[0163] In some embodiments, the method for forming a semiconductor structure further includes: heat-treating the drain electrode to allow dopant ions from the first heavy doping process to diffuse to one end of the second active strip near the channel structure, forming a first lightly doped region; and heat-treating the source electrode to allow dopant ions from the first heavy doping process to diffuse to one end of the first active strip near the channel structure, forming a second lightly doped region. The size of the first lightly doped region is equal to the minimum size of the second channel region; the size of the second lightly doped region is equal to the minimum size of the third channel region.

[0164] right Figure 5c The source 105 and drain 102 in the semiconductor structure shown are subjected to thermal annealing, which causes the doped ions in the source 105 and drain 102 to diffuse into the undoped first active strip 401d and second active strip 401c, respectively, forming a structure as shown. Figure 5d The second lightly doped region 106 and the first lightly doped region 103 are shown.

[0165] In some embodiments, the method of forming a semiconductor structure further includes: forming a gate structure on the surface of a first lightly doped region. For example... Figure 5d As shown, a structure is formed on the surface of a portion of the first lightly doped region 103. Figure 5e The gate structure 104 shown is shown.

[0166] In some embodiments, please continue to see Figure 5e The method for forming a semiconductor structure further includes: forming a bit line structure 107 connected to the source 105; forming a word line structure (not shown) connected to the gate structure 104; and forming a capacitor structure 108 connected to the drain 102 and extending along the Y-axis.

[0167] It should be noted that in this embodiment, the word line structure and the bit line structure extend in different directions and intersect. For example, the word line structure extends along a third direction, and the bit line structure extends along a first direction; or, the word line structure extends along the first direction, and the bit line structure extends along a third direction.

[0168] The semiconductor structure formed by the semiconductor structure formation method provided in this embodiment has three channel regions of different sizes, and the electron mobility of the main material of the channel structure is greater than that of the main material of the drain or source. On the one hand, it can improve the gate-induced drain leakage current and improve the electrical performance of the semiconductor structure. On the other hand, it can also reduce the leakage current of the semiconductor structure during the pre-charging process.

[0169] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and other division methods may be used in actual implementation. Furthermore, the components shown or discussed are coupled or directly coupled to each other. The features disclosed in the several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or structural embodiments.

[0170] The above are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, At least including: Substrate; A memory cell is located on the surface of the substrate and arranged in an array along a first direction and a third direction; the memory cell includes at least a channel structure and a drain arranged along a second direction; the channel structure includes a first channel region and a second channel region; the electron mobility of the bulk material of the channel structure is greater than the electron mobility of the bulk material of the drain. The second channel region is connected to the drain electrode, and the size of the second channel region is less than or equal to the size of the first channel region.

2. The semiconductor structure according to claim 1, characterized in that, The memory cell further includes: a first lightly doped region located between the drain and the second channel region, and a gate structure covering the channel structure and the surface of the first lightly doped region; The gate structure includes a gate dielectric layer and a gate conductive layer located on the surface of the gate dielectric layer; The size of the second channel region decreases in the direction toward the first lightly doped region, and the size of the first lightly doped region is equal to the minimum size of the second channel region.

3. The semiconductor structure according to claim 2, characterized in that, The memory cell further includes a source and a second lightly doped region located between the source and the first channel region; The size of the second lightly doped region is equal to the size of the first channel region.

4. The semiconductor structure according to claim 2, characterized in that, The channel structure further includes a third channel region connected to the first channel region; the memory cell further includes a source and a second lightly doped region located between the source and the third channel region; The size of the third channel region decreases toward the second lightly doped region, and the electron mobility of the host material of the third channel region is greater than that of the host material of the source electrode; the size of the second lightly doped region is equal to the minimum size of the third channel region.

5. The semiconductor structure according to claim 4, characterized in that, The doping type of the first lightly doped region is the same as the doping type of the second lightly doped region; The doping type of the first lightly doped region is opposite to that of the first channel region, or the doping type of the first lightly doped region is the same as that of the first channel region, and the doping concentration of the first lightly doped region is greater than or equal to the doping concentration of the first channel region.

6. The semiconductor structure according to claim 4, characterized in that, The size of the source is equal to the size of the second lightly doped region; Furthermore, the size of the drain is equal to the size of the first lightly doped region.

7. The semiconductor structure according to claim 3, characterized in that, The first direction and the second direction are any two directions within the plane containing the substrate, and the third direction is perpendicular to the plane containing the substrate; The memory cell further includes a bit line structure connected to the source, a word line structure connected to the gate structure, and a capacitor structure connected to the drain and extending along the second direction. The bit line structure extends along one of the first direction and the third direction, and the word line structure extends along the other of the first direction and the third direction.

8. A method for forming a semiconductor structure, characterized in that, The method includes: Provide substrate; A memory cell array is formed on the surface of the substrate along a first direction and a third direction; the memory cell includes at least a channel structure and a drain arranged along a second direction; the channel structure includes a first channel region and a second channel region; the electron mobility of the bulk material of the channel structure is greater than the electron mobility of the bulk material of the drain. The second channel region is connected to the drain electrode, and the size of the second channel region is less than or equal to the size of the first channel region.

9. The method according to claim 8, characterized in that, The memory cell further includes a source electrode; memory cells are arrayed along a first direction and a third direction on the substrate surface, including: An initial active stripe is formed on the substrate surface, arranged in an array along the first direction and the third direction, and extending along the second direction; An initial channel structure is formed in the initial active strip; the initial channel structure is located between the first and second initial active strips arranged at intervals along the second direction, and the electron mobility of the bulk material of the initial channel structure is greater than the electron mobility of the bulk material of the initial active strip; The initial channel structure is processed to form the channel structure; The drain and the source are formed in the first initial active strip and the second initial active strip, respectively.

10. The method according to claim 9, characterized in that, The process of processing the initial channel structure to form the channel structure includes: A first photoresist layer having a first preset pattern is formed on the surfaces of the initial active strip and the initial channel structure; the first preset pattern exposes the second initial active strip and a portion of the initial channel structure in contact with the second initial active strip; The initial channel structure and the second initial active strip exposed by etching correspond to form the second channel region and the second active strip; wherein, the initial channel structure that is not etched constitutes the first channel region; the size of the second channel region decreases in the direction toward the second active strip.

11. The method according to claim 10, characterized in that, The channel structure further includes: a third channel region; the method further includes: While forming the second channel region and the second active strip, the first initial active strip and the portion of the initial channel structure in contact with the first initial active strip are etched to form the first active strip and the third channel region. The size of the third channel region decreases in the direction toward the first active strip, and the electron mobility of the bulk material of the third channel region is greater than that of the bulk material of the source electrode.

12. The method according to claim 11, characterized in that, The drain and the source are formed in the first initial active strip and the second initial active strip, respectively, including: The first initial active strip or the end of the first active strip away from the channel structure along the second direction is subjected to a first heavy doping to form the source electrode; The second active strip is subjected to the first heavy doping at the end away from the channel structure along the second direction to form the drain.

13. The method according to claim 12, characterized in that, The method further includes: The drain electrode is heat-treated so that the doped ions in the first heavy doping process diffuse to one end of the second active strip near the channel structure to form a first lightly doped region. Wherein, the size of the first lightly doped region is equal to the minimum size of the second channel region; The source electrode is heat-treated to allow the doped ions from the first heavy doping process to diffuse to the first initial active strip or to one end of the first active strip near the channel structure, forming a second lightly doped region; wherein the size of the second lightly doped region is equal to the size of the first channel region, or the size of the second lightly doped region is equal to the minimum size of the third channel region.

14. The method according to claim 13, characterized in that, Before forming the source and the drain, the method further includes: A gate structure is formed on the surface of the first channel region and the second channel region; or, The gate structure is formed on the surfaces of the first channel region, the second channel region, and the third channel region; the gate structure includes a gate dielectric layer and a gate conductive layer located on the surface of the gate dielectric layer.

15. The method according to claim 14, characterized in that, The method further includes: The gate structure is formed on the surface of the first lightly doped region.

16. The method according to claim 14 or 15, characterized in that, The initial channel structure is formed through the following steps: A sacrificial structure is formed in the gap between the plurality of the initial active strips; The sacrificial structure and the initial active strip are etched to form an etched groove extending along the first direction; the etched groove divides the initial active strip into a first initial active strip and a second initial active strip; The etched grooves expose the sidewalls of the first initial active strip and the second initial active strip; The initial channel structure is formed by extending the sidewall surface exposed by the etched groove.

17. The method according to claim 16, characterized in that, After forming the initial channel structure, the method further includes: The initial channel structure is subjected to a second doping; wherein the first doping and the second doping are of the same or opposite doping types.

18. The method according to claim 17, characterized in that, The first direction and the second direction are any two directions within the plane containing the substrate, and the third direction is perpendicular to the plane containing the substrate; the method further includes: A bitline structure is formed that is connected to the source electrode; A word line structure is formed in connection with the gate structure; wherein the bit line structure extends along one of the first direction and the third direction, and the word line structure extends along the other of the first direction and the third direction; A capacitor structure is formed that is connected to the drain and extends along the second direction.

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