A sample stage apparatus for semiconductor structure testing

Abstract

The utility model discloses an embodiment of the utility model discloses a kind of sample stage devices for semiconductor structure test, the sample stage device is composed of preset quantity height different sample stage, the preset quantity height different sample stage is arranged in ladder shape, and at least one sample groove for fixing the semiconductor structure to be tested is provided in each the sample;The preset quantity is greater than or equal to 2.The utility model is by setting the number of sample stage in sample stage device is at least two, and the height of each sample stage is different, when the semiconductor structure is tested, the sample of different height can only be tested in batches, the problem of affecting test efficiency and test data consistency is solved, improve test efficiency, guarantee the consistency of test data.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor structure testing, and in particular to a sample stage device for semiconductor structure testing. Background Technology

[0002] In the field of semiconductor manufacturing, electron microscopes (EM) are widely used as high-precision inspection equipment to detect and analyze the microstructure, material properties, and manufacturing processes of semiconductor devices. However, due to the complex structure of semiconductor samples, their height can vary significantly depending on different manufacturing steps, material stacking, or design requirements, resulting in different sample heights.

[0003] In the prior art, the sample stage device used for semiconductor structure testing has a fixed structure, which means that samples of different heights need to be placed into the machine in batches. This not only results in low testing efficiency but also affects the consistency of test data, causing problems such as wear and tear on the testing equipment and increased maintenance costs.

[0004] Therefore, it is particularly important to provide a sample stage device that can be used for testing semiconductor structures of different heights. Utility Model Content

[0005] To address the problems existing in the prior art, this utility model solves the problem that samples of different heights can only be tested in batches when testing semiconductor structures by setting the sample stage device to have at least two sample stages with different heights, which affects testing efficiency and test data consistency. This improves testing efficiency and ensures the consistency of test data.

[0006] On the one hand, this utility model provides a sample stage device for semiconductor structure testing. The sample stage device consists of a preset number of sample stages of different heights, which are arranged in a stepped manner, and each sample stage is provided with at least one sample slot for fixing the semiconductor structure to be tested; the preset number is greater than or equal to 2.

[0007] In some possible implementations, the sample groove includes a first support surface and a second support surface, the first support surface and the second support surface intersect, and the included angle between the first support surface and the second support surface is between 90° and 135°.

[0008] In some possible implementations, the first support surface and the second support surface intersect perpendicularly, and the angle between the first support surface and the opening of the sample groove, and the angle between the second support surface and the opening of the sample groove, are both 45°.

[0009] In some possible implementations, a sample fixing device is also provided in the sample cell, and the sample fixing device is movably disposed at the center of the sample cell.

[0010] In some possible implementations, the sample fixing device is a bolt.

[0011] In some possible implementations, the depth of the sample groove is less than the height of the sample stage, and the distance between the bottom of the sample groove and the bottom of the sample stage is 1 mm to 2 mm.

[0012] In some possible implementations, each of the sample stages is provided with a plurality of sample slots spaced apart, and the interval between adjacent sample slots is 1 mm to 2 mm.

[0013] In some possible implementations, the top view of the sample stage device is any one of a square, rectangle, or circle.

[0014] In some possible implementations, when the top view of the sample stage device is a square, the side length of the square is between 3cm and 10cm; when the top view of the sample stage device is a rectangle, the side length of the rectangle is between 3cm and 10cm; when the top view of the sample stage device is a circle, the diameter of the circle is between 3cm and 15cm.

[0015] In some possible implementations, the width of the sample slot in each of the sample stages is greater than the thickness of the semiconductor structure under test.

[0016] The above-mentioned technical solution provided by this utility model has the following beneficial effects: This invention discloses a sample stage device for semiconductor structure testing. The sample stage device consists of a predetermined number of sample stages of different heights, arranged in a stepped manner. Each sample stage contains at least one sample slot for fixing the semiconductor structure to be tested. The predetermined number is greater than or equal to two. By setting the sample stage device to have at least two sample stages of different heights, this invention solves the problem that samples of different heights can only be tested in batches, affecting testing efficiency and data consistency, thus improving testing efficiency and ensuring data consistency. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a sample stage device for semiconductor structure testing provided in an embodiment of this application.

[0019] Figure 2 In existing technology <100> A schematic diagram of a cleaved wafer.

[0020] Figure 3 In existing technology <100> SEM image of a crystal-oriented wafer after direct cleaving.

[0021] Figure 4 It is the existing technology for <100> A schematic diagram of chamfering the crystal-oriented wafer.

[0022] Figure 5 It is the existing technology for <100> Another schematic diagram of chamfering on a crystal-oriented wafer.

[0023] Figure 6 This is a schematic diagram of the structure of a scanning inspection sample stage used for wafer testing in the prior art.

[0024] Figure 7 For wafer edge <100> Schematic diagram of the grinding sample in the directional section.

[0025] Figure 8 This is another schematic diagram of the sample stage device for semiconductor structure testing provided in the embodiments of this application.

[0026] Figure 9 This is a top view of a sample stage device provided in an embodiment of this application. Figure 1 .

[0027] Figure 10 This is a top view of a sample stage device provided in an embodiment of this application. Figure 2 .

[0028] Figure 11 This is a top view of a sample stage device provided in an embodiment of this application. Figure 3 .

[0029] Figure 12 This is a top view of a sample stage device provided in an embodiment of this application. Figure 4 .

[0030] Figure 13This is a top view of a sample stage device provided in an embodiment of this application. Figure 5 .

[0031] Figure 14 This is a schematic diagram of the structure of a specific sample stage device provided in an embodiment of this application.

[0032] The corresponding reference numerals in the figure are: 1-Sample stage; 2-Sample groove; 21-First support surface; 22-Second support surface; 3-Sample fixing device. Detailed Implementation

[0033] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0034] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this application. In the description of this application, it should be understood that the terms "upper," "lower," "top," "bottom," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein.

[0035] When a numerical range is disclosed herein, the range is considered continuous and includes the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to an integer, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe a feature or characteristic, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are included. For example, a specified range from “1 to 10” should be considered to include any and all subranges between the minimum value 1 and the maximum value 10. Exemplary subranges of the range 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0036] To address the problem that samples of different heights can only be tested in batches when testing semiconductor structures, which affects testing efficiency and data consistency, this utility model provides a sample stage device for semiconductor structure testing. The sample stage device consists of a preset number of sample stages of different heights, which are arranged in a stepped manner, and each sample stage is provided with at least one sample slot for fixing the semiconductor structure to be tested; the preset number is greater than or equal to 2.

[0037] For example, such as Figure 1 As shown, the sample stage device includes at least two sample stages 1, each with a different height. The at least two sample stages 1 are arranged along a first direction, and adjacent sample stages 1 are connected together, thus creating a stepped arrangement. Here, the first direction refers to the direction perpendicular to the step formed by adjacent sample stages 1. Each sample stage 1 has at least one sample slot 2, which is used to accommodate and fix the semiconductor structure to be tested. This allows for the simultaneous testing of multiple semiconductor structures of different heights, improving testing efficiency and effectively enhancing data consistency.

[0038] Optionally, the preset quantity is ≥2, and can be any value such as 2, 3, or 4, which can be designed according to actual needs. For example, in order to reduce the difficulty of testing operations and the manufacturing difficulty of the sample stage device, it is preferable to set the number of sample stages 1 to two, that is, including a first sample stage and a second sample stage. The height of the first sample stage and the height of the second sample stage are different. The first sample stage is set on one side of the second sample stage, and the sample slots 2 in the first sample stage and the sample slots 2 in the second sample stage are arranged in parallel. This can prevent the semiconductor structure under test placed in the first sample stage from contacting or colliding with the semiconductor structure under test placed in the second sample stage during the test. Moreover, the first support surface 21 and the second support surface 22 of the sample slot 2 are both perpendicular to the arrangement direction of the sample stage 1.

[0039] Optionally, the sample stages 1 can be fixedly or movably connected. Specifically, the sample stage assembly can be manufactured using a one-piece molding process, allowing the sample stages 1 to be fixedly connected; alternatively, the sample stage assembly can be composed of movably connected sample stages 1. Manufacturing the entire sample stage assembly using a one-piece molding process can improve the structural stability of the sample stage assembly, while using movably connected methods can improve the structural flexibility, allowing for flexible selection of sample stages 1 for assembly based on the height of the semiconductor structure to be tested.

[0040] Optionally, for ease of manufacturing, the sample stage device is made of aluminum.

[0041] Furthermore, in the semiconductor manufacturing field, wafers are... <100> Crystal-directed VDMOS has the highest carrier mobility and the fewest interface states, so it is preferred for fabrication of Power VDMOS (Power Vertical Double-diffused Metal-Oxide Semiconductor). <100> Wafers with crystal orientation (100) plane, but <100> A wafer with a specific crystal orientation will split at a 45-degree angle along the wafer notch during dicing (e.g., Figure 2 As shown), this results in a side shadow when observed directly with a scanning electron microscope (e.g. Figure 3 As shown), this results in inaccurate measurements. In existing technology, to improve the measurement inaccuracy caused by the observation shadows resulting from the dicing, the bottom of the sample is chamfered after dicing (e.g., ...). Figure 4 As shown in the diagram, then along... <100> The crystal orientation is then processed by grinding until the section of interest is reached. However, this method, due to uneven stress during the chamfering process, can cause the bottom sections to not be on the same horizontal plane (e.g., Figure 5 As shown), while the current sample stages used for accommodating wafer testing have flat-bottomed recesses (such as...). Figure 6 As shown), this allows for the loading of samples with uneven bottoms (such as...). Figure 5 and Figure 7 When handling the sample shown, instability can occur, causing the sample to easily fall off the stage and resulting in abnormal shutdown of the scanning electron microscope.

[0042] Regarding the semiconductor structure manufacturing process, <100> Wafers with crystal orientation require chamfering before polishing. However, chamfering can easily cause the bottom surface of the wafer to be uneven, which may lead to it falling during testing by scanning electron microscopes or other testing equipment, causing abnormal downtime of the testing equipment, resulting in wasted time and sample problems. This application provides a sample stage device for semiconductor structure testing, which is equipped with... <100> The sample slot 2 is designed to fit the wafer in a crystal orientation, thereby reducing the risk of sample drop. The sample slot 2 includes a first support surface 21 and a second support surface 22, which intersect perpendicularly, and the included angle between the first support surface 21 and the second support surface 22 is 90°-135°.

[0043] Specifically, such as Figure 1 As shown, the sample stage device includes a sample stage 1 and at least one sample slot 2 disposed in the sample stage 1. The sample slot 2 is used to accommodate and fix the semiconductor structure to be tested. The opening of the sample slot 2 is located on the top surface of the sample stage 1. In order to enable the sample slot 2 to align with the cleaved semiconductor structure... <100> The crystal orientation of the wafer has a limiting function, and the first support surface 21 and the second support surface 22 are set with an included angle of 90°-135°, that is... Figure 1 The range of α in the sample is 90°-135°. This ensures the stability of the sample during testing and prevents the sample from falling out. As a result, the semiconductor structure does not require chamfering during the polishing process. The cleaved wafer structure can be directly placed into sample slot 2 for testing, thereby reducing the number of process steps.

[0044] In one specific embodiment, the included angle between the first support surface 21 and the opening of the sample groove 2, and the included angle between the second support surface 22 and the opening of the sample groove 2 are both 45°.

[0045] Specifically, such as Figure 8 As shown, the sample stage device is suitable for... <100> For wafer testing with crystal orientation, the side structure of sample slot 2 is set as an isosceles right triangle. Specifically, sample slot 2 includes a first support surface 21 and a second support surface 22, which intersect perpendicularly, forming a 90° angle. Furthermore, the angle between the first support surface 21 and the opening of sample slot 2, and the angle between the second support surface 22 and the opening of sample slot 2, are both 45°, allowing sample slot 2 to fit snugly. Figure 6 shown <100> A wafer structure with crystal orientation. Thus, it is used simultaneously for the structure of sample slot 2 and <100> The bottom structure of the wafer with the crystal orientation is attached, which reduces the risk of sample falling out, avoids abnormal shutdown of the test equipment, and improves test efficiency.

[0046] This embodiment of the invention does not impose a specific limit on the height of the sample stage 1, which can be set according to actual needs.

[0047] In an optional embodiment, the height difference between any two sample stages 1 in the sample stage device is between 0.06 mm and 20 mm; the depth of the sample groove 2 is less than the height of the sample stage 1, and the distance between the bottom of the sample groove 2 and the bottom of the sample stage 1 is between 1 mm and 2 mm.

[0048] For example, the depth of sample groove 2 refers to the distance between the bottom edge of sample groove 2, formed by the perpendicular intersection of the first support surface 21 and the second support surface 22, and the surface of sample groove 2. The depth of sample groove 2 is set to be less than the height of sample stage 1, and a 1mm to 2mm gap is provided between the bottom of sample groove 2 and the bottom of sample stage 1 to facilitate quick sample replacement by the operator. The depth of sample groove 2 being less than the height of sample stage 1 reduces sample movement during placement and improves imaging accuracy.

[0049] Furthermore, to enable the sample stage device to test semiconductor structures of different heights, the height difference between any two sample stages 1 is between 0.06 mm and 20 mm. Optionally, to make the sample stage device suitable for testing samples of more sizes, the height difference between any two sample stages 1 can be greater than 20 mm, depending on actual needs.

[0050] In one exemplary embodiment, a sample fixing device 3 is further provided in the sample cell 2, and the sample fixing device 3 is movably disposed at the center of the sample cell 2.

[0051] In one exemplary embodiment, the sample fixing device 3 is a bolt.

[0052] like Figure 7 As shown, to further improve the stability of the semiconductor structure under test and reduce the risk of sample falling during testing, a sample fixing device 3 is provided in the sample slot 2, and the sample fixing device 3 is located at the center of the sample slot 2. The sample slot fixing device 3 is movably connected to the sample slot 2. The center of the sample slot 2 refers to the center of the projection of the sample slot in the first direction. The projection of the sample slot in the first direction is a triangle, and the center of the sample slot 2 is the center of this triangle.

[0053] For example, the sample fixing device 3 can be a bolt.

[0054] Optionally, the sample fixing device 3 can also adopt a magnetic fixing device, a vacuum adsorption fixing device, an electrostatic adsorption fixing device, or other structures.

[0055] In one exemplary embodiment, each of the sample stages 1 is provided with a plurality of sample slots 2 spaced apart, and the interval between adjacent sample slots 2 is 1mm to 2mm.

[0056] like Figure 9 As shown, in order to achieve batch testing of samples, and to simultaneously test samples of different heights, multiple samples of the same height are tested at one time. Multiple sample slots 2 are set on each sample stage 1, and in order to prevent the test samples from interfering with each other, a gap of 1mm to 2mm is set between adjacent sample slots 2.

[0057] Optionally, all sample stages 1 in the sample stage assembly are arranged parallel to each other.

[0058] Optionally, multiple sample slots 2 can be arranged along a first direction in the same sample stage 1 (e.g., Figure 9 As shown), it can also be arranged along the second direction (such as...). Figure 10 (as shown), or arranged simultaneously along the first and second directions (as shown). Figure 11 As shown in the figure, this application does not impose specific restrictions on this. Here, the first direction refers to the direction perpendicular to the step formed by the adjacent sample stage 1, that is, the arrangement direction of the sample stage 1. The second direction refers to the direction parallel to the step formed by the adjacent sample stage 1. The first direction and the second direction are perpendicular.

[0059] In one exemplary embodiment, the top view of the sample stage device is any one of a square, rectangle, or circle.

[0060] In one exemplary embodiment, when the top view of the sample stage device is a square, the side length of the square is between 3cm and 10cm; when the top view of the sample stage device is a rectangle, the side length of the rectangle is between 3cm and 10cm; when the top view of the sample stage device is a circle, the diameter of the circle is between 3cm and 15cm.

[0061] For example, the top view of the sample stage device provided in this application embodiment can be any one of a square, rectangle or circle. Optionally, the top view of the sample stage device can also be other shapes, such as a semicircle, trapezoid, etc. This utility model embodiment does not specifically limit this and can be set according to actual needs.

[0062] In one specific embodiment Figure 12 This is a top view of a sample stage device provided in an embodiment of this application, as shown below. Figure 12 As shown, the top view of the sample stage device is a square. In this case, the side length of the square can be set between 3cm and 10cm. Of course, it can also be set to other sizes according to actual needs. When the top view of the entire sample stage device is a square, the top view of each sample stage 1 is a rectangle, arranged along any side length of the square.

[0063] In a specific embodiment, such as Figures 9-11 As shown, the top view of the sample stage device is rectangular. In this case, the side length of the rectangle can be set between 3cm and 10cm. Of course, it can also be set to other sizes according to actual needs. When the top view of the entire sample stage device is rectangular, the top view of each sample stage 1 is rectangular or square, and they are arranged along any side of the rectangle.

[0064] In one specific embodiment Figure 13 This is a top view of a sample stage device provided in an embodiment of this application, as shown below. Figure 14 As shown, the top view of the sample stage device is circular. In this case, the diameter of the circle can be set between 3cm and 15cm. Of course, it can also be set to other sizes according to actual needs. When the top view of the entire sample stage device is circular, the sample stage 1 includes a lens-shaped shape composed of arcs and straight lines, as well as an arc-shaped shape, and each sample stage 1 is arranged along the diameter direction of the circle.

[0065] It should be noted that in this embodiment of the invention, the width of each sample stage 1, i.e., the length of the sample stage 1 in the arrangement direction of the sample stages 1, is not specifically limited and can be set according to actual testing requirements. Furthermore, the number of sample slots 2 on each sample stage 1 can be set to be the same or different.

[0066] In one exemplary embodiment, the width of the sample slot 2 in each of the sample stages 1 is greater than the thickness of the semiconductor structure under test.

[0067] In one exemplary embodiment, when the sample stage device includes two sample stages 1, the heights of the two sample stages 1 are 6 mm and 13 mm, respectively.

[0068] Specifically, the width of the sample groove 2 can be set according to the thickness of the semiconductor structure to be tested, as long as the width of the sample groove 2 is greater than the thickness of the semiconductor structure to be tested. Preferably, the width of the sample groove 2 is set to be 1mm-2mm larger than the thickness of the semiconductor structure to be tested.

[0069] like Figure 14As shown in the illustration, this application provides a specific sample stage device, which includes a first sample stage with a first height of 13 mm and a second sample stage with a second height of 6 mm. The two sample stages of different heights can meet the need for simultaneous imaging of samples at different heights. For example, samples undergoing fixed-point dyeing can be placed on the first sample stage, while samples undergoing ordinary polishing can be placed on the second sample stage. Furthermore, in this sample stage device, the width and length of the first and second sample stages are equal, with a width of 40 mm and a length of 50 mm.

[0070] The technical solution of this utility model has the following beneficial effects: 1. This utility model solves the problem that samples of different heights can only be tested in batches when testing semiconductor structures by setting the sample stage device to have at least two sample stages 1, and each sample stage 1 has a different height. This improves the testing efficiency and ensures the consistency of the test data.

[0071] 2. By setting the first support surface 21 and the second support surface 22 to have an included angle of 90°-135°, this utility model ensures the stability of the sample during the test and prevents the sample from falling. As a result, the semiconductor structure does not need to be chamfer during the polishing process. The wafer structure after cleaving can be directly placed into the sample slot 2 for testing, thereby reducing the number of process steps.

[0072] 3. This utility model sets the first support surface 21 and the second support surface 22 of the sample groove 2 to intersect perpendicularly. The included angle between the first support surface 21 and the opening of the sample groove 2, and the included angle between the second support surface 22 and the opening of the sample groove 2, are both 45°. This makes the internal structure of the sample groove 2 an isosceles right triangle, allowing the sample groove 2 to fit snugly. <100> The structure after wafer dicing with crystal orientation. This eliminates the need for chamfering during polishing of the semiconductor structure; the diced wafer structure can be directly placed into sample slot 2 for testing, reducing process steps. This also benefits the structure of sample slot 2 and... <100> The bottom structure of the wafer with the crystal orientation is attached, which reduces the risk of sample falling out, avoids abnormal shutdown of the test equipment, and improves test efficiency.

[0073] 4. This utility model features a 1mm to 2mm gap between the bottom of the sample slot 2 and the bottom of the sample stage 1, facilitating quick sample replacement by the operator. The depth of the sample slot 2 is less than the height of the sample stage 1, reducing sample movement during placement and improving imaging accuracy.

[0074] 5. By setting up the sample fixing device 3, this utility model further improves the fixing stability of the semiconductor structure to be tested and further reduces the risk of the sample falling off during the test.

[0075] 6. This utility model, by setting multiple sample slots 2 on each sample stage 1, enables simultaneous testing of samples of different heights, while also enabling simultaneous testing of multiple samples of the same height at one time.

[0076] The above description is only an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A sample stage apparatus for semiconductor structure testing, characterized by, The sample stage device consists of a preset number of sample stages of different heights, which are arranged in a stepped manner, and each sample stage is provided with at least one sample slot for fixing the semiconductor structure to be tested; the preset number is greater than or equal to 2.

2. The sample stage apparatus of claim 1, wherein, The sample well includes a first support surface and a second support surface, the first support surface and the second support surface intersect, and the included angle between the first support surface and the second support surface is between 90° and 135°.

3. The sample stage apparatus of claim 2, wherein, The first support surface and the second support surface intersect perpendicularly, and the angle between the first support surface and the opening of the sample groove and the angle between the second support surface and the opening of the sample groove are both 45°.

4. The sample stage apparatus of claim 1, wherein, The sample cell is also provided with a sample fixing device, which is movably positioned at the center of the sample cell.

5. The sample stage apparatus of claim 4, wherein, The sample fixing device is a bolt.

6. The stage apparatus of any of claims 1-5, wherein, The depth of the sample groove is less than the height of the sample stage, and the distance between the bottom of the sample groove and the bottom of the sample stage is 1mm to 2mm.

7. The stage apparatus of any of claims 1-5, wherein, Each of the sample stages is provided with a plurality of sample slots spaced apart, and the interval between adjacent sample slots is 1 mm to 2 mm.

8. The sample stage apparatus according to any one of claims 1-5, characterized in that, The top view of the sample stage device is any one of a square, rectangle, or circle.

9. The sample stage apparatus of claim 8, wherein, When the top view of the sample stage device is a square, the side length of the square is between 3cm and 10cm; when the top view of the sample stage device is a rectangle, the side length of any side of the rectangle is between 3cm and 10cm; when the top view of the sample stage device is a circle, the diameter of the circle is between 3cm and 15cm.

10. The stage apparatus of any of claims 1-5, wherein, The width of the sample slot in each of the sample stages is greater than the thickness of the semiconductor structure under test.

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