A microelectromechanical sensor
Patent Information
- Application Number
- CN202522480498.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-21
- Publication Date
- 2026-11-03
- Estimated Expiration
- 2035-11-21
AI Technical Summary
In existing microelectromechanical sensors, the presence of parasitic capacitance leads to reduced signal detection accuracy and sensitivity, affecting the performance of the accelerometer.
A buried layer is introduced between the detection electrode and the substrate, and the vertical distance between the detection electrode and the substrate is increased by the stacked second and third insulating layers, thereby reducing the parasitic capacitance.
This effectively reduces the parasitic capacitance between the detection electrode and the substrate, thereby improving the sensitivity of the microelectromechanical sensor.
Smart Images
Figure CN224930295U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to a microelectromechanical sensor. Background Technology
[0002] In many control, detection, and navigation systems for moving objects, information on displacement, angular displacement, and velocity is needed, as well as acceleration and angular velocity. Microelectromechanical sensors (including accelerometers and angular velocity sensors) are instruments used to measure acceleration and angular velocity.
[0003] Since the late 1980s, with the development of MEMS (Micro-Electro-Mechanical System) technology, various sensors have achieved miniaturization. MEMS microelectromechanical sensors, based on MEMS technology, have achieved mass production due to the use of MEMS fabrication processes, overcoming the shortcomings of traditional microelectromechanical sensors such as large size and high cost, and have become the main direction of future development. Bulk micromachining, surface micromachining, and special micromachining are three important micromachining technologies in the MEMS field. Bulk micromachining involves etching the silicon substrate along its thickness direction (including wet etching and dry etching), and it is an important method for realizing three-dimensional structures. Special micromachining refers to technologies used in MEMS manufacturing, such as bonding, LIGA (Lithographie, Galvanoformung, and Abformung, i.e., photolithography, electroforming, and injection molding; LIGA is a MEMS fabrication technology based on X-ray photolithography), electroplating, soft lithography, and micromold casting. Surface micromachining technology employs processes such as thin film deposition, photolithography, and etching to deposit polycrystalline silicon thin films on a sacrificial layer, and then utilizes the sacrificial layer to release structural layers to achieve movable structures. In other words, surface micromachining technology "builds" microstructures on the surface of a silicon substrate and achieves complex wiring connections.
[0004] MEMS (Micro-Electro-Mechanical Systems) sensors fabricated using surface treatments utilize silicon wafers as a substrate, forming three-dimensional micromechanical structures through multiple thin-film depositions and patterning processes. Commonly used thin-film materials include polycrystalline silicon, silicon nitride, silicon dioxide, and metals. Because silicon dioxide and silicon nitride films are grown using deposition methods, their thickness is limited; achieving thicknesses greater than 5 μm is difficult. Furthermore, these films generate significant residual stress during deposition and annealing processes, leading to phenomena such as cracking. Therefore, silicon dioxide and silicon nitride films cannot be excessively thick.
[0005] Surface-mount microelectromechanical sensors (MEMS) can include: a substrate, an insulating layer (e.g., a SiO2 layer), wiring polysilicon, a sacrificial layer (e.g., a SiO2 layer), a polycrystalline movable mass, and a metal layer. The wiring polysilicon and the substrate silicon, and the movable mass and the substrate silicon, form parasitic capacitances. The presence of parasitic capacitance has many negative impacts on the performance of capacitive accelerometers. Parasitic capacitance increases circuit noise, interferes with normal signal detection, and reduces the accuracy of the detected signal. It reduces the sensitivity of the capacitive accelerometer; parasitic capacitance is equivalent to adding an extra capacitor in parallel with the detection capacitor, making the actual detected capacitance change relatively smaller, thus weakening the accelerometer's response to acceleration changes. Taking a charge amplifier circuit as an example, parasitic capacitance forms an extra signal path between the inverting input of the operational amplifier and the signal ground. During the transfer of charge from the measured capacitor to the feedback capacitor, some charge transfers to the parasitic capacitance, reducing the charge in the feedback capacitor, ultimately decreasing the output voltage amplitude and reducing detection sensitivity. Utility Model Content
[0006] In view of the above problems, the purpose of this utility model is to provide a microelectromechanical sensor that reduces the parasitic capacitance of the microelectromechanical sensor by introducing a buried layer between the detection electrode and the substrate.
[0007] According to one aspect of this application, a microelectromechanical sensor is provided, comprising: a substrate; a first insulating layer covering a portion of the surface of the substrate; a buried layer comprising a stacked second insulating layer and a third insulating layer, the second insulating layer being located on the substrate where the first insulating layer is exposed, the third insulating layer being located on the second insulating layer and extending to the first insulating layer; a protective layer located on the first insulating layer and the buried layer; a detection electrode located on the protective layer and opposite to the buried layer; a functional layer located on the protective layer and the detection electrode, the functional layer comprising a fixed portion and a movable portion, the movable portion of the functional layer having a gap with the detection electrode; and a pad located on the functional layer and electrically connected to the functional layer and the detection electrode, respectively.
[0008] Optionally, the width of the buried layer is greater than or equal to the width of the detection electrode.
[0009] Optionally, the thickness of the second insulating layer 103 is 0.5 μm to 2 μm.
[0010] Optionally, the second insulating layer is formed by oxidation of the substrate, with a portion of the second insulating layer located below the first surface of the substrate and a portion located above the first surface of the substrate.
[0011] Optionally, the third insulating layer is formed by oxidizing a polycrystalline silicon layer.
[0012] Optionally, the thickness of the polycrystalline silicon layer is 0.1 μm to 1 μm.
[0013] Optionally, the thickness of the first insulating layer is less than the thickness of the second insulating layer.
[0014] Optionally, the thickness of the first insulating layer is less than 1000 Å.
[0015] Optionally, the third insulating layer conformally covers the surfaces of the first insulating layer and the second insulating layer, and the protective layer conformally covers the surface of the third insulating layer.
[0016] Optionally, the protective layer 106 includes a nitrided layer, and the thickness of the protective layer is 0.05 μm to 1 μm.
[0017] Optionally, the functional layer is formed by epitaxy of the seed layer.
[0018] Optionally, the seed layer is a polycrystalline silicon layer, and the thickness of the seed layer is 0.2 μm to 0.6 μm.
[0019] Optionally, the thickness of the functional layer is 10μm to 50μm.
[0020] Optionally, the thickness of the detection electrode is 0.2 μm to 2 μm.
[0021] In this embodiment, an insulating buried layer is introduced between the detection electrode and the substrate. The introduction of the buried layer increases the vertical distance between the detection electrode and the substrate, which greatly reduces the parasitic capacitance between the detection electrode and the substrate and improves the sensitivity of the microelectromechanical sensor.
[0022] Furthermore, the buried layer includes a first insulating layer and a second insulating layer stacked together, and the stacking of multiple insulating layers enables the buried layer to achieve the required thickness.
[0023] In a preferred embodiment, the first and second insulating layers are formed by oxidation. Compared to the insulating layers formed by deposition, the first and second insulating layers of this embodiment have better quality and lower stress.
[0024] In a preferred embodiment, the first insulating layer is formed by substrate oxidation. During the formation of the first insulating layer, a portion of the substrate is consumed, so that the overall thickness of the device does not increase excessively.
[0025] In a preferred embodiment, the detection electrode and the buried layer are positioned opposite each other to minimize the parasitic capacitance between the detection electrode and the substrate.
[0026] In a preferred embodiment, the functional layer is formed by epitaxy of the seed layer, so that the thickness of the functional layer can reach 10μm~50μm. Attached Figure Description
[0027] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
[0028] Figure 1 A schematic diagram of the structure of a microelectromechanical sensor provided according to an embodiment of this application is shown;
[0029] Figures 2a to 2k Cross-sectional views of various stages in the fabrication process of a microelectromechanical sensor are shown. Detailed Implementation
[0030] The present invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.
[0031] This utility model can be presented in various forms, some of which will be described below.
[0032] Figure 1 A schematic diagram of the structure of a microelectromechanical sensor provided according to an embodiment of this application is shown, such as... Figure 1 As shown, the microelectromechanical sensor includes a substrate 100, a protective layer 106 on the substrate 100, a functional layer 109 on the protective layer 106, and a detection electrode 107 located between the protective layer 106 and the functional layer 109. The functional layer 109 includes a fixed portion 109a and a movable portion 109b. The fixed portion 109a is located on the protective layer 106 for support. A cavity exists between the movable portion 109b and the protective layer 106, and the detection electrode 107 is located within this cavity. The detection electrode 107 is located on the protective layer 106 for support, and a gap exists between the top of the detection electrode 107 and the movable portion 109b.
[0033] Furthermore, in this embodiment, a buried layer is provided between the detection electrode 107 and the substrate 100. Specifically, the buried layer includes a second insulating layer 103 and a third insulating layer 105 stacked together, with the second insulating layer 103 located on the substrate 100 and the third insulating layer 105 located on the second insulating layer 103.
[0034] Both the second insulating layer 103 and the third insulating layer 105 are silicon oxides, formed by silicon oxidation. The second insulating layer 103 is formed by oxidizing the substrate 100, thereby consuming a portion of the substrate 100. This results in a portion of the second insulating layer 103 being located below the first surface of the substrate 100, and another portion being located above the first surface of the substrate 100. The thickness of the second insulating layer 103 is 0.5 μm to 2 μm. The third insulating layer 105 is formed by oxidizing a polycrystalline silicon layer, the thickness of which is 0.1 μm to 1 μm.
[0035] Furthermore, in this embodiment, a first insulating layer 101 is also included. The first insulating layer 101 is located on a first surface of the substrate 100, surrounding and adjacent to the second insulating layer 103. The thickness of the first insulating layer 101 is less than the thickness of the second insulating layer 103. The thickness of the first insulating layer 101 is less than 1000 Å; in one embodiment, the thickness of the first insulating layer 101 is 200 Å.
[0036] Furthermore, the third insulating layer 105 also covers the surface of the first insulating layer 101, that is, the third insulating layer 105 conformally covers the surfaces of the first insulating layer 101 and the second insulating layer 103, and the protective layer 106 conformally covers the surface of the third insulating layer 105.
[0037] Furthermore, it also includes pads 110, which are located on the functional layer 109, specifically on the fixed portion 109a of the functional layer 109. Pads 110 are electrically connected to the functional layer 109 and the detection electrode 107, respectively.
[0038] In this embodiment, an insulating buried layer is introduced between the detection electrode 107 and the substrate 100. The introduction of the buried layer increases the vertical distance between the detection electrode 107 and the substrate 100, which greatly reduces the parasitic capacitance between the detection electrode 107 and the substrate 100 and improves the sensitivity of the microelectromechanical sensor.
[0039] In a preferred embodiment, the detection electrode 107 is positioned opposite the buried layer to minimize the parasitic capacitance between the detection electrode 107 and the substrate 100.
[0040] Furthermore, the width of the buried layer is greater than or equal to the width of the detection electrode 107. In a preferred embodiment, the width of the buried layer is equal to the width of the detection electrode 107.
[0041] Corresponding to Figure 1 The microelectromechanical sensor shown in this application embodiment also provides a method for fabricating a microelectromechanical sensor. Figures 2a to 2k Cross-sectional views of various stages in the fabrication process of microelectromechanical sensors are shown below. Figures 2a to 2kThe fabrication method of the microelectromechanical sensor according to the embodiments of this application will be described.
[0042] like Figure 2a As shown, a first insulating layer 101 and a hard mask layer 102 are sequentially formed on a substrate 100. The first insulating layer 101 is an oxide layer (e.g., a SiO2 layer), and the hard mask layer 102 is a nitride layer (e.g., a Si3N4 layer). The thickness of the first insulating layer 101 is, for example, less than 1000 Å, and the thickness of the hard mask layer 102 is, for example, 500 Å to 2000 Å. In one embodiment, the thickness of the first insulating layer 101 is 200 Å, and the thickness of the hard mask layer 102 is 1000 Å.
[0043] Next, a resist mask layer is formed on the surface of the hard mask layer 102, and the resist mask layer is patterned using a photolithography process. The hard mask layer 102 and the first insulating layer 101 are then etched sequentially through the patterned resist mask layer to form an opening that penetrates the hard mask layer 102 and the first insulating layer 101.
[0044] like Figure 2b As shown, a second insulating layer 103 is formed at the opening in the hard mask layer 102 and the first insulating layer 101.
[0045] In this step, the surface of the exposed substrate 100 is thermally oxidized using the LOCOS (Local Oxidation of Silicon) process to form an oxide layer (SiO2 layer), namely the second insulating layer 103. After the second insulating layer 103 is formed, the hard mask layer 102 is removed.
[0046] The second insulating layer 103 is adjacent to the first insulating layer 101, and the first insulating layer 101 and the second insulating layer 103 together cover the surface of the substrate 100. Further, the thickness of the second insulating layer 103 is greater than the thickness of the first insulating layer 101. The thickness of the second insulating layer 103 is, for example, 0.5 μm to 2 μm. In one embodiment, the thickness of the second insulating layer 103 is, for example, 1.5 μm.
[0047] like Figure 2c As shown, for example, a polysilicon layer 104 is formed using an LPCVD (Low Pressure Chemical Vapor Deposition) process, wherein the polysilicon layer 104 conformally covers the surfaces of the first insulating layer 101 and the second insulating layer 103. The thickness of the polysilicon layer is, for example, 0.1 μm to 1 μm. In one embodiment, the thickness of the polysilicon layer is, for example, 0.5 μm.
[0048] like Figure 2dAs shown, the polycrystalline silicon layer 104 is thermally oxidized at high temperature, so that all the polycrystalline silicon in this layer is converted into a SiO2 layer, namely the third insulating layer 105. The third insulating layer 105 conformally covers the surfaces of the first insulating layer 101 and the second insulating layer 103.
[0049] like Figure 2e As shown, a protective layer 106 is formed, for example, using a deposition process. The protective layer 106 conformally covers the surface of the third insulating layer 105. The protective layer 106 is, for example, a Si3N4 layer, and its thickness is, for example, 0.05 μm to 1 μm. In a preferred embodiment, the thickness of the protective layer 106 is, for example, 0.1 μm to 0.2 μm. In one embodiment, the thickness of the protective layer 106 is 0.1 μm.
[0050] like Figure 2f As shown, a detection electrode 107 is formed.
[0051] In this step, for example, an LPCVD process is used to form a polysilicon layer on the surface of the protective layer 106, the polysilicon layer conformally covering the surface of the protective layer 106. The thickness of the polysilicon layer is, for example, 0.2 μm to 2 μm, and in a preferred embodiment, the thickness of the polysilicon layer is, for example, 0.4 μm to 0.8 μm. In one embodiment, the thickness of the polysilicon layer is 0.4 μm.
[0052] Next, the polysilicon layer is patterned using, for example, photolithography and etching processes, and the remaining polysilicon layer forms the detection electrode 107. The protective layer 106 includes a first portion above the first insulating layer 101 and a second portion above the second insulating layer 103. The detection electrode 107 is located on the surface of the second portion, and the projection of the detection electrode 107 onto the surface of the second portion falls within the edge of the second portion. A portion of the surface of the second portion is exposed around the detection electrode 107.
[0053] like Figure 2g As shown, a sacrificial layer 108 is formed.
[0054] In this step, a SiO2 layer is formed using processes such as LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition), and then planarized using CMP (Chemical-Mechanical Polishing) to give the SiO2 layer a flat surface. The SiO2 layer covers the surface of the first portion of the protective layer 106, the surface of the detection electrode 107, and the surface of the second portion of the protective layer 106 exposed by the detection electrode 107. The thickness of the SiO2 layer is, for example, 0.5 μm to 2 μm. In a preferred embodiment, the thickness of the SiO2 layer is, for example, 0.7 μm to 1.5 μm. In one embodiment, the thickness of the SiO2 layer is, for example, 1.6 μm.
[0055] Next, the SiO2 layer is patterned using, for example, photolithography and etching processes, and the remaining SiO2 layer forms a sacrificial layer 108. The sacrificial layer 108 covers the top surface and sidewalls of the detection electrode 107. In one embodiment, the sacrificial layer 108 covers the top surface of the detection electrode 107 and the surface of the second portion of the protective layer 106 exposed by the detection electrode 107.
[0056] like Figure 2h As shown, structural layer 109 is formed.
[0057] In this step, for example, an LPCVD process is used to form a polycrystalline silicon seed layer, and a thick polycrystalline silicon layer is epitaxially grown using an epitaxial polycrystalline silicon process. Then, the thick polycrystalline silicon layer is planarized using a CMP process to form the functional layer 109. The thickness of the deposited polycrystalline silicon seed layer is typically 0.2 μm to 0.6 μm; in one embodiment, the thickness of the polycrystalline silicon seed layer is 0.2 μm. The thickness of the epitaxially grown thick polycrystalline silicon layer is, for example, 10 μm to 50 μm; in a preferred embodiment, the thickness of the thick polycrystalline silicon layer is, for example, 15 μm to 25 μm. In one embodiment, the thickness of the thick polycrystalline silicon layer is 20 μm.
[0058] like Figure 2i As shown, pad 110 is formed.
[0059] In this step, a metal layer (e.g., an Al layer) is formed, for example, using a PVD process, and the metal layer covers the surface of the structural layer 109. The thickness of the metal layer is, for example, 0.5 μm to 5 μm, and in a preferred embodiment, the thickness of the metal layer is, for example, 1 μm to 2 μm. In one embodiment, the thickness of the metal layer is 1.5 μm.
[0060] Next, for example, photolithography and etching processes are used to pattern the metal layer to form pad 110.
[0061] like Figure 2j As shown, the structural layer 109 is patterned, for example, using a deep silicon etching process. Typically, a BOSCH deep silicon etching process is used to pattern the structural layer 109 to form vias penetrating the structural layer 109. These vias expose at least a portion of the surface of the sacrificial layer 108.
[0062] like Figure 2k As shown, a sacrificial layer 108 is formed between the protective layer 106, the detection electrode 107, and the structural layer 109 by vapor phase etching using a VHF (vapor HF) process. After the sacrificial layer 108 is removed, a portion of the functional layer 109 forms a fixed portion 109a, and a portion forms a movable portion 109b.
[0063] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to effectively utilize the present invention and its modifications. The present invention is limited only by the claims and their full scope and equivalents.
Claims
1. A microelectromechanical sensor, comprising: Base; A first insulating layer covers a portion of the surface of the substrate; A buried layer comprising a stacked second insulating layer and a third insulating layer, the second insulating layer being located on the substrate exposed by the first insulating layer, and the third insulating layer being located on the second insulating layer and extending onto the first insulating layer; A protective layer is located on the first insulating layer and the buried layer; The detection electrode is located on the protective layer and opposite to the buried layer; A functional layer is located on the protective layer and the detection electrode. The functional layer includes a fixed part and a movable part, and there is a gap between the movable part of the functional layer and the detection electrode. The pads are located on the functional layer and are electrically connected to both the functional layer and the detection electrode.
2. The microelectromechanical sensor according to claim 1, wherein, The width of the buried layer is greater than or equal to the width of the detection electrode.
3. The microelectromechanical sensor according to claim 1, wherein, The thickness of the second insulating layer is 0.5μm to 2μm.
4. The microelectromechanical sensor according to claim 1, wherein, The second insulating layer is formed by oxidation of the substrate, with a portion of the second insulating layer located below the first surface of the substrate and a portion located above the first surface of the substrate.
5. The microelectromechanical sensor according to claim 1, wherein, The third insulating layer is formed by oxidizing a polycrystalline silicon layer.
6. The microelectromechanical sensor according to claim 5, wherein, The thickness of the polycrystalline silicon layer is 0.1 μm to 1 μm.
7. The microelectromechanical sensor according to claim 1, wherein, The thickness of the first insulating layer is less than the thickness of the second insulating layer.
8. The microelectromechanical sensor according to claim 1, wherein, The thickness of the first insulating layer is less than 1000 Å.
9. The microelectromechanical sensor according to claim 1, wherein, The third insulating layer conformally covers the surfaces of the first insulating layer and the second insulating layer, and the protective layer conformally covers the surface of the third insulating layer.
10. The microelectromechanical sensor according to claim 1, wherein, The protective layer includes a nitrided layer, and the thickness of the protective layer is 0.05 μm to 1 μm.
11. The microelectromechanical sensor according to claim 1, wherein, The functional layer is formed by epitaxy of the seed layer.
12. The microelectromechanical sensor according to claim 11, wherein, The seed layer is a polycrystalline silicon layer, and the thickness of the seed layer is 0.2μm~0.6μm.
13. The microelectromechanical sensor according to claim 11, wherein, The thickness of the functional layer is 10μm~50μm.
14. The microelectromechanical sensor according to claim 1, wherein, The thickness of the detection electrode is 0.2 μm to 2 μm.