Coated carrier plate

Abstract

The application discloses a coating carrier plate, which comprises a carrier plate body and a plurality of positioning members. The carrier plate body is provided with at least one silicon wafer placing area, and the silicon wafer placing area is provided with a silicon wafer placing groove. The plurality of positioning members are arranged on the silicon wafer placing area, and the plurality of positioning members are arranged in the circumferential direction of the silicon wafer placing groove. The side of the positioning member facing the silicon wafer is provided with a first transition surface, the first transition surface is an arc surface or an inclined plane, and the height of the positioning member is 0.5mm-2mm. Compared with the prior art, the probability of the phenomenon of uneven coating thickness or local film peeling in the edge area is reduced.

Description

Technical Field

[0001] This application relates to the field of photovoltaic module technology, specifically a coated carrier plate. Background Technology

[0002] Currently, the manufacturing process of photovoltaic modules mainly includes four steps: texturing and cleaning, PECVD, PVD, and screen printing. Among them, Plasma Enhanced Chemical Vapor Deposition (PECVD) is a thin film preparation technology that combines plasma technology with chemical vapor deposition (CVD), and it is widely used in semiconductors, photovoltaics, display panels, and other fields. Its core principle is to activate the reactive gas through plasma to achieve efficient deposition of high-quality thin films at relatively low temperatures.

[0003] To meet the requirements of the coating process, a coating carrier is generally used to support the silicon wafer. The silicon wafer is then transferred from the coating carrier to the coating chamber of the coating apparatus for the coating process. However, the limiting strips around the placement area of ​​the existing coating carrier have right-angled tops. When the silicon wafer is placed in the carrier placement area for the coating process, the right-angled design of the limiting strips may increase the blocking area of ​​plasma flow in the area where the limiting strips contact the edge of the silicon wafer. This can block electrons or ions in the plasma, preventing them from depositing onto the corresponding edge area of ​​the silicon wafer. This can lead to uneven coating thickness or local film peeling at the edge area. Summary of the Invention

[0004] This application provides a coating carrier plate that reduces the probability of uneven coating thickness or local film peeling in the edge area.

[0005] In a first aspect, embodiments of this application provide a coating carrier, including a carrier body and a plurality of positioning members. The carrier body has at least one silicon wafer placement area, and the silicon wafer placement area has a silicon wafer placement groove. The plurality of positioning members are disposed in the silicon wafer placement area, arranged circumferentially along the silicon wafer placement groove. A first transition surface is provided on the side of each positioning member facing the silicon wafer; the first transition surface is an arc surface or an inclined plane, and the height of the positioning member is 0.5mm-2mm.

[0006] In the above technical solution, the combined effect of the first transition surface and the height reduces the obstruction of plasma flowing from all directions, allowing more electrons or ions in the plasma to be deposited on the edge area of ​​the silicon wafer, thereby reducing the probability of uneven coating thickness or local film peeling in the edge area.

[0007] In some embodiments, a limiting member is provided on the inner sidewall of the silicon wafer placement groove. The limiting member is arranged circumferentially along the inner sidewall of the silicon wafer placement groove. A first inclined plane is provided on the side of the limiting member facing the silicon wafer. The angle between the first inclined plane and the bottom surface of the silicon wafer placement groove is 18°-42°.

[0008] In the above technical solution, the limiting member has a first inclined plane on the side facing the silicon wafer. The angle of the first inclined plane is 18°-42°. Since the silicon wafer itself is very thin, when the silicon wafer is placed in the silicon wafer placement groove, the silicon wafer will be placed in a state where the middle of the silicon wafer is lower and the two sides are higher due to its own weight. This makes the two sides of the silicon wafer tilted. The first inclined plane can better fit with the silicon wafer that is tilted on both sides, thereby supporting the silicon wafer, reducing the probability of the silicon wafer directly contacting the inner wall of the silicon wafer placement groove, reducing the probability of friction between the silicon wafer and the inner wall of the silicon wafer placement groove, and thus reducing the pitting phenomenon.

[0009] In some embodiments, the roughness of the first inclined plane is 2.8 μm to 7.2 μm.

[0010] In the above technical solution, the surface roughness of the first inclined plane is set to 2.8~7.2um, so that the surface of the first inclined plane is a smooth level, thereby reducing the friction between the first inclined plane and the silicon wafer, and thus reducing the pitting phenomenon.

[0011] In some embodiments, a first guide channel is provided on the first inclined plane, one end of the first guide channel extends to the bottom surface of the silicon wafer placement groove, the other end of the first guide channel extends to the upper edge of the silicon wafer placement groove, and a first vent hole is provided on the bottom surface of the silicon wafer placement groove.

[0012] In the above technical solution, a first guide groove is provided on the first inclined plane, and a first vent hole is provided on the bottom surface of the silicon wafer placement groove. When the silicon wafer is placed on the silicon wafer placement groove, the cavity formed between the silicon wafer and the silicon wafer placement groove allows the first guide groove and the first vent hole to be connected by a gas path through the cavity. The gas pressure in the cavity can be adjusted through the first guide groove and the first vent hole, so that the gas pressure applied by the plasma to the surface of the silicon wafer is balanced with the gas pressure in the cavity, thereby reducing the probability of silicon wafer movement. This reduces the defect of uneven coating on the silicon wafer surface caused by the local temperature rise of the silicon wafer when it contacts the bottom surface of the silicon wafer placement groove.

[0013] In some embodiments, at least one set of support members is provided at the center of the bottom surface of the silicon wafer placement groove, and each set of support members includes a plurality of support members arranged at intervals.

[0014] In the above technical solution, by setting a support member on the bottom surface of the silicon wafer placement groove, the silicon wafer can be supported, creating a gap between the silicon wafer and the bottom surface of the groove. This reduces the probability of direct contact between the silicon wafer and the bottom surface of the groove, thereby improving the film deposition effect. It also reduces friction between the silicon wafer and the bottom surface of the groove, thus affecting the quality of the coating.

[0015] In some embodiments, the upper end of the support member is provided with a support portion, which is spherical or ellipsoidal in shape.

[0016] In the above technical solution, by setting the shape of the support part to a sphere or an ellipsoid, the support column forms a point-to-surface contact with the silicon wafer through the support part, thereby further reducing the friction between the silicon wafer and the support column.

[0017] In some embodiments, the support is spherical in shape, with a diameter of 0.5mm-2mm.

[0018] In the above technical solution, by setting the diameter of the sphere to 0.5mm-2mm, the size of the support part is within a suitable size range, which reduces the contact area between the support part and the silicon wafer, and further reduces the friction between the silicon wafer and the support column.

[0019] In some embodiments, the positioning element includes four sets of positioning elements. Two sets of positioning elements are respectively disposed on both sides of the silicon wafer placement groove along a first direction, wherein each set of positioning elements includes two positioning elements spaced apart along a second direction. The other two sets of positioning elements are respectively disposed on both sides of the silicon wafer placement groove along the second direction, wherein each set of positioning elements includes three positioning elements spaced apart along the first direction, and the first direction and the second direction are perpendicular to each other.

[0020] In the above technical solution, by arranging the positioning elements, the number of positioning elements can be minimized when placing and positioning the silicon wafer, thereby reducing the area of ​​the positioning elements that obstructs the plasma flow.

[0021] In some embodiments, the orthographic projection of the silicon wafer placement slot is rectangular in a projection plane perpendicular to the third direction, and the four corners of the silicon wafer placement slot are respectively provided with second vent holes, and the third direction is perpendicular to the surface of the carrier plate body.

[0022] In the above technical solution, by providing second vent holes at the four corners of the silicon wafer placement groove, gas can be blown out from the second vent holes by an external air source, which can provide good support for the four corners of the silicon wafer, thereby enabling the silicon wafer to be better positioned within the area defined by the positioning component.

[0023] In some embodiments, the length of the carrier plate body is 1500mm-2500mm, and the width of the carrier plate body is 1500mm-2500mm.

[0024] In the above technical solution, by setting the length of the carrier plate body to 1500mm-2500mm and the width of the carrier plate body to 1500mm-2500mm, the size of the carrier plate body can be adapted to the size of the coating cavity of different coating devices. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the structure of the coating carrier plate provided in some embodiments of this application.

[0027] Figure 2 This is a schematic diagram of the structure of a coating carrier plate provided for other embodiments of this application.

[0028] Figure 3 This is a partial schematic diagram of the silicon wafer placement area in a coating carrier provided in some embodiments of this application.

[0029] Figure 4 This is a partial schematic diagram of the silicon wafer placement area in a coating carrier provided in other embodiments of this application.

[0030] Figure 5 This is a partial schematic diagram of the silicon wafer placement area in a coating carrier provided in some embodiments of this application.

[0031] Figure 6 A partial schematic diagram of the silicon wafer placement area in a coating carrier provided in some embodiments of this application (showing the support).

[0032] Figure 7 A partial schematic diagram of the silicon wafer placement area in a coating carrier provided for other embodiments of this application (showing the support).

[0033] icon: 10-Carrier board body, 11-Silicon wafer placement area, 12-Silicon wafer placement groove, 121-Bottom surface, 122-First vent hole, 123-Second vent hole, 124-Top edge; 20 - Positioning element, 21 - First transition surface; 30 - Limiting component; 31 - First inclined plane; 32 - First guide channel; 40 - Support component, 41 - Support part; X - First direction; Y - Second direction; Z - Third direction. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used in the description of this application is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms "comprising" and "having," and any variations thereof, in the description, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the description, claims, or accompanying drawings of this application are used to distinguish different objects, not to describe a specific order or hierarchy.

[0036] In this application, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments.

[0037] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "attachment" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0038] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, in this application, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0039] In the embodiments of this application, the same reference numerals denote the same components, and for the sake of brevity, detailed descriptions of the same components are omitted in different embodiments. It should be understood that the thickness, length, width, and other dimensions of various components in the embodiments of this application shown in the accompanying drawings, as well as the overall thickness, length, width, and other dimensions of the integrated device, are merely illustrative and should not constitute any limitation on this application.

[0040] Currently, the manufacturing process of photovoltaic modules mainly includes four steps: texturing and cleaning, PECVD, PVD, and screen printing. Among them, Plasma Enhanced Chemical Vapor Deposition (PECVD) is a thin film preparation technology that combines plasma technology with chemical vapor deposition (CVD), and it is widely used in semiconductors, photovoltaics, display panels, and other fields. Its core principle is to activate the reactive gas through plasma to achieve efficient deposition of high-quality thin films at relatively low temperatures.

[0041] To meet the requirements of the coating process, a coating carrier is generally used to support the silicon wafer. The silicon wafer is then transferred from the coating carrier to the coating chamber of the coating apparatus for the coating process. However, the limiting strips around the placement area of ​​the existing coating carrier have right-angled tops. When the silicon wafer is placed in the carrier placement area for the coating process, the right-angled design of the limiting strips may increase the blocking area of ​​plasma flow in the area where the limiting strips contact the edge of the silicon wafer. This can block electrons or ions in the plasma, preventing them from depositing onto the corresponding edge area of ​​the silicon wafer. This can lead to uneven coating thickness or local film peeling at the edge area.

[0042] Based on the above considerations, in order to solve the technical problem that electrons or ions in plasma cannot be deposited onto the corresponding edge area of ​​the silicon wafer, resulting in uneven coating thickness or local film peeling at the edge area of ​​the silicon wafer, this application provides a coating carrier, including a carrier body and a plurality of positioning members. The carrier body is provided with at least one silicon wafer placement area, and the silicon wafer placement area is provided with a silicon wafer placement groove. The plurality of positioning members are disposed in the silicon wafer placement area and are arranged circumferentially along the silicon wafer placement groove. The side of the positioning member facing the silicon wafer is provided with a first transition surface, which is an arc surface or a sloping plane. The height of the positioning member is 0.5mm-2mm.

[0043] In such a coating carrier, multiple positioning elements are arranged circumferentially in the silicon wafer placement groove. The side of the positioning element facing the silicon wafer has a first transition surface, which is set as a sloping plane or an arc surface. Firstly, by setting the sloping plane or arc surface, the obstruction area of ​​the plasma flow by the positioning elements can be reduced when the plasma flows along the direction perpendicular to the carrier body, so that more electrons or ions in the plasma can be deposited on the edge area of ​​the silicon wafer. Secondly, by setting the height of the positioning elements to 0.5mm-2mm, the positioning elements have a suitable height dimension, which can reduce the obstruction area of ​​the plasma flow by the positioning elements when the plasma flows along the length or width direction of the carrier body, so that more electrons or ions in the plasma can be deposited on the edge area of ​​the silicon wafer.

[0044] In summary, the combined effect of the first transition surface and the height reduces the obstruction of plasma flowing from all directions, allowing more electrons or ions in the plasma to be deposited on the edge region of the silicon wafer, thereby reducing the probability of uneven coating thickness or local film peeling in the edge region.

[0045] Please refer to Figures 1-3 , Figure 1 This is a schematic diagram of the structure of the coating carrier plate provided in some embodiments of this application. Figure 2 This is a schematic diagram of the structure of the coating carrier plate provided in some other embodiments of this application. Figure 3 This is a partial schematic diagram of a silicon wafer placement area 11 in a coating carrier provided in some embodiments of this application. Embodiments of this application provide a coating carrier including a carrier body 10 and a plurality of positioning members 20. At least one silicon wafer placement area 11 is provided on the carrier body 10, and a silicon wafer placement groove 12 is provided on the silicon wafer placement area 11. The plurality of positioning members 20 are disposed in the silicon wafer placement area 11, and the plurality of positioning members 20 are arranged circumferentially along the silicon wafer placement groove 12. A first transition surface 21 is provided on the side of each positioning member 20 facing the silicon wafer. The first transition surface 21 is an arc surface or an inclined plane, and the height of the positioning member 20 is 0.5 mm to 2 mm.

[0046] The carrier plate body 10 can be made of high-temperature resistant graphite material or high-temperature resistant ceramic composite material, so that the carrier plate body 10 can be adapted to the high-temperature environment in the coating process.

[0047] The thickness of the carrier plate body 10 can be the dimension of the carrier plate body 10 along the third direction Z. The thickness of the carrier plate body 10 can be in the range of 3mm-8mm. The thickness of the carrier plate body 10 can be any one of 3mm, 4mm, 5mm, 6mm, 7mm, and 8mm or a range between any two.

[0048] The positioning element 20 can be a positioning strip or a positioning post. The positioning element 20 can be made of high-temperature resistant graphite material or high-temperature resistant ceramic composite material to reduce the probability of the positioning element 20 deforming in the high-temperature environment of the coating process, which would cause the silicon wafer to shift.

[0049] Along the first direction X, the positioning member 20 may have a first surface and a second surface arranged opposite to each other, wherein the first surface faces the silicon wafer and the second surface faces away from the silicon wafer. Along the third direction Z, the positioning member 20 may have a third surface facing the silicon wafer placement area 11. The first transition surface 21 may be the second surface and may be connected to the first surface and the third surface respectively. Along the third direction Z, the positioning member 20 may also have a fourth surface and a fifth surface arranged opposite to each other. The first transition surface 21 may be the second surface and may be connected to the fourth surface and the fifth surface respectively.

[0050] Along the second direction Y, the positioning member 20 may have a sixth surface and a seventh surface arranged opposite to each other, wherein the sixth surface faces the silicon wafer and the seventh surface faces away from the silicon wafer. Along the third direction Z, the positioning member 20 may have an eighth surface facing the silicon wafer placement area 11. The first transition surface 21 may be the sixth surface and may be connected to the sixth surface and the seventh surface respectively. Along the third direction Z, the positioning member 20 may also have a ninth surface and a tenth surface arranged opposite to each other. The first transition surface 21 may be the sixth surface and may be connected to the ninth surface and the tenth surface respectively.

[0051] The first transition surface 21 can be entirely curved or entirely inclined. The first transition surface 21 can also be partially curved and partially inclined, with the curved surface and the inclined surface connected.

[0052] The height of the positioning element 20 can be any one of 0.5mm, 0.8mm, 1mm, 1.3mm, 1.6mm, 1.9mm, or 2mm, or a range between any two.

[0053] The bottom surface 121 of the silicon wafer placement groove 12 can be polished or ceramic sandblasted.

[0054] The roughness of the bottom surface 121 of the silicon wafer placement groove 12 can be a point value or a range between any two of the following: 2.8μm, 3.1μm, 3.3μm, 3.9μm, 4.2μm, 4.5μm, 4.9μm, 5.2μm, 5.5μm, 5.9μm, 6.2μm, 6.5μm, 6.9μm, and 7.2μm.

[0055] In this embodiment, multiple positioning elements 20 are arranged circumferentially in the silicon wafer placement groove 12. Each positioning element 20 has a first transition surface 21 on its side facing the silicon wafer. The first transition surface 21 is either a sloping plane or an arc surface. Firstly, by setting the sloping plane or arc surface, the obstruction area of ​​the positioning elements 20 on the plasma flow is reduced when the plasma flows along the direction perpendicular to the carrier plate body 10 (i.e., the third direction Z), allowing more electrons or ions in the plasma to deposit on the edge region of the silicon wafer. Secondly, by setting the height of the positioning elements 20 to 0.5mm-2mm, a suitable height dimension is achieved for each positioning element 20. When the plasma flows along the length direction (i.e., the second direction Y) or the width direction (i.e., the first direction X) of the carrier body 10, the obstruction area of ​​the positioning element 20 on the plasma flow is reduced, allowing more electrons or ions in the plasma to be deposited on the edge region of the silicon wafer. In summary, through the combined effect of the first transition surface 21 and the height, the obstruction of the plasma when it flows from various directions is reduced, allowing more electrons or ions in the plasma to be deposited on the edge region of the silicon wafer, thereby reducing the probability of uneven coating thickness or local film peeling in the edge region.

[0056] In some embodiments, please continue to refer to Figures 3-5 , Figure 4 This is a partial schematic diagram of the silicon wafer placement area in a coating carrier provided in other embodiments of this application. Figure 5 This is a partial schematic diagram of the silicon wafer placement area in a coating carrier provided in some embodiments of this application. A limiting member 30 is provided on the inner sidewall of the silicon wafer placement groove 12. The limiting member 30 is arranged circumferentially along the inner sidewall of the silicon wafer placement groove 12. A first inclined plane 31 is provided on the side of the limiting member 30 facing the silicon wafer. The angle between the first inclined plane 31 and the bottom surface 121 of the silicon wafer placement groove 12 is 18°-42°.

[0057] The limiting member 30 and the inner wall of the silicon wafer placement groove 12 can be directly connected. For example, the surface of the limiting member 30 facing the inner wall of the silicon wafer placement groove 12 and the surface of the inner wall of the silicon wafer placement groove 12 facing the limiting member 30 can be directly and fixedly connected. Alternatively, they can be indirectly connected. For example, the surface of the limiting member 30 facing the inner wall of the silicon wafer placement groove 12 and the surface of the inner wall of the silicon wafer placement groove 12 facing the limiting member 30 can be connected by an adhesive.

[0058] The limiting member 30 can be an annular structure surrounding the inner wall of the silicon wafer placement groove 12. In an embodiment where the orthographic projection of the silicon wafer placement groove 12 in the projection plane perpendicular to the third direction Z is rectangular, the limiting member 30 can be a rectangular ring structure. It is understood that the orthographic projection of the limiting member 30 in the projection plane perpendicular to the third direction Z is rectangular.

[0059] The limiting member 30 can also be composed of multiple limiting members 30, which are arranged circumferentially along the inner sidewall of the silicon wafer placement groove 12.

[0060] The angle between the first inclined plane 31 and the bottom surface 121 of the silicon wafer placement groove 12 can be any point value or a range between any two of 18°, 20°, 23°, 26°, 30°, 33°, 36°, 40°, and 42°.

[0061] In this embodiment, since the existing carrier placement area is a groove structure with vertical right-angled inner walls around the groove, when the silicon wafer is placed in the carrier placement area, the edge of the silicon wafer will directly contact the inner wall of the groove. During the coating process, when the silicon wafer is subjected to plasma impact, the silicon wafer will move relative to the inner wall of the groove, causing friction between the silicon wafer and the inner wall of the groove, thereby damaging the textured surface of the silicon wafer edge. Since the damaged area of ​​the textured surface is more prone to adsorbing dust and other contaminants, these contaminants may cause edge pitting in subsequent processes. Therefore, by setting a limiting member 30 facing the side of the silicon wafer, a first... The first inclined plane 31 has an angle of 18°-42°. Since the silicon wafer itself is very thin, when the silicon wafer is placed in the silicon wafer placement groove 12, the silicon wafer will be placed in a state where the middle of the silicon wafer is lower and the two sides are higher due to its own weight. This makes the two sides of the silicon wafer tilted. The first inclined plane 31 can better fit with the silicon wafer that is tilted on both sides, thereby supporting the silicon wafer and reducing the probability of the silicon wafer directly contacting the inner wall of the silicon wafer placement groove 12. This reduces the probability of friction between the silicon wafer and the inner wall of the silicon wafer placement groove 12, and thus reduces the pitting phenomenon.

[0062] In some embodiments, please continue to refer to Figure 4 The roughness of the first inclined plane 31 is 2.8μm-7.2μm.

[0063] The surface of the first inclined plane 31 can be polished or ceramic sandblasted.

[0064] The roughness of the first inclined plane 31 can be a point value or a range between any two of the following: 2.8μm, 3.1μm, 3.3μm, 3.9μm, 4.2μm, 4.5μm, 4.9μm, 5.2μm, 5.5μm, 5.9μm, 6.2μm, 6.5μm, 6.9μm, and 7.2μm.

[0065] In this embodiment, the surface roughness of the first inclined plane 31 is set to 2.8~7.2um, so that the surface of the first inclined plane 31 is a smooth horizontal surface, thereby reducing the friction between the first inclined plane 31 and the silicon wafer, and thus reducing the pitting phenomenon.

[0066] In some embodiments, please continue to refer to Figure 4 A first guide groove 32 is provided on the first inclined plane 31. One end of the first guide groove 32 extends to the bottom surface 121 of the silicon wafer placement groove 12, and the other end of the first guide groove 32 extends to the upper edge 124 of the silicon wafer placement groove 12. A first vent hole 122 is provided on the bottom surface 121 of the silicon wafer placement groove 12.

[0067] There can be multiple first guide channels 32. The multiple first guide channels 32 can be evenly and spaced along the first direction X on the first inclined plane 31. The multiple first guide channels 32 can also be evenly and spaced along the second direction Y on the first inclined plane 31.

[0068] There can be multiple first vent holes 122, and the multiple first vent holes 122 can be evenly arranged on the bottom surface 121 of the silicon wafer placement groove 12.

[0069] The diameter of the first vent 122 is 0.5mm-3mm. The direct value of the first vent 122 can be any one of 0.5mm, 0.8mm, 1mm, 1.3mm, 1.6mm, 1.9mm, 2mm, 2.3mm, 2.6mm, 2.9mm, 3mm or any range between two of them.

[0070] In this embodiment, a first guide groove 32 is provided on the first inclined plane 31, and a first vent hole 122 is provided on the bottom surface 121 of the silicon wafer placement groove 12. When the silicon wafer is placed on the silicon wafer placement groove 12, the cavity formed between the silicon wafer and the silicon wafer placement groove 12 allows the first guide groove 32 and the first vent hole 122 to be connected by a gas path. The gas pressure in the cavity can be adjusted through the first guide groove 32 and the first vent hole 122, so that the gas pressure applied by the plasma to the surface of the silicon wafer is balanced with the gas pressure in the cavity, thereby reducing the probability of silicon wafer movement. This reduces the defect of uneven coating on the surface of the silicon wafer caused by the local temperature rise when the silicon wafer contacts the bottom surface 121 of the silicon wafer placement groove 12. At the same time, it can also reduce the friction between the silicon wafer and the bottom surface 121 of the silicon wafer placement groove 12, thereby affecting the coating quality.

[0071] In some embodiments, please refer to Figure 6 and Figure 7 , Figure 6 A partial schematic diagram of the silicon wafer placement area in a coating carrier provided in some embodiments of this application (showing the support member); Figure 7 This is a partial schematic diagram of the silicon wafer placement area in a coating carrier provided in some other embodiments of this application (showing the support members). At least one set of support members 40 is provided in the middle of the bottom surface 121 of the silicon wafer placement groove 12, and each set of support members 40 includes a plurality of support members 40 arranged at intervals.

[0072] Along the first direction X, the bottom surface 121 of the silicon wafer placement groove 12 has a first region on both sides and a second region in the middle. The support member 40 can be multiple sets, and the multiple sets of support members 40 can be respectively arranged in the first region and the second region.

[0073] Along the second direction Y, the bottom surface 121 of the silicon wafer placement groove 12 has a third region on both sides and a fourth region in the middle. The support member 40 can be multiple sets, and the multiple sets of support members 40 can be respectively set in the third region and the fourth region.

[0074] Each set of support members 40 may include support members 40 spaced apart and evenly arranged along a first direction X or a second direction Y.

[0075] The support member 40 can be fixedly connected to the bottom surface 121 of the silicon wafer placement slot 12, for example, by the engagement of threads and threaded holes, or it can be detachably connected to the bottom surface 121 of the silicon wafer placement slot 12, for example, the support member 40 can be inserted into the mounting hole on the bottom surface 121 of the silicon wafer placement slot 12.

[0076] In this embodiment, since the coating carrier is heated during the coating process, if the silicon wafer directly contacts the bottom surface 121 of the silicon wafer placement groove 12, the temperature in the contact area will locally increase, resulting in uneven coating on the silicon wafer surface. Therefore, by providing a support member 40 on the bottom surface 121 of the silicon wafer placement groove 12, the silicon wafer can be supported, creating a gap between the silicon wafer and the bottom surface 121 of the silicon wafer placement groove 12. This reduces the probability of direct contact between the silicon wafer and the bottom surface 121 of the silicon wafer placement groove 12, thereby improving the film formation effect. It also reduces friction between the silicon wafer and the bottom surface 121 of the silicon wafer placement groove 12, thus affecting the coating quality.

[0077] In some embodiments, please refer to Figure 6 and Figure 7 The upper end of the support member 40 is provided with a support part 41, which is in the shape of a sphere or an ellipsoid.

[0078] In this embodiment, by setting the shape of the support part 41 to a spherical or ellipsoidal shape, the support column forms a point-to-surface contact with the silicon wafer through the support part 41, thereby further reducing the friction between the silicon wafer and the support column.

[0079] In some embodiments, please refer to Figure 6 and Figure 7 The support part 41 is spherical in shape, and the diameter of the sphere is 0.5mm-2mm.

[0080] The diameter of the sphere can be any one of 0.5mm, 0.8mm, 1mm, 1.3mm, 1.6mm, 1.9mm, or 2mm, or a range between any two.

[0081] In this embodiment, by setting the diameter of the sphere to 0.5mm-2mm, the size of the support part 41 is within a suitable size range, thereby reducing the contact area between the support part 41 and the silicon wafer, and further reducing the friction between the silicon wafer and the support column.

[0082] In some embodiments, please refer to Figure 6 and Figure 7 The positioning element 20 includes four sets of positioning elements 20. Two sets of the four sets of positioning elements 20 are respectively disposed on both sides of the silicon wafer placement groove 12 along the first direction X, wherein each set of positioning elements 20 includes two positioning elements 20 spaced apart along the second direction Y. The other two sets of the four sets of positioning elements 20 are respectively disposed on both sides of the silicon wafer placement groove 12 along the second direction Y, wherein each set of positioning elements 20 includes three positioning elements 20 spaced apart along the first direction X, wherein the first direction X and the second direction Y are perpendicular.

[0083] In this embodiment, the positioning element 20 includes four sets of positioning elements 20. Two sets of positioning elements 20 are respectively arranged on both sides of the silicon wafer placement groove 12 along the first direction X, and each set of positioning elements 20 includes two positioning elements 20 spaced apart along the second direction Y. The other two sets of positioning elements 20 are respectively arranged on both sides of the silicon wafer placement groove 12 along the second direction Y, and each set of positioning elements 20 includes three positioning elements 20 spaced apart along the first direction X. Through the arrangement of the positioning elements 20, the number of positioning elements 20 can be minimized when placing and positioning the silicon wafer, thereby reducing the area of ​​the positioning elements 20 that obstructs the plasma flow.

[0084] In some embodiments, please refer to Figure 6 and Figure 7 In the projection plane perpendicular to the third direction Z, the orthographic projection of the silicon wafer placement groove 12 is rectangular, and the four corners of the silicon wafer placement groove 12 are respectively provided with second vent holes 123, and the third direction Z is perpendicular to the surface of the carrier body 10.

[0085] In this embodiment, by providing second vent holes 123 at the four corners of the silicon wafer placement groove 12, gas can be blown out from the second vent holes 123 by an external air source, which can provide good support for the four corners of the silicon wafer, thereby enabling the silicon wafer to be better positioned within the area defined by the positioning member 20.

[0086] In some embodiments, please refer to Figure 6 and Figure 7 The length of the carrier plate body 10 is 1500mm-2500mm, and the width of the carrier plate body 10 is 1500mm-2500mm.

[0087] The length of the carrier plate body 10 can be the size of the carrier plate body 10 along the second direction Y, and the width of the carrier plate body 10 can be the size of the carrier plate body 10 along the first direction X.

[0088] The length and width of the carrier plate body 10 may be the same or different.

[0089] The length of the carrier plate body 10 can be any one of 1500mm, 1600mm, 1700mm, 1800mm, 1900mm, 2000mm, 2100mm, 2200mm, 2300mm, 2400mm, or 2500mm, or a range between any two.

[0090] The width of the carrier plate body 10 can be any point value or a range between any two of the following: 1500mm, 1600mm, 1700mm, 1800mm, 1900mm, 2000mm, 2100mm, 2200mm, 2300mm, 2400mm, and 2500mm.

[0091] In this embodiment, by making the length of the carrier plate body 10 1500mm-2500mm and the width of the carrier plate body 10 1500mm-2500mm, the size of the carrier plate body 10 can be adapted to the size of the coating cavity of different coating devices.

[0092] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0093] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit this application. For those skilled in the art, this application can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A coating carrier substrate, comprising a carrier substrate body, wherein at least one silicon wafer placement area is disposed on the carrier substrate body, and a silicon wafer placement groove is disposed on the silicon wafer placement area, characterized in that, Also includes: Multiple positioning elements are disposed in the silicon wafer placement area and arranged circumferentially along the silicon wafer placement groove. A first transition surface is provided on the side of the positioning element facing the silicon wafer. The first transition surface is an arc surface or an inclined plane. The height of the positioning element is 0.5mm-2mm.

2. The coating carrier plate as described in claim 1, characterized in that, A limiting member is provided on the inner sidewall of the silicon wafer placement groove. The limiting member is arranged circumferentially along the inner sidewall of the silicon wafer placement groove. A first inclined plane is provided on the side of the limiting member facing the silicon wafer. The angle between the first inclined plane and the bottom surface of the silicon wafer placement groove is 18°-42°.

3. The coating carrier plate as described in claim 2, characterized in that, The roughness of the first inclined plane is 2.8μm-7.2μm.

4. The coating carrier plate as described in claim 2, characterized in that, A first guide groove is provided on the first inclined plane. One end of the first guide groove extends to the bottom surface of the silicon wafer placement groove, and the other end of the first guide groove extends to the upper edge of the silicon wafer placement groove. A first vent hole is provided on the bottom surface of the silicon wafer placement groove.

5. The coating carrier plate as described in claim 1, characterized in that, At least one set of support members is provided in the middle of the bottom surface of the silicon wafer placement groove, and each set of support members includes multiple support members arranged at intervals.

6. The coating carrier plate as described in claim 5, characterized in that, The upper end of the support member is provided with a support part, which is in the shape of a sphere or an ellipsoid.

7. The coating carrier plate as described in claim 6, characterized in that, The support part is spherical in shape, and the diameter of the sphere is 0.5mm-2mm.

8. The coating carrier plate according to any one of claims 1-7, characterized in that, The positioning components include four sets of positioning components. Two sets of the positioning components are respectively disposed on both sides of the silicon wafer placement slot along a first direction, wherein each set of positioning components includes two positioning components spaced apart along a second direction. The other two sets of the positioning components are respectively disposed on both sides of the silicon wafer placement slot along the second direction, wherein each set of positioning components includes three positioning components spaced apart along the first direction, wherein the first direction and the second direction are perpendicular to each other.

9. The coating carrier plate according to any one of claims 1-7, characterized in that, In a projection plane perpendicular to the third direction, the orthographic projection of the silicon wafer placement slot is rectangular, and the four corners of the silicon wafer placement slot are respectively provided with second vent holes, and the third direction is perpendicular to the surface of the carrier plate body.

10. The coating carrier plate according to any one of claims 1-7, characterized in that, The length of the carrier plate body is 1500mm-2500mm, and the width of the carrier plate body is 1500mm-2500mm.

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