A high-precision over-current protection circuit applied to a large-current power device

Abstract

The utility model discloses a kind of high-precision overcurrent protection circuit applied to high-current power device, belong to integrated circuit technical field.The protection circuit includes power tube M1, first mirror tube M2, second mirror tube M3, first sampling resistance R1, second sampling resistance R2, reference current I_BN and comparator.The utility model utilizes reference current I_BN and the resistance R2 of the same type with sampling resistance R1 to generate reference voltage VREF, replace the method of fixed voltage used in comparator VREF end in traditional technology, reduce the overcurrent protection threshold fluctuation caused by sampling resistance under PVT resistance fluctuation.Ampere level overcurrent protection threshold can be measured only by flowing through milliamper level current under the condition of not enabling power tube, reduce the requirement of ampere level current to power board card and test board card when traditional overcurrent protection test, reduce test cost.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit technology, and in particular to a high-precision overcurrent protection circuit and method for high-current power devices. Background Technology

[0002] With the rapid development of integrated circuit technology, high-power devices have been widely used, and the requirements for driving capability are becoming increasingly higher. In order to avoid the devices from being subjected to excessive current for a long time, which would cause the devices to overheat and be damaged, overcurrent protection measures need to be added to the circuit to ensure that the current that the devices can withstand is within the allowable range, which not only ensures the reliability of the chip but also improves the lifespan of the chip.

[0003] Currently, there are many methods for implementing overcurrent protection. A common approach is to use a current sampling mirror to scale the current proportionally, then pass it through a small resistor to generate a voltage that is compared with a reference voltage to determine whether the device current exceeds a threshold. Figure 1 As shown. However, due to the large resistance deviation at different temperatures, the overcurrent threshold of the detection circuit fluctuates significantly at different temperatures. Moreover, testing requires turning on the power transistor and inputting a large current to ensure the comparator flips. Therefore, traditional overcurrent protection circuits have very wide overcurrent ranges and high testing costs. With the gradual popularization of advanced processes, testing costs are increasing dramatically, and the current that devices can withstand is decreasing. Therefore, designing a high-precision, low-testing-cost overcurrent protection circuit is becoming increasingly important. Summary of the Invention

[0004] In response to the differences in existing technologies, this utility model adopts an overcurrent protection architecture with switchable working modes. In normal applications, the overcurrent protection has high sampling accuracy and small fluctuations in the overcurrent point under PVT. In test mode, the overcurrent threshold of the circuit can be accurately measured without providing ampere-level current, which greatly reduces the current drive requirements of the power supply and test board.

[0005] To achieve the above objectives, this utility model provides a high-precision overcurrent protection circuit for high-current power devices, comprising: a power transistor M1, a first image transistor M2, a second image transistor M3, a first sampling resistor R1, a second sampling resistor R2, a reference current I_BN, and a comparator. The drains of the power transistor M1, the first image transistor M2, and the second image transistor M3 are connected together; the gates of the power transistor M1 and the first image transistor M2 are connected together and are also connected to the first drive signal DRIVER; the gate of the second image transistor M3 is connected to the second drive signal TEST; the sources of the first image transistor M2 and the second image transistor M3 are connected together and then connected to the second input terminal of the comparator, and are also connected to the source of the power transistor M1 through the first sampling resistor and grounded; one end of the second sampling resistor R2 is connected to the first input terminal of the comparator and connected to the reference current I_BN, and the other end is grounded.

[0006] Furthermore, the reference current I_BN is a zero-temperature drift current.

[0007] Furthermore, the zero-temperature drift current is obtained by the bandgap module.

[0008] Furthermore, the first mirror tube M2 and the second mirror tube M3 have the same size, and their ratio to the power tube M1 is 1:N; The first sampling resistor R1 and the second sampling resistor R2 are resistors of the same type, and their resistance values ​​satisfy R2:R1=n:1.

[0009] Furthermore, the overcurrent protection circuit has two operating modes: In normal mode, the first drive signal DRIVER of power transistor M1 and first mirror transistor M2 is enabled, while the second drive signal TEST of second mirror transistor M3 is disabled. The voltage VIN generated across resistor R1 is: VIN=I_FET / (N+1)*R1 Where: I_FET is the drain current of power transistor M1 and the first image transistor M2; The comparator's reference terminal VREF is: VREF = I_BN * R2 = I_BN * n * R1 When VIN > VREF, that is: I_FET / (N+1)*R1>I_BN*n*R1 I_FET>I_BN*n*(N+1) At this point, the comparator output flips, and the module experiences an overcurrent phenomenon. In test mode, enable the first drive signal DRIVER of power transistor M1 and first mirror transistor M2, and disable the second drive signal TEST of second mirror transistor M3. The on-resistance Rdson of power transistor M1 is obtained by testing. The first drive signal DRIVER of the power transistor M1 and the first mirror transistor M2 is disabled, and the second drive signal TEST of the second mirror transistor M3 is enabled. A slowly rising ramp voltage is input to the drain terminal of the second mirror transistor M3, while the output voltage of the comparator is monitored, and the ramp voltage V1 corresponding to the flip of the comparator output is obtained by testing. The overcurrent protection threshold I_OC = V1 / Rdson is obtained at this temperature.

[0010] The beneficial effects of this utility model are: 1. This utility model uses a reference current I_BN and a resistor R2 of the same type as the sampling resistor R1 to generate a reference voltage VREF, replacing the fixed voltage method used in the comparator VREF terminal in the traditional technology, thereby reducing the overcurrent protection threshold fluctuation caused by the resistance fluctuation of the sampling resistor under PVT.

[0011] 2. This utility model can measure the overcurrent protection threshold of the ampere level by only requiring a current in the milliampere level without enabling the power transistor, which reduces the requirements of the ampere level current on the power supply board and test board during traditional overcurrent protection testing, and reduces testing costs. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a conventional overcurrent protection circuit architecture according to an embodiment of the present invention.

[0013] Figure 2 This is a schematic diagram of a high-precision overcurrent protection circuit architecture applied to high-current power devices according to an embodiment of this utility model. Detailed Implementation

[0014] The present invention will be further explained and described below with reference to the accompanying drawings and embodiments.

[0015] like Figure 2 As shown, this utility model provides a high-precision overcurrent protection circuit for high-current power devices. The protection circuit consists of a power transistor M1, a first image transistor M2, a second image transistor M3, a first sampling resistor R1, a second sampling resistor R2, a reference current I_BN, and a comparator.

[0016] The drains of power transistor M1, first image transistor M2, and second image transistor M3 are connected together, and the input current (current to be monitored) is also connected to them. The gates of power transistor M1 and first image transistor M2 are connected together, and the first drive signal DRIVE is also connected to them. The gate of second image transistor M3 is connected to the second drive signal TEST. The sources of one image transistor M2 and the second image transistor M3 are connected together and then connected to the second input terminal of the comparator. At the same time, they are connected to the source of power transistor M1 through the first sampling resistor and grounded. One end of the second sampling resistor R2 is connected to the first input terminal of the comparator and connected to the reference current I_BN, and the other end is grounded.

[0017] The first image transistor M2 and the second image transistor M3 are identical in size and have a 1:N ratio with the power transistor M1, and are physically matched. The first sampling resistor R1 and the second sampling resistor R2 are of the same type, and their resistance values ​​satisfy R2:R1=n:1. Furthermore, the resistance value of R1 is much smaller than the on-resistance of M2. The reference current I_BN is a zero-temperature-drift current and can be generated by the bandgap module.

[0018] The overcurrent protection circuit has two operating modes: (a) In normal mode, it is used to monitor whether the input current I_FET is overcurrent.

[0019] In this mode, the first drive signal DRIVE of power transistor M1 and the first image transistor M2 is enabled, while the second drive signal TEST of the second image transistor M3 is disabled. Since the resistance of resistor R1 is much smaller than the on-resistance of M2, the voltage VIN generated across resistor R1 by the current is: VIN=I_FET / (N+1)*R1 Where: I_FET is the drain current of power transistor M1 and the first mirror transistor M2 (which is also the input current monitored by the protection current).

[0020] The comparator's reference terminal VREF: VREF = I_BN * R2 = IBN * n * R1 When VIN > VREF, that is: I_FET / (N+1)*R1>I_BN*n*R1 I_FET>I_BN*n*(N+1) At this point, the comparator output flips, and the module experiences an overcurrent phenomenon. Because resistors R1 and R2 are of the same type, the fluctuation of the overcurrent protection point caused by the fluctuation of the resistance value under PVT can be effectively reduced, and the accuracy is higher than that of traditional overcurrent protection.

[0021] (b) Test mode, used to measure the threshold of the protection current.

[0022] When the power transistor M1 is enabled, it operates in the linear region and can be approximated as a small resistor with a resistance of Rdson. Therefore, we only need to measure the voltage V1 at the drain of the power transistor M1 when the comparator OC_OUT flips to calculate the overcurrent protection threshold.

[0023] The steps for testing the overcurrent protection trigger threshold are as follows: (1) Enable the first drive signal DRIVER of power transistor M1 and first mirror transistor M2, and disable the second drive signal TEST of second mirror transistor M3. Test the on-resistance Rdson of power transistor M1. (2) The first drive signal DRIVER of the power transistor M1 and the first mirror transistor M2 is not enabled, and the second drive signal TEST of the second mirror transistor M3 is enabled, and it is a slowly rising ramp voltage. The voltage V1 corresponding to the flip of the comparator output OC_OUT is obtained by testing. (3) Obtain the overcurrent protection threshold I_OC=V1 / Rdson at this temperature.

[0024] The preferred embodiments of this utility model have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of this utility model without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of this utility model through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A high-precision overcurrent protection circuit for high-current power devices, characterized in that, include: The components include a power transistor M1, a first image transistor M2, a second image transistor M3, a first sampling resistor R1, a second sampling resistor R2, a reference current I_BN, and a comparator. The drains of the power transistor M1, the first image transistor M2, and the second image transistor M3 are connected together; the gates of the power transistor M1 and the first image transistor M2 are connected together and are also connected to the first drive signal DRIVER; the gate of the second image transistor M3 is connected to the second drive signal TEST; the sources of the first image transistor M2 and the second image transistor M3 are connected together and then connected to the second input terminal of the comparator, and are also connected to the source of the power transistor M1 through the first sampling resistor R1 and grounded; one end of the second sampling resistor R2 is connected to the first input terminal of the comparator and connected to the reference current I_BN, and the other end is grounded.

2. The high-precision overcurrent protection circuit for high-current power devices according to claim 1, characterized in that: The reference current I_BN is a zero-temperature drift current.

3. The high-precision overcurrent protection circuit for high-current power devices according to claim 2, characterized in that: The zero-temperature drift current I_BN is obtained from the bandgap module.

4. The high-precision overcurrent protection circuit for high-current power devices according to claim 1, characterized in that: The first mirror tube M2 and the second mirror tube M3 have the same size, and their ratio to the power tube M1 is 1:N; The first sampling resistor R1 and the second sampling resistor R2 are resistors of the same type, and their resistance values ​​satisfy R2:R1=n:

1.

5. The high-precision overcurrent protection circuit for high-current power devices according to claim 4, characterized in that, The overcurrent protection circuit has two operating modes: In normal mode, the first drive signal DRIVER of power transistor M1 and first mirror transistor M2 is enabled, while the second drive signal TEST of second mirror transistor M3 is disabled. The voltage VIN generated across resistor R1 is: VIN=I_FET / (N+1)*R1 Where: I_FET is the drain current of power transistor M1 and the first image transistor M2; The comparator's reference terminal VREF is: VREF = I_BN * R2 = I_BN * n * R1 When VIN > VREF, that is: I_FET / (N+1)*R1>I_BN*n*R1 I_FET>I_BN*n*(N+1) At this point, the comparator output flips, and the module experiences an overcurrent phenomenon. In test mode, enable the first drive signal DRIVER of power transistor M1 and first mirror transistor M2, and disable the second drive signal TEST of second mirror transistor M3 to obtain the on-resistance Rdson of power transistor M1. The first drive signal DRIVER of the power transistor M1 and the first mirror transistor M2 is disabled, and the second drive signal TEST of the second mirror transistor M3 is enabled. A slowly rising ramp voltage is input to the drain terminal of the second mirror transistor M3, while the output voltage of the comparator is monitored, and the ramp voltage V1 corresponding to the flip of the comparator output is obtained by testing. The overcurrent protection threshold I_OC = V1 / Rdson is obtained at the current temperature.

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