A multi-head electrically controlled timer circuit

Abstract

The utility model discloses a kind of multi-head electric control timer circuits, comprising: control module, using multi-pin central processing unit, with multiple independent button input interface and multiple control output interface, for receiving independent object selection signal and executing parallel timing control logic;Display module, using matrix LED drive structure, with multiple control lines and multiple bit control lines, the simultaneous display of multiple object states is realized by matrix connection mode;Key module, including multiple independent object buttons, using the direct mapping structure of one button corresponding to one object, each independent object button is connected to the corresponding input interface of the control module by pull-up resistor circuit;Drive module, the multiple LED lamps of display module are controlled by matrix drive mode;The utility model is through independent object button design, matrix state display technology and multi-task parallel processing architecture, solve the technical problem that traditional multi-head timer is cumbersome, state display is not intuitive.

Description

Technical Field

[0001] This utility model relates to the field of household appliance control technology, and in particular to a multi-burner electronic timer circuit, which is suitable for timing control of multi-burner household appliances such as multi-burner stoves, induction cookers, and ceramic cooktops. Background Technology

[0002] Currently, most multi-burner household appliances on the market (such as cooktops, induction cookers, and ceramic cooktops) typically use a button with a selection button for setting the timer. Users need to frequently press the selection button to choose the desired timer before setting the timer. When the appliance has three or more burners, selecting the timer becomes cumbersome. This not only requires frequent button presses but also increases the risk of errors and makes the operation less intuitive. These problems are particularly pronounced in multi-burner appliances (such as multi-burner cooktops and induction cookers), increasing user complexity and reducing usability and user experience. Utility Model Content

[0003] The purpose of this invention is to provide a multi-head electronically controlled timer circuit to solve the problems mentioned in the background art.

[0004] To achieve the above objectives, this utility model provides the following technical solution: The purpose of this utility model is to provide a multi-head electronically controlled timer circuit, which allows users to directly select the object to be timed by setting intuitive shortcut object buttons, simplifying the operation process and improving the user experience.

[0005] This utility model provides a multi-head electronically controlled timer circuit, comprising: a control module, a display module, a button module, a drive module, and a power supply module; wherein: The control module, as the core of the entire circuit, is responsible for receiving key signals, processing timing logic, driving the display, and outputting control signals. The display module is used to display the timing status and remaining time of each head; The button module includes multiple object buttons and function buttons, which are used by users to directly select timed objects and set timed parameters; The driver module is used to control the working status of multiple heads; The power module provides a stable power supply for the entire circuit.

[0006] Furthermore, the control module is the core of the entire circuit, employing a central processing unit (CPU) MCU-20. This CPU is a 20-pin package, featuring high integration and low power consumption, operating at 3.3V. The left-side BAT_AD pin is used for battery voltage detection, and pins KEY1 to KEY4 are connected to four independent object buttons for direct selection of the target object for timing control. The CLK and DAT pins are connected to the driver module. The right-side pins are primarily used for outputting control signals, including multiple signal lines from SEG1 / TMR0_CH to SEG17 / TX0, for driving external loads. The CPU integrates clock, timer, and memory circuits, enabling it to handle multiple timing control tasks simultaneously.

[0007] Furthermore, the display module adopts a 7×4 matrix layout structure, namely 7 segment control lines (SEG1-SEG7) and 4 bit control lines (COM0-COM3). The LED array is arranged in a matrix manner, containing a total of 28 LEDs, forming a complete multi-head status display system. Each COM line connects to the cathode of up to 7 LEDs, while each SEG line connects to the anode of LEDs on different COM lines. Through this matrix connection method, the on / off state of 28 LEDs can be independently controlled using only 11 signal lines, greatly simplifying the circuit connection.

[0008] Furthermore, the independent object button adopts a single-pole single-throw switch structure, which is connected to the positive terminal of the power supply through a pull-up resistor, and is also connected to the corresponding button input pin of the control module.

[0009] Furthermore, the button module includes four independent object buttons, each corresponding to a different timing control object, for direct mapping control of one object per button.

[0010] Furthermore, it also includes a timing latch circuit to prevent accidental triggering. The timing latch circuit includes a monostable multivibrator, a D flip-flop, and an XOR gate. The output of the monostable multivibrator is connected to the clock terminal of the D flip-flop. The data terminal of the D flip-flop receives the key signal via an RC delay circuit. The output of the D flip-flop is compared with the original key signal by the XOR gate and then output to the control module.

[0011] Furthermore, the power module adopts a two-stage voltage regulation structure, with the front stage being a switching voltage regulator circuit and the rear stage being a low-dropout linear voltage regulator circuit, forming a power supply architecture with low ripple and strong anti-interference.

[0012] Furthermore, the driver module uses the TM1650 LED driver module, where pins DIG1 to DIG4 and pins SEG1 to SEG7 are respectively connected to the four bit control lines (COM0-COM3) and seven segment control lines (SEG1-SEG7) of the display module, controlling multiple LEDs through a matrix drive method. The CLK and DAT pins of this LED driver module are connected to the control module via a two-wire interface to receive display data and control commands.

[0013] The purpose of this utility model is to provide a control method for a multi-head electronically controlled timer, including: Step 1: Generate an object selection signal by pressing the independent object button, and input the object selection signal to the control module; Step 2: The control module generates multiple control signals based on parallel timing control logic, and outputs them to the corresponding external loads through the drive module. Step 3: Simultaneously display the status of each controlled object using a matrix LED display module; Step 4: In the key input path, a timing latch circuit composed of a monostable multivibrator, a D flip-flop, and an XOR gate samples and compares the key signal, and outputs a valid key signal after anti-false triggering processing to the control module. Compared with the prior art, the beneficial effects of this utility model are: by using independent object button design, matrix status display technology and multi-task parallel processing architecture, it solves the technical problems of cumbersome operation and unintuitive status display of traditional multi-head timers, realizes efficient and intuitive operation of multi-channel timing control, and has significant technical effects and practical value. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the multi-head electronically controlled timer circuit in specific implementation method 1.

[0015] Figure 2 Circuit principle of specific implementation method 1 Figure 1 .

[0016] Figure 3 Circuit principle of specific implementation method 1 Figure 2 .

[0017] Figure 4 Circuit principle of specific implementation method 1 Figure 3 .

[0018] Figure 5 Circuit principle of specific implementation method 1 Figure 4 .

[0019] Figure 6 Circuit principle of specific implementation method 1 Figure 5 .

[0020] Figure 7 Circuit principle of specific implementation method 1 Figure 6 .

[0021] Figure 8 Circuit principle of specific implementation method 1 Figure 6 .

[0022] Figure 9 Circuit principle of specific implementation method 1 Figure 6 .

[0023] Figure 10 This is a schematic diagram of the pinout of the CD4538 monostable trigger in specific implementation method 2.

[0024] Figure 11 This is a schematic diagram of the pinout of the 74HC86 four-way XOR gate in specific implementation method 2.

[0025] Figure 12 This is a pin diagram of the 74HC74 dual-channel D flip-flop in specific implementation method 2.

[0026] Figure 13 This is a schematic diagram of the MCP2515 pinout for Specific Implementation Method 3.

[0027] Figure 14 This is a schematic diagram of the MCP2551 pinout for Specific Implementation 3.

[0028] Figure 15 This is a schematic diagram of the STM32F030 pinout for Specific Implementation Method 3.

[0029] Figure 16 This is a schematic diagram of the modules in Specific Implementation Method 2.

[0030] Figure 17 This is a schematic diagram of the modules in specific implementation method 3. Detailed Implementation

[0031] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model. Detailed Implementation Method 1 The multi-head electronically controlled timer circuit mainly consists of five parts: control module, display module, button module, drive module, and power supply module. These modules are interconnected and work together to form a complete control system.

[0033] The control module is the core of the entire circuit, employing a central processing unit (CPU) MCU-20. This CPU is a 20-pin package, featuring high integration and low power consumption, operating at 3.3V. The left-side BAT_AD pin is used for battery voltage detection, and pins KEY1 to KEY4 are connected to four independent object buttons for direct selection of the target object for timing control. The CLK and DAT pins connect to the driver module. The right-side pins primarily output control signals, including multiple signal lines from SEG1 / TMR0_CH to SEG17 / TX0, used to drive external loads. The COM0 to COM7 pins connect to the display driver circuit, enabling dynamic scanning display of multi-digit LED displays. The CPU integrates clock, timer, and memory circuits, capable of handling multiple timing control tasks simultaneously.

[0034] The driver module uses the TM1650 LED driver module, which, together with multiple LED indicator arrays, forms an intuitive status display system. The TM1650 is a dedicated LED driver device in a 16-pin package, operating at 3.3V. Pins DIG1 to DIG4 and SEG1 to SEG7 form the basis of the display control, connecting to the four bit control lines (COM0-COM3) and seven segment control lines (SEG1-SEG7) of the display module, respectively, controlling multiple LEDs through a matrix drive method. The CLK and DAT pins of this LED driver module are connected to the control module via a two-wire interface to receive display data and control commands.

[0035] The display module adopts a 7×4 matrix layout structure, namely 7 segment control lines (SEG1-SEG7) and 4 bit control lines (COM0-COM3). The LED array is arranged in a matrix manner, containing a total of 28 LEDs, forming a complete multi-head status display system. Each COM line connects to the cathode of up to 7 LEDs, while each SEG line connects to the anode of LEDs on different COM lines. Through this matrix connection method, the on / off state of 28 LEDs can be independently controlled using only 11 signal lines, greatly simplifying the circuit connection.

[0036] The display module features a multi-zone layout: each column of LEDs (COM0 to COM3) represents an independent timed control object, while each row of LEDs (SEG1 to SEG7) indicates a different status or digital segment. This design allows users to clearly observe the working status, timer settings, and remaining time of each control object, avoiding the inconvenience of switching between different displays required in traditional methods. The control module sends display data to the LED driver module via serial communication. The scanning control circuit inside the driver module automatically completes the dynamic scanning display of the LEDs, achieving a stable and flicker-free display effect.

[0037] The button module adopts an independent object button design. This module contains four independent buttons, each corresponding to a different timing control object. Each button uses a single-pole single-throw switch structure, with one end directly connected to the ground wire and the other end connected to the positive power supply through a 10KΩ pull-up resistor, and also connected to the corresponding input pin (KEY1, KEY2, KEY3, KEY4) of the control module.

[0038] The button module adopts a direct mapping design concept of "one button corresponds to one object," breaking through the limitation of traditional timers that require cyclic switching of objects. Users only need to press the corresponding button to immediately select the control object to be timed, without having to remember complex operation sequences. This design greatly simplifies the user's operation process and improves the intuitiveness and efficiency of operation.

[0039] From a circuit perspective, the button module uses pull-up resistors to generate a stable high-level signal. When a button is pressed, the input pin is pulled low. The control module accurately identifies the user's button press by detecting changes in the level of each input pin. To improve anti-interference capabilities, the pull-up resistor values ​​in the circuit are precisely calculated to ensure stable signal recognition under various operating environments.

[0040] The external drive module CN1, through its standardized interface design, enables efficient connection and control between the system and external load devices. Centered on a 10-pin standard connector, this module provides eight independent control signals and two ground interfaces. Each control signal is connected to the control module's output pin via a 470Ω precision current-limiting resistor, providing drive capability while protecting the control module from overcurrent damage. The connector's standardized design ensures reliable connection with various types of external devices.

[0041] The external drive module enables independent control of multiple channels, with each controlled object having its own dedicated control signal line, avoiding the control confusion that can occur due to signal multiplexing in traditional designs. The control module precisely controls the operating state and timing function of each external load device by controlling the high and low levels of the output pins through timing control.

[0042] In terms of electrical characteristics design, the external drive module considers compatibility with various load types, simultaneously adapting to resistive, inductive, or capacitive loads. Precise selection of the current-limiting resistor ensures signal integrity and interference immunity under various operating conditions. The entire drive module adopts a modular design concept, meeting current application requirements while reserving the possibility of system expansion, enabling the product to adapt to future functional upgrades.

[0043] The power module employs a two-stage conversion architecture to ensure a high-efficiency, low-ripple, and highly interference-resistant power supply for the system. The module comprises a main power conversion circuit and a backup power detection circuit.

[0044] The main power conversion circuit consists of two stages: the first stage uses a 7550 switching regulator in a small SOT-89 package, featuring high efficiency and a wide input range. The input filter network consists of a 47μH power inductor and a 100μF / 6V electrolytic capacitor, effectively suppressing high-frequency noise and voltage fluctuations on the input side.

[0045] The second stage employs a low-dropout linear regulator (LDO) to further stabilize the output voltage of the first stage to a precise 3.3V, providing low-noise, high-precision power for the control and display circuits. The regulator's output is equipped with a 100nF high-quality filter capacitor to meet the stringent power supply requirements of digital circuits. The low-dropout linear regulator features extremely low dropout characteristics, maintaining stable output even at low input voltages, thus improving system reliability in harsh power environments.

[0046] The backup power detection circuit is implemented using a precision voltage divider network. This circuit uses an RC network consisting of a 330KΩ high-precision resistor and a 100nF filter capacitor to convert the battery voltage to a range suitable for the analog-to-digital converter in the control module. This design enables the system to monitor the power status in real time, promptly detect low battery conditions, and alert the user to prevent data loss. A Schottky diode SS14 in the circuit prevents reverse current flow, protecting U3 (7550) and subsequent circuitry.

[0047] It also includes a conversion module, which is mainly used to convert alternating current (AC) to direct current (DC) and perform preliminary voltage regulation and filtering.

[0048] Includes: AC input (ACN1, ACL1): Alternating current input.

[0049] Fuse (FUSE1): Protects the circuit from damage caused by overcurrent.

[0050] Rectifier bridge (D1, D2): Rectifies alternating current into pulsating direct current.

[0051] Filter capacitor (EC2): Filters the rectified voltage to reduce ripple.

[0052] Voltage regulator chip (U1, model BP8522): further stabilizes the voltage and outputs +5V DC. The two-stage conversion architecture further converts +5V to +3.3V.

[0053] The operation of the multi-head timer circuit based on timing latch to prevent accidental triggering in this embodiment mainly includes the following steps: Initial state setup: After the system powers on, the power supply filter circuit stabilizes the operating voltage, and each logic device enters its initial state. The Q output of the D flip-flop is low, the input signal is high when the button is not pressed, the XOR gate outputs a high level, and the control module detects a high level to indicate that no button has been pressed.

[0054] Timing window creation: When the user presses a button, the button signal changes from high to low. This change is transmitted simultaneously to two paths: one path goes directly to the trigger terminal of the monostable multivibrator, and the other path goes through an RC delay circuit to the D terminal of the D flip-flop. The monostable multivibrator detects the rising edge when the button is released and immediately generates a timing window pulse with a width of 100ms, which serves as the clock signal for the D flip-flop.

[0055] Delayed sampling processing: The key signal is delayed by approximately 50ms by an RC delay circuit before reaching the D terminal of the D flip-flop. This delay ensures that the sampling point is located in the middle of the timing window, enabling the system to effectively filter out transient interference.

[0056] Midpoint state latch: When the rising edge of the pulse output by the monostable multivibrator reaches the clock terminal of the D flip-flop, the D flip-flop latches the current level state of the D terminal. For valid key presses, the D terminal should remain at a low level; for false triggers caused by transient interference or moisture, the D terminal may have already returned to a high level.

[0057] State comparison verification: The Q output of the D flip-flop and the original button signal are simultaneously fed into an XOR gate for logical comparison. The two signals will remain consistent if and only if the button is pressed for more than the midpoint of the sampling window (50ms), at which point the XOR gate will output a low level, indicating that a valid button press has been detected; otherwise, the XOR gate will output a high level, indicating that the button press is invalid.

[0058] Effective signal transmission: The output signal of the XOR gate is sent to the button input terminal of the control module after passing through the debouncing circuit. The control module only executes the corresponding button function when it detects a low-level signal, thus effectively distinguishing between intentional user operation and environmental interference.

[0059] State Reset Preparation: After a complete key press detection cycle, when the key is released, the system returns to its initial state, preparing for the next key press detection. Even after the key is released, the timing latch circuit retains the state of the last valid key press until a new key press triggers the entire detection process to restart.

[0060] The multi-head electronically controlled timer circuit of this embodiment solves the technical problems of cumbersome operation and unintuitive status display of traditional multi-head timers through independent object button design and matrix status display technology. It realizes efficient and intuitive operation of multi-channel timing control and has significant technical effects: First, the independent object button design changes the traditional timer operation method that requires cycling through selected objects. Users only need to press the corresponding independent button to directly select the target control object, eliminating the need to remember complex operation sequences. This direct mapping design of "one button to one object" makes the operation more intuitive, reducing the user's learning cost and operational difficulty. Compared with the traditional cyclic selection method, the independent object button design significantly shortens the operation time for users to complete object selection, improving operational efficiency.

[0061] Secondly, the matrix LED status display system enables simultaneous display of multiple object statuses, allowing users to clearly observe the working status and timing settings of all controlled objects at a glance. This design avoids the inconvenience of switching between different object statuses in traditional display methods, improving the efficiency and accuracy of information acquisition. Compared to traditional single display areas, matrix status displays enable users to obtain status information for all controlled objects more quickly.

[0062] Third, the multi-task parallel processing architecture enables the system to manage the timing tasks of multiple controlled objects simultaneously, with each task running independently and without interference. Users can set or modify the timing parameters of other controlled objects at any time while one controlled object's timing task is in progress, achieving true multi-task parallel control. The system maintains a high level of timing accuracy, meeting the requirements for precise timing control.

[0063] Fourth, the modular hardware design and standardized interfaces give the system excellent scalability and compatibility. The standardized interface design of the driver modules allows the system to easily connect to various external load devices, adapting to the needs of different application scenarios. At the same time, the modular hardware architecture also facilitates future functional upgrades; users can expand functionality through simple module replacement without replacing the entire system.

[0064] Fifth, intelligent power management technology effectively extends the lifespan of the device. The system dynamically adjusts the operating mode based on the user's operation frequency, automatically reducing display brightness or turning off some display areas during periods of inactivity to reduce power consumption. This intelligent power management technology significantly extends the device's battery life and improves the product's usability.

[0065] In summary, the multi-head electronically controlled timer circuit of this embodiment solves the technical problems of cumbersome operation and unintuitive status display of traditional multi-head timers by using independent object button design, matrix status display technology and multi-task parallel processing architecture. It achieves efficient and intuitive operation of multi-channel timing control, and has significant technical effects and practical value. Detailed Implementation Method 2 In practical applications of multi-head electronically controlled timers, especially in kitchen environments, a serious technical problem exists: false triggering. Due to the widespread presence of moisture and grease in kitchen environments, the button surface is easily contaminated, creating conductive paths and causing false triggering. Traditional button detection circuits typically employ a simple pull-up resistor design. When a button is pressed, the input pin is pulled low, and the control module detects this low level as a valid button press. However, this simple design cannot distinguish between genuine user button presses and false triggers caused by environmental factors. This allows the system to unintentionally change the timing settings without user intervention, posing a safety hazard. Furthermore, users may accidentally touch the buttons during cooking; without a confirmation mechanism, this can also lead to unintended changes to the timing settings, affecting normal use and potentially causing safety accidents.

[0067] This embodiment proposes a multi-head timer circuit for preventing false triggering based on timing latch, which adds a timing latch circuit structure between each target button and the control module. This circuit structure mainly consists of three logic devices: a 74HC74 D flip-flop, a CD4538 monostable multivibrator, and a 74HC86 XOR gate, forming a complete timing latch mechanism for preventing false triggering.

[0068] Specifically, the anti-false triggering circuit of this embodiment adopts the following structural design: The target button output is divided into two paths: one path is directly connected to the trigger input of the monostable multivibrator CD4538, and the other path is connected to the data terminal of the D multivibrator 74HC74 after passing through an RC delay circuit.

[0069] The CD4538 monostable multivibrator employs a positive edge triggering mode. Its RC time constant network consists of a 10KΩ resistor and a 0.01μF capacitor, generating a positive pulse with a fixed width of 100ms. This pulse serves as the clock input signal for the 74HC74 D flip-flop. The trigger terminal of the monostable multivibrator is held low by a pull-down resistor of less than 1KΩ to ensure static stability. It is only triggered when a button is pressed and released, generating a rising edge.

[0070] The other path of the button signal is processed through an RC delay circuit, which consists of a 10KΩ resistor and a 4.7μF capacitor, providing a delay of approximately 50ms. The delayed signal is then connected to the D data input of a 74HC74 D flip-flop. The D flip-flop uses a standard DIP-14 package, operates at 5V, and its clock input is connected to the output of a monostable multivibrator, while the D terminal is connected to the RC-delayed button signal.

[0071] The Q output of the D flip-flop and the original button signal are simultaneously fed into the two inputs of the XOR gate 74HC86. The XOR gate uses a logic comparison principle, outputting a high level only when the two input signals are different, and a low level when they are the same. The output of the XOR gate is ultimately connected to the button input of the control module.

[0072] In addition, the entire timing latch circuit also includes power supply filtering and protection circuitry, consisting of a 0.1μF decoupling capacitor and a 10Ω current-limiting resistor, to ensure stable circuit operation. All power supply pins of the digital logic chips are connected to the same 5V power supply, and the ground pins are connected to a common ground, forming a complete power supply system.

[0073] The operation of the multi-head timer circuit based on timing latch to prevent accidental triggering in this embodiment mainly includes the following steps: Initial state setup: After the system powers on, the power supply filter circuit stabilizes the operating voltage, and each logic device enters its initial state. The Q output of the D flip-flop is low, the input signal is high when the button is not pressed, the XOR gate outputs a high level, and the control module detects a high level to indicate that no button has been pressed.

[0074] Timing window creation: When the user presses a button, the button signal changes from high to low. This change is transmitted simultaneously to two paths: one path goes directly to the trigger terminal of the monostable multivibrator, and the other path goes through an RC delay circuit to the D terminal of the D flip-flop. The monostable multivibrator detects the rising edge when the button is released and immediately generates a timing window pulse with a width of 100ms, which serves as the clock signal for the D flip-flop.

[0075] Delayed sampling processing: The key signal is delayed by approximately 50ms by an RC delay circuit before reaching the D terminal of the D flip-flop. This delay ensures that the sampling point is located in the middle of the timing window, enabling the system to effectively filter out transient interference.

[0076] Midpoint state latch: When the rising edge of the pulse output by the monostable multivibrator reaches the clock terminal of the D flip-flop, the D flip-flop latches the current level state of the D terminal. For valid key presses, the D terminal should remain at a low level; for false triggers caused by transient interference or moisture, the D terminal may have already returned to a high level.

[0077] State comparison verification: The Q output of the D flip-flop and the original button signal are simultaneously fed into an XOR gate for logical comparison. The two signals will remain consistent if and only if the button is pressed for more than the midpoint of the sampling window (50ms), at which point the XOR gate will output a low level, indicating that a valid button press has been detected; otherwise, the XOR gate will output a high level, indicating that the button press is invalid.

[0078] Effective signal transmission: The output signal of the XOR gate is sent to the button input terminal of the control module after passing through the debouncing circuit. The control module only executes the corresponding button function when it detects a low-level signal, thus effectively distinguishing between intentional user operation and environmental interference.

[0079] State Reset Preparation: After a complete key press detection cycle, when the key is released, the system returns to its initial state, preparing for the next key press detection. Even after the key is released, the timing latch circuit retains the state of the last valid key press until a new key press triggers the entire detection process to restart.

[0080] The multi-head timer circuit based on timing latches successfully solves the problem of false triggering faced by traditional multi-head timers in a kitchen environment through timing detection and dual verification mechanisms. The specific technical effects are reflected in the following aspects: Significantly reduced false trigger rate: By employing a timing latch mechanism to double-verify key signals, the system can effectively distinguish between genuine user operations and false triggers caused by moisture or oil contamination. Real-world testing shows that this design can reduce the false trigger rate by over 95%, decreasing it from multiple false triggers per day in traditional circuits to almost none, greatly improving system reliability.

[0081] Significantly enhanced anti-interference capability: The timing latch circuit requires the key signal to remain stable within the sampling window, a design that inherently provides immunity to short-term interference. Experiments have shown that this design effectively resists common electromagnetic and electrostatic interference in kitchen environments, with anti-interference capability more than three times higher than traditional designs.

[0082] Through the above-mentioned technical effects, this implementation method successfully solves the technical problem that traditional multi-head timers are easily affected by moisture and oil stains in the kitchen environment, leading to false triggering. It significantly improves the reliability and safety of the product in complex environments, and provides users with a more stable and safer multi-head electrical appliance timing control solution. Detailed Implementation Method 3 Several key technical challenges exist when applying multi-head electronic timers in large venues such as commercial kitchens: First, commercial kitchens typically require controlling far more cooking equipment than the 2-6 controlled objects in home settings. However, traditional multi-head timer designs concentrate all control logic on a single control module, directly controlling each device via parallel I / O ports. This design leads to insufficient I / O port resources in the control module when the number of controlled objects increases, failing to meet expansion needs. Second, the complex environment and wide distribution of equipment in commercial kitchens make traditional parallel wiring susceptible to noise interference and severe signal attenuation over long distances, affecting control reliability. Finally, existing multi-head timers are usually fixed-design hardware, with no flexible adjustment of the number of control heads. When users need to add controlled objects, the entire system often needs to be replaced, resulting in resource waste and increased operating costs. These problems severely restrict the large-scale application of multi-head electronic timers in commercial environments.

[0084] This embodiment proposes a cascaded expansion circuit for multi-head timers based on a CAN bus. It employs a distributed control architecture and a standardized communication bus to achieve modular expansion capabilities for the multi-head timer system. The circuit system consists of a main control board and multiple expansion modules, interconnected via a CAN bus to form a complete distributed control network.

[0085] The main control board is the core control unit of the entire system. Based on the original multi-head timer circuit, it adds two core components: the CAN controller MCP2515 and the CAN transceiver MCP2551. The MCP2515 is a high-performance CAN controller in a 28-pin SOIC package, operating at 3.3V or 5V, and supporting the CAN 2.0A / B protocol. This chip connects to the control module via an SPI interface, with the SCK, SI, SO, and CS pins connected to the corresponding SPI bus pins of the control module. The MCP2515 integrates a CAN protocol controller responsible for assembling, sending, receiving, and parsing CAN messages. It integrates three transmit buffers and two receive buffers, supporting standard and extended frames. The OSC1 and OSC2 pins of the MCP2515 are connected to a 16MHz crystal oscillator, providing a precise clock source for the CAN controller. The INT pin is connected to the external interrupt input of the control module to notify the control module of the arrival of new CAN messages.

[0086] The MCP2551 CAN transceiver, packaged in an 8-pin SOIC, is an interface device connecting the CAN controller and the physical CAN bus. This device converts the logic level signals of the CAN controller into differential signals to drive the CAN bus. The TXD pin of the MCP2551 connects to the TXCAN pin of the MCP2515, and the RXD pin connects to the RXCAN pin. The CANH and CANL pins are the actual physical interfaces of the CAN bus, transmitting data via differential signals. The RS pin is connected to ground through a 10KΩ resistor, setting the transceiver to high-speed mode. The VDD pin is connected to a 5V power supply, and the VSS pin is grounded.

[0087] The main control board also features a CAN bus power isolation circuit, consisting of a TPS2372 isolated DC-DC converter and an optocoupler isolator HCPL-0601, ensuring electrical isolation between the CAN bus and the main control circuit and improving the system's anti-interference capability. The bus termination matching resistor is a 120Ω precision resistor, connected between CANH and CANL via a DIP switch, allowing users to flexibly configure the termination resistor according to the network topology.

[0088] The expansion modules are the functional units of the system, each capable of independently controlling several timing objects. The expansion modules utilize the STM32F030 microcontroller as their core, a 32-bit microcontroller based on the ARM Cortex-M0 architecture, featuring 16KB of flash memory and 4KB of RAM, operating at frequencies up to 48MHz. This microcontroller integrates various peripherals, including timers, ADCs, UART, SPI, and I2C, meeting the diverse functional requirements of the expansion modules. Pins PA9 and PA10 of the STM32F030 are connected to the UART debug interface, while pins PA4 to PA7 are configured as SPI interfaces, connecting to the MCP2551 CAN transceiver. Furthermore, pins PB0 to PB7 of the microcontroller are configured as GPIO outputs, connecting to relays or solid-state relays via ULN2003A Darlington drivers to control external load devices.

[0089] The address allocation for the expansion modules uses a daisy-chain structure. Each module's ADDR_IN pin is connected to the ADDR_OUT pin of the previous module, and the first module's ADDR_IN is directly connected to the main control board's ADDR_START signal. Internally, each module uses an RC delay circuit (10KΩ resistor and 10μF capacitor) to generate a delay of approximately 100ms to ensure the sequential nature of address allocation. The module's ADDR_ACK pin is connected to the CAN bus to confirm successful address allocation to the main control board.

[0090] The system's clock synchronization mechanism employs a master-slave design. The main control board includes a high-precision temperature-compensated crystal oscillator (TCXO) with a frequency of 16.384MHz and a temperature stability of ±2ppm. The control module periodically broadcasts clock synchronization information to all expansion modules via the CAN bus. Each expansion module uses a PLL circuit to lock the master clock, ensuring precise synchronization of all timers in the system.

[0091] The operation of a CAN bus-based multi-head timer cascade expansion circuit mainly includes the following steps: System Initialization: When the system powers on, the main control board first completes its own initialization, including setting the CPU operating frequency, initializing peripheral interfaces, and configuring CAN controller parameters. The MCP2515 is set to a communication rate of 125Kbps, using the standard CAN2.0A frame format. Subsequently, the main control board enters the address allocation preparation state, setting the ADDR_START signal to a high level, ready to begin the address allocation process for the expansion modules.

[0092] Automatic Address Allocation: The main control board broadcasts an address allocation command, which is contained in the frame with identifier 0x000 in the CAN message. Upon receiving this command, the first expansion module connected with ADDR_IN high immediately sends an address request message (identifier 0x7FF) to the CAN bus. Upon receiving the request, the main control board assigns a unique address (between 1 and 15) and sends an address allocation message via the CAN bus. After receiving the assigned address, the first module sets its ADDR_OUT pin high, triggering the address allocation process for the next module. Due to the daisy-chain structure and RC delay design, the system automatically assigns a unique address to each expansion module according to the physical connection order, without manual intervention.

[0093] Clock synchronization establishment: After address allocation is complete, the main control board begins sending a clock synchronization message (identifier 0x001) once per second. This message contains the main control board's high-precision clock count value. Upon receiving the synchronization message, each expansion module adjusts its local clock frequency through its internal PLL circuit to ensure synchronization with the main control clock. This mechanism ensures precise synchronization of timers across all modules in the entire system, avoiding potential time deviations that may occur after prolonged operation.

[0094] Command Distribution and Execution: When the user operates on the main control board, they select the target control object and set timing parameters. The main control board converts these operations into CAN command messages. The message identifier contains the address information of the target expansion module, and the data field contains the specific timing setting parameters. For example, the identifier 0x101 indicates that it is sent to the module with address 1, and the data 0x0230 indicates that a 30-minute timer is set. After receiving the command message, the target expansion module parses the timing parameters and controls the corresponding output channel to drive the external load device.

[0095] Status monitoring and feedback: Each expansion module continuously monitors the timing status of each channel during operation. When the status changes (such as timer start, timer end, or anomaly), the expansion module proactively sends a status message to the CAN bus. The message identifier includes the module address and channel information. The main control board receives these status messages and updates the display content, enabling users to understand the working status of each controlled object in real time. This proactive reporting mechanism reduces the polling burden on the main control board and improves the system's real-time performance and efficiency.

[0096] Abnormal Situation Handling: The system has multiple built-in abnormal handling mechanisms. When an error occurs in CAN bus communication, such as five consecutive failed message transmissions, the main control board will attempt to reset the CAN controller and reinitialize the bus. If an expansion module does not respond to a query from the main control board within 20 seconds, the system will mark the module as offline and report the fault to the user through the display module. In addition, each expansion module has an independent watchdog timer that automatically resets the module in case of software malfunction, ensuring stable system operation.

[0097] Dynamic expansion support: The system supports hot-swapping, allowing new expansion modules to be added during operation. When a new module is detected, the main control board automatically executes the address allocation process to assign an available address to the new module. Similarly, when a module is disconnected and then reconnected, the system will reallocate its original address to ensure continuity of control.

[0098] The CAN bus-based multi-head timer cascade expansion circuit successfully solves the scalability and reliability problems faced by traditional multi-head timers in commercial environments through a distributed architecture and communication mechanism. The specific technical effects are manifested in the following aspects: The system's scalability is significantly enhanced: By connecting multiple expansion modules via a CAN bus, the system breaks through the limitation of a single control module's I / O port, theoretically supporting up to 15 expansion modules, each controlling 4-8 timing objects, greatly expanding the upper limit of the number of controllable objects. This enables the system to meet the multi-head control needs of large venues such as commercial kitchens, expanding the number of controllable objects from the traditional 2-6 to dozens or even hundreds.

[0099] The preferred embodiments of this patent have been described in detail above. However, this patent is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of this patent.

Claims

1. A multi-head electronically controlled timer circuit, characterized in that, include: The control module uses a multi-pin central processing unit with multiple independent key input pins and multiple control output pins, which are used to receive independent object selection signals and execute parallel timing control logic. The display module adopts a matrix LED driving structure, which refers to the structure in which the LED array is arranged in a matrix manner. It has multiple control lines and multiple control lines, and can display the status of multiple objects simultaneously through matrix connection. The button module includes multiple independent object buttons, which adopt a direct mapping design of one button to one object. Each independent object button is connected to the corresponding input pin of the control module through a pull-up resistor circuit. The driver module controls multiple LEDs of the display module through a matrix driving method; The power module adopts a two-stage conversion architecture, including a switching regulator and a linear regulator.

2. The multi-head electronically controlled timer circuit according to claim 1, characterized in that, The control module uses a 20-pin packaged central processing unit, which has a battery voltage detection pin, multiple independent key input pins and multiple segment control output pins, and integrates a clock circuit, a timer circuit and a storage circuit.

3. The multi-head electronically controlled timer circuit according to claim 1, characterized in that, The display module includes an LED driver and an LED indicator array. The LED driver is packaged in a 16-pin package and has bit control pins DIG1 to DIG4 and segment control pins SEG1 to SEG7. The DIG1 to DIG4 pins and the SEG1 to SEG7 pins are respectively connected to the four bit control lines and seven segment control lines of the display module. Multiple LEDs are controlled by a matrix drive method and connected to the control module through a two-wire interface.

4. The multi-head electronically controlled timer circuit according to claim 3, characterized in that, The LED indicator array adopts a seven-by-four matrix layout structure, including seven segment control lines and four bit control lines. Each column of LEDs represents an independent timing control object, and each row of LEDs represents a different state segment.

5. The multi-head electronically controlled timer circuit according to claim 1, characterized in that, The independent object button adopts a single-pole single-throw switch structure, which is connected to the positive terminal of the power supply through a pull-up resistor, and is also connected to the corresponding button input pin of the control module.

6. The multi-head electronically controlled timer circuit according to claim 1, characterized in that, The button module includes four independent object buttons, each corresponding to a different timing control object, for direct mapping control of one object per button.

7. The multi-head electronically controlled timer circuit according to claim 1, characterized in that, It also includes a timing latch circuit to prevent accidental triggering. The timing latch circuit includes a monostable multivibrator, a D flip-flop, and an XOR gate. The output of the monostable multivibrator is connected to the clock terminal of the D flip-flop. The data terminal of the D flip-flop receives the key signal via an RC delay circuit. The output of the D flip-flop is compared with the original key signal by the XOR gate and then output to the control module.

8. The multi-head electronically controlled timer circuit according to claim 1, characterized in that, The power module adopts a two-stage voltage regulation structure, with the front stage being a switching voltage regulator circuit and the rear stage being a low-dropout linear voltage regulator circuit, forming a power supply architecture with low ripple and strong anti-interference.

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