integrated circuit

Abstract

An integrated circuit includes a first semiconductor fin and a second semiconductor fin; a trench isolation region between the first semiconductor fin and the second semiconductor fin; a first dielectric layer on top surfaces of the first semiconductor fin and the second semiconductor fin and on side surfaces of the first semiconductor fin and the second semiconductor fin and on a top surface of the trench isolation region; a second dielectric layer on the first dielectric layer; and a source / drain trench in the first semiconductor fin.

Description

Technical Field

[0001] This disclosure concerns integrated circuits. Background Technology

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advancements in integrated circuit materials and design have yielded generation after generation of integrated circuits, each generation smaller and more complex than the last. Throughout the development of integrated circuits, functional density (i.e., the number of interconnect devices per wafer area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This scaling-up process typically benefits production efficiency and reduces associated costs. However, this scaling-up also increases the complexity of processes and the manufacture of integrated circuits. Utility Model Content

[0003] Some embodiments described herein provide an integrated circuit comprising: a first region comprising: each of a plurality of first semiconductor fins comprising a stack of a plurality of first semiconductor layers, and each of the stacks of first semiconductor layers having a first width; and a plurality of first trench isolation regions interspersed with the first semiconductor fins, and each of the first trench isolation regions having a second width; and a second region comprising: each of a plurality of second semiconductor fins comprising a stack of a plurality of second semiconductor layers, and each of the stacks of second semiconductor layers having a third width; and a plurality of second trench isolation regions interspersed with the second semiconductor fins, and each of the second trench isolation regions having a fourth width, wherein the ratio of the first width to the second width is greater than the ratio of the third width to the fourth width, and wherein the sidewalls of the top first semiconductor layer of the first semiconductor fin and the sidewalls of the top second semiconductor layer of the second semiconductor fin have the same angle relative to the vertical direction.

[0004] Some embodiments described herein provide an integrated circuit comprising: a first region comprising: each of a plurality of first semiconductor fins comprising a stack of a plurality of first semiconductor layers, and each of the stacks of first semiconductor layers having a first width; and a plurality of first trench isolation regions interspersed with the first semiconductor fins, and each of the first trench isolation regions having a second width; and a second region comprising: each of a plurality of second semiconductor fins comprising a stack of a plurality of second semiconductor layers, and each of the stacks of second semiconductor layers having a third width; a plurality of second trench isolation regions interspersed with the second semiconductor fins, and each of the second trench isolation regions having a fourth width; and a dielectric shielding structure located on one of the first trench isolation regions and having a top surface of the lowest first semiconductor layer of an adjacent first semiconductor fin.

[0005] Some embodiments described herein provide an integrated circuit comprising: a first semiconductor fin and a second semiconductor fin; a trench isolation region between the first semiconductor fin and the second semiconductor fin; a first dielectric layer located on the top surface and side surface of the first semiconductor fin and the second semiconductor fin, and located on the top surface of the trench isolation region; a second dielectric layer located on the first dielectric layer; and a source / drain trench located in the first semiconductor fin. Attached Figure Description

[0006] The best understanding of this disclosure is achieved by reading the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figures 1-15 Cross-sectional and top views of integrated circuits at various process stages, according to some embodiments;

[0008] Figure 16 Here is a flowchart of a method for manufacturing an integrated circuit according to some embodiments;

[0009] Figure 17 This is a flowchart of a method for manufacturing an integrated circuit according to some embodiments.

[0010] [Symbol Explanation]

[0011] 100: Integrated Circuits

[0012] 101: Transistor

[0013] 102:Substrate

[0014] 103: Stacking

[0015] 104: Semiconductor layer

[0016] 105: Channel

[0017] 106: Sacrificial Semiconductor Layer

[0018] 107: Sacrificial Semiconductor Nanostructures

[0019] 108: Fins

[0020] 110: Trench

[0021] 112: Trench isolation zone

[0022] 114: Padding layer (dielectric layer)

[0023] 116: Padding layer (dielectric layer)

[0024] 118: Padding layer (dielectric layer)

[0025] 120: Shallow trench isolation layer (dielectric layer)

[0026] 122: Semiconductor layer

[0027] 124: Dielectric backing layer (dielectric layer)

[0028] 126: Dielectric layer

[0029] 127: Dielectric shielding structure

[0030] 128: Dielectric layer (BARC layer)

[0031] 130: Sacrificial gate structure

[0032] 131: Trench

[0033] 132: Dielectric layer

[0034] 134: Sacrificial gate layer

[0035] 136: Gate spacer layer

[0036] 138: Stacking

[0037] 140: Sacrificial Dielectric Nanostructure

[0038] 141: Groove

[0039] 142: Inner Spacer Layer

[0040] 144: Source / Drain Region

[0041] 145: Contact Etching Stop Layer (CESL Layer)

[0042] 146: Interface gate dielectric layer

[0043] 147: Interlayer Dielectric Layer (ILD)

[0044] 148: High-K gate dielectric layer

[0045] 150: Hard mask layer

[0046] 152: Gate metal

[0047] 1600: Method

[0048] 1602, 1604, 1606, 1608, 1610, 1612: Operations

[0049] 1700: Method

[0050] 1702, 1704, 1706, 1708, 1710: Operations

[0051] D1, D2: Width dimensions

[0052] X, Y, Z: Direction

[0053] XX,YY: Cut-off line Detailed Implementation

[0054] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, references to numbers and / or letters may be repeated. This repetition is for simplicity and clarity and does not, in itself, define relationships between the various embodiments and / or configurations discussed.

[0055] Additionally, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper,” and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another. These spatial relative terms are intended to cover not only the orientations depicted in the figures but also different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0056] Terms indicating relative degree, such as “about”, “substantially”, etc., should be interpreted as understood by one of ordinary skill in the art in light of current technical specifications.

[0057] This disclosure relates generally to semiconductor devices, and more specifically to field-effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructured devices. Examples of nanostructured devices include gate-all-around (GAA) devices, nanosheet FETs (NSFETs), nanowire FETs (NWFETs), and similar devices. In advanced technology nodes, the active area spacing between nanostructured devices is typically uniform, the source / drain epitaxial structure is symmetrical, and a metal gate surrounds the four sides of the nanostructure (e.g., a nanosheet).

[0058] The embodiments disclosed herein provide a method for forming nanostructured transistors that minimizes damage to the top nanostructures / channels of the transistor, regardless of the local density of the semiconductor fins (OD) forming the transistor. After forming shallow trench isolation regions between these fins, a process is performed to form a dielectric shielding structure on the shallow trench isolation regions to protect the shallow trench isolation regions during subsequent process steps. The process of forming the dielectric shielding structure includes depositing a dielectric layer on the shallow trench isolation regions and the sidewalls and top surfaces of the semiconductor fins, and depositing a bottom anti-reflective coating (BARC) on the dielectric layer.

[0059] The embodiments disclosed herein employ a multi-step etching process to remove the BARC layer and dielectric layer from the top of all fins without damaging the top layer of these fins, regardless of the local density of the fins. The multi-step etching process includes performing a chemical mechanical planarization process on the BARC layer, followed by an etch-back process to reduce the height of the BARC layer relative to the dielectric layer, and finally an etching process to remove the dielectric layer from the top of the fins. This ensures that the top channel of the transistor is not substantially damaged, regardless of the local density of the fins. This maintains the required effective width of the top channel of the transistor, resulting in superior electrical characteristics and better overall performance. Furthermore, this can improve wafer yield and the overall functionality of the integrated circuit and the electronic components embedded in it.

[0060] While the accompanying figures and description focus primarily on examples of stacked nanostructure transistors containing channels, the principles disclosed herein extend to other types of transistors. These principles are extended to MOS transistors, FinFET transistors, and other types of transistors.

[0061] Figures 1-15 This is a cross-sectional view of an integrated circuit 100 manufactured according to some embodiments of the present disclosure. This manufacturing process produces a plurality of transistors 101, which will be described in further detail below.

[0062] Figure 1 This is a cross-sectional view of integrated circuit 100 at an intermediate stage of its process. Integrated circuit 100 includes substrate 102. Substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, or the like, which may be doped (e.g., with P-type or N-type dopants) or undoped. The semiconductor material of substrate 102 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium rhodium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof. Other substrates, such as single-layer, multilayer, or gradient substrates, may be used.

[0063] Integrated circuit 100 includes a semiconductor stack 103, which comprises a plurality of alternating semiconductor layers 104 and sacrificial semiconductor layers 106. Figure 1 In the example, stack 103 comprises three semiconductor layers 104 and three sacrificial semiconductor layers 106. However, in practice, different numbers of semiconductor layers 104 and sacrificial semiconductor layers 106 can be used without departing from the scope of this disclosure.

[0064] As will be explained in further detail below, semiconductor layer 104 will be patterned to form stacked channels of multiple transistors. As explained in more detail below, sacrificial semiconductor layer 106 will eventually be completely removed and used to enable the formation of gate metal and other structures around the semiconductor nanostructure.

[0065] In some embodiments, the semiconductor layer 104 may be formed of a suitable first semiconductor material such as silicon or silicon carbide, and the sacrificial semiconductor layer 106 may be formed of a second semiconductor material such as silicon or germanium. Each layer of the multilayer stack 103 may use chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or similar methods.

[0066] Due to the high etch selectivity between the materials of semiconductor layer 104 and sacrificial semiconductor layer 106, the sacrificial semiconductor layer 106 composed of the second semiconductor material can be removed without significantly etching the semiconductor layer 104 composed of the first semiconductor material, thereby allowing the semiconductor layer 104 to be released to form the stacked channel region of the transistor, as will be explained in more detail below.

[0067] In one embodiment, semiconductor layer 104 is silicon, and sacrificial semiconductor layer 106 is silicon-germanium. In some embodiments, sacrificial semiconductor layer 106 has a germanium concentration between 10% and 50%, but other concentrations may be used without departing from the scope of this disclosure. This allows sacrificial semiconductor layer 106 to be selectively etched relative to semiconductor layer 104. Other materials and concentrations may be used without departing from the scope of this disclosure.

[0068] exist Figure 2 In the stack 103, a plurality of semiconductor fins 108 are formed. The semiconductor fins 108 are formed by forming trenches 110 in the stack 103 and in the substrate 102. Although Figure 1 Not shown, but a hard mask layer is first formed and patterned on stack 103. Trench 110 can be formed using an anisotropic etching process that etches in a downward direction in the presence of the patterned hard mask. The etching process defines semiconductor fin 108 by forming trench 110 through sacrificial semiconductor layer 106, semiconductor layer 104 and substrate 102.

[0069] exist Figure 3 In this process, a shallow trench isolation region 112 is formed by depositing dielectric material in the trench 110 between the fins 108. Figure 3 The shallow trench isolation zone 112 is illustrated as a single layer of material. However, in reality, the shallow trench isolation zone 112 is multi-layered, such as... Figure 5 This will be described in further detail. The dielectric layer can be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes. In an exemplary embodiment, the dielectric material comprises silicon oxide. However, the dielectric material may include SiN, SiCN, SiOC, SiOCN, or other dielectric materials without departing from the scope of this disclosure.

[0070] After depositing the dielectric material of the shallow trench isolation region 112, an etch-back process is performed to recess the top of the shallow trench isolation region 112 below the lowest sacrificial semiconductor layer 106. This results in the top surface of the shallow trench isolation region 112 being lower than the bottom surface of the lowest sacrificial semiconductor layer 106 of each fin. Other processes can be used to form the shallow trench isolation region 112 without departing from the scope of this disclosure.

[0071] Figure 4 It is integrated circuit 100 in such Figure 3 A top view showing the process stages. Figure 4 The diagram illustrates a region of integrated circuit 100 in which multiple semiconductor fins 108 have been formed. The semiconductor fins 108 extend along the X direction. Shallow trench isolation regions 112 are formed between adjacent fins 108 and extend along the X direction.

[0072] The semiconductor fin has a width dimension D1 in the Y direction, and the shallow trench isolation region 112 has a width dimension D2 in the Y direction. The area of ​​the fin 108 can also be referred to as the OD area. The density of the fin 108 in a specific region can be calculated as D1 / (D1+D2). In some embodiments, D1 is between 15 nm and 25 nm. In some embodiments, D2 is between 40 nm and 50 nm. Other dimensions can be used without departing from the scope of this disclosure.

[0073] Figure 4 The diagram illustrates a single region of an integrated circuit 100 with a specific density of fins 108 (or OD density). However, in practice, the integrated circuit 100 may contain multiple regions of fins 108 with different fin densities. For example, a single integrated circuit may have logic transistors, I / O transistors, electrostatic discharge (ESD) protection transistors, or other types of transistors. Each of these types of transistors may be formed by fins 108 with different widths in the Y direction and shallow trench isolation regions with different widths.

[0074] As will be explained in more detail below, due to different fin densities, process steps can lead to different types of damage or problems in various different regions at different fin densities. The embodiments disclosed herein provide for reducing or completely preventing various types of damage in all regions with different fin densities.

[0075] Figure 4 The diagram also illustrates the YY and XX sections. The YY section indicates the location of the cross-section for various "Y-view" views, where the horizontal axis of the diagram is in the Y direction. The XX section indicates the location of the cross-section for various "X-view" views, where the horizontal axis of the diagram is in the X direction.

[0076] Figure 5 According to some embodiments, this is the Y-view of integrated circuit 100. Figure 5 The formation of the layer is illustrated, which will form a dielectric shielding structure to cover the shallow trench isolation area 112.

[0077] Figure 5 An embodiment of the shallow trench isolation region 112 comprising multiple layers is also illustrated. Specifically, the shallow trench isolation region 112 includes a first liner layer 114. The first liner layer 114 is disposed in the trench 110 and on the bottom of the trench 110. Figure 5 The sidewalls of substrate 102 (not shown) are in direct contact. Dielectric pad layer 114 may comprise SiO, SiN, SiON, SiCN, SiOC, SiOCN, or other suitable dielectric materials. In the specific embodiments given herein, dielectric pad layer 114 comprises silicon oxide. Dielectric pad layer 114 may be deposited by CVD, ALD, PVD, or other suitable dielectric processes.

[0078] The shallow trench isolation region 112 includes a second backing layer 116. The second backing layer 116 is in direct contact with the first backing layer 114. The dielectric backing layer 116 may contain SiO, SiN, SiON, SiCN, SiOC, SiOCN, or other suitable dielectric materials. The dielectric backing layer 116 may be deposited by CVD, ALD, PVD, or other suitable dielectric processes.

[0079] The shallow trench isolation region 112 includes a third dielectric liner layer 118. Liner layer 118 is in direct contact with liner layer 116. The dielectric liner layer 118 may contain SiO, SiN, SiON, SiCN, SiOC, SiOCN, or other suitable dielectric materials. The dielectric liner layer 118 may be deposited using CVD, ALD, PVD, or other suitable dielectric processes.

[0080] The shallow trench isolation region 112 includes a shallow trench isolation layer 120. The shallow trench isolation layer 120 corresponds to the main layer of the shallow trench isolation region 112. In some embodiments, the shallow trench isolation layer 120 may comprise SiO, SiN, SiON, SiCN, SiOC, SiOCN, or other suitable dielectric materials. In a particular example, the shallow trench isolation layer 120 comprises silicon oxide. The shallow trench isolation layer 120 may be deposited by CVD, ALD, PVD, or other suitable dielectric processes.

[0081] exist Figure 5 In this process, a thin semiconductor layer 122 has been deposited on the side and top surfaces of the semiconductor fin 108 and the top surface of the shallow trench isolation region 112. The thin semiconductor layer 122 is in direct contact with the semiconductor layer 104, the sacrificial semiconductor layer 106, and the dielectric layers 114, 116, 118, and 120 of the shallow trench isolation region 112. The semiconductor layer 122 may comprise silicon, silicon germanium, or other suitable semiconductor materials. In one embodiment, the material of the semiconductor layer 122 is the same as the material of the substrate 102 and the semiconductor layer 104. The semiconductor layer 122 may be formed by CVD, ALD, PVD, epitaxial growth, or other suitable deposition processes.

[0082] exist Figure 5 In this process, a dielectric liner layer 124 is deposited on the semiconductor layer 122. The dielectric liner layer 124 liner the top and side surfaces of the semiconductor fin 108 and the top surface of the shallow trench isolation region 112, wherein the semiconductor layer 122 is located between the dielectric layer 124, the dielectric fin 108, and the shallow trench isolation region 112. The dielectric liner layer 124 may comprise SiO, SiN, SiON, SiCN, SiOC, SiOCN, or other suitable dielectric materials. In a particular embodiment, the dielectric liner layer 124 comprises silicon oxide. The dielectric liner layer 124 may be formed by CVD, ALD, PVD, or other suitable dielectric processes.

[0083] exist Figure 5 In this process, dielectric layer 126 has been deposited on the top and side surfaces of semiconductor fin 108 and on the top surface of shallow trench isolation region 112. Dielectric layer 126 is in direct contact with dielectric pad layer 124. Dielectric layer 126 may comprise SiO, SiN, SiON, SiCN, SiOC, SiOCN, or other suitable dielectric materials. In a particular embodiment, dielectric layer 126 comprises silicon oxide. Dielectric layer 126 may be formed by CVD, ALD, PVD, or other suitable deposition processes.

[0084] As will be described in further detail below, dielectric layer 126 is the main layer of the dielectric shielding structure, which protects trench isolation region 112 in subsequent process steps. To form the dielectric shielding structure, dielectric layer 126 is removed from the top of fin 108 and the upper surface of fin 108. However, removing dielectric layer 126 from the top surface of fin 108 can cause various problems in different regions of the integrated circuit 100 with varying fin densities. Specifically, a portion of dielectric layer 126 may remain on the top surface of fin 108 in high-fin-density regions. Furthermore, the top semiconductor layer 104 may be damaged or its width reduced in lower-fin-density layers. However, as will be explained in more detail below, the embodiments disclosed herein avoid these problems and remove dielectric layer 126 from the top of fin 108 in all various density regions without damaging the top semiconductor layer 104 in any of the various density regions.

[0085] exist Figure 5 In this configuration, dielectric layer 128 is formed on dielectric layer 126. In some embodiments, dielectric layer 128 is a BARC layer comprising an organic polymer or other type of dielectric layer. Dielectric layer 128 fills the remaining space between semiconductor fins 108. Dielectric layer 128 extends significantly above the top surface of dielectric layer 126. Although Figure 5 Only a single region of integrated circuit 100 with a specific fin density is shown, but unless otherwise stated, the processes and structures formed in one region are also formed in other regions with different fin densities. Dielectric layer 128 may also comprise SiO, SiN, SiON, SiCN, SiOC, SiOCN, or other suitable dielectric materials.

[0086] exist Figure 6 In some embodiments, a CMP process is performed. The CMP process reduces the height of dielectric layer 128. Specifically, the CMP process gives dielectric layer 128 a top surface that is coplanar with the top surface of dielectric layer 126. In some embodiments, dielectric layer 126 is not etched by the CMP process due to an etch stop layer used in the CMP process. In some embodiments, dielectric layer 126 is partially etched by the CMP process.

[0087] exist Figure 7 In some embodiments, an etch-back process is performed. The etch-back process reduces the height of the top surface of dielectric layer 128 without substantially reducing the height of dielectric layer 126. Therefore, the etch process used for etch-back selectively etches the material of dielectric layer 128 relative to the material of dielectric layer 126. The etch-back process may include a dry etching process or other suitable etching process. The etching process may include timed etching to etch dielectric layer 128 to a selected height.

[0088] In some embodiments, after the etch-back process, the top surface of the BARC layer 128 is higher than the top surface of the fin 108 and lower than the top surface of the dielectric layer 126. In some embodiments, the top surface of the dielectric layer 128 is lower than the top surface of the fin 108 after the etch-back process.

[0089] exist Figure 8 In this process, an etching process is performed to remove at least a portion of the dielectric layer 126 on top of the fin 108. The etching process may also partially etch the BARC layer 128. The etching process may include wet etching, dry etching, timed etching, or other etching processes. The etching process may selectively etch the dielectric layer 126 relative to the material of the BARC layer 128. In some embodiments, in Figure 8 As shown in the process stages, the top surfaces of dielectric layer 126 and BARC layer 128 are not flat. In some embodiments, the etch-back process is a dry etching process using etching gas to selectively etch dielectric layer 126 relative to BARC layer 128.

[0090] exist Figure 9A In this process, an etching process is performed to completely remove the BARC layer 128 and completely remove the dielectric layer 126 from the top surface and upper sidewalls of the semiconductor fin 108. The etching process also removes the dielectric layer 124 from the top surface and upper sidewalls of the semiconductor fin 108. The etching process may include wet etching, dry etching, timed etching, or other suitable etching processes. In some embodiments, the etch-back process is a dry process using an etching gas to selectively etch the dielectric layer 126 and the BARC layer 128 relative to the other materials being etched.

[0091] In some embodiments, the top surface of dielectric layer 126 is... Figure 9A The etching process shown results in a surface that is essentially level with the top surface of dielectric layer 124. Figure 9A In this process, the top surface of the dielectric layer 126 is lower than the bottom surface of the lowest sacrificial semiconductor nanostructure 106.

[0092] exist Figures 9A-9G In the process stage shown, a dielectric shielding structure 127 is formed on a shallow trench isolation region 126. The dielectric shielding structure 127 includes a dielectric layer 124 and a dielectric layer 126. The dielectric layer 126 is the main layer of the dielectric shielding structure 127.

[0093] The dielectric shielding structure 127 protects the shallow trench isolation region 112 during subsequent etching processes. For example, the final sacrificial semiconductor layer 106 is replaced by a sacrificial dielectric nanostructure. In some embodiments, the sacrificial dielectric nanostructure has the same material as the shallow trench isolation layer 120. Ultimately, the sacrificial dielectric nanostructure is removed and replaced by gate metal. Removing the sacrificial dielectric nanostructure severely impairs or removes the shallow trench isolation layer 120, thereby adversely affecting the function of the shallow trench isolation region 112. However, due to the presence of the dielectric shielding structure 127, the sacrificial dielectric nanostructure can be removed without significantly impairing the shallow trench isolation region 112. Alternatively, the dielectric shielding structure 127 can protect the shallow trench isolation region 112 during other process steps. In some embodiments, the dielectric shielding structure 127 is retained after the transistor is fully formed. In some embodiments, the dielectric shielding structure 127 can be removed in subsequent process steps.

[0094] Figure 9B , Figure 9C and Figure 9D According to some embodiments, the process of... Figures 6-9A The relevant etching steps pertain to the low-fin density regions, medium-fin density regions, and high-fin density regions of the integrated circuit 100. In one embodiment, Figure 9B The fin density in the medium is between 20% and 30%. Figure 9C The fin density in the middle is between 30% and 40%, while Figure 9D The fin density is between 40% and 60%, but other fin densities may be used without departing from the scope of this disclosure. Figures 9B-9D This illustrates that in various fin density regions, the dielectric layer 126 has been completely removed from the fin 108 without damaging the top semiconductor layer 104. In some embodiments, the sidewalls of the top semiconductor layer 104 in each region are between 85° and 90°. In some embodiments, the thickness of the dielectric shielding structure 127 in each region is between 20 nm and 60 nm. The angle of the sidewalls of the semiconductor layer 104 is defined beforehand during fin formation. The principles of this disclosure help ensure that the angle of the top semiconductor layer 104 does not decrease during process steps following the initial definition of the fin.

[0095] In some embodiments, the fin concentration can be expressed as the ratio of the width of the semiconductor fin in the region to the width of the trench isolation region in the region. In this way, regions with different fin concentrations all have the top semiconductor layer forming substantially the same angle with respect to the vertical direction from the sidewalls.

[0096] Figures 9E-9G The diagram shows regions of low, medium, and high fin density in an integrated circuit, where unutilized fins are present. Figures 6-9A The etching process removes the dielectric layer 126 from the top of the fin 108. For example... Figure 9EAs shown, the top semiconductor layer 104 is significantly damaged in the low fin density region. Figures 9A-9G The sidewalls of the top semiconductor layer 104 form a small angle, therefore, most of the top layer is relatively narrow in the Y direction. The top semiconductor layer 104 is ultimately separated into top channels of multiple transistors, as will be explained in more detail below. The width of the top channel in the Y direction (corresponding to the channel width) is effectively reduced. This results in a lower overall conductivity of the top channel in saturation mode. Therefore, by Figure 9E The electrical performance of the transistor formed by the fin 108 is reduced.

[0097] exist Figure 9G In high-fin density regions, a portion of the dielectric layer 126 remains on top of the fins 108. This can cause significant damage to the transistors formed by these fins. In some embodiments, if the source / drain trenches cannot be properly formed due to the presence of the dielectric layer 126 on top of the fins 108, the transistor may become completely inoperable. Figure 9F In this region, dielectric layer 126 is completely removed without damaging the top semiconductor layer 104. Therefore, the process performed according to the principles of this disclosure... Figures 9B-9D The semiconductor fins 108 in the sample have been correctly formed and will produce normally functioning transistors.

[0098] Figure 10 This is, according to some embodiments, the X-view of integrated circuit 100. Figure 10 In this configuration, a sacrificial gate structure 130 is formed on the fin 108. (Reference) Figure 4 Multiple sacrificial gate structures extend in parallel above the fin 108 and the shallow trench isolation region 112.

[0099] The sacrificial gate structure 130 includes a dielectric layer 132. In one embodiment, the dielectric layer 132 comprises silicon oxide. However, alternatively, the dielectric layer 132 may comprise SiN, SiCN, SiOC, SiOCN, or other dielectric materials without departing from the scope of this disclosure. In some embodiments, the dielectric layer 132 has a low-k dielectric material. The dielectric layer 132 can be deposited by CVD, ALD, or PVD.

[0100] The sacrificial gate structure includes a sacrificial gate layer 134 on the dielectric layer 132. The sacrificial gate layer 134 may contain a material with high etch selectivity relative to the trench isolation region 112. In one embodiment, the sacrificial gate layer 134 contains polysilicon. However, the sacrificial gate layer 134 may be a conductive, semiconductor non-conductive material, and may be or contain amorphous silicon, polysilicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The sacrificial gate layer 134 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques used for depositing the selected material. Figure 4 For illustration, in some embodiments, the sacrificial gate structure 130 may include an additional dielectric layer above the sacrificial gate layer.

[0101] exist Figure 10 In this configuration, a gate spacer layer 136 is formed on the sidewalls of the sacrificial gate structure 130. Specifically, the gate spacer layer 136 can be formed on the sidewalls of the dielectric layer 132 and the sacrificial gate layer 134. The gate spacer layer 136 can also be formed on other exposed surfaces of the integrated circuit. The gate spacer layer 136 can be formed by PVD, CVD, ALD, or other suitable deposition processes. After forming the gate spacer layer 136, the horizontal portion of the gate spacer layer 136 (e.g., in the XY plane) can be removed by an anisotropic etching process, thereby exposing the upper surface of the fin 108. After patterning the gate spacer layer, the vertically thicker portion of the gate spacer layer 136 can be retained. The gate spacer layer 136 can contain one or more of SiO, SiN, SiON, SiCN, SiOCN, SiOC, or other suitable dielectric materials. Figure 4 Not shown, in some embodiments, an additional gate spacer layer or pad layer is also formed on the gate spacer layer 136. The additional gate spacer layer may comprise one or more of SiO, SiN, SiON, SiCN, SiOCN, SiOC, or other suitable dielectric materials.

[0102] exist Figure 11 In some embodiments, a source / drain trench 131 is formed. After patterning the gate spacer layer 136, one or more etching processes are performed to form the source / drain trench 131 in the fin 108. Forming the source / drain trench 131 includes etching each semiconductor layer 104, each sacrificial semiconductor layer 106, and a portion of the substrate 102. Therefore, the removal operation may include suitable etching operations for removing material from the semiconductor layers 104, sacrificial semiconductor layers 106, and substrate 102. The etching process may include reactive ion etching (RIE), neutral beam etching (NBE), atomic layer etching (ALE), or other etching methods.

[0103] The formation of the source / drain trench 131 results in the formation of a stack 138 of channels 105. Specifically, after the formation of the source / drain trench 131, the remaining portion of the semiconductor layer 104 now corresponds to the stacked channels 105 of the transistor. The formation of the source / drain trench 131 results in the formation of a plurality of sacrificial semiconductor nanostructures 107 by the sacrificial semiconductor layer 106.

[0104] exist Figure 12In some embodiments, an etching process is performed. The etching process completely removes the sacrificial semiconductor nanostructure 107. Therefore, the etching process can utilize an etchant to selectively etch the material of the sacrificial semiconductor nanostructure 107 relative to other exposed materials (including the materials of the substrate 102 and the channel 105).

[0105] exist Figure 12 In some embodiments, a sacrificial dielectric nanostructure 140 is formed to replace the sacrificial semiconductor nanostructure 107. The sacrificial dielectric nanostructure 140 can be formed by depositing dielectric material in the trench 131 and in the gaps formed between the channels 105 by removing the sacrificial semiconductor nanostructure 107. The dielectric material can be deposited by CVD, ALD, or other suitable deposition processes. The dielectric material may comprise SiO, SiN, SiON, SiCN, SiOC, SiOCN, or other suitable dielectric materials. In a particular embodiment, the dielectric material is the same as the material of the shallow trench isolation layer 120.

[0106] After depositing the dielectric material, an anisotropic etching process is performed to remove the dielectric material from the trench 131. The sacrificial gate structure 130 includes a gate spacer layer 136, which acts as a mask during the etching process. The dielectric material is removed from all locations except directly beneath the sacrificial gate structure 130 and the gate spacer layer 136. This etching process results in the formation of a sacrificial dielectric nanostructure 140 from the dielectric material. According to some embodiments, the sacrificial dielectric nanostructure may also be referred to as a dielectric oxide interposer.

[0107] exist Figure 13 In this process, a selective etching process is performed to recess the exposed end portions of the sacrificial dielectric nanostructure 140 while substantially not etching the channel 105. More specifically, the recess 141 is formed in the sacrificial dielectric nanostructure 140 adjacent to the channel 105 or between the lowest channel 105 and the substrate 102. The recess 141 can be formed by performing an etching process that selectively etches the material of the sacrificial dielectric nanostructure 140 relative to the materials of the channel 105 and the substrate 102.

[0108] Although Figure 13 The view shows the trench isolation region 112, but the trench isolation region 112 is protected by the dielectric shielding structure 127 during the etching process. As mentioned above, in some embodiments, the shallow trench isolation layer 120 has the same material as the sacrificial dielectric nanostructure 140. Therefore, the shallow trench isolation layer may also be etched if the dielectric shielding structure 127 is not present during the etching process.

[0109] exist Figure 14In this process, a dielectric layer is deposited. This dielectric layer is deposited on the exposed surfaces of channel 105, gate spacer layer 136, sacrificial dielectric nanostructure 140, and substrate 102 using a conformal deposition process. The dielectric layer 132 may contain SiCN, SiOCN, SiON, SiN, or other suitable dielectric materials. The dielectric layer can be formed using suitable deposition methods, such as CVD, ALD, PVC, or other deposition processes.

[0110] exist Figure 14 In this process, an inner spacer layer 142 is also formed in the groove 141. The inner spacer layer 142 contacts the end of the sacrificial semiconductor nanostructure 107 and also contacts the channel 105. As will be described in detail below, the inner spacer layer 142 separates the gate metal from the source / drain.

[0111] exist Figure 15 In some embodiments, source / drain regions 144 are formed in source / drain trenches 131. Source / drain regions 144 are epitaxially grown from channels 105. Source / drain regions 144 grow on exposed portions of fins 108 and contact channels 105. For each stack 138 of channels 105, there are two source / drain regions 144. Some stacks 138 of channels 105 may share source / drain regions 144 with stacks 138 of channels 105 adjacent to each other in the X direction.

[0112] The source / drain region 144 may comprise any acceptable semiconductor material, such as a semiconductor material suitable for N-type or P-type devices. In some embodiments, for an N-type region, the source / drain region 144 comprises a material subjected to tensile strain in the channel region, such as silicon, SiC, SiCP, SiP, or the like. According to some embodiments, for a P-type transistor, the source / drain region 144 comprises a material subjected to compressive strain in the channel region, such as SiGe, SiGeB, Ge, GeSn, or the like. The source / drain region 144 may have a surface protruding from the corresponding surface of the fin and may have facets. In some embodiments, adjacent source / drain regions 144 may be merged to form a single source / drain region 144 over two adjacent fins 108.

[0113] In some embodiments, an in-situ doping process may be performed during the formation of the source / drain region 144 to implant N-type or P-type dopant into the source / drain region 144 according to the conductivity type of the formed transistor or region. The N-type dopant may comprise phosphorus, arsenic, antimony, or other suitable N-type dopant. The P-type dopant may comprise boron, gallium, indium, or other suitable P-type dopant. The source / drain region 144 may be doped and subsequently annealed. The source / drain region 144 may have approximately 10-1 19 cm -3 To about 10 21 cm-3 The doping concentration between them.

[0114] exist Figure 15 In some embodiments, a contact etch stop layer (CESL) 145 and an interlayer dielectric (ILD) 147 are formed. The CESL layer 145 may comprise a thin dielectric layer conformally deposited on the exposed surfaces of the source / drain regions 144, the gate spacer layer 136, and other exposed surfaces. The CESL layer 145 may comprise SiN, SiC, SiOC, SiOCN, SiON, or other suitable charge-giving materials. The CESL layer 145 can be deposited using CVD, ALD, PVD, or other suitable deposition processes.

[0115] Interlayer dielectric layer 147 covers CESL layer 145. Interlayer dielectric layer 147 fills the remaining space between adjacent sacrificial gate structures 130. Interlayer dielectric layer 147 may correspond to the lowest interlayer dielectric layer of integrated circuit 100. In some embodiments, interlayer dielectric layer 147 may be referred to as ILD0. Although not shown herein, additional interlayer dielectric layers may be formed above interlayer dielectric layer 147. A network of conductive vias and metal lines may be formed on the upper interlayer dielectric layer. Interlayer dielectric layer 147 may contain SiO, SiON, SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. Interlayer dielectric layer 147 may be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0116] In some embodiments, a CMP process is performed after depositing the interlayer dielectric layer 147. The CMP process makes the top surface of the interlayer dielectric layer 147, the CESL layer 145, the gate spacer layer 136, and the sacrificial gate layer 134 coplanar. The CMP process also reduces the height of the sacrificial gate structure 130.

[0117] exist Figure 15 In some embodiments, the sacrificial gate layer 134 is removed. The sacrificial gate layer 134 can be removed by an etching process that selectively etches the material of the sacrificial gate layer 134 relative to adjacent materials (e.g., dielectric layer 132 and gate spacer layer 124). The removal of the sacrificial gate layer 134 results in the formation of gate metal 152 between the gate spacers 136.

[0118] exist Figure 15In some embodiments, an etching process is performed to remove the sacrificial dielectric nanostructure 140. The sacrificial dielectric nanostructure 140 can be removed by a selective etching process using an etchant selective to the material of the channel 105, such that the sacrificial dielectric nanostructure 140 is removed without substantially etching the channel 105. In some embodiments, the etching process is an isotropic etching process using an etching gas and optionally a carrier gas, wherein the etching gas comprises F2 and HF, and the carrier gas can be an inert gas such as Ar, He, N2, combinations thereof, or similar gases. In some embodiments, the etching process causes the side surfaces of the channel 105 to become rounded. The etching process also causes gaps to be created between the channels 105.

[0119] The shallow trench isolation region 112 is protected by the dielectric shielding structure 127 during the removal of the sacrificial dielectric nanostructure 140. As described above, in some embodiments, the shallow trench isolation layer 120 has the same material as the sacrificial dielectric nanostructure. Therefore, if the dielectric shielding structure 127 is not present during the etching process, the shallow trench isolation layer may also be etched.

[0120] exist Figure 15 In some embodiments, a gate dielectric layer is formed. The gate dielectric layer includes an interface gate dielectric layer 146 and a high-k gate dielectric layer 148. In some embodiments, the interface gate dielectric layer 146 is deposited on an exposed portion of the channel 105. The interface gate dielectric layer is formed directly on the exposed portion of the channel 105. The high-k gate dielectric layer 148 is formed on the interface gate dielectric layer 146 and other surfaces, such as on the exposed sidewalls of the gate spacer layer 136 and on the inner spacer layer 142.

[0121] An interface gate dielectric layer 146 surrounds channel 105. The interface gate dielectric layer 146 may comprise a dielectric material, such as silicon oxide, silicon nitride, or other suitable dielectric materials. The interface gate dielectric layer 146 may comprise a low-k dielectric relative to a high-k dielectric (e.g., hafnium oxide or other high-k dielectric materials that can be used in the gate dielectric layer of a transistor). High-k dielectrics may comprise dielectric materials with a dielectric constant higher than that of silicon oxide. The interface gate dielectric layer 146 may be formed using a thermal oxidation process, a chemical vapor deposition (CVD) process, or an ion layer deposition (ALD) process. The interface gate dielectric layer 146 may have a thickness between 0.5 nm and 2 nm. Other materials, deposition processes, and thicknesses may be used for the interface gate dielectric layer 146 without departing from the scope of this disclosure.

[0122] A high-k gate dielectric layer 148 is deposited in a conformal deposition process. This conformal deposition process deposits the high-k gate dielectric layer 148 on the interface gate dielectric layer 146, on the substrate 102, and on the gate spacer layer 136. The high-k gate dielectric layer surrounds the channel 105. The high-k gate dielectric layer 148 has a thickness between 1 nm and 3 nm. The high-k dielectric layer comprises one or more dielectric materials, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The high-k gate dielectric layer 148 can be formed by CVD, ALD, or any suitable method. Other thicknesses, deposition processes, and materials may be used for the high-k gate dielectric layer 148 without departing from the scope of this disclosure.

[0123] exist Figure 15 In some embodiments, a gate metal 152 is deposited. This gate metal 152 is deposited to replace the sacrificial gate layer 134 and the sacrificial dielectric nanostructure 140. Therefore, the gate metal 152 is located above the hard mask layer 150 and in the gate trench above the hard mask layer 150. The gate metal 152 also surrounds the channel 105.

[0124] exist Figure 15 In the diagram, a single gate metal 152 is shown as the gate electrode of transistor 101. However, in practice, gate metal 152 may comprise multiple gate metals. For example, gate metal 152 may comprise one or more pad layers, one or more work function layers, and gate fill material filling the remaining space between gate spacer layers 136. Gate metal 152 may comprise one or more of Ti, TiN, Ta, TaN, Al, Cu, Co, Ru, W, Au, or other suitable conductive materials. Gate metal 152 may be deposited by PVD, ALD, or CVD.

[0125] exist Figure 15 In this process, the fabrication of transistor 101 is essentially complete. The top channel 105 of each transistor 101 corresponds to a portion of the top semiconductor layer 104. In various regions with different fin densities, the top channel 105 of each transistor has, respectively, a... Figures 9B-9D The Y-direction profile is shown. This results in each transistor 101 in each region having a well-functioning top channel 105, which helps to improve the overall performance of the transistor 101.

[0126] Figure 16 This is a flowchart of a method 1600 for forming an integrated circuit according to some embodiments. Method 1600 can utilize... Figures 1-15The described structure, process, and system. In operation 1602, method 1600 includes forming a first semiconductor fin and a second semiconductor fin. One embodiment of the first semiconductor fin and the second semiconductor fin is... Figure 5 Semiconductor fin 108 is included. In operation 1604, method 1600 includes forming a trench isolation region between the first semiconductor fin and the second semiconductor fin. One embodiment of the trench isolation region is... Figure 5 The trench isolation region 112 is included. In operation 1606, method 1600 includes forming a first dielectric layer on the top and side surfaces of the first and second semiconductor fins, and on the top surface of the trench isolation region. One embodiment of the first dielectric layer is... Figure 5 The dielectric layer 126 is described above. In operation 1608, method 1600 includes forming a second dielectric layer on the first dielectric layer. One embodiment of the second dielectric layer is... Figure 5 The dielectric layer 128 is in the first semiconductor fin. In operation 1610, method 1600 includes removing the second dielectric layer from the upper surface of the first dielectric layer by performing a chemical mechanical planarization (CMP) process on the second dielectric layer. In operation 1612, method 1600 includes forming a source / drain trench in the first semiconductor fin after performing the CMP process. One embodiment of the source / drain trench is... Figure 11 One of the source / drain trenches in the 131.

[0127] Figure 17 This is a flowchart of a method 1700 for forming an integrated circuit according to some embodiments. Method 1700 can utilize... Figures 1-15 The described structure, process, and system. In operation 1702, method 1700 includes forming a trench isolation region between a first semiconductor fin and a second semiconductor fin. One embodiment of the first semiconductor fin and the second semiconductor fin is... Figure 5 Semiconductor fin 108 in the middle. In operation 1704, method 1700 includes forming a dielectric shielding structure on a shallow trench isolation region by a first dielectric layer. In operation 1706, method 1700 includes forming the dielectric shielding structure by performing a chemical mechanical planarization (CMP) process on the first dielectric layer. One embodiment of the dielectric shielding structure is... Figure 9A The dielectric shielding structure 127. In operation 1708, method 1700 includes forming a dielectric shielding structure by removing a portion of the first dielectric layer from above the first semiconductor fin and the second semiconductor fin using a first etching process. In operation 1710, method 1700 includes forming a dielectric shielding structure by performing a second etching process to recess the top surface of the first dielectric layer below a plurality of semiconductor layers below the first semiconductor fin and the second semiconductor fin.

[0128] The embodiments disclosed herein provide a method for forming nanostructured transistors that reduces damage to the top nanostructures / channels of the transistor, regardless of the local density of the semiconductor fins (OD) forming the transistor. After forming shallow trench isolation regions between the fins, a process is performed to form a dielectric shielding structure on the shallow trench isolation regions, which protects the shallow trench isolation regions during subsequent process steps. The process of forming the dielectric shielding structure includes depositing a dielectric layer on the shallow trench isolation regions and the sidewalls and top surface of the semiconductor fins, and depositing a bottom anti-reflective coating (BARC) on the dielectric layer.

[0129] The embodiments disclosed herein employ a multi-step etching process to remove the BARC layer and dielectric layer from the top of all fins without damaging the top layer of the fins, regardless of the local density of the fins. The multi-step etching process includes performing a chemical mechanical planarization (CMP) process on the BARC layer, followed by an etch-back process to reduce the height of the BARC layer relative to the dielectric layer, and finally an etching process to remove the dielectric layer from the BARC layer. This results in no substantial damage to the top channel of the transistor, regardless of the local density of the fins. This maintains the required effective width of the top channel of the transistor, resulting in superior electrical characteristics and better overall performance. Furthermore, it improves wafer yield and the overall functionality of the integrated circuit and the electronic components embedded in it.

[0130] In some embodiments, a method includes forming a first semiconductor fin and a second semiconductor fin, forming a trench isolation region between the first semiconductor fin and the second semiconductor fin, and forming a first dielectric layer on the top and side surfaces of the first semiconductor fin and the second semiconductor fin, and on the top surface of the trench isolation region. The method includes forming a second dielectric layer on the first dielectric layer and performing a chemical mechanical polishing (CMP) process on the second dielectric layer to remove the second dielectric layer from the top surface of the first dielectric layer. The method includes forming a source / drain trench in the first semiconductor fin after performing the CMP process.

[0131] In some embodiments described herein, a method is provided that further includes performing a first etching process after a chemical mechanical planarization process to cause the top surface of a second dielectric layer to be recessed to a level below the top surface of the first dielectric layer and above the top surface of the first semiconductor fin.

[0132] In some embodiments described herein, a method is provided that further includes removing at least a portion of the first dielectric layer by performing a second etching process after a first etching process.

[0133] In some embodiments described herein, a method is provided that further includes removing the second dielectric layer by performing a third etching process after a second etching process.

[0134] In some embodiments described herein, a method is provided that further includes removing a first dielectric layer from the top surface of a first semiconductor fin and the top surface of a second semiconductor fin by performing a third etching process.

[0135] In some embodiments described herein, a method is provided that includes defining a dielectric shielding structure on a shallow trench isolation region by performing a third etching process, the dielectric shielding structure including the remainder of a first dielectric layer.

[0136] In some embodiments described herein, a method is provided that includes forming a sacrificial gate structure spanning a first semiconductor fin and a second semiconductor fin after performing a third etching process and before forming a plurality of source / drain trenches.

[0137] In some embodiments described herein, a method is provided that includes forming a plurality of stacked channels of a transistor by forming source / drain trenches from a first semiconductor fin, and a plurality of sacrificial semiconductor nanostructures interleaved with these channels.

[0138] In some embodiments described herein, a method is provided comprising: removing a sacrificial semiconductor nanostructure; and forming a gate metal of a transistor to replace the sacrificial semiconductor nanostructure.

[0139] In some embodiments described herein, a method is provided comprising: forming a plurality of sacrificial dielectric nanostructures to replace a sacrificial semiconductor nanostructure; removing the sacrificial dielectric nanostructures; and forming a gate metal to replace the sacrificial dielectric nanostructures.

[0140] In some embodiments described herein, a method is provided that includes removing a sacrificial dielectric nanostructure by performing an etching process when a dielectric shielding structure is located above a trench isolation region.

[0141] In some embodiments, some of the examples described herein provide a method in which the sacrificial dielectric nanostructure and the trench isolation region have the same dielectric material.

[0142] In some embodiments, a method includes forming a trench isolation region between a first semiconductor fin and a second semiconductor fin, and performing a chemical mechanical planarization (CMP) process on a first dielectric layer, removing a portion of the first dielectric layer from above the first semiconductor fin and the second semiconductor fin by a first etching process, and performing a second etching process to recess the top surface of the first dielectric layer below a plurality of semiconductor layers of the first semiconductor fin and the second semiconductor fin, such that a dielectric shielding structure is formed by the first dielectric layer on the shallow trench isolation region.

[0143] In some embodiments, some of the examples described herein provide a method comprising performing a third etching process between a chemical mechanical planarization process and a first etching process.

[0144] In some embodiments described herein, a method is provided in which: a chemical mechanical planarization process is performed to remove a portion of a second dielectric layer from the top surface of a first dielectric layer; and a third etching process is performed to recess the top surface of the second dielectric layer to a level below the top surface of the first dielectric layer.

[0145] In some embodiments described herein, a method is provided in which a second etching process completely removes the second dielectric layer.

[0146] In some embodiments described herein, a method is provided in which the first dielectric layer is silicon nitride and the second dielectric layer is an organic polymer.

[0147] In some embodiments described herein, a method is provided that includes forming source / drain regions of a transistor in a first semiconductor fin after forming a dielectric shielding structure.

[0148] In some embodiments, an integrated circuit includes a first region comprising a plurality of semiconductor fins, each semiconductor fin having a stack of a plurality of first semiconductor layers, each stack of the first semiconductor layers having a first width, and a plurality of first trench isolation regions interspersed with the first semiconductor fins, each first trench isolation region having a second width. The integrated circuit includes a second region comprising a plurality of second semiconductor fins, each second semiconductor fin having a stack of a plurality of second semiconductor layers, each stack of the second semiconductor layers having a third width, and a plurality of second trench isolation regions interspersed with the second semiconductor fins, each second trench isolation region having a fourth width. The ratio of the first width to the second width is greater than the ratio of the third width to the fourth width. The sidewalls of a semiconductor layer at the top of the first fin and the sidewalls of the second semiconductor layer at the top of the second fin have the same angle relative to the vertical direction.

[0149] In some embodiments described herein, an integrated circuit is provided that includes a dielectric shielding structure located on one of the first trench isolation regions and has a top surface of the lowest first semiconductor layer adjacent to the first semiconductor fin.

[0150] In some embodiments, an integrated circuit includes a first region comprising a plurality of semiconductor fins, each semiconductor fin having a stack of a plurality of first semiconductor layers, each stack of the first semiconductor layers having a first width, and a plurality of first trench isolation regions interspersed with the first semiconductor fins, each first trench isolation region having a second width. The integrated circuit includes a second region comprising a plurality of second semiconductor fins, each second semiconductor fin having a stack of a plurality of second semiconductor layers, each stack of the second semiconductor layers having a third width, and a plurality of second trench isolation regions interspersed with the second semiconductor fins, each second trench isolation region having a fourth width. The integrated circuit includes a dielectric shielding structure located on one of the first trench isolation regions and having a top surface of the lowest first semiconductor layer adjacent to the first semiconductor fin.

[0151] In some embodiments, the ratio of the first width to the second width is greater than the ratio of the third width to the fourth width. The sidewall of a semiconductor layer at the top of the first fin and the sidewall of the second semiconductor layer at the top of the second fin have the same angle relative to the vertical direction.

[0152] In some embodiments, an integrated circuit includes a first semiconductor fin and a second semiconductor fin; a trench isolation region between the first semiconductor fin and the second semiconductor fin; a first dielectric layer located on the top surface and side surface of the first semiconductor fin and the second semiconductor fin, and located on the top surface of the trench isolation region; a second dielectric layer located on the first dielectric layer; and a source / drain trench located in the first semiconductor fin.

[0153] In some embodiments, the top surface of the second dielectric layer is lower than the top surface of the first dielectric layer and higher than the top surface of the first semiconductor fin.

[0154] In some embodiments, a shallow trench isolation region defines a dielectric shielding structure, which includes a portion of a first dielectric layer.

[0155] In some embodiments, the integrated circuit further includes source / drain regions of transistors located in the first semiconductor fin.

[0156] In some embodiments, the sidewalls of the top first semiconductor layer of the first semiconductor fin and the sidewalls of the top second semiconductor layer of the second semiconductor fin have the same angle relative to the vertical direction.

[0157] In some embodiments, multiple stacked channels of a transistor are formed from a first semiconductor fin by forming source / drain trenches.

[0158] The foregoing summary outlines several features of the embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit, characterized in that, Include: The first region includes: Each of the plurality of first semiconductor fins comprises a stack of a plurality of first semiconductor layers, and each of the stack of the plurality of first semiconductor layers has a first width; as well as A plurality of first trench isolation regions are interspersed with the plurality of first semiconductor fins, and each of the plurality of first trench isolation regions has a second width; as well as The second region includes: Each of the plurality of second semiconductor fins comprises a stack of a plurality of second semiconductor layers, and each of the stack of the plurality of second semiconductor layers has a third width; and A plurality of second trench isolation regions are interspersed with the plurality of second semiconductor fins, and each of the plurality of second trench isolation regions has a fourth width, wherein a ratio of the first width to the second width is greater than a ratio of the third width to the fourth width, wherein a sidewall of a top first semiconductor layer of the plurality of first semiconductor fins and a sidewall of a top second semiconductor layer of the plurality of second semiconductor fins have the same angle relative to the vertical direction.

2. The integrated circuit as described in claim 1, characterized in that, It includes a dielectric shielding structure located on one of the first trench isolation regions and has a top surface of a lowest first semiconductor layer adjacent to a first semiconductor fin.

3. An integrated circuit, characterized in that, Include: The first region includes: Each of the plurality of first semiconductor fins comprises a stack of a plurality of first semiconductor layers, and each of the stack of the plurality of first semiconductor layers has a first width; as well as A plurality of first trench isolation regions are interspersed with the plurality of first semiconductor fins, and each of the plurality of first trench isolation regions has a second width; as well as The second region includes: Each of the plurality of second semiconductor fins comprises a stack of a plurality of second semiconductor layers, and each of the stack of the plurality of second semiconductor layers has a third width; A plurality of second trench isolation regions are interspersed with the plurality of second semiconductor fins, each of the plurality of second trench isolation regions having a fourth width; as well as A dielectric shielding structure is located on one of the first trench isolation regions and has a top surface of a lowest first semiconductor layer adjacent to a first semiconductor fin.

4. The integrated circuit as described in claim 3, characterized in that, The ratio of the first width to the second width is greater than the ratio of the third width to the fourth width, and one sidewall of the top first semiconductor layer of the plurality of first semiconductor fins and one sidewall of the top second semiconductor layer of the plurality of second semiconductor fins have the same angle relative to the vertical direction.

5. An integrated circuit, characterized in that, Include: A first semiconductor fin and a second semiconductor fin; A trench isolation region is located between the first semiconductor fin and the second semiconductor fin; A first dielectric layer is located on the top surface of the first semiconductor fin and the second semiconductor fin and on the side surface of the first semiconductor fin and the second semiconductor fin, and is located on a top surface of the trench isolation region; A second dielectric layer, located on the first dielectric layer; and A source / drain trench is located in the first semiconductor fin.

6. The integrated circuit as described in claim 5, characterized in that, The top surface of the second dielectric layer is lower than the top surface of the first dielectric layer and higher than the top surface of the first semiconductor fin.

7. The integrated circuit as described in claim 5, characterized in that, The shallow trench isolation region defines a dielectric shielding structure, which includes a portion of the first dielectric layer.

8. The integrated circuit as described in claim 7, characterized in that, It further includes a source / drain region of a transistor located in the first semiconductor fin.

9. The integrated circuit as described in claim 5, characterized in that, The first semiconductor fin has a top first semiconductor layer sidewall and the second semiconductor fin has a top second semiconductor layer sidewall with the same angle relative to the vertical direction.

10. The integrated circuit as claimed in claim 5, characterized in that, Multiple stacked channels of a transistor are formed from the first semiconductor fin by forming the source / drain trench.

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