Image sensor

Abstract

Image sensor, especially CMOS image sensor, for electronic cameras, with a plurality of pixels (11) arranged in rows and columns, wherein the pixels (11) each comprise: a light-sensitive detector element (15) to generate an electric charge from incident light, a transfer gate (39), a readout node (41) which is charge-coupled to the detector element (15) via the transfer gate (39), a converter circuit (43) to generate a measurement signal proportional to a charge present in the readout node (41), and a reset device (45) to reset a charge present in the readout node (41) to a reference value; and furthermore with a control device (53) for controlling the transfer gate (39) and the reset device (45) of the respective pixel (11); wherein the control device (53) is designed such that at least two successive transfer control signals are applied to the transfer gate (39) to read out the charge generated in the respective detector element (15) during a single exposure process, enabling a respective charge transfer from the detector element (15) to the readout node (41), wherein the reset device (45) is activated between the respective successive transfer control signals in order to generate a separate partial value measurement signal for each charge transfer by means of the converter circuit (43), which is proportional to the charge present in the readout node (41) as a result of the respective charge transfer, wherein the pixels (11) arranged in a respective column are connected via a common column line (17) to a column amplifier circuit (13) controllable by the control device (53), which comprises an amplifier (19) and a number of partial value signal storage devices (21A, 21B, 21C) corresponding to the number of successive transfer control signals, wherein the control device (53) is configured such that each of the partial value measurement signals corresponding to the charge transfers is transmitted to its own partial value signal storage device (21A, 21B, 21C), characterized by that the respective column amplifier circuit (13) comprises an additional amplifier (31) and a residual value signal memory (33), wherein the control device (53) is designed such that one of the partial value measurement signals corresponding to the charge transfers is simultaneously transmitted to the associated partial value signal memory (21C) and the residual value signal memory (33).

Description

[0001] The present invention relates to an image sensor, in particular a CMOS image sensor, for electronic cameras. The image sensor comprises a plurality of pixels arranged in rows and columns. The pixels each comprise a light-sensitive detector element for generating electrical charge from incident light, a transfer gate, a readout node charge-coupled to the detector element via the transfer gate, a converter circuit for generating a measurement signal proportional to a charge present in the readout node, and a reset device for resetting a charge present in the readout node to a reference value. The image sensor further comprises a control device for controlling the transfer gate and the reset device of the respective pixel. The present invention further relates to a method for reading an image sensor, in particular a CMOS image sensor, for electronic cameras.

[0002] An electronic camera, for example, is used to digitally record image sequences that are later shown in a cinema. It is advantageous for such a camera to have high light sensitivity and a high dynamic range. These two properties are essential for the quality of the recording and help, for example, reduce the costs of lighting the scene.

[0003] The image sensor of such a camera converts light entering the camera lens into electrical signals. The image sensor comprises a multitude of light-sensitive elements, known as pixels. The incoming light is converted into electrical charge in the pixels. To read out an image captured by the camera, for example, the pixels are addressed sequentially, and a voltage proportional to the charge of the respective pixel is generated, which is then fed to an output of the image sensor.

[0004] An image sensor of the type mentioned above can, for example, be used as in Fig. 1, in which only a single pixel 11 is shown. The illustrated pixel 11 comprises a light-sensitive detector element in the form of a so-called pinned diode (PD) 15, which is charge-coupled via a transfer gate 39 to a readout node 41, which is designed as a so-called floating diffusion (FD). The readout node 41 is connected to the gate of a converter field-effect transistor (FET) 43, which is designed as a source-follower and represents a charge-to-voltage converter circuit. Furthermore, the readout node 41 is connected to a positive voltage supply 51 via a reset FET 45. One of the two channel terminals of the converter FET 43 is also connected to the positive supply 51, whereas the other of the two channel terminals of the converter FET 43 can be connected to the column line 17 assigned to the displayed pixel via a selection FET 47, which acts as a row selection switch.

[0005] Column line 17 is provided for connecting the pixels arranged in the associated column, in particular pixel 11, to a common column amplifier circuit 113. Column amplifier circuit 113 comprises a first capacitor 127, which has one terminal connected to ground and the other terminal selectively connectable to column line 17 via a switch 149E. Column amplifier circuit 113 further comprises a second capacitor 133, which has one terminal likewise connected to ground and the other terminal selectively connectable to column line 17 via a further switch 149D. In addition, column amplifier circuit 113 comprises an amplifier 131, to whose negative input 137 the voltage applied to first capacitor 127 is input, and to whose positive input 135 the voltage applied to second capacitor 133 is input.

[0006] The transfer gate 39 is controllable via a control line TRF, the reset FET 45 is controllable via a control line RES, the selection FET 47 is controllable via a control line SEL, the switch 149E is controllable via a control line S1 and the switch 149D is controllable via a control line S2 by a common control device 153 of the image sensor.

[0007] The functionality of such a pixel 11 is described below as an example, based on a 3.3V CMOS technology.

[0008] First, the light incident during an exposure process is converted into electrical charge by the pinned diode 15, so that the pinned diode 15 fills with electrons. During the exposure, the control lines TRF, RES, and SEL are each kept at 0V, meaning that the switches 39, 45, and 47 controlled by them are closed.

[0009] For reading, in a first step (Reset 1) a voltage of 3.3V is briefly applied to the control line RES in order to remove charge formed by leakage currents and / or stray light from the readout node 41.

[0010] In a second step (reading the reference value), a voltage of 3.3V is applied to the control line SEL (closing switch 47), and switch 149E is closed. This switches the voltage level of readout node 41 via converter FET 43 and select FET 47 to column line 17 and thus to capacitor 127. After the system has settled, capacitor 127 is again disconnected from pixel 11 by opening switch 149E.

[0011] Subsequently, in a third step (transfer of the charge), a voltage of 3.3V is briefly applied to the control line TRF so that the electrons can flow from the pinned diode 15 to the readout node 41.

[0012] Subsequently, in a fourth step (reading the signal), switch 149D is closed. This switches the voltage level of readout node 41 via converter FET 43 and select FET 47 to column line 17 and thus to capacitor 133. After the system has settled, capacitor 133 is again disconnected from pixel 11 by opening switch 149D, and the control line SEL is returned to 0V.

[0013] Finally, in a fifth step (Reset 2), a voltage of 3.3V is briefly applied to the control lines RES and TRF in order to remove the charge from the readout node 41 and any residual charge from the pinned diode 15 so that the next exposure process can begin again with a completely “empty” pixel.

[0014] At the output of the amplifier 131 there is now a voltage which corresponds to the amount of charge generated in the pinned diode 15 by the exposure process.

[0015] In order to Fig. To ensure high light sensitivity in the image sensor described in Figure 1, it is necessary for the charges generated by the incident light in the pinned diode 15 to produce a high voltage at the gate of the converter FET 43. This is achieved by keeping the capacitance of the readout node 41 small. With a capacitance of, for example, 2 fF, each electron causes a voltage change of 80 µV. If the camera has a noise level of, for example, 240 µV, 3 electrons or 3 photons are already detectable.

[0016] The one based on Fig. The image sensor described in Figure 1 thus possesses high light sensitivity, but only a limited dynamic range. At the aforementioned capacitance of 2 fF, the readout node 41 is already completely filled with 12,000 electrons. 12,000 electrons result in a voltage of approximately 1 V, which reaches the limit of the electrical range that can be passed to the outputs.

[0017] This results in a maximum achievable dynamic range of 4000:1. Photographic film, on the other hand, has a dynamic range of over 10000:1.

[0018] To increase dynamic range, it is known to combine at least two images with different exposure times, taking the images one after the other. However, this is not possible with moving objects due to the temporal offset of the images to be combined.

[0019] The document JP 2001-177775 A discloses an image sensor having the features of the preamble of claim 1 and a method for reading an image sensor having the features of the preamble of claim 16. The documents DE 10 2007 012 279 A1, DE 199 29 733 A1, DE 199 07 971 A1, US 2007 / 0138375 A1, US 2007 / 0007559 A1, EP 1 235 277 A2 and US 6 133 862 A disclose further image sensors and readout methods.

[0020] The invention is based on the object of providing a possibility of ensuring not only a high light sensitivity but also a high dynamic range in an image sensor or a method of the type mentioned above.

[0021] This object is achieved by an image sensor having the features of claim 1.

[0022] In such an image sensor, the control device is designed such that, in order to read out the charge generated in the respective detector element during a single exposure process, at least two successive transfer control signals are applied to the transfer gate, so that a respective charge transfer from the detector element to the readout node is enabled, wherein the reset device is activated between the respective successive transfer control signals in order to generate, by means of the converter circuit, for each charge transfer a separate partial value measurement signal which is proportional to the charge present in the readout node due to the respective charge transfer.

[0023] The pixels arranged in a respective column are connected via a common column line to a column amplifier circuit which can be controlled by the control device and which comprises an amplifier and a number of partial value signal memories corresponding to the number of successive transfer control signals, wherein the control device is designed such that each of the partial value measurement signals corresponding to the charge transfers is transmitted to a separate one of the partial value signal memories.

[0024] The respective column amplifier circuit comprises an additional amplifier and a residual value signal memory, wherein the control device is designed such that one of the partial value measurement signals corresponding to the charge transfers is transmitted simultaneously to the associated partial value signal memory and the residual value signal memory.

[0025] Furthermore, this object is achieved by a method having the features of claim 16.

[0026] In order to read out the charge generated in the respective detector element during a single exposure process, at least two successive transfer control signals are applied to the transfer gate, so that a respective charge transfer from the detector element to the readout node is enabled, wherein between the respective successive transfer control signals the reset device is activated in order to generate, by means of the converter circuit, for each charge transfer a separate partial value measurement signal which is proportional to the charge present in the readout node due to the respective charge transfer.

[0027] The pixels arranged in a respective column are connected via a common column line to a column amplifier circuit which can be controlled by the control device and which comprises an amplifier and a number of partial value signal memories corresponding to the number of successive transfer control signals, wherein each of the partial value measurement signals corresponding to the charge transfers is transmitted to a separate one of the partial value signal memories.

[0028] The respective column amplifier circuit comprises an additional amplifier and a residual value signal memory, wherein one of the partial value measurement signals corresponding to the charge transfers is transmitted simultaneously to the associated partial value signal memory and the residual value signal memory.

[0029] With this image sensor or method, it is therefore possible to read out the charge generated in the detector element as a result of a single exposure process in multiple portions. By means of step-by-step readout, the dynamic range of the image sensor can be increased by a factor corresponding to the number of charge transfers compared to the dynamic range known from the prior art. If, for example, the charge generated in the detector element is read out based on three charge transfers, the dynamic range can be increased by a factor of three. If, for example, the readout node has a saturation limit of 12,000 electrons and the detector element a saturation limit of 36,000 electrons, a dynamic range of 12,000:1 is achieved at a noise level of three electrons. If the detector element has an even higher saturation limit, the dynamic range can be increased even further by subdividing the readout into more than three.Since the capacity of the readout node does not need to be changed, high light sensitivity is maintained.

[0030] The image sensor and method according to the invention thus eliminate the need for switchable capacitances for the pixels. While such switchable capacitances increase the dynamic range, they reduce light sensitivity because the space required by the respective capacitance, a respective additional transistor for the capacitance, and an additional control line is no longer available for the respective detector element. Furthermore, such switchable capacitances require undesirable calibrations.

[0031] The term "charge coupling" refers to the fact that a charge present in the detector element can be shifted to the readout node. The charge present in the readout node can, in particular, be a zero charge, meaning that after resetting by the reset device, no charge remains in the readout node. This applies in particular to the reference value mentioned.

[0032] Preferably, at least two of the transfer control signals have different control values. In particular, the absolute value of the control value of the later of the two transfer control signals can be greater than the absolute value of the control value of the earlier of the two transfer control signals. For example, in a CMOS image sensor, the at least two transfer control signals can have different control voltage values. This means, in particular, that not every control voltage value has to correspond to the full operating voltage underlying the respective technology generation. This can reduce the power consumption of the image sensor. Above all, a transfer control signal whose absolute control value is greater than the absolute control value of another transfer control signal enables the transfer of charges that are (still) not transferable by the other (lower-magnitude) transfer control signal.By graduating the control values ​​of the transfer control signals, partial value measurement signals corresponding to a zero charge can also be generated when the detector element is not saturated.

[0033] The detector element can comprise exactly two terminals, one terminal being coupled to a predetermined reference potential (e.g. ground) and the other terminal being coupled only to the transfer gate, ie the charge generated in the detector element can be transferred (via the transfer gate) directly to the readout node without an additional switch or bias voltage of the detector element.

[0034] In particular, the detector element can be designed as a photodiode, preferably as a pinned diode whose potential level is fixed.

[0035] The readout node can be formed as a floating diffusion region whose potential level varies with the amount of charge present in the charge node.

[0036] Preferably, the partial value measurement signals are combined and digitized together only after they have been stored in the partial value signal memories. The combined signal or total value measurement signal can then be smaller than one or more of the partial value measurement signals – since all partial value signal memories are switched to a common input of the respective amplifier or A / D converter during readout (adding the capacitances of the partial value signal memories). In principle, however, it is also possible to first digitize each of the partial value measurement signals individually and store it as a digital value in the respective partial value signal memory, with the digital values ​​then being combined.

[0037] For example, two or three partial value signal memories can be provided. The partial value signal memories can have identical capacities and / or be integrated.

[0038] According to a further embodiment of the invention, the respective column amplifier circuit comprises first switch means, wherein the partial value signal memories can be simultaneously connected to a first input of the amplifier via the first switch means. This allows the partial value measurement signals to be combined in a simple manner to generate the above-described total value measurement signal proportional to the charge generated in the detector element.

[0039] In particular, the control device can be designed such that, after activation of the reset device, a reference value measurement signal corresponding to the reference value of the charge is generated by the converter circuit and transmitted to a reference value signal memory of the respective column amplifier circuit, wherein the reference value signal memory is connected or connectable to a second input of the amplifier. The reference value measurement signal corresponds to a defined charge in the readout node, in particular a zero charge. The reference value measurement signal can, in principle, be generated before or after the generation of any of the partial value measurement signals.

[0040] The partial value measurement signal present in the residual value signal buffer can be compared with the total value measurement signal described above. Depending on the result of this comparison, the partial value measurement signal present in the residual value signal buffer, the total value measurement signal, or a combination of these two signals can be used to determine the charge generated in the detector element.

[0041] The aforementioned partial value measurement signal is, in particular, the measurement signal corresponding to the last charge transfer. If it is determined that charge was actually transferred from the detector element to the readout node only during the last charge transfer, the partial value measurement signal stored in the residual value signal memory alone can be used to determine the charge generated in the detector element, thereby improving the signal-to-noise ratio compared to using the total value measurement signal described above.

[0042] Preferably, the respective residual value signal memory is connected or connectable to a first input of the additional amplifier and / or the above-described reference value signal memory is connected or connectable to a second input of the additional amplifier.

[0043] To selectively connect the column line to one or more of the signal memories, the respective column amplifier circuit comprises second switching means. Preferably, a separate switch is provided between the column line and each of the signal memories.

[0044] Preferably, the signal memories, ie the partial value signal memories, the reference value signal memory described above and the residual value signal memory, are each designed as a capacitor.

[0045] Non-limiting embodiments of the invention are illustrated in the drawings and are described below.

[0046] They show, in schematic representation, Fig. 1 shows a 4-transistor CMOS image sensor according to the prior art, wherein only one pixel of the image sensor and a column amplifier circuit associated with the pixel are shown, Fig. 2 shows a 4-transistor CMOS image sensor according to the present invention in a Fig. 1 analog representation, Fig. 3 a partial cross-section through the pixel Fig. 2, and Fig. 4 to 18 potential diagrams for the Fig. 3 shown cross-section at different times during the readout of the pixel.

[0047] The Fig. The image sensor according to the invention shown in Figure 2 comprises a pixel 11 and a column line 17, which corresponds to the Fig. 1 of the prior art described pixel 11 or the pixel 12 of Fig. 1 of the prior art. In addition, the image sensor according to Fig. 2 an amplifier circuit 13, which has a signal from the amplifier 131 Fig. 1 corresponding amplifier 31 (with a positive input 35 and a negative input 37), which is referred to below as additional amplifier 31, a capacitor 133 from Fig. 1 corresponding residual value capacitor 33, one corresponding to the capacitor 127 from Fig. 1 corresponding reference value capacitor 27, one of the switch 149E from Fig. 1 corresponding switch 49E and one corresponding to switch 149D Fig. 1 corresponding switch 49D. The above components are interconnected in the same way as the corresponding components of Fig. 1. The above statements on Fig. 1 are therefore also part of the disclosure of the invention.

[0048] The image sensor according to Fig. 2 further comprises three partial value capacitors 21A, 21B, 21C, which are connected in parallel and each connected to ground. These capacitors are identical and can each be connected to the column line 17 via a separate switch 49A, 49B, 49C, which are referred to below as second switches 49A, 49B, 49C. Furthermore, a further switch 23A, 23B, 23C is provided for each partial value capacitor 21A, 21B, 21C, wherein the further switches 23A, 23B, 23C are referred to below as first switches 23A, 23B, 23C. The three partial value capacitors 21A, 21B, 21C are connected to each other via the first switches 23A, 23B, 23C and simultaneously to the positive input 25 of an amplifier 19. The negative input 29 of amplifier 19 is connected to the reference value capacitor 27.

[0049] In addition, the image sensor includes Fig. 2 one of the control device 153 from Fig. 1 corresponding control device 53, which in addition to the already Fig. 1 also controls the first switches 23A, 23B, 23C and the second switches 49A, 49B, 49C (via the control lines S3, S4, S5, S6, S7, S8).

[0050] Fig. Figure 3 shows a semiconductor substrate in which the pinned diode 15 is provided, which is charge-coupled via a transfer gate 39 to the readout node 41, which is designed as a "floating diffusion." Via the reset FET 45, the readout node 41 is connectable to a diffused channel terminal to which the positive supply 51 is applied.

[0051] The following describes the operation of the pixel 11 of the image sensor according to the invention of the Fig. 2 and Fig. 3 based on the Fig. 4 to 18 are described as examples based on 3.3V CMOS technology, where the charge generated in the pinned diode 15 is read out in three charge transfer steps. Alternatively, however, the readout process can also be performed in two or more than three steps.

[0052] After an exposure process, the pinned diode 15 or its potential well is filled with charge, as in Fig. 4 (after exposure, immediately before readout). The readout node 41 or its potential well also contains a small amount of charge generated by leakage currents and / or stray light.

[0053] To read the data, a voltage of 3.3V is first applied to the control line RES. This allows, as shown in Fig. 5 (Reset 1), the charge generated in the pinned diode 15 flows from the readout node 41 to the positive supply voltage 51. The control line RES is then set back to 0V ( Fig. 6, End Reset 1). This ensures that the readout node 41 does not already contain charge before a first charge transfer, as described below.

[0054] According to Fig. 7 (Transfer 1), a medium voltage of 2.5V is then applied to the control line TRF by means of a first transfer control signal, so that a first portion of the charge generated in the pinned diode 15 can flow into the readout node 41. Subsequently, the control line TRF is set back to 0V, so that the first portion of the charge is now in the readout node 41 ( Fig. 8, end of transfer 1).

[0055] The control line SEL is then set to a voltage of 3.3V, and the second switch 49A is closed. As a result, the voltage level generated by the charge in the readout node 41 via the converter FET 43 is switched to the column line 17 via the select FET 47 and thus fed to the partial value capacitor 21A (read signal 1). After the system has settled, the partial value capacitor 21A is again separated from the pixel 11 by opening the second switch 49A, so that an analog first partial value voltage signal is ultimately stored in the partial value capacitor 21A in the form of a corresponding charge, which is proportional to the charge present in the readout node 41 after the first charge transfer.

[0056] Now the control line RES is set to a voltage of 3.3V so that the charge from the readout node 41 can flow to the positive supply 51 ( Fig. 9, Reset 2). The control line RES is then set back to 0V ( Fig. 10, end of Reset 2). This in turn ensures that the readout node 41 does not already contain charge before a second charge transfer, as described below.

[0057] According to Fig. 11 (Transfer 2), the control line TRF is set to a slightly higher voltage of 2.8V by means of a second transfer control signal, so that a second part of the charge generated in the pinned diode 15 can flow into the readout node 41. Subsequently, the control line TRF is set back to 0V, so that the second part of the charge is now in the readout node 41 ( Fig. 12, end of transfer 2).

[0058] Subsequently, the second switch 49B is closed. As a result, the voltage level of the readout node 41 caused by the second charge transfer is conducted via the converter FET 43 and the selection FET 47 to the column line 17 and thus to the partial-value capacitor 21B (read signal 2). After the system has settled, the capacitor 21B is again disconnected from the pixel 11 by opening the second switch 49B, so that an analog second partial-value voltage signal is stored in the partial-value capacitor 21B, which is proportional to the charge present in the readout node 41 after the second charge transfer.

[0059] After this, the control line RES is set to a voltage of 3.3V so that the charge from the readout node 41 can flow to the positive supply 51 ( Fig. 13, Reset 3). The control line RES is then set back to 0V ( Fig. 14, End Reset 2). This ensures that the readout node 41 does not already contain charge before generating a reference voltage signal, as described below.

[0060] Subsequently, the second switch 49E is closed—now without applying a transfer control signal to the control line TRF again. This switches the voltage level of the readout node 41 via the converter FET 43 and the select FET 47 to the column line 17 and thus to the reference value capacitor 27 (read reference). After the system has settled, the reference value capacitor 27 is again disconnected from the pixel 11 by opening the second switch 49E.

[0061] In a next step, the control line TRF is set to the full voltage of 3.3V by means of a third transfer control signal. This allows the entire remaining charge generated in the pinned diode 15 to flow into the readout node 41 ( Fig. 15, Transfer 3). The control line TRF is then set back to 0V, so that the third part of the charge is now in the readout node 41 ( Fig. 16, end of transfer 3).

[0062] In a further step, the second switches 49C, 49D are then closed. As a result, the voltage level of the readout node 41 caused by the third charge transfer is switched to the column line 17 via the converter FET 43 and the selection FET 47 and thus fed to both the partial value capacitor 21C and the residual value capacitor 33. After the system has settled, the partial value capacitor 21C and the residual value capacitor 33 are separated from the pixel 11 again by opening the second switches 49C, 49D, so that an analog third partial value voltage signal is stored in the partial value capacitor 21C and the residual value capacitor 33, which is proportional to the charge present in the readout node 41 after the third charge transfer.

[0063] Afterwards, the control line SEL is set back to 0V. The control lines RES and TRF are set to a voltage of 3.3V ( Fig. 17, Reset 4). This removes the charge in the readout node 41 (and any residual charge in the pinned diode 15). Subsequently, the control lines RES and TRF are set back to 0V ( Fig. 18, end reset 4). The pixel is "empty" and the next exposure process can begin.

[0064] Finally, the first switches 23A, 23B, 23C are closed. The LOW and HIGH voltages now present at amplifiers 19, 31 are fed to a common A / D converter or to separate A / D converters and digitized. By subtracting the reference value voltage signal, i.e., the voltage signal of the empty readout node 41, from the total value voltage signal (at amplifier 19) or from the partial value voltage signal of the third charge transfer (at amplifier 31), lower noise is achieved because the charge uncertainty (KTC noise) of the readout node 41 and all offset voltages are subtracted.

[0065] In principle, it is also possible to perform the first two readouts with the same voltage at TRF, e.g. 2.8V.

[0066] In particular, the voltage values ​​of the transfer control signals are adapted to the depth of the potential well of the pinned diode 15.

[0067] If the pinned diode 15 is filled by the respective exposure process to less than a level that corresponds to the height of the potential barrier controlled by the transfer gate 39 when the second transfer control signal is applied, in particular less than one-third, no charges are transferred from the pinned diode 15 to the readout node 41 during the first two readout processes. The two partial value capacitors 21A, 21B thus each contain the partial value voltage signal of the "empty" readout node 41, i.e. the reference value voltage signal, which is also stored in the reference value capacitor 27. The HIGH voltage at the output of the amplifier 19 is therefore exactly a fraction equal to one-third of the LOW voltage at the output of the amplifier 31. In this case, the LOW voltage is used to determine the charge generated in the pinned diode 15, and HIGH is ignored.

[0068] It is a particular advantage of the invention that the aforementioned fraction (here: one third) is precisely known without calibrating the column amplifier circuit 13, since due to the integrated design of the capacitors 21A, 21B, 21C and 33, they can be provided with identical respective capacitance.

[0069] If the pinned diode 15 is filled to more than the aforementioned level, charges are transferred from the pinned diode 15 to the readout node 41 during at least two, in particular three, readout processes. The capacitors 21B, 21C or 21A, 21B, 21C thus contain the corresponding partial-value voltage signals of the respectively filled readout node 41. The LOW voltage at the output of the amplifier 31 is invalid in this case and is ignored because it does not represent the entire charge generated in the pinned diode 15. Consequently, only the HIGH voltage is used to determine the charge generated in the pinned diode 15 in this case.

[0070] In the case of a strong exposure, in which a charge of more than 12,000 electrons is reached in the pinned diode 15, the signal at the output of the amplifier 19 is switched to HIGH.

[0071] Thus, for each pixel 11, either the HIGH signal or the LOW signal is selected, taking into account the ratio of the total capacitance of capacitors 21A, 21B, and 21C to the capacitance of capacitor 33 (the HIGH signal corresponds to one-third of the LOW signal for identical capacitances). In a transition region, both signals can also be considered, i.e., offset against each other (e.g., for a charge of 10,000 to 14,000 electrons in pinned diode 15). The signals selected for the individual pixels 11 are ultimately combined to form a common image.

[0072] This allows the dynamic range of the image sensor to be increased compared to an image sensor that only delivers the LOW signal. List of reference symbols 11 pixels 13, 113 Column amplifier circuit 15 pinned diode 17 Column line 19 amplifiers 21 Partial value capacitor 23 first switch 25 positive input 27, 127 Reference value capacitor 29 negative input 31, 131 additional amplifier 33, 133 Residual value capacitor 35, 135 positive input 37, 137 negative input 39 Transfer Gate 41 readout nodes 43 converter FET 45 Reset FET 47 Selection FET 49, 149 second switch 51 positive supply 53, 153 control device

Claims

[1] Image sensor, in particular CMOS image sensor, for electronic cameras, with a plurality of pixels (11) arranged in rows and columns, the pixels (11) each comprising: a light-sensitive detector element (15) for generating electrical charge from incident light, a transfer gate (39), a readout node (41) which is charge-coupled to the detector element (15) via the transfer gate (39), a converter circuit (43) for generating a measurement signal proportional to a charge present in the readout node (41), and a reset device (45) for resetting a charge present in the readout node (41) to a reference value; and further comprising a control device (53) for controlling the transfer gate (39) and the reset device (45) of the respective pixel (11); wherein the control device (53) is designed such that, in order to read out the charge generated in the respective detector element (15) during a single exposure process, at least two successive transfer control signals are applied to the transfer gate (39), so that a respective charge transfer from the detector element (15) to the readout node (41) is enabled, wherein between the respective successive transfer control signals, the reset device (45) is activated in order to generate, by means of the converter circuit (43), for each charge transfer a separate partial value measurement signal which is proportional to the charge present in the readout node (41) due to the respective charge transfer, wherein the pixels (11) arranged in a respective column are connected via a common column line (17) to a column amplifier circuit (13) controllable by the control device (53), which comprises an amplifier (19) and a number of partial value signal memories (21A, 21B, 21C) corresponding to the number of successive transfer control signals, wherein the control device (53) is designed such that each of the partial value measurement signals corresponding to the charge transfers is transmitted to a separate one of the partial value signal memories (21A, 21B, 21C), characterized by , that the respective column amplifier circuit (13) comprises an additional amplifier (31) and a residual value signal memory (33), wherein the control device (53) is designed such that one of the partial value measurement signals corresponding to the charge transfers is transmitted simultaneously to the associated partial value signal memory (21C) and the residual value signal memory (33). [2] Image sensor according to claim 1, characterized by that at least two of the transfer control signals have different control values. [3] Image sensor according to claim 2, characterized in that the absolute value of the control value of the later of the two transfer control signals is greater than the absolute value of the control value of the earlier of the two transfer control signals. [4] Image sensor according to one of the preceding claims, characterized in that the detector element (15) comprises exactly two terminals, one terminal being coupled to a reference potential and the other terminal being coupled only to the transfer gate (39). [5] Image sensor according to one of the preceding claims, characterized by that the detector element (15) is designed as a photodiode. [6] Image sensor according to one of the preceding claims, characterized in that the readout node (41) is formed as a floating diffusion region. [7] Image sensor according to one of the preceding claims, characterized in that two or three partial value signal memories (21A, 21B, 21C) are provided. [8] Image sensor according to one of the preceding claims, characterized in that the partial value signal memories (21A, 21B, 21C) have identical capacities and / or are integrated. [9] Image sensor according to one of the preceding claims, characterized in that the respective column amplifier circuit (13) comprises first switch means (23A, 23B, 23C), wherein the partial value signal memories (21A, 21B, 21C) can be connected simultaneously to a first input (25) of the amplifier (19) via the first switch means (23A, 23B, 23C). [10] Image sensor according to claim 9, characterized in that the control device (53) is designed such that, after activation of the reset device (45), a reference value measurement signal corresponding to the reference value of the charge is generated by means of the converter circuit (43) and transmitted to a reference value signal memory (27) of the respective column amplifier circuit (13), wherein the reference value signal memory (27) is connected or connectable to a second input (29) of the amplifier (19). [11] Image sensor according to one of the preceding claims, characterized in that the one partial value measurement signal is the partial value measurement signal which corresponds to the last charge transfer. [12] Image sensor according to one of the preceding claims, characterized in that the respective residual value signal memory (33) is connected or connectable to a first input (35) of the additional amplifier (31). [13] Image sensor according to one of the preceding claims, characterized in that a reference value signal memory (27) is connected or connectable to a second input (37) of the additional amplifier (31). [14] Image sensor according to one of the preceding claims, characterized by that the respective column amplifier circuit (13) comprises second switch means (49A, 49B, 49C, 49D, 49E), wherein the column line (17) can be selectively connected to one or more of the signal memories (21A, 21B, 21C, 27, 33) via the second switch means (23A, 23B, 23C). [15] Image sensor according to one of the preceding claims, characterized by that the signal memories (21A, 21B, 21C, 27, 33) are each designed as a capacitor. [16] Method for reading an image sensor, in particular a CMOS image sensor, for electronic cameras, wherein the image sensor comprises a plurality of pixels (11) arranged in rows and columns, in which electrical charge generated from incident light by means of a light-sensitive detector element (15) is transferred to a readout node (41) which is charge-coupled to the detector element (15) via a transfer gate (39), a measuring signal is generated by means of a converter circuit (43) which is proportional to a charge present in the readout node (41), and by means of a reset device (45) a charge present in the readout node (41) is reset to a reference value, wherein, for reading out the charge generated in the respective detector element (15) during a single exposure process, at least two successive transfer control signals are applied to the transfer gate (39), so that a respective charge transfer from the detector element (15) to the readout node (41) is enabled, wherein between the respective successive transfer control signals, the reset device (45) is activated in order to generate, by means of the converter circuit (43), for each charge transfer a separate partial value measurement signal which is proportional to the charge present in the readout node (41) due to the respective charge transfer, wherein the pixels (11) arranged in a respective column are connected via a common column line (17) to a column amplifier circuit (13) controllable by the control device (53), which comprises an amplifier (19) and a number of partial value signal memories (21A, 21B, 21C) corresponding to the number of successive transfer control signals, wherein each of the partial value measurement signals corresponding to the charge transfers is transmitted to a separate one of the partial value signal memories (21A, 21B, 21C), characterized by that the respective column amplifier circuit (13) comprises an additional amplifier (31) and a residual value signal memory (33), wherein one of the partial value measurement signals corresponding to the charge transfers is transmitted simultaneously to the associated partial value signal memory (21C) and the residual value signal memory (33). [17] Method according to claim 16, characterized in that the respective column amplifier circuit (13) comprises first switch means (23A, 23B, 23C), wherein the partial value signal memories (21A, 21B, 21C) are connected via the first switch means (23A, 23B, 23C) simultaneously to a first input (25) of the amplifier (19). [18] Method according to claim 17, characterized in that by means of the converter circuit (43) after activation of the reset device (45) a reference value measurement signal corresponding to the reference value of the charge is generated and transmitted to a reference value signal memory (27) of the respective column amplifier circuit (13), wherein the reference value signal memory (27) is or will be connected to a second input (29) of the amplifier (19). [19] Method according to one of claims 16 to 18, characterized in that the respective residual value signal memory (33) is or will be connected to a first input (35) of the additional amplifier (31) and / or a reference value signal memory (27) is or will be connected to a second input (37) of the additional amplifier (31). [20] Method according to one of claims 16 to 19, characterized in that the respective column amplifier circuit (13) comprises second switch means (49A, 49B, 49C, 49D, 49E), wherein the column line (17) is selectively connected to one or more of the signal memories (21A, 21B, 21C, 27, 33) via the second switch means (23A, 23B, 23C).

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