Optoelectronic semiconductor chip and methods for its manufacture

Abstract

Optoelectronic semiconductor chip (100) comprising: - a first semiconductor layer sequence (1) comprising a plurality of microdiodes (11), and - a second semiconductor layer sequence (2) comprising an active region (12), wherein: - the first semiconductor layer sequence (1) and the second semiconductor layer sequence (2) are based on a nitride compound semiconductor material, - the first semiconductor layer sequence (1) is positioned upstream of the second semiconductor layer sequence (2) in the growth direction, - the microdiodes (11) provide ESD protection for the active region (12), - at least one of the microdiodes (11) comprises a pn junction, - the active region (12) comprises at least one pn junction, - the pn junction of the microdiode (11) and the pn junction of the active region (12) are aligned, - the pn junction of the microdiode (11) has a lower reverse breakdown voltage (UBR) than the pn junction of the active region. (12)and at least 75% of the microdiodes (11) are arranged within an ESD layer (9) which has a thickness (d9) of at least half and at most three times the thickness of the active area (11).

Description

An optoelectronic semiconductor chip is specified.The publication US 2009 / 0 014 713 A1 describes a light-emitting nitride semiconductor device and a method for its production.The document JP 2002-270 514 A describes a method for manufacturing a gallium nitride semiconductor layer.The publication US 2007 / 0 122 994 A1 describes a light-emitting nitride semiconductor element.One object to be achieved is to specify an optoelectronic semiconductor chip which is particularly stable against electrostatic discharges, so-called ESD voltage pulses. It is a further object to specify a method for producing such an optoelectronic semiconductor chip.The optoelectronic semiconductor chip is a radiation-receiving or radiation-emitting optoelectronic semiconductor chip. For example, the optoelectronic semiconductor chip is a light-emitting diode chip which emits green and / or blue light during operation.The optoelectronic semiconductor chip has a first semiconductor layer sequence which comprises a multiplicity of microdiodes. A semiconductor layer sequence is understood here to mean a sequence of semiconductor layers. In an extreme case, the semiconductor layer sequence can comprise a single semiconductor layer. A semiconductor layer is in particular characterized in that the material composition within the layer does not change or hardly changes and / or that the region which the layer forms performs a specific function in the semiconductor chip. A semiconductor layer may comprise a plurality of monolayers of a semiconductor material.The microdiodes are pn junctions in the semiconductor layer sequence, which have a current-voltage characteristic characteristic characteristic typical of a semiconductor diode. During operation of the optoelectronic semiconductor chip, there is preferably no radiative recombination of charge carriers in the region of the microdiodes. That is to say that the microdiodes are not provided for generating electromagnetic radiation, at least not for generating electromagnetic radiation in the visible range.The microdiodes have a breakdown voltage in their reverse direction. The microdiodes are preferably designed in such a way that they are not destroyed when the breakdown voltage is exceeded-at least in a specific range of the current intensity of the current flowing through the microdiodes.The microdiodes also have an threshold voltage in the forward direction, starting from which a current can flow through the microdiodes.The fact that the first semiconductor layer sequence comprises the micro-diodes means here that at least a part of the micro-diodes is arranged in the first semiconductor layer sequence. For example, the n-side or the p-side of the microdiodes can be arranged in the first semiconductor layer sequence. The remaining part of the microdiodes can then be arranged in another layer or layer sequence.The optoelectronic semiconductor chip comprises a second semiconductor layer sequence comprising an active region. The active region is provided for generating or detecting electromagnetic radiation during operation of the optoelectronic semiconductor chip. This means that, for example, radiative recombination of charge carriers takes place in the active region, in which visible light can be generated. For this purpose, the active region comprises, for example, at least one multiple quantum well structure.The designation quantum well structure does not in this case have any significance with regard to the dimensionality of the quantization. It thus comprises, inter alia, quantum troughs, quantum wires and quantum dots and any combination of these structures. Examples of multiple quantum well structure structures are described in the publications WO 01 / 39 282 A2, U.S. Pat. No. 5,831,277 A1, U.S. Pat. No. 6,172,382 B1 and U.S. Pat. No. 5,684,309 A1.The active region is arranged in the second semiconductor layer sequence if at least a part of the active region, for example the n-side or the p-side, is arranged in the second semiconductor layer sequence. For example, the multiple quantum well structure is arranged completely in the second semiconductor layer sequenceThe first semiconductor layer sequence and the second semiconductor layer sequence are based on a nitride compound semiconductor material.Based on nitride compound semiconductor material in the present context means that the semiconductor layer sequences or at least a part thereof comprise or consist of a nitride compound semiconductor material, preferably Al n Ga m In 1-n-m N, where 0≤n≤1, 0≤m≤1 and n+m≤1. Rather, it can have, for example, one or more dopants and additional constituents. For the sake of simplicity, however, the above formula contains only the essential constituents of the crystal lattice (Al, Ga, In, N), even if these may be partially replaced and / or supplemented by small amounts of further substances.For example, the first semiconductor layer sequence and the second semiconductor layer sequence are based on an InGaN and / or a GaN semiconductor material.The first semiconductor layer sequence is arranged upstream of the second semiconductor layer sequence in a growth direction of the semiconductor layer sequence. This means that, during the production of the optoelectronic semiconductor chip, the first semiconductor layer sequence is first grown and then the second semiconductor layer sequence is grown. The second semiconductor layer sequence can be arranged directly on the first semiconductor layer sequence. This proves to be advantageous in particular in the case of semiconductor chips which form green light-emitting light-emitting diodes. In particular in the case of blue light-emitting diodes, it is possible for an intermediate layer to be arranged between the first and the second semiconductor layer sequence.The microdiodes form an ESD protection for the active region of the optoelectronic semiconductor chip. That is, in the case of an ESD voltage pulse, the microdiodes are configured to dissipate an electrical current. The charge impressed by the ESD voltage pulse therefore drains off via at least a part of the microdiodes and does not flow or hardly flows over the active region, with the result that no damage to the active region takes place. The optoelectronic semiconductor chip thus has an ESD strength of at least 1 kV. For example, an ESD strength of at least 1 kV, typically of about 2 kV, is achieved.According to at least one embodiment of the optoelectronic semiconductor chip, the optoelectronic semiconductor chip has a first semiconductor layer sequence which comprises a multiplicity of microdiodes. Furthermore, the optoelectronic semiconductor chip has a second semiconductor layer sequence which comprises an active region. The first and the second semiconductor layer sequence are arranged on top of one another in the growth direction and are each based on a nitride compound semiconductor material. The microdiodes form an ESD protection for the active region and thus increase the ESD strength of the optoelectronic semiconductor chip.According to at least one embodiment of the optoelectronic semiconductor chip, at least one of the microdiodes is formed by a V-defect (V-pit). For example, all microdiodes of the optoelectronic semiconductor chip are each formed by a V defect. A V-defect in the nitride compound semiconductor material has, for example, the shape of an open pyramid inverted in the growth direction, which has, for example, a hexagonal base surface. In cross section, this defect is in the form of a Vs. A V-defect can be generated in the nitride compound semiconductor material-for example in a layer based on GaN or consisting of this semiconductor material-by adjusting the growth parameters, in particular the growth temperature. The size of the V defect then depends on the thickness of the layer in which it is produced. V-defects form, for example, in the region of threading dislocations (threading dislocations), which arise, for example, during heteroepitaxy of the semiconductor material onto a growth substrate which has a different lattice constant than the semiconductor material. For example, the nitride compound semiconductor material is presently grown on a growth substrate made of sapphire, to which the nitride compound semiconductor material has a lattice mismatch of approximately 14%. Threading dislocations are however also observed in homoepitaxy, so that the semiconductor layer sequences can also be deposited, for example, on a growth substrate which is based on GaN or consists of GaN.The V-defects are arranged, for example, completely in the first semiconductor layer sequence.At least one of the microdiodes comprises a pn junction. For example, all microdiodes comprise a pn junction. The active region comprises at least one pn junction. For example, the active region comprises a multiple quantum well structure, which can be described as a pn junction. That is, both the microdiodes and the active region may be described as semiconductor diodes having a current-voltage characteristic typical of semiconductor diodes. The pn junction of the photodiode and the pn junction of the active region are rectified.The pn junction of the photodiode has a lower reverse breakdown voltage than the pn junction of the active region. The breakdown behavior of the microdiodes is preferably embodied in the same way.This can be achieved in that the microdiodes are each formed by a V defect.In the case of an ESD voltage pulse in the reverse direction, some, for example at least 50% in the extreme case, then preferably open all microdiodes simultaneously. Thus, the charge impressed by the ESD voltage pulse does not flow exclusively via one or a few leakage paths with a low breakdown voltage, but rather is distributed over the ensemble of the leakage paths predefined by the microdiodes. As a result, no critical current density is achieved in any of the current paths through which the charge drains, leading to destruction of the optoelectronic semiconductor chip. In the ideal case, this results in a quasi two-dimensional breakdown over the entire cross-sectional area of the optoelectronic semiconductor chip. Thus, an ESD voltage pulse does not cause damage. In this way, for example, an ESD strength of at least 1 kV can be achieved.According to at least one embodiment of the optoelectronic semiconductor chip, the pn junction of the photodiode has a higher threshold voltage in the forward direction than the pn junction of the active region. This means that during proper operation of the optoelectronic semiconductor chip, when the pn junctions of the microdiodes and of the active region are thus energized in the forward direction, the current flows through the active region, while the microdiodes still block. The microdiodes thus do not interfere, for example, with the generation of radiation in the active region. That is to say that the microdiodes do not influence or hardly influence the forward characteristic of the optoelectronic semiconductor chip. This can also be achieved by using the above-described V-defects to form the microdiodes.According to at least one embodiment of the optoelectronic semiconductor chip, the density of the microdiodes in the optoelectronic semiconductor chip is at least 5×10 7 per cm 2. For example, the density of the microdiodes is at least 10 8 per cm 2. This can be achieved, for example, by a corresponding growth temperature at which the ESD layer in which the microdiodes are arranged is grown. The density indicated here refers to a sapphire substrate in the case of epitaxy. With smaller lattice mismatches between growth substrate and material of the semiconductor layer sequences, lower densities are possible and prove to be useful for increasing the ESD strength.At least 75% of the microdiodes are disposed within an ESD layer. It is sufficient if the p-sides or the n-sides of the microdiodes are arranged in the ESD layer. It is possible that all microdiodes are arranged in the ESD layer. That is, all the V defects are then arranged in the ESD layer.The thickness of the ESD layer is at least half the thickness of the active region in the growth direction and at most three times the thickness of the active region in the growth direction. For example, the ESD layer has a thickness of at least 80 nm and at most 150 nm.The thickness of the ESD layer also specifies the size of the individual microdiodes if they are formed as V-defects. For example, the thickness of the ESD layer is proportional to the base surface (i.e., for example, the base surface of the hexagonal pyramid forming the defect) of a V defect in the ESD layer. Such a large thickness of the ESD layer and the associated size of the micro-diodes ensures sufficient ESD strength of the micro-diodes. For example, all microdiodes, i.e., for example, all V-defects, are arranged within the ESD layer.According to at least one embodiment of the optoelectronic semiconductor chip, an ESD voltage pulse which is applied to the optoelectronic semiconductor chip in the reverse direction flows away at least over 50% of the microdiodes in the reverse direction of the microdiodes. That is, a majority of the microdiodes-at least 50%-have a breakdown voltage similar such that the ESD pulse drains across them. In this way, it is made possible for a voltage pulse to be able to flow away virtually over the entire cross-sectional area of the optoelectronic semiconductor chip, such that the current density in the individual microdiodes does not become so high that destruction of the semiconductor material can occur. However, it is sufficient if the ESD pulse drains out via a few microdiodes. As a result, a certain ESD strength of the semiconductor chip is already achieved.According to at least one embodiment of the optoelectronic semiconductor chip, at least 75% of the microdiodes are each arranged in the region of a thread offset in the semiconductor material of the optoelectronic semiconductor chip. This is achieved, for example, by the microdiodes being designed as V-defects. The V defects are preferably formed at threading dislocations. The density of the threading dislocations in the semiconductor material can thus also be used to adjust the density of the microdiodes.A method for producing an optoelectronic semiconductor chip is also specified. An optoelectronic semiconductor chip described here can preferably be produced with the method. That is to say that the features described for the method are also disclosed for the semiconductor chip and vice versa.The method comprises, for example, the following steps: First a growth substrate is provided.In a subsequent method step, a first semiconductor layer sequence and a second semiconductor layer sequence, which follows the first semiconductor layer sequence, can be epitaxially deposited. In this case, the first semiconductor layer sequence comprises an ESD layer which is deposited at a growth temperature at which V defects are produced in high density in the ESD layer.Usually, attempts are made to prevent the occurrence of the V defects during epitaxy. In the present case, however, for the production of the microdiodes, the ESD layer is grown at low growth temperatures in order to produce V defects in sufficient density. The actual temperature range suitable for producing the V defects depends on the growth plant used. It can be determined by growing an ESD layer at different temperatures and selecting a temperature range at which the density of the V defects is sufficient or particularly high.In the present case, a temperature range is selected at least 790° C. and at most 880° C., at which the ESD layer is deposited. This temperature range has been found to be suitable for forming V-defects, which form microdiodes in the ESD layer, via which microdiodes an ESD voltage pulse can be discharged. The second semiconductor layer sequence preferably comprises an active region which is configured for radiation detection or radiation generation.According to at least one embodiment of the method, the material of the growth substrate has a lattice mismatch with the material of the semiconductor layer sequences to be grown. For example, sapphire is selected as growth substrate and the subsequent semiconductor layer sequences are based on a nitride compound semiconductor material. In this case, V defects are produced at a particularly high density. However, the method is even advantageous in homoepitaxy, even if the density of the V defects can be reduced in this case.According to at least one embodiment, the ESD layer is based on GaN. That is, the ESD layer may consist of GaN, for example, except for small impurities or a doping.The optoelectronic semiconductor chip described here and the method described here are explained in more detail below on the basis of exemplary embodiments and the associated figures.With reference to FIGS. 1A, 1B and 1C, the problem underlying the optoelectronic semiconductor chip described here is explained in more detail by way of example.Embodiments of optoelectronic semiconductor chips described here and of methods described here are explained in more detail on the basis of FIGS. 2, 3A, 3B, 3C, 4A, 4B, 4C, 5 and 6.Identical, similar or identically acting elements are provided with the same reference numerals in the figures. The figures and the proportions of the elements shown in the figures with respect to one another are not to be considered as true to scale. Rather, for improved clarity and / or for improved understanding, individual elements may be represented with an exaggerated size.FIG. 1A shows an exemplary conventional optoelectronic semiconductor chip in a schematic sectional illustration. The optoelectronic semiconductor chip comprises, for example, a first semiconductor layer sequence 1 and a second semiconductor layer sequence 2. the first semiconductor layer sequence 1 can be an n-doped region which is based, for example, on a nitride compound semiconductor material. The second semiconductor layer sequence 2 follows the first semiconductor layer sequence 1 in a growth direction and is likewise based on a nitride compound semiconductor material, for example. The second semiconductor layer sequence 2 comprises an active region 12. The active region 12 comprises, for example, at least one multiple quantum well structure which is provided for generating electromagnetic radiation during operation of the optoelectronic semiconductor chip. Furthermore, the second semiconductor layer sequence 2 can comprise a p-doped region 8. A pn junction is thus formed at the active region 12.The optoelectronic semiconductor chip 100 is traversed by dislocations, for example so-called threading dislocations 3. These occur in particular in the heteroepitaxy of the nitride compound semiconductor material on sapphire in high density. The threading dislocations 3 represent potential paths for an ESD voltage pulse 4, the electrical charge of which is dissipated in the reverse direction of the pn junction. It is problematic here that the charge drains through the weakest or few weak leakage paths which form along one or less of the threading dislocations 3.FIG. 1B shows, by way of example, the current (I) time (t) characteristic curve of a conventional ESD voltage pulse 4.As a result of the charge of an ESD voltage pulse 4 flowing away by one or a few threading dislocations 3, destruction 6 of the optoelectronic semiconductor chip 100 occurs, as is illustrated by way of example in FIG. 1C.FIG. 1C shows, by way of example, a plan view of the radiation passage area 10 of an optoelectronic semiconductor chip 100, wherein an electrical contact 5 is arranged on the radiation passage area 10.The optoelectronic semiconductor chip described here is now based, inter alia, on the concept of encapsulating the leakage current paths formed by the threading dislocations 3 via microdiodes 11 in an ESD layer 9 specifically inserted for this purpose. The basis for the microdiodes 11 are the V-defects which are produced over certain growth conditions and which preferably arise exactly at the lines of the threading dislocations 3. That is to say that V defects are generated in a targeted manner on the potential current paths, said V defects forming microdiodes 11. Preferably, at least 75%, particularly preferably all threading dislocations 3 comprise a photodiode 11.The optoelectronic semiconductor chip 100 comprises a substrate 7, which contains sapphire, for example, or consists of sapphire. The first semiconductor layer sequence 1 and the second semiconductor layer sequence 2 are subsequently deposited on the substrate 7.In contrast to the optoelectronic semiconductor chip 100 described in connection with FIG. 1A, the first semiconductor layer sequence 1 now comprises the ESD layer 9 which contains V defects which form the microdiodes 11. FIG. 3A shows a schematic circuit diagram for the optoelectronic semiconductor chip 100 of FIG. 2.The microdiodes 11 have a similar breakdown behavior, i.e., they have the same or substantially the same breakdown voltage. The breakdown voltage of the microdiodes 11 is lower than the breakdown voltage of the pn junction formed by the active region. The microdiodes 11 therefore open simultaneously in the reverse direction in the case of an ESD voltage pulse 4 (compare FIG. 3B ). Thus, the charge impressed by the ESD voltage pulse 4 does not flow via the weakest leakage path or paths along the offset lines 3, as shown in FIG. 1A, but rather the charge distributes itself to the ensemble of the micro-diodes 4. A quasi-two-dimensional breakdown takes place over the entire cross-sectional area of the optoelectronic semiconductor chip 100, so that an ESD strength of at least 1 kV, for example of typically 2 kV, is achieved. This means that the weakest leakage current paths in the optoelectronic semiconductor chip are protected via the microdiodes and the load due to an ESD voltage pulse is distributed over all microdiodes 11 or at least a large part of the microdiodes 11, so that the current densities occurring are each so small that no damage occurs.FIG. 3C schematically shows the current (I) voltage (U) characteristic curves of the microdiodes 11 and of the active region 12 The breakdown voltage UBRof the microdiodes 11 is smaller than the breakdown voltage of the active region 12 The threshold voltage UFof the active region 12 is smaller than the threshold voltage of the microdiodes 11 to this extent, so that the forward characteristic of the optoelectronic semiconductor chip 100 is hardly disturbed or is not disturbed at all by the microdiodes 11.Referring now to FIGS. 4A through 4C, the growth conditions under which the ESD layer 9 can be formed with the microdiodes 11 will be described in more detail. FIG. 4A shows images of the optoelectronic semiconductor chip, wherein the ESD layers 9 are grown at different temperatures between 820° C. and 860° C. FIG. 4B shows images of ESD layers 9 that have been grown at temperatures between 880° C. and 1080° C.Figure 4C shows a graph of the density of the V defects as a function of the growth temperature. As can be seen from Figs. 4A to 4C, the density of the V defects greatly depends on the growth temperature T. The ESD layer 9 is made of gallium nitride, for example. In the present case, a sufficient density of V defects and thus of microdiodes 11 for protecting the optoelectronic semiconductor chip 100 is achieved below the critical temperature TC of approximately 870° C. This temperature may depend on the growth plant used and / or the location of temperature measurement in the plant. However, the critical temperature below which the density of the V defects is sufficiently high can be determined as shown in Figs. 4A to 4C.While the density of the microdiodes 11 can thus be adjusted via the growth temperature T, the size of the V defects is also important in order to achieve a sufficient ESD strength of the optoelectronic semiconductor chip 100.The graphical plot of FIG. 5 shows the thickness D 9 of the ESD layer 9 (in this regard, compare also FIG. 2 ) plotted against the probability W that an optoelectronic semiconductor chip 10 protrudes undamaged beyond an ESD voltage pulse 4 as shown, for example, in FIG. 3B. As can be seen from FIG. 5, a thickness of the ESD layer 9 of at least 80 nm, preferably of at least 100 nm, proves to be particularly suitable in the present case. The suitable thickness depends on the thickness of the active region, as described above.The graph of FIG. 6 shows the error rate of the optoelectronic semiconductor chips 100 for conventional optoelectronic semiconductor chips a and optoelectronic semiconductor chips b described here plotted against the ESD voltage in volts.As can be seen from FIG. 6, the error rate falls significantly in the case of ESD voltage pulses 4.It has been found that ESD protection is particularly advantageous in particular for light-emitting diode chips emitting green light, since these are particularly susceptible to ESD, owing to the high indium content in the active zone, without the microdiodes 11.

Claims

Optoelectronic semiconductor chip (100) having - a first semiconductor layer sequence (1) comprising a plurality of microdiodes (11), and - a second semiconductor layer sequence (2) comprising an active region (12), wherein - the first semiconductor layer sequence (1) and the second semiconductor layer sequence (2) are based on a nitride compound semiconductor material, - the first semiconductor layer sequence (1) is arranged upstream of the second semiconductor layer sequence (2) in the growth direction, - the microdiodes (11) form an ESD protection for the active region (12), - at least one of the microdiodes (11) comprises a pn junction, - the active region (12) comprises at least one pn junction, - the pn junction of the microdiodes (11) and the pn junction of the active region (12) are rectified, the pn junction of the micro diode (11) has a lower breakdown voltage (UBR) in the reverse direction than the pn junction of the active region (12), and at least 75% of the micro diodes (11) are arranged within an ESD layer (9) having a thickness (d9) of at least half and at most three times the thickness of the active region (11).Optoelectronic semiconductor chip (100) according to the preceding claim, in which - at least one of the microdiodes (11) is formed by a V defect.Optoelectronic semiconductor chip (100) according to one of the preceding claims, in which - at least one of the microdiodes (11) comprises a pn junction, - the active region (12) comprises at least one pn junction, wherein - the pn junction of the microdiode (11) and the pn junction of the active region (12) are rectified, and - the pn junction of the microdiode (11) has a higher threshold voltage (UF) in the forward direction than the pn junction of the active region (12).Optoelectronic semiconductor chip (100) according to one of the preceding claims, in which - the density of the microdiodes (11) is at least 5*10^7 / cm^2.Optoelectronic semiconductor chip (100) according to one of the preceding claims, in which - an ESD voltage pulse (4) flows away at least over 50% of the microdiodes (11) in the reverse direction of the microdiodes (11).Optoelectronic semiconductor chip (100) according to one of the preceding claims, in which - at least 75% of the microdiodes (11) are each arranged in the region of a thread offset (3).Optoelectronic semiconductor chip (100) according to one of the preceding claims, in which - the second semiconductor layer sequence (2) directly follows the first semiconductor layer sequence (1).Optoelectronic semiconductor chip (100) according to one of the preceding claims, which emits blue and / or green light during operation.Method for producing an optoelectronic semiconductor chip (100), comprising the steps of: - providing a growth substrate (7), - epitaxially depositing a first semiconductor layer sequence (1), - epitaxially depositing a second semiconductor layer sequence (2) on the first semiconductor layer sequence (1), wherein - the first semiconductor layer sequence (1) comprises an ESD layer (9) which is deposited at a growth temperature at which V defects occur in high density in the ESD layer (9) and the V defects form microdiodes in the ESD layer, and - the second semiconductor layer sequence (2) comprises an active region (12), wherein - at least one of the microdiodes (11) comprises a pn junction, - the active region (12) comprises at least one pn junction, the pn junction of the photodiode (11) and the pn junction of the active region (12) are rectified, the pn junction of the photodiode (11) has a lower breakdown voltage (UBR) in the reverse direction than the pn junction of the active region (12).The method of the preceding claim, wherein the growth substrate comprises or consists of sapphire.Method according to claim 9 or 10, wherein the ESD layer (9) is based on GaN.Method according to at least one of Claims 9 to 11, wherein an optoelectronic semiconductor chip (100) according to one of Claims 1 to 8 is produced.Use of a plurality of V-defects for forming microdiodes (11) in an optoelectronic semiconductor chip (100) according to one of claims 1 to 8, wherein the microdiodes (11) increase the ESD strength of the optoelectronic semiconductor chip (100) compared to an optoelectronic semiconductor chip (100) having fewer V-defects.

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