System and method for delay-lock loop relock mode

Abstract

Storage device (200) comprising: a delay locked loop (DLL) circuit (220) comprising: a delay line (310) for receiving an input clock signal and for generating an output clock signal, a feedback circuit (340) coupled to the delay line (310), the feedback circuit (340) comprising: a phase detector (341) coupled to the delay line (310) for detecting a phase difference between the clock input signal and the clock output signal and for generating a phase output corresponding to the phase difference, and a temperature sensing mechanism for detecting a temperature change of the storage device (200); a control logic (343) coupled to the phase detector (341) and the delay line (310) for receiving the phase output from the phase detector and for generating a control signal corresponding to the phase output, wherein the feedback circuit is to set a delay interval with the control signal to match the clock phase of the output clock signal to the clock phase of the input clock signal, and wherein the set delay interval is to be locked on the delay line, and wherein the entire feedback circuit is to be turned off after the set delay interval has been locked onto the delay line and while the delay line remains on, and wherein the feedback circuit is to be turned on in response to a temperature detected by the temperature sensing mechanism exceeding a predetermined level to readjust the clock phase of the output clock signal to the clock phase of the input clock signal and to relock the set delay interval onto the delay line.

Description

BACKGROUND1. AREA

[0001] One or more embodiments of the invention relate to the field of memory devices, and more particularly to a system and method for controlling a delay locked loop (DLL) in a dynamic random access memory (DRAM) device. 2. DISCUSSION OF RELATED TECHNOLOGY

[0002] In high-performance digital systems, clock synchronization between different electronic devices is a critical design criterion for maintaining system performance. For example, the output of a memory device must be synchronized with the system clock to avoid operational errors and delays that affect overall system performance.

[0003] The memory device, specifically a dynamic random-access memory (DRAM) device, implements a delay-locked loop (DLL) that synchronizes the DRAM output with the system clock. The DLL monitors the system clock signal received from the DRAM device and synchronizes its output clock signal with the system clock signal to ensure that the data output from the DRAM device is synchronized with the system clock. Typically, the DLL includes a feedback loop that monitors an input clock signal, which is usually the system clock, and adjusts its output clock signal to be in phase with the input clock signal.

[0004] In DRAM, the DLL helps control read response timing and on-die termination (ODT) operations. Thus, the DLL improves bus latency and overall system performance. However, during DRAM operation, the DLL constantly receives power to maintain synchronization between DRAM output and the system clock. Thus, the DLL contributes to the high power consumption of DRAM, which also requires constant power to maintain data integrity. A memory designer could implement a DLL off state to bypass the entire DLL to save power, but this would result in asynchronous timing between the read response timing and the ODT.

[0005] Reference is also made to the documents US 2007 / 0 152 723 A1, US 2002 / 0 136 082 A1, US 2004 / 0 174 760 A1, US 2007 / 0 091 705 A1 and US 2006 / 0 221 759 A1. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram illustrating a system including a delay locked loop in accordance with an embodiment of the invention. Fig. 2 is a block diagram illustrating a delay locked loop in accordance with an embodiment of the invention. Fig. 3 is a simplified state diagram illustrating the state transitions of a memory module in accordance with an embodiment of the invention. Fig. 4 is a block diagram illustrating a processing system in which an embodiment of the invention may be used. DETAILED DESCRIPTION

[0006] In the following description, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments of the invention. In other instances, well-known functionality and features of storage devices have not been described in particular detail in order not to unnecessarily obscure this detailed description.

[0007] Embodiments of the invention include a memory device comprising a delay-locked loop (DLL) circuit. The DLL circuit includes a delay line for receiving an input clock signal and for generating an output clock signal. A feedback circuit is coupled to the delay line. The feedback circuit has the capability of adjusting a delay interval to match the clock phase of the output clock signal to the clock phase of the input clock signal. The delay interval is to be locked on the delay line. Once the delay interval is locked, the feedback circuit is to be turned off. By turning off the feedback circuit and turning on the delay line, power consumption is reduced without compromising the synchronization of the input and output clock signals.Subsequently, the feedback circuit should be periodically activated to adjust the clock phase of the output clock signal to the input clock signal based on the previously locked delay interval. By periodically enabling the feedback circuit, the DLL circuit prevents phase deviation between the input and output clock signals. Fig. 1 illustrates a system for controlling a memory module. In one embodiment of the invention, the system includes a memory controller 120 coupled to a memory module 200. The memory module 200 includes a delay locked loop (DLL) 220 coupled to the memory controller 120. In one embodiment of the invention, the memory module 200 is a dynamic random access memory (DRAM) module. In a particular embodiment, the memory module 200 is a double-data-rate (DDR) DRAM module, such as, but not limited to, DDR3 DRAM or DDR4 DRAM.

[0008] Fig. Figure 2 illustrates DLL 220 in accordance with one embodiment of the invention. DLL 220 is coupled to a clock input pad 410 and a data output pad 420. In one embodiment, clock input pad 410 is coupled to a system clock pad (not shown) for receiving a system clock signal. In one embodiment, data output 420 is coupled to a data strobe (DQS) pad (not shown).

[0009] The DLL 220 includes a delay line 310 coupled to the clock input pad 410 and the data output pad 420. In one embodiment, the delay line 310 includes an input 311 to receive an input clock signal and an output 312 to generate an output clock signal. In one embodiment, the delay line 310 is a digitally controlled variable delay line. In one embodiment, an input clock buffer 411 is coupled between the clock input pad 410 and the input 311 of the delay line 310. The input clock buffer 411 receives a system clock signal from the clock input pad 410 and generates an input clock signal on the delay line 310. Additionally, a data output buffer 421 is coupled between the output 312 of the delay line 310 and the data output pad 420.

[0010] In one embodiment, the DLL 220 further includes a feedback circuit 340 coupled to the delay line 310. The feedback circuit 340 has the capability of adjusting a delay interval to match the clock phase of the output clock signal generated by the delay line 310 to the clock phase of the input clock signal received by the delay line 310. The delay interval is then locked onto the delay line 310. In one embodiment of the invention, the feedback circuit 340 includes a phase detector 341 coupled to the delay line 310. In one embodiment, the phase detector 341 is coupled to the input 311 and the output 312 of the delay line 310 to detect the phase difference between the input clock signal at input 311 and the output clock signal at output 312.The phase detector then generates a phase output signal according to the phase difference between the input clock signal and the output clock signal. In one embodiment, a delay replica 342 is coupled between the phase detector 341 and the output 312 of the delay line 310.

[0011] In one embodiment, feedback circuit 340 further includes control logic 343 coupled to phase detector 341. Control logic 343 receives the phase output signal from phase detector 341 and generates a control signal according to the phase output signal. The control signal generated by control logic 343 corresponds to a delay interval that adjusts the clock phase of the output clock signal to the clock phase of the input clock signal.

[0012] In one embodiment of the invention, the DLL 220 further includes a control register 350 coupled to the delay line 310 and the control logic 343. The control register 350 receives the control signal generated by the control logic 343 and stores a control value corresponding to the delay interval. In other words, the delay interval is now "locked" on the delay line 310.

[0013] In a conventional DRAM module, the entire DLL constantly receives power to set and lock the delay interval to synchronize the DRAM output with the system clock. In particular, the typical DLL constantly receives power when the DRAM is in run mode. Run mode refers to a powered-on DRAM performing operations such as, but not limited to, a read operation, such as reading data from the DRAM's memory bank, or a write operation, such as writing data to the memory bank. Additionally, the run mode also includes an idle mode in which the DRAM waits for commands to read or write data to the memory bank. In one embodiment of the invention, the feedback circuit 340 is enabled to set and lock the delay interval only when commanded by the memory controller 120.When the memory module 200 is in operation mode, the feedback circuit 340 sets and locks the delay interval on the delay line 310. Once the delay interval is locked, the feedback circuit 340 is powered down to reduce power consumption. In one embodiment, the phase detector 341, delay replica 342, and control logic 343 are powered down. Furthermore, when the feedback circuit 340 is powered down or turned off, the delay line 310 remains powered up with the delay interval from the previous update of the feedback circuit 340. Then, the feedback circuit 340 is periodically powered up to set or lock the delay interval on the delay line 310. In one embodiment, the operations of the DLL 220 are separated from the read or write operations of the memory module 200.In other words, the switching on or off of operations of the feedback circuit 340 does not depend on the read or write operations of the memory module 200.

[0014] In one embodiment of the invention, memory controller 120 is coupled to DLL 220 to control the operations of DLL 220. In one embodiment, memory controller 120 turns off the entire feedback circuit 340 after the delay interval is locked without turning off delay line 310. To maintain clock synchronization, memory controller 120 periodically turns on feedback circuit 340 to readjust the clock phase of the input clock signal at input 311 to the clock phase of the output clock signal at output 312. In one embodiment of the invention, memory controller 120 includes a scheduler module (not shown) that determines periodic intervals for turning on feedback circuit 340.

[0015] Fig. Figure 3 illustrates a simplified state diagram showing the state transitions of memory module 200 in accordance with an embodiment of the invention. In the powered-on state 710, power is supplied to memory module 200. When powered on, the memory module undergoes initialization and calibration before entering an idle mode, shown as the sleep state 720.

[0016] From the idle state 720, the memory module 220 may transition to a read / write state 730 when it receives a read or write command. In the read / write state 730, the memory module 220 performs read or write operations. In one embodiment of the invention, the memory module 200 includes a memory bank (not shown) coupled to the DLL 220. During the read or write operations, data is either received, stored, or output from the memory bank. After the read or write operations are performed, the memory module 220 transitions back to the idle state 720. In the idle state 720, data is neither read nor written from the memory bank. In other words, the memory bank waits for commands to receive, store, or output data.In the powered-on state 710, the DLL 220 is initialized to lock a delay interval so that the timing of the read response of the memory module 200 is aligned with the system clock. In other words, the entire DLL 220 is enabled so that the feedback circuit 340 can set a delay interval to align the clock phase of the output clock signal generated by the delay line 310 with the clock phase of the input clock signal received by the delay line 310. The delay interval is then locked on the delay line 310. Once the delay interval has been locked, the feedback circuit 340 is shut down to reduce the power consumption of the memory module 200.

[0017] When the feedback circuit 340 is powered down, the delay line 310 remains powered up with the locked delay interval. By keeping the delay line 310 powered up, the DLL 220 remembers the previously locked delay interval to quickly power up or power down. Keeping the delay line 310 powered up also allows the memory module 200 to achieve synchronous clocking even though the feedback circuit 340 is powered down.

[0018] Subsequently, feedback circuit 340 is enabled at periodic intervals based on the previously locked delay interval to readjust the clock phase of the output clock signal to the clock phase of the input clock signal. In one embodiment, the periodic interval is approximately 10 clock cycles. If there is no phase mismatch between the output clock signal and the input clock signal, DLL 220 relocks the previously locked delay interval on delay line 310. On the other hand, if there is a phase mismatch between the output clock signal and the input clock signal, DLL 200 adjusts the delay interval and locks the adjusted delay interval on delay line 310.

[0019] In one embodiment of the invention, the memory module 200 may transition from the sleep state 720 to a DLL relock state 770, as shown in Fig. 3. In the DLL relock state 770, the memory module 200 receives a DLL relock command from the memory controller 120 to enable the feedback circuit 340 and adjust the clock phase of the output clock signal to the clock phase of the input clock signal. When the feedback circuit 340 is enabled, in one embodiment, the DLL 220 uses the previously locked delay interval to adjust the clock phase of the output clock signal to the input clock signal. However, due to a voltage or temperature shift, the timing of the read response may deviate from the system clock signal. In this case, the DLL 220 adjusts the delay interval so that the clock phase of the output clock signal is again adjusted to the input clock signal before locking the adjusted delay interval on the delay line 310.Thus, the feedback circuit 340 can be periodically enabled in the DLL relock state 770 to correct any phase deviation between the input clock signal and the output clock signal. In one embodiment, a developer has the flexibility to define the degree of clock synchronization by varying the execution frequency of the DLL relock instruction.

[0020] By performing a periodic relock of the delay interval, the DLL 220 overcomes a major performance concern with a typical DDR3 DLL off state where the ODT and read response timing are asynchronous, because DRAM designers could implement the DLL off state by bypassing the entire DLL to conserve delay line power, or because the implementation does not allow locking the delay interval on a variable delay line when the feedback circuit is off.

[0021] In an alternative embodiment, a temperature sensing mechanism may be implemented to detect any significant temperature change of memory module 200. If the detected temperature exceeds a desired level, there may be a voltage or temperature shift causing a phase deviation. Memory controller 120 then transmits a DLL relock command to enable feedback circuit 340 and correct any phase deviation.

[0022] In one embodiment of the invention, the memory module 200 may transition from the read / write state 730 to the DLL relock state 770. In one embodiment of the invention, the feedback circuit 340 is enabled during a read or write operation based on the previously locked delay interval to adjust the clock phase of the output clock signal to the input clock signal. Similarly, the previously locked delay interval on the delay line is locked once the feedback circuit 340 is enabled if there is no phase mismatch between the output clock signal and the input clock signal. Alternatively, the DLL 220 adjusts the delay interval if there is a phase mismatch so that the clock phase of the output clock signal is re-adjusted to the input clock signal before the adjusted delay interval is locked on the delay line 310.In another embodiment, the feedback circuit 340 is turned on before a read / write operation is initiated or after a read / write operation is performed.

[0023] From the sleep state 720, the memory module 200 can also transition to a self-refresh state 740. In one embodiment of the invention, the memory module 220 is forced into the DLL relock state 770 after exiting the self-refresh state 740. In other words, when the memory module 200 exits a self-refresh state 740, the memory controller 120 sends a DLL relock command to the memory module 200 to enable the feedback circuit 340. Once the feedback circuit 340 is enabled, the DLL 220 relocks the previously locked delay interval. If a phase deviation is present, the DLL 220 sets and locks the delay interval.

[0024] It goes without saying that Fig. 3 is a simplified state diagram of the memory module 200 and certain well-known operations such as reset, ZQ calibration, bank active, precharge, active power, precharged shutdown are not shown for simplicity.

[0025] Fig. 4 illustrates a processing system including a processor 810, a power supply 820, and a random access memory (RAM) 830. In one embodiment, the processor 810 includes an arithmetic logic unit 811 and an internal cache 812. The processing system further includes a graphics interface 840, a chipset 850, a cache 860, and a network interface 870. In one embodiment, the processor 810 may be a microprocessor or any type of processor. If the processor 810 is a microprocessor, it may be included on a chip die with all or combinations of the remaining features, or one or more of the remaining features may be electrically coupled to the microprocessor die via known connections or interfaces. Fig.4, one or more embodiments of DLL 220 may be implemented in RAM 830, for example, to reduce the power consumption of RAM 830. In one embodiment, memory controller 120 may be implemented in chipset 850.

[0026] Embodiments of the invention may be implemented in a variety of electronic devices and logic circuits. Furthermore, devices or circuits incorporating embodiments of the invention may be included within a variety of computer systems, including point-to-point (p2p) computer systems and shared-bus computer systems. Embodiments of the invention may also be included in other computer system topologies and architectures.

[0027] Several embodiments of the invention have thus been described. However, those skilled in the art will recognize that the invention is not limited to the described embodiments, but may be practiced with modifications and changes within the spirit and scope of the appended claims that follow.

Claims

[1] A storage device (200) comprising: a delay locked loop (DLL) circuit (220) comprising: a delay line (310) for receiving an input clock signal and for generating an output clock signal, a feedback circuit (340) coupled to the delay line (310), the feedback circuit (340) comprising: a phase detector (341) coupled to the delay line (310) for detecting a phase difference between the clock input signal and the clock output signal and for generating a phase output corresponding to the phase difference, and a temperature sensing mechanism for detecting a temperature change of the storage device (200); a control logic (343) coupled to the phase detector (341) and the delay line (310) for receiving the phase output from the phase detector and for generating a control signal corresponding to the phase output, wherein the feedback circuit is to set a delay interval with the control signal to match the clock phase of the output clock signal to the clock phase of the input clock signal, and wherein the set delay interval is to be locked on the delay line, and wherein the entire feedback circuit is to be turned off after the set delay interval has been locked onto the delay line and while the delay line remains on, and wherein the feedback circuit is to be turned on in response to a temperature detected by the temperature sensing mechanism exceeding a predetermined level to readjust the clock phase of the output clock signal to the clock phase of the input clock signal and to relock the set delay interval onto the delay line. [2] The storage device (200) of claim 1, further comprising: a memory bank coupled to the DLL circuit (220), and wherein the feedback circuit (340) is to be switched on when the memory bank is to receive, store or output data. [3] The memory device (200) of claim 2, wherein the feedback circuit (340) is to be turned on when the memory bank is waiting to receive, store, or output data. [4] The storage device (200) of claim 1, further comprising: a control register (350) coupled to the control logic (343) and the delay line (310), the control register to receive the control signal generated by the control logic and to store a control value corresponding to the delay interval. [5] The memory device (200) of claim 1, wherein the delay line (310) is not to turn off when the feedback circuit (340) is turned off after the delay interval on the delay line (310) is locked. [6] The memory device (200) of claim 1, wherein the feedback circuit (340) is to adjust the delay interval locked on the delay line (310) when the feedback circuit is turned on. [7] System comprising: a storage device (200) comprising: a delay locked loop (DLL) circuit (220) comprising: a delay line (310) for receiving an input clock signal and for generating an output clock signal, and a feedback circuit (340) coupled to the delay line (310), the feedback circuit comprising: a phase detector coupled to the delay line for detecting a phase difference between the clock input signal and the clock output signal and for generating a phase output corresponding to the phase difference, and a control logic coupled to the phase detector and the delay line for receiving the phase output from the phase detector and for generating a control signal corresponding to the phase output, wherein the feedback circuit (340) is to set a delay interval with the control signal to adjust the clock phase of the output clock signal to the clock phase of the input clock signal, and wherein the set delay interval is to be locked on the delay line (310), a temperature sensing mechanism for detecting a temperature change of the storage device (200); and a memory controller (120) coupled to the DLL circuit (220), wherein the memory controller is to turn off the feedback circuit (340) after the set delay interval is locked onto the delay line (310) and while the delay line remains on, and wherein the memory controller is to turn on the feedback circuit in response to a temperature detected by the temperature sensing mechanism exceeding a predetermined level, to readjust the clock phase of the output clock signal to the clock phase of the input clock signal and to relock the set delay interval onto the delay line. [8] The system of claim 7, wherein the memory controller (120) is not to turn off the delay line (310) when the feedback circuit (340) is to be turned off. [9] The system of claim 7, wherein the feedback circuit (340) is to set the delay interval when the memory controller (120) is to turn on the feedback circuit (340). [10] The system of claim 7, further comprising: a temperature sensor coupled to the storage device (200) to detect a temperature change of the storage device (200), and wherein the memory controller (120) is to switch on the feedback circuit (340) according to the detected temperature change to adjust the delay interval. [11] The system of claim 7, wherein the memory controller (120) comprises a scheduler to determine a periodic interval to turn on the feedback circuit (340). [12] The system of claim 7, wherein the storage device (200) further comprises: a memory bank coupled to the DLL circuit (220), and wherein the feedback circuit (340) is to be switched on when the memory bank is to receive, store or output data. [13] The system of claim 12, wherein the feedback circuit (340) is to be turned on when the memory bank is waiting to receive, store, or output data. [14] Method for controlling a storage device (200), with a phase detector (341) of a feedback circuit (340) comprising: Detecting a phase difference between a clock input signal and a clock output signal, wherein the feedback circuit is coupled to a delay line, the delay line receiving the clock input signal and generating the clock output signal; and Generate a phase output corresponding to the phase difference using feedback circuit control logic: Receiving the phase output from the phase detector, and Generating a control signal corresponding to the phase output with the control signal; Setting a delay interval by the feedback circuit to match a clock phase of the output clock signal to a clock phase of the input clock signal; Locking the set delay interval on the delay line (310); shutting down the entire feedback circuit (340) after the set delay interval has been locked and while the delay line (310) remains switched on, and Turning on the feedback circuit (340) in response to a temperature detected by a temperature sensing mechanism exceeding a predetermined level to readjust the clock phase of the output clock signal to the clock phase of the input clock signal using the delay interval locked on the delay line (310) and to relock the adjusted delay interval onto the delay line. [15] The method of claim 14, wherein shutting down the entire feedback circuit (340) after the feedback circuit has locked the delay interval does not include shutting down the delay line (310). [16] The method of claim 14, further comprising: Detecting a temperature change of the storage device (200) and Switching on the feedback circuit (340) according to the detected temperature to set the delay interval. [17] The method of claim 14, further comprising: coupling a memory bank to the delay line (310), the memory bank receiving, storing and outputting data; wherein turning on the feedback circuit (340) is performed at periodic intervals to relock the delay interval when the memory bank receives, stores, and outputs data. [18] The method of claim 17, wherein turning on the feedback circuit (340) is performed at periodic intervals to relock the delay interval when the memory bank is waiting to receive, store, and output data.

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