Memory cell

Abstract

Memory cell, comprehensive: a static read / write memory (SRAM) cell (102) with two pass transistors (120, 122) and four logic transistors (104, 106, 114, 116) connected in two cross-coupled inverters, the SRAM cell being formed by complementary metal oxide semiconductor (CMOS) technology; and a phase-change memory (PCM) area (130) layered on the SRAM cell (102) to provide the SRAM cell with non-volatility, wherein two of the four logic transistors are NMOS transistors (104, 114) each having a source coupled to a first node of a chalcogenic material in the PCM area (130); further comprising a first pass-gate transistor (136) coupling a bit line to the source of the first NMOS transistor (104) and a second pass-gate transistor (138) coupling a complement bit line to the source of the second NMOS transistor (114).

Description

Background of the invention

[0001] The demands for increased functionality and reduced overall system costs can set system constraints for consumer electronics devices. Volatile and non-volatile memory have been used in consumer devices such as car navigation systems, smartphones, digital cameras, PDAs, and MP3 players, as well as in countless other portable applications. New non-volatile technologies are planned for an increasing number of functions in digital consumer devices. These new non-volatile memories possess characteristics that provide opportunities for improvements in these consumer devices.

[0002] US 6,847,543 B2 shows an SRAM cell coupled to a phase-change memory, which may incorporate chalcogenide material. DE 10 2005 024 897 A1 shows a non-volatile memory cell with a CMOS circuit arrangement comprising two p-type and four n-type field-effect transistors. Programmable resistors are connected between the source and drain of one p-type and one n-type field-effect transistor, respectively. US 2007 / 0 165 446 A1 shows a bistable multivibrator constructed conventionally from two inverters. A first programmable resistor is connected between the output of the first inverter and the input of the second inverter. A second programmable resistor is connected between the output of the second inverter and the input of the first inverter. The programmable resistors may be phase-change memories.WO 2003 / 085 741 A1 and US 2006 / 0 181 916 A1 each show a non-volatile memory with an SRAM cell coupled to phase-change memories via switching elements. Brief description of the drawings

[0003] The subject matter considered to be the invention is set out and clearly claimed, in particular in the concluding section of the documents. However, the invention is best understood, both in terms of its organization and operating procedures, together with its tasks, features, and advantages, by referring to the following detailed description when read together with the drawings, which: Fig. 1 and Fig. Two exemplary embodiments of a static random access memory (SRAM) cell are illustrated, which incorporates phase change memory materials to provide non-volatile properties; Fig. Figure 3 illustrates an embodiment of an SRAM cell combined with a PCM (phase change memory) area, where pass gates are assigned for programming the PCM; and Fig. Figure 4 illustrates the use of data stored in the combination of SRAM cell and PCM to control a switch in a crossover application.

[0004] It is appreciated that, for the sake of simplicity and clarity, the elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Furthermore, reference symbols have been repeated within the figures where deemed appropriate to indicate corresponding or analogous elements. Detailed description

[0005] The following detailed description presents numerous specific details to facilitate a thorough understanding of the invention. However, those skilled in the art will understand that the present invention can be carried out without these specific details. Elsewhere, well-known methods, procedures, components, and circuits are not described in detail so as not to obscure the present invention.

[0006] The terms "coupled" and "connected," along with their variations, may be used. It should be understood that these terms are not synonymous. Instead, in certain embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in either direct or indirect (with other elements between them) physical or electrical contact with each other, and / or that two or more elements cooperate or interact with each other (e.g., as in a cause-and-effect relationship).

[0007] Fig. Figure 1 illustrates a matrix of enhanced SRAM (e-SRAM (Enhanced Static Random Access Memory) cells 100, each containing a static random access memory (SRAM) cell 102 combined with a phase change memory (PCM) area 130 to provide non-volatile memory properties. The PCM can be combined with an SRAM cell that is essentially integrated using a standard CMOS process, adding layers after the front-end setup layers. The PCM essentially sits on top of the SRAM logic and results in only a small additional loss of area on a standard SRAM while providing non-volatileity. The PCM material can be integrated on top of the NMOS source and drain contacts in the SRAM cell.This SRAM and PCM memory combination eliminates the need for a separately integrated PCM, an integrated flash memory, or a non-volatile off-chip memory.

[0008] The materials of the PCM cell are an alloy of elements from Group VI of the periodic table, elements such as Te or Se, also known as chalcogenides or chalcogenic materials. Chalcogenides can advantageously be used to provide data retention and remain stable even when the current is disconnected from the volatile SRAM memory. Taking the phase-change material Ge₂Sb₂Te₅ as an example, two or more phases occur, each with different electrical properties that are useful for storage. In this embodiment, the chalcogenic material can be electrically switched between two states, i.e., between the amorphous and the crystalline state, resulting in non-volatile storage capability for the extended SRAM (e-SRAM) cell 100.

[0009] The figure shows the six-transistor CMOS SRAM cell with two cross-coupled CMOS inverters, which store one bit of information. The NMOS transistor 104 and the PMOS transistor 106 form one inverter of the latch, and the NMOS transistor 114 and the PMOS transistor 116 form the other inverter of the latch. Two NMOS pass transistors 120 and 122 are controlled by the read / write (R / W) line to pass bit line (B) and bit line' (B') information into the cell. The phase-change memory materials are layered on top of the CMOS devices, so that the e-SRAM cell 100 has non-volatile properties provided by the PCM resistor elements 132 and 134. The figure shows that the pass-gate transistor 136 is coupled to the resistor element 132 and the pass-gate transistor 138 is coupled to the resistor element 134.Transistors 136 and 138 are enabled by a program line (PGM) to supply a current applied via a bit line voltage to the selected resistive element, raising the local temperature above the melting point of the chalcogenide material. Note that the PMOS devices 140 and 141 can be amortized over many cells or, in some embodiments, omitted from the matrix.

[0010] As long as PCM area 130 is not programmed, e-SRAM cell 100 can be read and written in the conventional manner, like volatile memory. For example, in read mode, the R / W line can be activated to read the stored value of the CMOS latch on bit lines B and B'. The cross-coupled inverters within SRAM cell 102 drive the bit lines whose values ​​can be read. One advantage of SRAM cell 102 is that data can be read almost as fast as with a conventional SRAM cell.

[0011] To write new data to e-SRAM cell 100, the R / W line is activated to enable transistors 120 and 122 to clear the previous state of the cross-coupled inverters with the data provided on bit lines B and B'. A subsequent command can be issued to e-SRAM cell 100 to activate the programming line PGM and load the latched value of SRAM cell 102 into PCM area 130. After PCM area 130 is loaded, e-SRAM cell 100 can then be switched off, and current can subsequently be reapplied, with the non-volatile properties of the PCM preserving the stored data.

[0012] Alternatively, data can be written directly to PCM cell 130. The loaded data sets the PCM resistors, which bias the SRAM "off balance," so that when an e-SRAM cell 100 is powered on, the latch in SRAM cell 102 receives the data contained in the pair of PCM resistors. Using this method, the SRAM cell combined with the PCM cell is useful in applications requiring non-volatile properties while maintaining the high read and write speeds associated with conventional SRAM. Mixing volatile and non-volatile memory in the same memory cell provides relatively low densities, which are valuable in embedded logic.

[0013] Fig. Figure 2 illustrates another embodiment in which PCM material is layered in an SRAM cell, as shown with a matrix of extended SRAM (e-SRAM) cells 200, each comprising a static read / write memory (SRAM) cell 202 combined with a phase-change memory (PCM) region 230 to provide non-volatile memory characteristics. In this embodiment, the PCM resistive element 132 is connected between a source of an NMOS transistor 104 and a separate source line designated SRC1; and the resistive element 134 is connected between a source of an NMOS transistor 114 and a separate source line designated SRC2.

[0014] It is assumed that resistors 132 and 134 are programmed to the SET state, meaning that both resistors are programmed to the low-resistance state. Because the SRC1 and SRC2 source lines are at ground potential (GND), the R / W and B / B' lines operate in the conventional manner for reading and writing to the SRAM cell 202. The e-SRAM cell 200 is volatile, and its read / write speeds are similar to state-of-the-art SRAM.

[0015] To prevent the contents of an e-SRAM cell 200 from becoming volatile, the PCM area 230 can be written. For example, the PCM resistor 132 can remain in the SET condition and undisturbed by increasing the potential on the SRC1 source line to, for example, an inhibit voltage of 4 volts. On the other hand, the PCM resistor 134 can be subjected to a RESET pulse by holding the SRC2 source line at ground potential.

[0016] Pass transistors 120 and 122 can then be activated, for example, with 5 volts on the R / W line, which drives the reverse bias voltage in pass-through transistor 120. The supply and N-wells can also be raised to the reverse bias voltage of 4 volts to prevent forward bias in PMOS transistors 106 and 116. NMOS transistor 104 and PMOS transistor 106 do not conduct current because both transistors are biased to the 4-volt reverse bias voltage. The gates of NMOS transistor 114 and PMOS transistor 116 also receive the 4 volts. The pass transistor 122 passes a programming voltage of, for example, 3 volts, which is received at B' and passed through the NMOS transistor 114 and the PCM resistor element 134. This high-current programming current is sufficient to switch the PCM resistor element 134 into the RESET state.At the end of this programming pulse, the bias voltages are quickly disconnected to allow the cell to cool down into the quench state. Because PCM resistor element 134 is in the quench high-resistance state and PCM resistor element 132 is in the set low-resistance state, the e-SRAM cell 200 can be switched off.

[0017] After power-up, the potential on both SRC1 and SRC2 lines is held at ground while the supply voltage ramps up to an e-SRAM cell 200. A small current flows as the NMOS and PMOS devices turn on, and a rising potential develops across the high resistance of the PCM resistor element 134 at the source of the NMOS transistor 114. As the gate-to-source voltage (Vgs) of transistor 114 decreases relative to the Vgs of NMOS transistor 104, the drain voltage of NMOS transistor 114 increases. Data is acquired after power-up because the common node between transistors 114 and 116 accepts a logic "1," and the common node between transistors 104 and 106 accepts a logic "0."Consequently, the symmetry of the SRAM is off-balance and returns to the correct state after being switched on, as caused by the two different resistances of the PCM cells.

[0018] Fig. Figure 3 is another embodiment of an SRAM cell 302 combined with a PCM area 330 to provide non-volatile memory capabilities. Both PCM resistor elements 132 and 134 are connected to ground (GND) in this embodiment. Pass gates 332 and 334 are dedicated to programming the PCM and can be either NMOS or PMOS transistors. This embodiment offers advantages in terms of reduced routing, power consumption, and voltage dissipation, as programming is performed by a single pass gate.

[0019] Fig. Figure 4 is an embodiment of an SRAM cell combined with a PCM area, as shown in Fig.Figure 1 illustrates this with the addition of a switch 440, which is controlled by the data stored in the SRAM. In this embodiment, the user can write to the SRAM or to the non-volatile area of ​​the cell. The switch 440 can be turned "ON" to connect two wires together (shunt together) by programming the SRAM cell 404 or the PCM area 430. The switch 440 has applications in field-programmable gate arrays (FPGAs) and other types of programmable logic devices, such as programmable logic devices (PLDs) and programmable logic arrays (PLAs). In the FPGA embodiment, it may be desirable to write only to the non-volatile area of ​​the cell.The data stored in PCM area 430 is used to represent the PCM states in the SRAM latch by either turning on the cell or switching the PMOS transistor 140.

[0020] It should already be evident that embodiments of the present invention take advantage of a particular capability of PCM with regard to easy integration with standard CMOS processes. Therefore, PCM material can be added to the circuits in CMOS applications based on latches, such as programmable logic arrays (PLAs), SRAM matrices, field-programmable gate arrays (FPGAs), and crosspoint switches, among others, to provide non-volatile memory functionality. The SRAM cell becomes non-volatile provided that one of the PCM resistors is programmed to the set state and the other PCM resistor is programmed to the reset state.After being switched on, the SRAM cell receives the data contained in the PCM cells, and in some embodiments the SRAM can be read / written in the conventional way.

Claims

[1] Memory cell, comprising: a static read / write memory (SRAM) cell (102) with two pass transistors (120, 122) and four logic transistors (104, 106, 114, 116) connected in two cross-coupled inverters, the SRAM cell being formed by complementary metal oxide semiconductor (CMOS) technology; and a phase-change memory (PCM) area (130) layered on the SRAM cell (102) to provide the SRAM cell with non-volatility, wherein two of the four logic transistors are NMOS transistors (104, 114) each having a source coupled to a first node of a chalcogenic material in the PCM area (130); further comprising a first pass-gate transistor (136) coupling a bit line to the source of the first NMOS transistor (104) and a second pass-gate transistor (138) coupling a complement bit line to the source of the second NMOS transistor (114). [2] Storage cell according to claim 1, wherein a second node of the chalcogenic material is coupled to an earth potential. [3] Memory cell according to claim 1, in which the gates of the first and second pass-gate transistor (136, 138) are activated together to program one of the chalcogenic materials into a SET state and the other into a RESET state. [4] Memory cell according to claim 3, wherein the SRAM cell (102) stores the data contained in the PCM area (130). [5] Memory cell according to claim 1, which is arranged in a non-volatile storage device. [6] Memory cell according to claim 1 for forming a memory for a cross-point switch. [7] Memory cell, comprising: a first and a second pass transistor (120, 122) in a static read / write memory (SRAM) cell (102) which are coupled by bit lines to program two cross-coupled inverters, and first and second pass-gate transistors (136, 138) coupled to the bit lines to program a first phase-change memory (PCM) element (132) into a set state and a second PCM element (134) into a reset state, with the two cross-coupled inverters receiving the data of the first and second PCM elements. [8] Memory cell according to claim 7, wherein the first and second PCM element (132, 134) are coupled to two source nodes of the NMOS transistors (104, 114) in the two cross-coupled inverters with a line to earth potential. [9] Memory cell according to claim 7, further comprising a transistor coupled between a current line and PMOS transistors (106, 116) in the two cross-coupled inverters. [10] Memory cell according to claim 7, which is arranged in a non-volatile storage device. [11] Memory cell according to claim 7 for forming a memory for a cross-point switch. [12] Memory cell, comprising: a first and a second pass transistor (120, 122) in a static read / write memory (SRAM) cell (102) coupled by bit lines to program two cross-coupled inverters; and a first and a second line to program a first phase change memory (PCM) element (132) into a SET state and a second PCM element (134) into a RESET state, wherein the two cross-coupled inverters receive the data of the PCM elements, wherein the first PCM element (132) is coupled to the first line from a source of an NMOS transistor (104) in the two cross-coupled inverters and the second PCM element (134) is coupled to the second line from a source of another NMOS transistor (114) in the two cross-coupled inverters.

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