Methods in the field of pipeline ADC with shared transconductance operational amplifier and with a sample-and-hold amplifier and multiple MDAC stages

Abstract

A method for jointly receiving a differential input signal in a pipeline ADC having a first and a second ADC input terminal, the method comprising: a) providing an operational transconductance amplifier (OTA) having a differential input and a differential output and a first quantizer terminal; b) for each ADC input port: 1) Providing multiple input signal sampling capacitors (C S <0:3>), a first feedback capacitor (Cf), wherein a second lead of the feedback capacitor (Cf) is connected to second lead wires of the input signal sampling capacitors (C S <0:3>); 2) coupling a first lead of the feedback capacitor (Cf) to a first voltage, coupling the second lead of the input signal sampling capacitors (C S<0:3>) with a second common-mode voltage, and coupling first leads of the input signal sampling capacitors (C S <0:3>) to each of the ADC input terminals; 3) Decoupling the first connecting wires of the input signal sampling capacitors (C S <0:3>) from the respective ADC input terminals and decoupling the second connecting wires of the input signal sampling capacitors (C S <0:3>) from the second common mode voltage; 4) Coupling the second leads of the input signal sampling capacitors (C S <0:3>) to a respective one of the differential inputs of the OTA and coupling a respective output of the OTA to the first leads of the input signal sampling capacitors (C S <0:3>) and with an input to a first quantizer; c) locking an output of the first quantizer; and d) for each ADC input port: 1) Coupling the first lead of the first feedback capacitor (Cf) to the output of the OTA, and coupling the first lead of each of the input signal sampling capacitors (C S <0:3>) with a positive or a negative voltage in response to the output latched in the first quantizer.

Description

Background of the invention 1. Field of the invention

[0001] The present invention relates to a method in the field of pipeline ADCs (analog-to-digital converters). 2. General state of the art

[0002] Pipeline ADCs and flash ADCs are well known in the art. A pipeline ADC typically has a sample-and-hold circuit at the analog signal input, which dissipates power and introduces noise into the ADC. The prior art attempts to solve this problem by completely eliminating the sample-and-hold circuit and sampling directly at the first MDAC (multiplying analog-to-digital converter) capacitors. This prior art implementation requires an independent sampling device in parallel with the MDAC for the comparators.

[0003] ADCs that use a shared operational transconductance amplifier (OTA) are also known. In such implementations, a single OTA is shared by multiple multiplication analog-to-digital converters during different phases.

[0004] Manganaro (MANGANARO, G. ; [et al.]: A 1.8V 10b 210MS / s CMOS Pipelined ADC Featuring 86dB SFDR without Calibration. In: 2007 IEEE Custom Integrated Circuits Conference, San Jose, 2007, pp. 317-320. - ISBN: 978-1-4244-0786-6) describes an architecture for a pipelined analog-to-digital converter that achieves particularly low power consumption by sharing amplifiers in multiple stages. He explains, however, that the disadvantages of this pipelined analog-to-digital converter are the additional noise and the reduced feedback factor of the operational amplifier.

[0005] US 2008 / 0068237 A1 also discloses an approach to reducing power consumption in a pipeline ADC and reducing chip size by sharing amplifiers across multiple stages.

[0006] Junmin (JUNMIN, C. ; [et al.]: A Cost-Efficient 12-Bit 20Msamples / s Pipelined ADC. In: 2008 International Conference on Solid-State and Integrated-Circuit Technology, 2008, pp. 1961-1964. - ISBN: 978-1-4244-2185-5) also discloses a pipelined ADC. A special first stage is proposed to eliminate the need for SHA, thus further reducing power and area.

[0007] Devarajan (DEVARAJAN, S. ; [et al.]: A 16-bit, 125 MS / s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC. In: IEEE Journal of Solid-State Circuits, Vol. 44, No. 12, pp. 3305-3313, 2009. - ISSN: 0018-9200) also suggests that SHA should be avoided in order to reduce the power consumption and the size of the pipeline ADC. Short description of the drawings Fig. Figure 1 is a simplified circuit diagram of the 4-phase SHA / MDAC1 / MDAC2. Fig. Figure 2 illustrates the active part of the circuit for phase D, which is defined by the closed switches according to Table 1. Fig. Figure 3 illustrates only the active part of the circuit for phase A, which is defined by the closed switches for phase A. Fig. Figure 4 illustrates only the active part of the circuit for phase B, which is defined by the closed switches for phase B. Fig. Figure 5 illustrates only the active part of the circuit for phase C, which is defined by the closed switches for phase C. Fig. 6 illustrates the clock phases A, B, C and D. Fig. Figure 7 illustrates the typical configuration of a multi-stage pipeline ADC that includes an input sample-and-hold amplifier. Fig. Figure 8 shows the MDAC1 transfer function for an exemplary embodiment of the present invention. Fig. Figure 9 shows the MDAC2 transfer function for an exemplary embodiment of the present invention. Fig. 10A and Fig. 10B illustrate a differential embodiment of the present invention. Fig. 11A and Fig. 11B illustrate another differential embodiment of the present invention. Detailed description of the preferred embodiments

[0008] This invention solves the problem of additional noise and power dissipation of an input sample and hold (SHA) circuit in a pipelined ADC. This text describes a 4-phase shared OTA stage implementing SHA (sample and hold), MDAC1, and MDAC2. Although the additional clock phases come at the expense of speed, this is largely compensated for by the minimal settling time required for SHA. Furthermore, the noise penalty of SHA is eliminated by using a charge-preserving fliparound architecture.

[0009] A simplified circuit diagram of the 4-phase MDAC1 / MDAC2 is shown in Fig.1. In this embodiment, MDAC1 resolves 2 bits plus one bit for error correction, and MDAC2 resolves 1 bit plus one bit for error correction. For the sake of clarity and comprehensibility of the following figures, a single embodiment is shown therein in single-ended form. However, a preferred embodiment is realized as a differential circuit in which the OTA is used as a differential amplifier and the single-ended circuit is essentially repeated in reverse polarity, along with a common-mode transient response circuit. Furthermore, such a differential circuit typically includes a common-mode transient response circuit. Single-ended and differential circuits, as well as common-mode transient response circuits, are well known to those skilled in the art and do not, as such, form part of this invention.

[0010] In Fig.1, the switching configuration represents the input signal tracking phase, which is also the MDAC2 amplification phase. The 4-phase timing of the switch states is shown in Table 1 below. Fig. Figure 1 shows all switches except some reset switches, with switch settings corresponding to phase D in Table 1. Overview of switch states in relation to clock phases Table 1 PHASE A B C D SHA MDAC1 RESET MDAC2 swSAMP1 OUT OF OUT OF A A swSTG1 (p / m) A A OUT OF OUT OF swSER1 (p / m) OUT OF OUT OF OUT OF A swRST OUT OF OUT OF A OUT OF swSHA (p / m) A OUT OF OUT OF OUT OF swMD1 (p / m) OUT OF A OUT OF OUT OF swCOMP (p / m) OUT OF OUT OF A A swFB1 (p / m) OUT OF A OUT OF OUT OF swSAMP2 A A OUT OF OUT OF swSTG2 (p / m) OUT OF OUT OF A A swSER2 (p / m) OUT OF A OUT OF OUT OF swMD2 (p / m) OUT OF OUT OF A A swFB2 (p / m) OUT OF A A A swQ1 A OUT OF OUT OF OUT OF swQ2 OUT OF A OUT OF OUT OF

[0011] To make the switch settings easier to follow, Fig. 2 only the active part of the circuit for phase D, which is defined by the closed switches according to Table 1; Fig. Figure 3 illustrates only the active part of the circuit for phase A, which is defined by the closed switches for phase A; Fig. 4 illustrates only the active part of the circuit for phase B, which is defined by the closed switches for phase B; and Fig. 5 illustrates only the active part of the circuit for phase C, which is defined by the closed switches for phase C. The clock phases are shown in Fig. 6 shown.

[0012] In Phase D ( Fig. 2) the input signal Vin is sampled and stored in the input signal sampling capacitors C S <0:3> on the falling edge of PHI D ( Fig. 6). The capacitor Cf is reset (discharged) when both leads from it are connected to circuit ground. At this time, the two-bit output of MDAC2 controls switch swMD2, and the remainder of MDAC2 is amplified and output to the next stage of the ADC (see Fig. 7). Immediately after the sampling process in phase A ( Fig.3) The sampling capacitors around the OTA are connected to drive the MDAC1 quantizer as shown. This means, in practice, that the output of the OTA settles to a voltage that drives the high-impedance differential input to the OTA to zero, i.e., the output of the OTA settles to the negative value of the voltage across the input signal sampling capacitors C S <0:3>. In this state, the differential input to the OTA is zero (assuming infinite gain), so the negative input to the OTA is also practically at the circuit ground voltage, so that the capacitor Cf remains uncharged and the capacitors C S<0:3> remain charged to the voltage of the sampled input Vin. Consequently, no effective charge transfer occurs, as all capacitors still contain the charge from phase D. Since no charge transfer occurs, no noise is added during this SHA phase. The SHA phase can be relatively short (approximately T / 8) because it sets quickly and particularly precise settling is not required.

[0013] At the end of phase A, the MDAC1 quantizer locks and the capacitors C S <0:3> are connected to the references based on the decision of the quantizer, and the capacitor Cf is connected around the OTA (phase B, Fig.4). This is the MDAC1 amplification phase, where the output of the OTA causes capacitor Cf to drive the effective voltage at the negative input to the OTA to a virtual circuit ground and outputs the residual voltage as the OTA output. It is also the MDAC2 decision phase, where the OTA has charged capacitors Cf2 and capacitors C12<0:1> with the residue of the first stage (MDAC1). During this time, approximately 3T / 8 is available for the MDAC1 output to settle. This corresponds to a 33% higher sampling rate compared to a full settling period T / 2. The capacitors C12<0:1> are referred to as the MDAC2 input capacitors to distinguish them from the input sampling capacitors C S <0:3> to distinguish.

[0014] On the sloping flank of PHI B ( Fig. 6, start of Phase C, Fig.5) the MDAC2 quantizer locks based on the MDAC1 residual output, and the MDAC1 capacitors C S <0:3> are reset during phase C (approximately T / 8). Resetting these capacitors is optional, as they are charged to the input signal Vin during phase D anyway, but it is preferred. The capacitors C S <0:3> are connected to the references based on the decision of the MDAC2 quantizer. The output of the OTA is the residue of MDAC2, which is coupled to the next stage or to a flash ADC, and the system is fed back to track the input signal during phase D, as described above. Fig. Figure 7 illustrates an exemplary 10-bit ADC with error correction in which the present invention is applied. The number of bits resolved in each stage is freely selectable.

[0015] Fig.Figure 8 shows the MDAC1 transfer function for an exemplary embodiment. Table 2 below shows the MDAC1 code and voltage ranges. Input voltage MDAC1 code CS-MDAC1 upper limits MDAC1 residual voltage Subsequent 12-bit output code area V IN < -0,75 100 0 to V REF + 4 to V REF - 2*(V IN + 1,0) 0-511 -0,75 < V IN < -0,25 000 1 to V REF + 3 to V REF - 2*(V IN + 0,5) 512-1535 -0,25 < V IN < -0,25 001 2 to V REF + 2 to V REF - 2*(V IN ) 1536-2559 +0,25 < V IN < +0,75 010 3 to V REF + 1 to V REF - 2*(V IN - 0,5) 2560-3583 +0,75 < V IN 011 4 to V REF + 0 to V REF - 2*(V IN - 1,0) 3584-4095 VREF+=+0.5V VREF−=−0.5V

[0016] Note: The MDAC code is 3 bits because there are 5 subranges. Only half of each outer subrange is used within the full scale range of the ADC. Table 2

[0017] Fig. Figure 9 shows the MDAC2 transfer function for an exemplary embodiment. Table 3 below shows the MDAC1 code and voltage ranges. Input voltage MDAC2 code C 12 -MDAC2 upper limits MDAC2 residual voltage V IN < -0,75 00 0 to V REF + 2 to V REF - 2*(V IN + 0,5) -0,25 < V IN < 0,25 01 1 to V REF + 1 to V REF - 2*(V IN ) +0,25 < V IN 10 2 to V REF + 0 to V REF - 2*(V IN - 0,5) VREF+=+0.5V VREF−=−0.5V

[0018] Note: The MDAC code is 2 bits because there are 3 subranges. Only half of each outer subrange is used within the nominal input range (MDAC output). This allows for over-range sensing to correct for skew and other non-idealities in the analog circuits. Table 3

[0019] Let us now turn to the Fig. 10A and Fig. 10B, where a differential embodiment of the present invention can be seen. Fig. 10A is a repetition of the general figure of Fig. 1, but shows the positive side V IN + of the differential input V IN (V IN + and V IN - ), the OTA as a differential input, the differential output amplifier, the quantizers as differential input quantizers, and also shows the common-mode voltage sources V CM1 , V CM2 and V CM3These common-mode voltages could be the same common-mode voltage, although the use of three different common-mode voltages is preferred because this can achieve some performance improvement. In addition to the differential circuits, Fig. 10A primarily deals with the processing of the positive side of the differential design. Fig. 10B receives the negative side of the differential input V IN - of the differential input V IN + and V IN - . Fig. 10B is connected to the circuit of Fig. 10A connected to the signal out - to receive and the signal SUM - and to receive the switching control outputs of the quantizer and the common switching controls. This figure is also essentially a repetition of Fig.1 for the negative side of the differential input. However, it should be noted that the reference voltage REF + and REF - compared to Fig. 10A polarity is reversed. In Fig. 10B, the various switches and capacitors have the same designations as in Fig. 10A, because adding more identifiers would make the figures confusing, so that they Fig. 10B is merely a repetition of that of Fig. 10A and have the same function and switching sequences as those of the Fig. 1 and Fig. 10A.

[0020] The Fig. 11A and Fig. 11B illustrate an alternative differential embodiment. In these figures, one side of the switch swCOMP is connected to the input signal sampling capacitors C S<0:3> rather than coupled to a common-mode voltage. This affects the required capacitor size, but otherwise does not affect circuit operation. Furthermore, the Fig. 10A and Fig. 10B as well as in the Fig. 11A and Fig. 11B, the input signal sampling capacitors are reset to circuit ground. Alternatively, and most preferably, these capacitors, as well as the feedback capacitors Cf, would be reset to a common-mode voltage, or would be reset by coupling the capacitors of Fig. 10A (11A) with those of Fig. 10B (11B), although resetting is optional and well known in itself.

[0021] The present invention solves the problem of additional noise and power dissipation of an input SHA in a pipelined ADC. While certain preferred embodiments of the present invention have been disclosed and described herein for purposes of illustration and not limitation, it will be apparent to those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims

[1] A method for jointly receiving a differential input signal in a pipeline ADC having a first and a second ADC input terminal, the method comprising: a) providing an operational transconductance amplifier (OTA) having a differential input and a differential output and a first quantizer terminal; b) for each ADC input port: 1) Providing multiple input signal sampling capacitors (C S <0:3>), a first feedback capacitor (Cf), wherein a second lead of the feedback capacitor (Cf) is connected to second lead wires of the input signal sampling capacitors (C S <0:3>); 2) coupling a first lead of the feedback capacitor (Cf) to a first voltage, coupling the second lead of the input signal sampling capacitors (C S<0:3>) with a second common-mode voltage, and coupling first leads of the input signal sampling capacitors (C S <0:3>) to each of the ADC input terminals; 3) Decoupling the first connecting wires of the input signal sampling capacitors (C S <0:3>) from the respective ADC input terminals and decoupling the second connecting wires of the input signal sampling capacitors (C S <0:3>) from the second common mode voltage; 4) Coupling the second leads of the input signal sampling capacitors (C S <0:3>) to a respective one of the differential inputs of the OTA and coupling a respective output of the OTA to the first leads of the input signal sampling capacitors (C S <0:3>) and with an input to a first quantizer; c) locking an output of the first quantizer; and d) for each ADC input port: 1) Coupling the first lead of the first feedback capacitor (Cf) to the output of the OTA, and coupling the first lead of each of the input signal sampling capacitors (C S <0:3>) with a positive or a negative voltage in response to the output latched in the first quantizer. [2] The method of claim 1, wherein the first voltage is a first common mode voltage. [3] The method of claim 1, wherein the first voltage is the voltage across the first leads of the respective input signal sampling capacitors (C S <0:3>). [4] The method of claim 1, further comprising: e) providing a second quantizer having a differential input, and coupling the differential output of the OTA to an input in the second quantizer; f) for each ADC input port: 1) providing a plurality of second quantizer input capacitors (C12<0:1>) and a second feedback capacitor (Cf2), wherein a second lead of the second feedback capacitor (Cf2) is coupled to second leads of the second quantizer input capacitors (C12<0:1>); 2) coupling a respective output of the OTA to the first leads of the respective second quantizer input capacitors (C12<0:1>) and the first lead of the respective feedback capacitor (Cf2), and coupling the second leads of the second quantizer input capacitors (C12<0:1>) to the second common-mode voltage; g) locking the output of the second quantizer; h) for each ADC input port: 1) Coupling the second leads of the respective second feedback capacitor (Cf2) and the respective second quantizer input capacitors (C12<0:1>) to a respective input of the OTA, coupling the first lead of the respective second feedback capacitor (Cf2) to a respective output of the OTA, and coupling the first lead of each of the second quantizer input capacitors (C12<0:1>) to a positive or a negative voltage in response to the output latched in the second quantizer. [5] The method of claim 4, further comprising: i) Providing the output of the OTA as a residue for another stage of the pipeline ADC. [6] The method of claim 4, further comprising: after locking an output of the first quantizer in c), decoupling the first connecting wires of the input signal sampling capacitors (C S<0:3>) from the input to the first quantizer. [7] The method of claim 4, further comprising: after locking the output of the second quantizer in g), decoupling the first connecting wires of the second quantizer input capacitors (C12<0:1>) from the input to the second quantizer. [8] The method of claim 4, wherein the first voltage is a first common mode voltage and the first and second common mode voltages are the same voltage. [9] The method of claim 4, wherein the first voltage is a first common mode voltage and the first and second common mode voltages are different voltages. [10] The method of claim 4, further comprising: Resetting the input signal sampling capacitors (C S <0:3>) and the first feedback capacitor (Cf) during h) 1). [11] The method of claim 4, further comprising: Resetting the input signal sampling capacitors (C S <0:3>) and the first feedback capacitor (Cf) by coupling their first connecting wires to a third common-mode voltage and their second connecting wires to the second common-mode voltage during h) 1). [12] The method of claim 11, wherein the first voltage is a first common mode voltage and the first, second and third common mode voltages are the same voltage. [13] The method of claim 11, wherein the first voltage is a first common mode voltage and the first, second and third common mode voltages are different voltages. [14] The method of claim 1, wherein after d) 1) the output of the OTA is output as a residue to another stage of the pipeline ADC. [15] The method of claim 1, further comprising: after locking an output of the first quantizer in c), decoupling the first connecting wires of the input signal sampling capacitors (C S <0:3>) from the input to the first quantizer.

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