Semiconductor memory element, method for verifying a multi-cycle self-refresh operation of a semiconductor memory element and test system

Abstract

Semiconductor memory element (100), comprising: - a memory cell array (190) with a plurality of memory cells, which are subdivided into first cells and second cells according to associated data retention times, - a tag information register (210) configured to store refresh cycle information for each word line (WLj) connected to the first cells and the second cells, wherein the refresh cycle information includes a line address designated for each word line and information on whether a refresh release signal (REFEN) applied to each word line is released, - a refresh control circuit (300) configured to generate the refresh enable signal (REFEN) and a refresh address (REFADD) based on the refresh cycle information, and - an output (220) configured to transmit the refresh enable signal, the refresh address and data stored in the memory cell array to the outside.

Description

[0001] The invention relates to a semiconductor memory element, a method for verifying a multi-cycle self-refresh operation of a semiconductor memory element and a test system.

[0002] DRAM cells typically store data in capacitors as a configuration of electrical charges, and these electrical charges (data) can be lost due to fault current. Therefore, lost data in the DRAM cells must be restored to prevent permanent data loss; this process is called a refresh operation.

[0003] However, DRAM cells can have different data retention characteristics. This means that some DRAM cells may have shorter data retention times than others. The refresh operation must therefore be performed starting with the DRAM cells exhibiting the shortest data retention times, which requires higher power consumption.

[0004] US 2005 / 0099868A1 discloses a refresh method for dynamic cells with weak retention. It provides methods and circuit configurations for utilizing memory cells with weak retention times. Rows identified as cells with weak retention can be refreshed more frequently than cells with "normal retention." For example, if a normal refresh period is TREF, cells with weak retention can be refreshed every TREF / 2 or TREF / 4 (possibly depending on the actual measured retention time).

[0005] US 2008 / 0239853A1 discloses a semiconductor memory device. The semiconductor memory device includes an instruction decoder, a refresh address counter, an address delivery unit, and an address output selector. The instruction decoder decodes an instruction signal to generate a refresh signal. The refresh address counter generates a refresh address in response to the refresh signal. The address delivery unit delivers either the refresh address or an address from outside the semiconductor memory device to a memory core area. The address output selector outputs the refresh address to the outside of the semiconductor memory device.

[0006] The invention is based on the technical problem of providing a semiconductor memory element, a method for verifying a multi-cycle self-refresh operation of a semiconductor memory element and a test system that enable reliable and easy testing of multi-cycle self-refresh operations in semiconductor memory elements, preferably with reduced energy consumption.

[0007] This problem is solved by the independent claims. Further advantageous embodiments and developments are the subject of the subsequent claims.

[0008] The invention solves this problem by providing a semiconductor memory element with the features of claim 1, a method for verifying a multi-cycle self-refresh operation of a semiconductor memory element with the features of claim 8, and a test system with the features of claim 16.

[0009] Advantageous embodiments of the invention are specified in the dependent claims, the wording of which is hereby incorporated by reference into the content of this description in order to avoid unnecessary repetition.

[0010] According to exemplary embodiments, a semiconductor memory element comprises a memory cell array, a tag information register, a refresh control circuit, and an output. The memory cell array comprises a plurality of memory cells, which are subdivided into first cells and second cells according to their associated data hold times. The tag information register stores refresh cycle information for each word line connected to the first and second cells, wherein the refresh cycle information includes a line address designated for each word line and information about whether a refresh enable signal applied to each word line is enabled. The refresh control circuit is configured to generate the refresh enable signal and a refresh address based on the refresh cycle information.The output is designed to transmit the refresh enable signal, the refresh address, and data stored in the memory cell array to the outside.

[0011] In various embodiments, the data retention time of a respective first cell is shorter than the data retention time of a respective second cell.

[0012] In various embodiments, the refresh enable signal applied to a given word line has a logic level that depends on whether the word line is connected to a line containing at least one first cell. The refresh enable signal can be applied twice consecutively to word lines connected to lines containing at least one first cell, and the refresh enable signal can be applied once to a line containing two cells and no first cells.

[0013] In various embodiments, a cycle of a self-refresh operation, which is performed for the memory cell field based on the refresh address, can be individually set for each word line.

[0014] In various embodiments, the refresh control circuit can include: a resonant circuit (oscillator) that generates a pulse signal depending on a refresh command, an address counter that generates the refresh address synchronously with the pulse signal, and a refresh enable signal generator that generates the refresh enable signal, which is selectively enabled according to an associated word line based on the refresh cycle information.

[0015] In various embodiments, the refresh cycle information can be transmitted externally via the output.

[0016] According to exemplary embodiments, a method for verifying a multi-cycle self-refresh operation of a semiconductor memory element comprising a memory cell array is provided. The method comprises: storing initial self-refresh performance information relating to each word line of a plurality of word lines connected to the memory cell array in a first register of a tester via a DQ pin, wherein the initial self-refresh performance information is associated with an initial self-refresh operation performed for memory cells in the memory cell array according to refresh cycle information for each word line stored in a tag information register, wherein the refresh cycle information includes a line address designated for each word line and information on whether a refresh enable signal applied to each word line,is released, storing second self-refresh performance information regarding a respective word line in a second register in the tester via the DQ pin, wherein the second self-refresh performance information is associated with a second self-refresh operation performed for the memory cells according to the refresh cycle information, and determining whether a multi-cycle self-refresh operation is performed for the memory cells based on the refresh cycle information, the first self-refresh performance information, and the second self-refresh performance information.

[0017] In various embodiments, determining whether the multi-cycle self-refresh operation is performed may involve storing identification information in a third register of the tester by performing an AND operation on the first self-refresh performance information stored in the first register and the second self-refresh performance information stored in the second register, and determining whether the identification information stored in the third register is identical to the refresh cycle information. Determining whether the identification information stored in the third register is identical to the refresh cycle information may involve performing an exclusive NOR operation on the identification information and the refresh cycle information.

[0018] In various embodiments, the first self-refresh performance information can include whether the refresh enable signal applied to each word line is enabled, and a line address that identifies each word line assigned to the first self-refresh operation. The second self-refresh performance information can include whether the refresh enable signal applied to each word line is enabled, and a line address that identifies each word line assigned to the second self-refresh operation.

[0019] In various embodiments, the refresh release signal can be applied to word lines connected to at least one first cell with a data hold time shorter than that of any second cell while the first self-refresh operation is being performed. The refresh release signal can also be applied to any word line, regardless of whether at least one first cell is connected, while the second self-refresh operation is being performed.

[0020] In various embodiments, a cycle of self-refresh operation, which is performed for memory cells based on the refresh address, can be individually set for each word line.

[0021] According to exemplary embodiments, a test system comprises a test board and a tester. The test board includes a socket on which a semiconductor memory element under test is mounted. The semiconductor memory element performs a multi-cycle self-refresh operation using refresh cycle information for each row address stored in a tag information register. The refresh cycle information includes a row address designated for each word line and information on whether a refresh enable signal applied to each word line has been enabled. The tester is configured to verify the multi-cycle self-refresh operation performed in the semiconductor memory element based on a refresh address, the refresh enable signal corresponding to the refresh address, and the refresh cycle information.The refresh address and refresh enable signal are output when a refresh operation is performed in the semiconductor memory element.

[0022] In various embodiments, the tester can include a first, a second, a third, and a fourth register. The first register can store initial self-refresh power information associated with a first self-refresh operation performed on memory cells in the semiconductor memory element. The second register can store second self-refresh power information associated with a second self-refresh operation performed on the memory cells. The third register can store the result of an AND operation performed on the first and second self-refresh power information. The fourth register can store the refresh cycle information for each row address.

[0023] The tester may further include an exclusive NOR gate (NOR gate) that performs an exclusive NOR operation with the result of the AND operation stored in the third register and the refresh cycle information stored in the fourth register.

[0024] In various embodiments, the refresh address and information on whether the refresh enable signal is enabled can be transmitted to the tester via a DQ pin of the semiconductor memory element.

[0025] Accordingly, exemplary embodiments provide a simple testing of multi-cycle self-refresh operations in semiconductor memory elements, with reduced energy consumption.

[0026] Advantageous embodiments of the invention, as described in detail below, are illustrated in the drawings, in which: Fig. Figure 1 shows a block diagram representing a semiconductor memory element according to exemplary embodiments. Fig. Figure 2 shows a block diagram illustrating an example of the refresh control circuit of Fig. 1 represents exemplary embodiments. Fig. Figure 3 shows a block diagram illustrating the refresh enable signal generator of Fig. 2 according to exemplary embodiments. Fig. Figure 4 shows a flowchart illustrating a method for storing refresh cycle information in the day information register according to exemplary embodiments. Fig. 5, which are listed in the day information register of Fig. 1 represents stored refresh cycle information according to exemplary embodiments. Fig. Figure 6 shows a block diagram illustrating the multicycle self-refresh operation in the semiconductor memory element of Fig. 1 is verified according to exemplary embodiments. Fig. Figure 7 shows a block diagram representing a test system according to exemplary embodiments. Fig. Figure 8 shows a circuit diagram that is an example of the logic circuit of Fig. 7 represents exemplary embodiments. Fig. Figure 9 shows a flowchart illustrating a method for verifying a multi-cycle self-refreshment operation according to exemplary embodiments. Fig. 10 shows a flowchart that details the step for determining the multi-cycle self-refreshment operation of Fig. 9 represents exemplary embodiments. Fig. 11A the first self-refresher performance information, which is in the first register of Fig. 8 are stored, according to exemplary embodiments. Fig. 11B the second self-refresher performance information, which is in the second register of Fig. 8 are stored, according to exemplary embodiments. Fig. 11C the identification information contained in the third register of Fig. 8 are stored, according to exemplary embodiments. Fig. 11D the refresher cycle information, which is in the fourth register of Fig. 8 are stored, according to exemplary embodiments.

[0027] It is understood that when an element is described as "connected" or "coupled" with another element, it may be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is described as "directly connected" or "directly coupled" with another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in the same way (e.g., "between" and "directly between," "next to" and "directly beside," etc.).

[0028] Fig. Figure 1 shows a block diagram representing a semiconductor memory element according to exemplary embodiments.

[0029] With reference to Fig. 1 comprises a semiconductor memory element 100, an instruction decoder 110, a mode set register (MSR) 120, an address register 130, a selection circuit 140, a data input / output circuit (DATA I / O) 150, a line decoder 160, a read / write circuit (S / A and W / D) 180, a memory cell array 190, a tag information register (TIR) ​​210 and a refresh control circuit 300.

[0030] The command decoder 110 receives a CMD command sent externally via a command pin 240. The command decoder 110 decodes the CMD command, generating a refresh command REF, a write command WR, a read command RD, and a mode register setting command MRS. The command decoder 110 also provides the refresh command REF, the write command WR, the read command RD, and the mode register setting command MRS to associated circuit blocks. For example, the command decoder 110 can provide the refresh command REF to the refresh control circuit 300, the selection circuit 140, and the data input / output circuit 150.

[0031] The mode setting register (MSR) 120 determines an operating mode of the semiconductor memory element 100 based on an external address ADD received via an address pin 230 and the mode register setting instruction MRS received by the instruction decoder 110. Typically, the semiconductor memory element 100 sequentially enters a mode register setting mode and an extended mode register setting mode (EMRS) while operations are being performed. The EMRS mode includes a hold verification mode, allowing the hold characteristics of memory cells to be tested in EMRS mode.

[0032] The TIR 210 can store refresh cycle information (or tag information, TI) for each memory cell contained in memory cell array 190, and each refresh cycle can be determined based on the hold characteristics of each memory cell tested in hold verification mode. The refresh cycle information stored in the TIR 210 can be used to control the self-refresh cycle of each word line connected to memory cell array 190 while a refresh operation is being performed on memory cell array 190. Additionally, refresh cycle information stored in the TIR 210 can be externally transmitted via an output pin, for example, designated as DQ pin 220.The refresh cycle information stored in the TIR 210 may also include a line address (refresh address) designated for each word line, and information on whether a refresh enable signal REFEN, applied to each word line, has been enabled.

[0033] The refresh control circuit 300 generates a refresh address REFADD and the refresh enable signal REFEN based on the refresh command REF and the tag information TI relating to the refresh cycle information. The refresh address REFADD is provided to the selector circuit 140, and the refresh enable signal REFEN is provided to the line decoder 160.

[0034] The address register 130 temporarily stores the external address ADD received via address pin 230 and provides a row address RADD of the external address ADD to the row decoder 160 and a column address CADD of the external address ADD to the column decoder 170.

[0035] The selection circuit 140 selects the refresh address REFADD or the line address RADD as the selected line address XADD, which is provided to the line decoder 160 depending on the refresh command REF. For example, the selection circuit 140 can select the refresh address REFADD as the selected line address XADD if the refresh command REF has a first logic level indicating a self-refresh operation, and the selection circuit 140 can select the line address RADD as the selected line address XADD if the refresh command REF has a second logic level indicating a write or read operation.

[0036] The data input / output circuit 150 supplies the read / write circuit 180 with data to be written to the memory cell array 190, or receives data from the read / write circuit 180 that has been read from the memory cell array 190, depending on the refresh command REF. Furthermore, the data input / output circuit 150 outputs the tag information TI, the refresh address REFADD, and information about whether a refresh enable signal REFEN is enabled, via the DQ pin 220, depending on the refresh command REF.

[0037] The line decoder 120 sequentially selects the word lines WLj depending on the refresh address REFADD from the selection circuit 140 in a self-refresh mode. Whether the selected word line is enabled is determined by the refresh control circuit 300 based on the refresh enable signal REFEN, while the word lines WLj are selected sequentially.

[0038] The column decoder 170 decodes the column address CADD from the address register 130 in order to select at least one of the bit lines BLi (or columns) depending on the decoded column address CADD.

[0039] The memory cell array 190 comprises a plurality of memory cells (not shown) connected by a plurality of bit lines BLi, where i is a natural number greater than two, and a plurality of word lines WLj, where j is a natural number greater than two. The memory cells can be divided into two groups, identified as first cells and second cells, respectively, according to the data retention characteristics (or data retention times) of each memory cell. The first cells are suitable for storing data without requiring refreshing at a time interval shorter than a reference interval. The second cells are suitable for storing data without requiring refreshing at a time interval longer than a reference interval.This means that, using the reference interval, the first cells cannot pass a data retention test, while the second cells can, because each of the first cells has a shorter data retention period. Therefore, the first cells need to be refreshed more frequently than the second cells because they retain data for a shorter time without data loss. Consequently, the first refresh cycle for the first cells is shorter than the second refresh cycle for the second cells. For example, the first cells can be refreshed twice as often as the second cells.

[0040] Although not shown, the memory cell array 190 can contain multiple memory banks. Each memory bank can be subdivided into memory blocks, and each memory block can be subdivided into multiple memory pages.

[0041] The read / write circuit 180 writes data to the memory cell array 190 or reads data from the memory cell array 190.

[0042] Fig. Figure 2 shows a block diagram illustrating an example of a refresh control circuit. Fig. 1 represents exemplary embodiments.

[0043] With reference to Fig. The refresh control circuit 300 comprises a resonant circuit (oscillator OSC) 310, an address counter 320, and a refresh enable signal generator (REFEN generator) 330. The resonant circuit 310 generates a pulse signal PLS with a regular period (cycle) depending on a refresh instruction REF. The address counter 320 generates the refresh address REFADD for designating line addresses to be refreshed and provides the refresh address REFADD depending on the refresh instruction REF of the selection circuit 140. The address counter 320 can terminate the counting operation depending on a self-refresh abort signal from the instruction decoder 110. The address counter 320 operates synchronously with the pulse signal PLS. The address counter 320 generates the refresh address REFADD sequentially by counting from a starting refresh address. The counting operation can be an upward counting operation or a downward counting operation.When the refresh address REFADD reaches an end refresh address REFM, the address counter 320 is initialized so that it counts from the start refresh address.

[0044] The refresh enable signal generator 330 operates in synchronization with the pulse signal PLS and generates the refresh enable signal REFEN, which, based on the refresh command REF, the tag information TI, and the end refresh address REFM, determines whether the word line designated by the refresh address REFADD is enabled. In other words, the refresh enable signal generator 330 generates the refresh enable signal REFEN, which determines whether the word line designated by the refresh address REFADD is enabled.

[0045] Fig. Figure 3 shows a block diagram illustrating the refresh enable signal generator of Fig. 2 according to exemplary embodiments.

[0046] With reference to Fig. The refresh enable signal generator 330 comprises a counter 331 and a refresh enable signal generator unit 333 (REFEN generator unit). The counter 331 counts the end refresh address REFM from the address counter 320 and outputs a counter output signal COUT. For example, when the refresh operation starts, the counter output signal COUT can be "0", and when the refresh address REFADD arrives at the end refresh address REFM, the counter output signal COUT can be "1". The refresh enable signal generator unit 333 generates the refresh enable signal REFEN based on the tag information TI and the refresh address REFADD, and by changing the operating mode as soon as the value of the counter output signal COUT changes.

[0047] For example, while a first self-refresh operation is being performed on a memory cell and the counter output signal COUT has a value of "0", the refresh release signal generator unit 333 can generate the refresh release signal REFEN based on the refresh address REFADD and the tag information TI. This signal is selectively released according to the refresh cycle information contained in the tag information TI. Furthermore, for example, while a second self-refresh operation is being performed on the memory cell and the counter output signal COUT has a value of "1", the refresh release signal generator unit 333 can generate the refresh release signal REFEN based on the refresh address REFADD and the tag information TI. This signal is released regardless of the refresh cycle information.Specifically, while the first self-refresh operation is being performed on the memory cell, the refresh enable signal REFEN, which is enabled, is applied to the word lines connected to the first cells of memory cell array 190, and the refresh enable signal REFEN, which is not enabled, is applied to the word lines connected to the second cells of memory cell array 190. That is, while the first self-refresh operation is being performed on the memory cell, the refresh operation is performed on rows that contain at least one first cell. Furthermore, while the first self-refresh operation is being performed on the memory cell, the refresh operation is performed sequentially on all rows, regardless of whether the row contains at least one first cell.Therefore, the first self-refresh operation and the second self-refresh operation are performed sequentially on the row that contains at least one first cell, and the second self-refresh operation is performed on the memory cell that does not contain a first cell.

[0048] Fig. Figure 4 shows a flowchart illustrating a method for storing refresh cycle information in the day information register according to exemplary embodiments.

[0049] With reference to the Fig. 1 and Fig. 4. The semiconductor memory element 100 enters hold verification mode in EMRS mode via the mode setting register 120 (S210). Data retention characteristics of the memory cells are tested in hold verification mode (S220). The memory cells are divided into first cells and second cells according to their data retention characteristics. The refresh cycle information for each row address (word line) is set according to the data retention characteristics of the memory cells (S230). For example, the first refresh cycle for row addresses (word lines) containing at least one first cell is set to be shorter than the second refresh cycle for row addresses (word lines) containing no first cell. The refresh cycle information for each row address (word line) is stored in TIR 210 (S240).The self-refresh operation is performed individually for the row addresses at memory cell field 190 according to the associated refresh cycle information stored in TIR 210 (S250).

[0050] Fig. 5 represents the information in the day information register of Fig. 1. Stored refresh cycle information according to exemplary embodiments.

[0051] With reference to Fig. 5. The TIR 210 stores the refresh cycle information for each of the line addresses (word lines) based on the data retention characteristics of the associated memory cells. The refresh cycle information stored in the TIR 210 can be transmitted externally via a DQ pin 220 to verify the self-refresh operation. Fig. In Section 5, a semiconductor memory element with a 4 Gb storage capacity is considered as an example. If each memory block contains 8 K word lines, the number of required address pins is thirteen (A0 to A12). The refresh cycle information 211 stored in the TIR 210 is output via the DQ pin 220, and thus the refresh cycle information 211 contains sixteen bits assigned to the DQ pins DQ0 to DQ15. The refresh cycle information 211 can be divided into a first part 212 and a second part 213. The first part 212 of the refresh cycle information 211 indicates whether the refresh enable signal REFEN is enabled, and the second part 213 of the refresh cycle information 211 specifies the line address that designates each word line.For example, a refresh cycle for a word line that includes at least one first cell can be set to a first refresh cycle (for example, 64 ms), and a refresh cycle for a word line that does not include a first cell can be set to a second refresh cycle (for example, 128 ms). If in . Fig. 5 If the first part 212 of the refresh cycle information 211 has a value of “1”, the refresh cycle for the associated line address (word line) is the first refresh cycle (for example, 64 ms), and if the first part 212 of the refresh cycle information 211 has a value of “0”, the refresh cycle for the associated line address (word line) is the second refresh cycle (for example, 128 ms).

[0052] Fig. Figure 6 shows a block diagram illustrating the multicycle self-refresh operation in the semiconductor memory element of Fig. 1 is verified according to exemplary embodiments.

[0053] Multi-cycle self-refresh operation offers advantages in reducing power consumption in standby mode by varying the self-refresh cycles of the first cells with a shorter data retention time and the second cells with a longer data retention time. However, with conventional semiconductor memory elements, it is usually not possible to verify whether the multi-cycle self-refresh operation has been performed.

[0054] With reference to the Fig. 5 and Fig. 6. The refresh enable signal REFEN and the refresh address XADD can be transmitted externally as refresh power information via data input / output circuit 150 and DQ pin 220. When the refresh enable signal REFEN and the refresh address XADD are transmitted externally as refresh power information via data input / output circuit 150 and DQ pin 220, sixteen DQ pins can be used. The most significant bit (MSB), i.e., a first part 222 of the refresh cycle information 211, indicates whether the refresh enable signal REFEN is enabled, and a second part 223 of the refresh cycle information 211 specifies a line address that designates an associated word line.For example, if the self-refresh operation is performed with the first refresh cycle of 64 ms, the first part 222 with a value of "0" indicates that the self-refresh operation is not performed on the corresponding line designated by the second part 223. Furthermore, the first part 222 with a value of "1" indicates that the self-refresh operation is performed on the corresponding line designated by the second part 223. Additionally, the refresh cycle information 211 stored in the TIR 210 can also be transmitted externally via the data input / output circuit 150 and the DQ pin 220.

[0055] Fig. Figure 7 shows a block diagram representing a test system according to exemplary embodiments.

[0056] Testing a semiconductor memory chip is the final process to determine whether the semiconductor memory chip has passed (i.e., exhibits the desired quality). With reference to Fig. 7 includes a test system 500, a test board 510 and a tester 520.

[0057] The 510 test board includes a 511 socket on which the semiconductor memory element under test is mounted, a clock pin CLK for transmitting a clock signal, address pins Ai (where i is an integer between 0 and n) for transmitting address signals, a control pin CONTROL for transmitting control signals such as RAS, CAS, WE, CKE, CS, DQM and DQS, data input / output pins DQ0, DQ1, ... and a reference voltage pin (not shown).

[0058] The semiconductor memory element 100 is placed on socket 511 in test board 510. The semiconductor memory element 100 can be, for example, an x16 memory chip or an x32 memory chip. The semiconductor memory element 100 can include a clock pin, address pins, a control pin, and data input / output pins, although these are not shown. Each of the pins of the semiconductor memory element 100 is connected to a corresponding pin of test board 510.

[0059] The tester 520 comprises a test pattern generator (TPG) 530, a comparator (COM) 540, and a logic circuit 600. The test pattern generator 530 generates test pattern data. The comparator 540 compares data transmitted by the semiconductor memory element 100 with reference data. The tester 520 may also include driver pins (not shown) connected to the test pattern generator 530 and / or to comparator 540 and comparison pins (not shown). The test board 510 is connected to the tester 520 via multiple channels CH. The logic circuit 600 verifies multicycle self-refresh operations of the semiconductor memory element 100.

[0060] The tester 520 sends the test pattern data generated by the test pattern generator 530 to the semiconductor memory element 100 via driver pins and receives output data from the semiconductor memory element 100 depending on the applied test pattern data. The tester 520 determines whether the semiconductor memory element 100 has passed the test by measuring the output data in the comparator 540.

[0061] Fig. Figure 8 shows a circuit diagram that is an example of the 600 logic circuit from Fig. 7 represents exemplary embodiments. Fig. Figure 9 shows a flowchart illustrating a method for verifying a multi-cycle self-refreshment operation according to exemplary embodiments.

[0062] With reference to Fig. The illustrated logic circuit 600 comprises a first register 610, a second register 620, an AND gate 630, a third register 640, a fourth register 650 and an exclusive NOR gate 660.

[0063] With reference to the Fig. 1, Fig. 2, Fig. 3, Fig. 8 and Fig. 9. The refresh control circuit 300 performs a first self-refresh operation on the memory cell array 190, using the refresh cycle information (or tag information TI) stored in the TIR 210, and stores in the first register 610 via the DQ pin 220 the first self-refresh performance information CYCLE1 of each word line assigned to the first self-refresh operation (S310 of Fig. 9) The first self-refresher performance information is in Fig. 8, designated CYCLE1, and the first self-refresh performance information may include line addresses (refresh addresses) that designate associated word lines, and information about whether the refresh enable signal REFEN, which is applied to the associated word line, is enabled.

[0064] The refresh control circuit 300 performs a second self-refresh operation on the memory cell array 190, accessing the refresh cycle information (or tag information TI) stored in the TIR 210, and stores second self-refresh power information CYCLE2 of each word line associated with the second self-refresh operation (S320) in the second register 620 via the DQ pin 220. The second self-refresh power information is in Fig. The second self-refresh operation, designated CYCLE2, can include row addresses (refresh addresses) that designate associated word lines and information about whether the refresh enable signal REFEN, applied to the associated word line, is enabled. The first and second self-refresh operations can be performed with equal cycles. The first self-refresh operation is performed on rows that have at least one first cell with a shorter data hold time than the second cell, and the second self-refresh operation is performed on every row, regardless of whether at least one first cell is present. Therefore, a row that does not contain a first cell has a longer (e.g., twice as long) refresh cycle than a row that does contain at least one first cell.Whether a multi-cycle self-refresh operation is performed on the memory cells of memory cell field 190 is determined based on the day information TI, the first self-refresh performance information CYCLE1 and the second self-refresh performance information CYCLE2.

[0065] Fig. Figure 10 shows a flowchart that details the step for determining the multicycle self-refreshment operation of Fig. 9 represents exemplary embodiments.

[0066] With reference to Fig. To determine whether the multicycle self-refresh operation is performed on the memory cells of the memory cell array 190, a logical AND operation is performed using the AND gate 630 on the first self-refresh performance information CYCLE1 stored in the first register 610 and the second self-refresh performance information CYCLE2 stored in the second register 620. The result of the AND operation is stored in the third register 640 as identification information (S311). Therefore, whether the first self-refresh performance information CYCLE1 is identical to the second self-refresh performance information CYCLE2 is determined based on the identification information stored in the third register 640 (S312).

[0067] A logical exclusive NOR operation is performed on the identification information stored in the third register 640 and the refresh cycle information TI stored in the fourth register 650 using the exclusive NOR gate 660, and a decision signal DS is provided indicating whether the multi-cycle self-refresh operation is performed on the memory cells of the memory cell array 190. For example, the decision signal DS can have a high logical level if the identification information stored for a row in the third register 640 is identical to the refresh cycle information TI stored in the fourth register 650 for a corresponding row.Furthermore, the decision signal DS may have a low logical level if the identification information stored for a row in the third register 640 is not identical to the refresh cycle information TI stored in the fourth register 650 for a corresponding row.

[0068] It is understood that various illustrative examples may include verification of multi-cycle self-refresher operations performed with three or more different refresher cycles, without deviating from the framework of the teaching described herein.

[0069] The Fig. 11A to 11D each show data that is stored in registers of Fig. 8 are stored, according to exemplary embodiments.

[0070] With reference to the Fig. For example, in sections 2 and 7 to 11D, the resonant circuit 310 generates the pulse signal PLS with a cycle time of 64 ms, which is provided to the address counter 320 and the refresh enable signal generator 330 depending on the refresh instruction REF. The address counter 320 outputs the refresh address REFADD on each rising edge of the pulse signal PLS, and the refresh enable signal generator 330 generates the refresh enable signal REFEN on a rising edge of the pulse signal PLS based on the refresh address REFADD and the refresh cycle information TI.

[0071] If the first and second self-refresh operations are performed sequentially, a check is performed to ensure that the refresh operation is carried out on every row. This is because the refresh operation must be performed more frequently on rows containing at least one first cell with a data hold time shorter than the data hold time of the second cell than on rows that do not contain at least one first cell. Therefore, the first self-refresh operation is performed only on rows containing at least one first cell, and the second self-refresh operation is performed on every row. Accordingly, rows containing at least one first cell might have a refresh cycle of, for example, 64 ms, and rows that do not contain at least one first cell might have a refresh cycle of, for example, 128 ms.

[0072] Fig. 11A provides the first self-refresher performance information, which is found in the first register of Fig. 8 are stored, according to exemplary embodiments.

[0073] With reference to Fig. In tester 520, the first self-refresh performance information CYCLE1 is stored in the first register 610 when the semiconductor memory element 100 outputs the line address XADD and the logic level of the refresh enable signal REFEN, generated in the first self-refresh operation, via the DQ pin 220. A most significant bit, DQ0, represents the logic level of the refresh enable signal REFEN (whether the refresh operation is performed on the associated word line), and other bits represent the line address of the associated word line. In the illustrated example, a most significant bit, DQ0, with a value of "0" indicates that the first self-refresh operation is not performed on the associated word line, and a most significant bit, DQ0, with a value of "1" indicates that the first self-refresh operation is performed on the associated word line.

[0074] For example, the most significant bit DQ0 of a second row has a value of "1", indicating that the first self-refresh operation is performed on the associated word line, and the most significant bit DQ0 for the first and third rows has a value of "0", indicating that the first self-refresh operation is not performed on the associated word line. This means that it is determined that the second row contains at least one first cell.

[0075] Fig. 11B represents the second self-refresher performance information, which is found in the second register of Fig. 8 are stored, according to exemplary embodiments.

[0076] With reference to Fig. 11B The tester 520 stores the second self-refresh performance information CYCLE2 in the second register 620 when the semiconductor memory element 100 outputs the line address XADD and the logic level of the refresh enable signal REFEN, generated in the second self-refresh operation, via the DQ pin 220. The most significant bit DQ0, with a value of "1" for all lines, indicates that the second self-refresh operation is performed on each word line, and not the first self-refresh operation.

[0077] Fig. 11C provides the identification information contained in the third register of Fig. 8 are stored, according to exemplary embodiments.

[0078] The identification information stored in the third register 640 corresponds to the result of the AND operation performed on the self-refresh performance information CYCLE1 stored in the first register 610 and the self-refresh performance information CYCLE2 stored in the second register 620. A most significant bit DQ0 of the identification information for the second row has a value of "1", and a most significant bit DQ0 of the identification information for the first and third rows has a value of "0", as shown in Fig. Figure 11C illustrates this. Accordingly, in the illustrated example, the first self-refresh operation with a cycle of 64 ms is performed on the second row, and the second self-refresh operation with a cycle of 128 ms is performed on the first and third rows.

[0079] Fig. 11D represents the refresher cycle information, which is stored in the fourth register of Fig. 8 are stored, according to exemplary embodiments.

[0080] The refresh cycle information (TI) stored in the fourth register 630 is identical to the refresh cycle information (TI) stored in TIR 210. As in Fig. As shown in Figure 11D, for example, a most significant bit DQ0 of the refresh cycle information TI for the first and third rows has a value of "1", indicating a self-refresh cycle of 128 ms, and a most significant bit DQ0 of the refresh cycle information TI for the second row has a value of "0", indicating a self-refresh cycle of 64 ms.

[0081] The decision signal DS exhibits a high logical level when the identification information stored in the third register 640 is identical to the refresh cycle information TI stored in the fourth register 650. When the decision signal DS exhibits a high logical level, it is confirmed that the multi-cycle self-refresh operation is performed on memory cell array 190 according to the refresh cycle information for the row addresses stored in TIR 210.

[0082] It is understood that various illustrative examples may include verification of a multi-cycle self-refreshment operation performed with three or more different refresher cycles, without deviating from the framework of the teaching described herein.

[0083] As described above, the semiconductor memory element that performs the multicycle self-refresh operation is configured to output the refresh cycle information stored in the tag information register, as well as information about whether the refresh enable signal has been enabled according to the refresh address, via the DQ pin. Furthermore, based on the refresh address and the refresh enable signal, it is externally verified whether the multicycle self-refresh operation is being performed. The exemplary embodiments can be applied in various memory and test areas.

Claims

[1] Semiconductor memory element (100), comprising: - a memory cell array (190) with a plurality of memory cells, which are subdivided into first cells and second cells according to associated data retention times, - a tag information register (210) configured to store refresh cycle information for each word line (WLj) connected to the first cells and the second cells, wherein the refresh cycle information includes a line address designated for each word line and information on whether a refresh release signal (REFEN) applied to each word line is released, - a refresh control circuit (300) configured to generate the refresh enable signal (REFEN) and a refresh address (REFADD) based on the refresh cycle information, and - an output (220) configured to transmit the refresh enable signal, the refresh address and data stored in the memory cell array to the outside. [2] Semiconductor memory element according to claim 1, wherein the data retention time of a respective first cell is shorter than the data retention time of a respective second cell. [3] Semiconductor memory element according to claim 1 or 2, wherein the refresh enable signal applied to a respective word line has a logic level that depends on whether the word line is connected to a line comprising at least one first cell. [4] Semiconductor memory element according to claim 3, wherein the refresh enable signal is applied twice successively to word lines connected to lines comprising at least one first cell, and the refresh enable signal is applied once to a line comprising second cells and no first cells. [5] Semiconductor memory element according to any one of claims 1 to 4, wherein a cycle of a self-refresh operation, which is performed for the memory cell field based on the refresh address, is individually set for each word line. [6] Semiconductor memory element according to any one of claims 1 to 5, wherein the refresh control circuit comprises: - a resonant circuit (310) that generates a pulse signal (PLS) depending on a refresh command, - an address counter (320) that generates the refresh address synchronously with the pulse signal, and - a refresh release signal generator (330) that generates the refresh release signal which is selectively released according to an associated word line based on the refresh cycle information. [7] Semiconductor memory element according to any one of claims 1 to 6, wherein the refresh cycle information is transmitted to the outside via the output. [8] Method for verifying a multi-cycle self-refresh operation of a semiconductor memory element (100) according to any one of claims 1 to 7, comprising a memory cell array (190), wherein the method comprises: - Storing initial self-refresh performance information relating to a given word line of a plurality of word lines connected to the memory cell array in a first register (610) of a tester (520) via a DQ pin, wherein the initial self-refresh performance information is associated with an initial self-refresh operation performed for memory cells in the memory cell array according to refresh cycle information for each word line stored in a tag information register (210), wherein the refresh cycle information includes a line address designated for each word line and information on whether the refresh enable signal (REFEN) applied to each word line is enabled. - Storing second self-refresh performance information relating to a respective word line in a second register (620) in the tester via the DQ pin, wherein the second self-refresh performance information is associated with a second self-refresh operation performed for the memory cells according to the refresh cycle information, and - Determine whether a multi-cycle self-refresh operation is performed for the memory cells based on the refresh cycle information, the first self-refresh performance information, and the second self-refresh performance information. [9] Method according to claim 8, wherein determining whether the multicycle self-refresher operation is performed comprises: - Storing identification information in a third register (640) of the tester by performing an AND operation with the first self-refresh performance information stored in the first register and the second self-refresh performance information stored in the second register, and - Determine whether the identification information stored in the third register is identical to the refresh cycle information. [10] Method according to claim 9, wherein determining whether the identification information stored in the third register is identical to the refresh cycle information comprises performing an exclusive NOR operation on the identification information and the refresh cycle information. [11] Method according to any one of claims 8 to 10, wherein the first self-refresh performance information includes whether the refresh release signal applied to each word line is released and includes a line address that determines each word line that is assigned to the first self-refresh operation. [12] Method according to claim 11, wherein the second self-refresh performance information includes whether the refresh enable signal applied to each word line is enabled and includes a line address that determines each word line that is assigned to the second self-refresh operation. [13] Method according to claim 12, wherein the refresh release signal is applied to word lines connected to at least one first cell having a data hold time that is less than the data hold time of second cells while the first self-refresh operation is performed. [14] Method according to claim 13, wherein the refresh release signal is applied to each word line regardless of whether at least one first cell is connected while the second self-refresh operation is performed. [15] Method according to any one of claims 8 to 14, wherein a cycle of the self-refresh operation, which is performed for memory cells based on the refresh address, is individually set for each word line. [16] Test system (500), comprising: - a test board (510) comprising a socket (511) on which a semiconductor memory element (100) to be tested according to any one of claims 1 to 7 is arranged, wherein the semiconductor memory element performs a multi-cycle self-refresh operation using refresh cycle information for each line address stored in a tag information register (210), wherein the refresh cycle information includes a line address designated for each word line and information on whether the refresh enable signal (REFEN) applied to each word line is enabled, and - a tester (520) trained to verify the multi-cycle self-refresh operation performed in the semiconductor memory element based on the refresh address (REFADD), the refresh enable signal (REFEN) according to the refresh address and the refresh cycle information, wherein the refresh address and refresh enable signal are output when a refresh operation is performed in the semiconductor memory element. [17] Test system according to claim 16, wherein the tester comprises: - a first register (610) that stores first self-refresh power information associated with a first self-refresh operation performed for memory cells in the semiconductor memory element, - a second register (620) that stores second self-refresh performance information associated with a second self-refresh operation performed for the memory cells, - a third register (640) that stores the result of an AND operation performed on the first self-refresh performance information and the second self-refresh performance information, and - a fourth register (650) that stores the refresh cycle information for each line address. [18] Test system according to claim 17, wherein the tester further comprises: - an exclusive NOR gate (660) that performs an exclusive NOR operation with the result of the AND operation stored in the third register and the refresh cycle information stored in the fourth register. [19] Test system according to one of claims 16 to 18, wherein the refresh address and the information on whether the refresh enable signal is enabled are transmitted to the tester via a DQ pin (220) of the semiconductor memory element. [20] Test system according to one of claims 16 to 19, wherein the semiconductor memory element comprises a plurality of memory cells which are divided into first memory cells and second memory cells according to associated data retention times.

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