Data bus participants and methods for synchronizing data bus participants

Abstract

Data bus participant (1) with a data bus interface which - a downstream data bus input (2) for receiving data from a higher-level data bus participant and - has a clock generator (6) for generating an internal clock signal (CLK) for the data bus participant (1), characterized in that - that the clock generator (6) of the data bus participant (1) has a quartz crystal component and a phase-control loop, - that the data bus participant (1) has a synchronization unit (7) for synchronizing the clock generator (6) to the clock signal of the superior data bus participant, wherein the synchronization unit (7) is configured to detect transitions in the downstream data stream (D) received at the downstream data bus input (2), to control the frequency of the internal clock signal (CLK) of the clock generator (6) depending on the detected transitions, and to set a defined phase angle of the internal clock signal (CLK) to the detected transitions, and - that the data bus participant (1) has a last register (9c) and a downstream data bus output (4) for outputting the downstream data stream (D) synchronously to the internal clock signal (CLK) at the downstream data bus output (4) of the data bus participant (1) for sending to a subordinate data bus participant.

Description

[0001] The invention relates to a data bus participant with a data bus interface which has a downstream data bus input for receiving data from a superior data bus participant and a clock generator for generating an internal clock signal for the data bus participant.

[0002] The invention further relates to a method for synchronizing such data bus participants.

[0003] When transmitting and processing data between data bus participants, the problem of synchronizing these participants often arises. In practice, they have their own local clock which drifts over time even after being set to a global clock. State of the art

[0004] EP 1 253 494 B1 proposes rigidly coupling previously free-running processing cycles to the cycle of a fieldbus system by specifying a clock signal for synchronization. For this purpose, a synchronization signal generation device is provided, which generates a synchronization signal that couples the cycles of the fieldbus system with the processing tasks in the control and / or regulation device. Thus, a central synchronization signal is provided for all connected data bus participants.

[0005] It is also known, for example, from DE 298 09 721 U1, to supply a synchronization signal to all connected participants in parallel on at least one separate line. However, this requires a separate line connection. Furthermore, propagation delays occur.

[0006] The synchronization of local clock generators with a global synchronization clock is also known in US 5 661 700 A, DE 196 26 287 A1 and DE 198 31 405 A1.

[0007] DE 197 51 302 A1 discloses a method for communication control with a main station and remote stations, in which time data for communication timers in the main station are sent together with communication data to the remote stations without a synchronization signal line in order to synchronize their communication timers. Before sending command data, the main station sends time data. The communication timers of the remote stations add transmission delay correction data to the received time data. This compensates for forwarding delays in the preceding stations.

[0008] DE 10 2010 000 962 A1 discloses a method for monitoring a frequency signal for data bus participants connected to each other via a serial peripheral interface (SPI). This SPI interface allows bidirectional, synchronous, and serial data transmission between a master unit and various slave units. For this purpose, at least three lines are provided between the master unit and the first slave unit connected to it for bidirectional data transmission: two data lines and one clock line. The clock line is unnecessary if the data lines are used to generate a clock signal from the edges of the data line. This clock signal is used to control a counter, which can be compared against a counter with an internal clock.

[0009] German patent DE 101 48 878 B4 also proposes synchronizing the transmission clocks of the data transmission system and the satellite system to an evaluation unit, whereby the transmission clocks of the satellite systems received by the evaluation unit are individually synchronized based on a system clock of the evaluation unit. Thus, a global system clock from a central evaluation unit is provided, which is used to synchronize all connected participants.

[0010] A circuit for broadband clock recovery is known from US patent 2012 / 0008727A1. The circuit features a phase-locked loop (PLL).

[0011] The object of the present invention is to create an improved data bus participant and an improved method for synchronizing data bus participants. Disclosure of the invention

[0012] The problem is solved by the data bus participant having the features of claim 1 and by the method for synchronizing such data bus participants having the features of claim 10.

[0013] Advantageous embodiments are described in the dependent claims.

[0014] For a data bus participant of the type mentioned above, it is proposed that the data bus participant have a synchronization unit for synchronizing a clock generator to the clock signal of the higher-level data bus participant. This synchronization unit is then configured to detect transitions in the downstream data stream received at the downstream data bus input, to regulate the frequency of the internal clock signal depending on the detected transitions, and to set a defined phase angle of the internal clock signal relative to the detected transitions.

[0015] In the context of the present inventions, a transition is understood to be any characteristic signal change in the data stream that can be used to synchronize the clock generator to the clock signal of a higher-level data bus participant. In practice, these transitions are preferably signal edges of a digital signal when changing, for example, from a low signal level to a high signal level, i.e., when changing from a digital "zero" to a digital "one" or vice versa. However, other characteristic signal patterns can also be used as transitions, provided that the signal timing can be determined with the accuracy required for synchronization.

[0016] This allows characteristic signal changes in a downstream data stream, which is passed from a higher-level data bus participant to the current data bus participant and thus received by the current data bus participant, to be detected. Based on the detected transitions, a defined phase angle of the internal clock signal is then set relative to the detected transitions. This means that the timing of a characteristic signal change in the downstream data stream provides the basis for synchronizing the clock such that the detected time of a transition is taken as the synchronization point to which the phase angle of the internal clock signal is adjusted.

[0017] The synchronization device measures the phase of the transitions in the downstream data stream relative to its own clock signal and adjusts the frequency of its own clock generator so that this clock frequency corresponds as closely as possible to the clock signal embedded in the downstream data bus signal, resulting in a defined phase relationship between the edge transitions in the downstream data bus stream and the device's own internal clock. The transitions detected in the downstream data stream are thus used as synchronization information to adjust the internal clock signal of the clock generator.

[0018] Compared to a separate synchronization message or synchronization line, the proposed synchronization based on the downstream data stream of a higher-level data bus participant has the advantage that the data bus participants of a more complex system always synchronize their clocks with their adjacent preceding bus participant. As a result, all data bus participants in a network, regardless of their interconnection, achieve the exact same frequency of their internal clocks without problems caused by propagation delays and without a separate synchronization line. Only the phase relationship between the clocks remains undefined due to propagation delays on the lines and latencies of data bus participants.Since each data bus participant synchronizes the clock of its receiver to the edges in the incoming data stream, and the phase of the clock in the sender of the higher-level data bus participant is irrelevant, a different phase of the clocks of the data bus participants in a network does not pose a problem.

[0019] It is particularly advantageous if the data bus interface is bidirectional and also has an upstream data bus output for sending data to a higher-level data bus participant. The data bus participant is thus configured not only to receive data from a higher-level data bus participant in the downstream data stream but also to send (back) data to the higher-level data bus participant in the upstream data stream. At least each higher-level data bus participant then has a phase correction unit for detecting transitions in the data stream received via the upstream data bus input from the directly subordinate data bus participant and for delaying this upstream data stream depending on the detection, such that a defined phase angle of the internal clock signal is set relative to the transitions of the delayed data stream. The phase correction unit can, for example, adjust the phase angle of the data stream received at the upstream data bus input.Determine the data stream using a delay line and, after phase correction, output it via its upstream data bus output to a higher-level data bus participant.

[0020] Since the clock frequency of the internal clock, i.e., the frequency and phase of the internal clock signal, is already set to the first downstream data stream, it is not possible to set the clock for the upstream data stream to match the upstream data stream. Therefore, it is proposed instead to use the phase correction unit to delay the received upstream data stream in the higher-level data bus participant, i.e., the receiver, so that a defined phase relationship is established between the internal clock signal set for the downstream data stream and the upstream data stream.This means that the upstream data stream received by the higher-level data bus participant is also synchronized with the downstream data stream received by the lower-level data bus participant, and the clock frequency and phase of the higher-level data bus participant and the lower-level data bus participant are aligned for the synchronized sending and receiving of data streams.

[0021] The upstream data stream can be delayed, for example, by inserting delay elements or data into the upstream data stream. It is advantageous if the data stream itself is not modified, but rather an electrical propagation delay of the data signal is introduced, for example, using delay elements connected in series. Such delay elements can be, for example, look-up tables (LUTs) in an FPGA (Field Programmable Gate Array) or gates in an ASIC (Custom Integrated Circuit). The synchronization unit and the phase correction unit can be implemented as separate hardware circuits. However, it is also conceivable that the synchronization unit and the phase correction unit are implemented as software logic, running on shared or separate hardware platforms such as microcontrollers, processors, or FPGAs.

[0022] The synchronization unit and / or the phase correction unit are preferably configured to set a defined phase angle in the range of 90° to 270°, and preferably in the range of approximately 180°. The defined phase angle should be set such that the sampling of the data signal can be ensured with as few errors as possible. In serial data transmission within a data stream, signal steepness, transient responses, and phase jitter often need to be considered, which prevent signal sampling immediately after a signal change. The most reliable sampling of a serial data signal is therefore ensured precisely between the activation and deactivation of a high and / or low data signal, i.e., exactly between the switching points or transitions of a data word; this corresponds to a phase angle of 180°.

[0023] The procedure for synchronizing data bus participants, like the structure of the data bus participant, comprises the following steps: - Receiving a downstream data stream from a higher-level data bus participant by a lower-level data bus participant via a downstream data bus input; - Detecting transitions in the downstream data stream received at the downstream data bus input; - Synchronizing an internal clock signal of a clock generator of the subordinate data bus participant depending on the detected transitions and - Setting a defined phase angle of the synchronized internal clock signal to the detected transitions, wherein the clock generator (6) of the data bus participant (1) comprises a quartz crystal and a phase-control loop; and - Outputting the downstream data stream at a downstream data bus output of the data bus participant synchronously to the internal clock signal using a last register of the data bus participant and sending it to a subordinate data bus participant.

[0024] For the synchronization of an upstream data stream, the procedure can be advantageously designed by the following steps: - Receipt of an upstream data stream from a further subordinate data bus participant via an upstream data bus input by a data bus participant; - Detecting transitions in the upstream data stream received at the upstream data bus input; - Delaying this received upstream data stream depending on the detected transitions such that a defined phase relationship between the synchronized internal clock signal and the transitions of the delayed upstream data stream is established and - Sending the delayed upstream data stream via an upstream data bus output to a higher-level data bus participant.

[0025] After delaying the received upstream data stream, it is synchronized to the data bus participant and can be sampled and used or further processed by the data bus participant.

[0026] It is particularly advantageous if no delay data is inserted into the upstream data stream to delay it, but rather purely electrical delay elements, such as LUTs (Look-Up Tables) in an FPGA (Field Programmable Gate Array), are used. Any hardware solution that does not modify the data stream itself, but delays it through its propagation delay, is suitable as a delay element. Several delay elements should be available, and their propagation delays should be approximately the same.

[0027] The invention is explained in more detail below with reference to an exemplary embodiment and the accompanying drawings. These show: Fig. 1 - Block diagram of a network of data bus participants as a sketch to illustrate synchronization; Fig. 2 - Block diagram of a data bus participant and a superior data bus participant with downstream and upstream data streams.

[0028] Fig. Figure 1 shows a block diagram of a network consisting of numerous data bus participants. A master, superior to all other data bus participants, is provided, on which, for example, a programmable logic controller (PLC) runs. This master can be a PLC, which is used in industrial automation processes or home automation in a manner known per se.

[0029] The data bus participants 1 are interconnected in a bus system in a string, star, or a combination thereof. Between any two adjacent bus participants 1 in a string, there are two unidirectional point-to-point connections, enabling bidirectional full-duplex communication between adjacent data bus participants 1. This is illustrated by the arrows pointing towards a subordinate data bus participant 1 for the downstream data stream D and the arrows pointing towards the superior data bus participant 1 for the upstream data stream U.

[0030] For reliable sampling of the serial data stream in each data bus participant 1, it is necessary that the clocks of the data bus participants 1 in the network are synchronized with each other. For this purpose, all subordinate data bus participants, each of which has a superior data bus participant from which it receives a downstream data stream D, are configured to synchronize their internal clocks with the adjacent superior data bus participant 1 that is closer to the master M than the subsequent data bus participant 1. This is functionally illustrated by the synchronization arrows pointing towards the master M.

[0031] Synchronization here does not occur, as is usual, using a separate synchronization signal or a separate synchronization line, as the separate arrows might suggest. Instead, synchronization is achieved by detecting transitions in the downstream data stream D received at the downstream data bus input of a data bus participant.

[0032] Fig. Figure 2 shows a block diagram of two directly adjacent data bus participants 1, such as Slave S1 and Slave S2. Each of these subordinate data bus participants 1 has a data bus input 2 for the downstream data stream D to receive the data stream from a superior data bus participant 1. Furthermore, each data bus participant 1 has an upstream data bus output 3 to send an upstream data stream U to the respective superior data bus participant.

[0033] Furthermore, the data bus participants 1 typically also have a downstream output 4 for sending a downstream data stream to a subordinate data bus participant 1. This downstream data stream can either be the unchanged downstream data stream received at the downstream data bus input 2, which carries messages from the master M to the slave S connected to the master M. i (with i = 1 to m or n, where i, m, and n are integers). It is also conceivable that a data bus participant 1 inserts its own messages to subsequent data bus participants 1 into the downstream data stream D received at the downstream data bus input 2, even after reading messages addressed to it. The synchronized and sampled data stream D arriving at the downstream data bus input 2 is either read in a processing unit 10 and passed through unchanged, or modified and then forwarded.

[0034] Similarly, data bus participants 1 typically also have an upstream data bus input 5 for receiving upstream data streams U from a subordinate data bus participant 1. In the last data bus participant 1 of a sequence of data bus participants, the downstream data bus outputs 4 and upstream data bus inputs 5 can be omitted. It is conceivable that the downstream data bus output 4 is internally connected directly to the upstream data bus input 5 within the data bus participant 1 to provide a loop.

[0035] It can be seen that the data bus participants 1 each have a clock generator 6, which is implemented in a manner known per se, e.g. using a quartz crystal and / or a PLL loop (phase control loop) or similar.

[0036] A synchronization unit 7 is provided for synchronizing the internal clock generator 6, which is set up to detect transitions in the downstream data stream D received at the downstream data bus input 2.

[0037] For this purpose, the synchronization unit 7 can be configured to measure the phase of the transitions in the serial downstream data stream D relative to its own clock either by means of a suitable electronic circuit as hardware or by means of suitable software-supported signal processing. The synchronization unit 7 is preferably configured to regulate the frequency of the internal clock signal of the clock generator 6 such that the regulated frequency of the internal clock signal of the clock generator 6 corresponds exactly to the frequency of the clock hidden in the downstream data stream D.

[0038] Synchronization unit 7 is further configured to set a defined phase angle between the internal clock signal and the detected transitions. The internal clock signal, provided by clock generator 6, is thus set so that a defined phase angle exists between the edge transitions in the downstream data stream D and its own clock signal, ensuring the most accurate possible sampling of the downstream data stream D. Therefore, the phase angle should be set in the range of 90° to 270°, and preferably in the range of approximately 180° (± 10%). For example, with a 180° phase shift, the downstream data stream D can be reliably sampled precisely midway between two edge transitions using two registers 9a and 9b connected in series.

[0039] This is clearly shown by the signal sketched in the downstream data stream D between the two data bus participants 1 with superimposed signal changes from high-level to low-level and vice versa, and the clock signal CLK sketched below with the edge change from low to high at 180° to the transition T.

[0040] The sampled downstream data stream D is then either read and passed through unchanged in processing unit 10, or modified and then forwarded. Subsequently, data stream D is output via a final register 9c, synchronously with the internal clock, at the downstream data bus output 4. For communication purposes, it is crucial that data stream D has passed through at least two registers, 9a and 9b, before being output at the downstream data bus output 4. This process refreshes not only the electrical amplitude of the signal but also the timing of the edges. In practice, this timing refresh is important not only on the downstream but also on the upstream side.

[0041] As a result, all data bus participants 1 in a network have their clock generators 6 set to exactly the same frequency. Only the phase relationship between the clocks is undefined due to propagation delays on the lines and the latencies of the data bus participants 1. This poses no problem for the serial downstream data stream D, since the synchronization unit 7 synchronizes the receiver's clock for the downstream data stream to the edges of the incoming data stream D, and the phase relationship of the clock in the transmitter of the higher-level data bus participant 1 is irrelevant in this context. In practice, the data bits on the serial upstream data stream U are output to the higher-level data bus participant 1 (i.e., the left neighbor) at exactly the same frequency as the downstream data stream D is received by the higher-level data bus participant 1.Due to the propagation delays in the lines and the latencies of data bus participants 1, the phase relationship between the edges in the upstream data stream U and the local clock of the superior bus participant of the upstream data stream U is completely undefined.

[0042] To reliably sample the upstream data stream U between two edge transitions, a phase correction unit 8 is provided in the data bus participants 8. This unit detects the phase relationship between the edge transitions in the received upstream data stream U and the local clock of the respective data bus participant 1, for example, by measurement. The phase correction unit 8 is then configured to delay the upstream data stream U received by the subordinate data bus participant 1 such that the signal transmitted with the upstream data stream U can subsequently be sampled by the data bus participant 1 precisely at the midpoint between the edge transitions and synchronized with the local clock of the superior data bus participant 1, which is the receiver of the upstream data stream U. For sampling, for example, two storage registers 9d and 9e can be provided, into which the upstream data stream U is successively shifted serially.

[0043] The delay of the upstream data stream U can be advantageously achieved, as outlined, by dynamically inserting delay elements. The data stream U itself is not modified, but rather slightly delayed overall by suitable logic elements (latency delay). For this purpose, the data stream signal is passed through the logic elements (e.g., LUTs or buffers) connected in series.

[0044] On the upstream U, the upstream data is already received at the correct frequency due to the synchronization of the subordinate data bus participant 1 to the downstream D. Only the phase needs to be corrected by the phase correction unit 8. For this purpose, the data stream is sent through a chain of digital logic elements that do not modify the data stream, but simply forward it. This forwarding is delayed by the propagation delay of the logic elements used. Such a chain is also called a delay line. Depending on which link (logic element) the data stream is tapped from, a specific delay can be set. Look-up tables (LUTs) in FPGAs are suitable examples of logic elements.

[0045] With such a synchronized network of data bus participants, uninterrupted transmission of infinitely long data streams is possible. Decomposition into data packets, as is necessary in Ethernet, for example, to enable new synchronization to a preamble for each data packet, is not required. This eliminates the bandwidth consumption for the preamble or similar components, and access to the transmission medium is always possible, since a preamble does not need to be sent first.

[0046] Furthermore, buffer memories, such as first-in-first-out (FIFO) memory or any type of receive or transmit buffer, are not required. This minimizes data throughput time and reduces costs due to the lower hardware requirements. Data processing in all data bus participants, down to the higher protocol layers and in some cases even to the software-implemented protocol layers, is clock-synchronous and deterministically precise, down to the clock, thanks to the synchronized clocks that supply the logic and processors of the data bus participants.

[0047] Furthermore, oversampling of the serial data stream during transmission and / or reception is not required. Therefore, clock frequencies higher than the baud rate are not necessary for data transmission in data bus participant 1. This results in lower power dissipation and reduced electromagnetic interference. The lower clock rates also minimize the complexity and cost of signal processing units in the form of FPGAs (Field Programmable Gate Arrays) or ASICs (User-Specific Integrated Circuits).

[0048] Another advantage is that special filler symbols or empty data bits, which are inserted into or removed from the data stream as needed in other solutions to compensate for slightly different baud rates, are not required.

[0049] The latency when passing data downstream and upstream is extremely low compared to other solutions that also refresh the timing of the signal.

Claims

[1] Data bus participant (1) with a data bus interface which - a downstream data bus input (2) for receiving data from a higher-level data bus participant and - has a clock generator (6) for generating an internal clock signal (CLK) for the data bus participant (1), characterized by , - that the clock generator (6) of the data bus participant (1) has a quartz crystal component and a phase-control loop, - that the data bus participant (1) has a synchronization unit (7) for synchronizing the clock generator (6) to the clock signal of the superior data bus participant, wherein the synchronization unit (7) is configured to detect transitions in the downstream data stream (D) received at the downstream data bus input (2), to control the frequency of the internal clock signal (CLK) of the clock generator (6) depending on the detected transitions, and to set a defined phase angle of the internal clock signal (CLK) to the detected transitions, and - that the data bus participant (1) has a last register (9c) and a downstream data bus output (4) for outputting the downstream data stream (D) synchronously to the internal clock signal (CLK) at the downstream data bus output (4) of the data bus participant (1) for sending to a subordinate data bus participant. [2] Data bus participant (1) according to claim 1, characterized by, that the data bus participant (1) has a processing unit (10) -to read and pass through unchanged the sampled downstream data stream (D) or -for modifying and forwarding the sampled downstream data stream (D). [3] Data bus participant (1) according to one of the preceding claims, characterized by , that the data bus participant (1) has logic and a processor for processing the data of the downstream data stream (D) up to higher protocol layers, partly up to software-implemented protocol layers, wherein the logic and the processor are supplied by the clock generator (6). [4] Data bus participant (1) according to any of the preceding claims, characterized by , that the downstream data stream (D) is serial and that the data bus participant (1) is configured to sample the serial downstream data stream (D). [5] Data bus participant (1) according to any of the preceding claims, characterized by, that the downstream data bus input (2) and the downstream data bus output (4) of the data bus participant (1) are suitable for a ring line. [6] Data bus participant (1) according to any of the preceding claims, characterized by , that the data bus participant (1) is configured as a slave (S1) for a network with a master (M). [7] Data bus participant (1) according to any of the preceding claims, characterized by , that the downstream data stream (D) has no preamble. [8] Data bus participant (1) according to any of the preceding claims, characterized by , that the data bus participant (1) does not perform oversampling of the serial downstream data stream (D) during sending and / or receiving. [9] Data bus participant (1) according to any of the preceding claims, characterized by , that the data bus participant (1) does not have clock frequencies greater than the baud rate for data transmission of the downstream data stream (D). [10] Method for synchronizing data bus participants (1), characterized by - Receipt of a downstream data stream (D) from a higher-level data bus participant (M) by a data bus participant (S1) via a downstream data bus input (2); - Detecting transitions in the downstream data stream (D) received at the downstream data bus input (2); - Synchronizing an internal clock signal (CLK) of a clock generator (6) of the data bus participant (S1) depending on the detected transitions; wherein the clock generator (6) of the data bus participant (1) comprises a quartz crystal and a phase-controlled loop, - Setting a defined phase relationship between the synchronized internal clock signal (CLK) and the detected transitions; - Output (1) of the downstream data stream (D) at a downstream data bus output (4) of the data bus participant (S1) synchronously to the internal clock signal (CLK) of the clock generator (6) by means of a last register (9c) of the data bus participant (S1) and transmission to a subordinate data bus participant (S2).

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