Device with two power semiconductor chips and method for its manufacture

Abstract

A device comprises a first power semiconductor chip having a first contact point and a second contact point on a first surface and a third contact point on the second surface. The device further comprises a second power semiconductor chip having a first contact point and a second contact point on a first surface and a third contact point on the second surface. The first and second power semiconductor chips are arranged one above the other, and the first surface of the first power semiconductor chip faces in the direction of the first surface of the second power semiconductor chip. Furthermore, the first power semiconductor chip is arranged laterally at least partially outside the outline of the second power semiconductor chip.

Description

TECHNICAL AREA

[0001] This invention relates to a device comprising two power semiconductor chips and a method for their manufacture. BACKGROUND

[0002] A power semiconductor chip is a specific type of semiconductor chip designed to handle significant power levels. Power semiconductor chips are particularly well-suited for switching and controlling currents and / or voltages. They can be implemented as power MOSFETs, IGBTs, JFETs, and power bipolar transistors. Power semiconductor chips are found in most power supplies, DC-to-DC converters, and motor control units. Power semiconductor chips can be stacked for specific applications such as half-bridge circuits.

[0003] DE 10 2009 040 557 A1 and DE 10 2005 007 373 A1 each show a component with two power semiconductor chips arranged side by side in opposite directions and at slightly different heights relative to each other. DE 10 2006 037 118 B3 shows two power semiconductor chips arranged side by side in opposite directions on a ceramic substrate and encapsulated in a potting compound. US 6,946,740 B2 also shows two power semiconductor chips arranged side by side in opposite directions on a common substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The accompanying drawings have been included to provide a further understanding of embodiments and are integrated into and form part of this description. The drawings depict embodiments and, together with the description, serve to explain the principles of these embodiments. Other embodiments and many of the intended advantages of the embodiments will be readily apparent when they are better understood by reference to the detailed description that follows. The elements of the drawings are not necessarily to scale relative to one another. The same reference numerals denote corresponding similar parts. Fig. Figure 1 schematically shows a cross-sectional view of a device not according to the invention, comprising two power semiconductor chips arranged one above the other; Fig. Figures 2A-2O schematically represent a cross-sectional view of an embodiment of a method comprising arranging two power semiconductor chips in opposite positions one above the other and coupling the two power semiconductor chips to each other; Fig. Figure 3 shows a basic circuit of a half-bridge circuit; and Fig. Figure 4 schematically represents a cross-sectional view of an embodiment of a system with the in Fig. 2O shows the device mounted on a circuit board. DETAILED DESCRIPTION OF EXPLANATORY EXECUTION FORMS

[0005] The following detailed description refers to the accompanying drawings, which form part thereof and illustrate specific embodiments in which the invention can be implemented. In this context, directional terminology, such as "top," "bottom," "front," "back," "anterior," "rear," etc., is used to refer to the orientation of the described figure(s). Since the components of the embodiments can be positioned in a number of different orientations, this directional terminology is used for explanatory purposes and is in no way limiting. Naturally, other embodiments can be used, and structural or logical modifications can be made without infringing upon the scope of protection of the present invention.The following detailed description should therefore not be interpreted in a limiting sense, and the scope of protection of the present invention is defined by the attached claims.

[0006] Naturally, the features of the various exemplary embodiments described here can be combined with each other, unless specifically stated otherwise.

[0007] As used in this patent description, the terms “coupled” and / or “electrically coupled” are not intended to imply that the elements must be directly coupled to each other; intermediate elements may be provided between the “coupled” or “electrically coupled” elements.

[0008] Devices containing semiconductor chips, particularly power semiconductor chips, are described below. The semiconductor chips can be of various types, manufactured using different technologies, and may include, for example, integrated electrical, electro-optical, or electromechanical circuits or passive elements. The integrated circuits may be designed, for example, as integrated logic circuits, analog integrated circuits, integrated mixed-signal circuits, integrated power circuits, memory circuits, or integrated passive elements. Furthermore, the semiconductor chips may be configured as so-called MEMS (microelectromechanical systems) and may include micromechanical structures such as bridges, membranes, or tongue structures.Semiconductor chips can be configured as sensors or actuators, such as pressure sensors, accelerometers, rotation sensors, magnetic field sensors, electromagnetic field sensors, microphones, etc. The semiconductor chips do not need to be made from a specific semiconductor material, such as Si, SiC, SiGe, or GaAs, and can also contain inorganic and / or organic materials that are not semiconductors, such as insulators, plastics, or metals. Furthermore, the semiconductor chips can be encapsulated or unencapsulated.

[0009] In particular, semiconductor chips with a vertical structure can be involved, meaning that the semiconductor chips can be manufactured in such a way that electrical currents can flow in a direction perpendicular to the main surfaces of the semiconductor chips. A semiconductor chip with a vertical structure has an electrode on its two main surfaces, that is, on its top and bottom surfaces. In particular, power semiconductor chips can have a vertical structure and have load electrodes on both main surfaces. The vertical power semiconductor chips can be configured, for example, as power MOSFETs (metal-oxide-semiconductor field-effect transistors), IGBTs (insulated-gate bipolar transistors), JFETs (junction field-effect transistors), or power bipolar transistors.For example, the source electrode and the gate electrode of a power MOSFET can be located on one surface, while the drain electrode of the power MOSFET is located on the other surface. Furthermore, the devices described below can include integrated circuits to control the integrated circuits of the power semiconductor chips.

[0010] Semiconductor chips have contact points (or contact elements or terminals) that allow electrical contact to be established with the integrated circuits contained within the semiconductor chips. These contact points can comprise one or more metal layers deposited onto the semiconductor material. The metal layers can be manufactured with any desired geometric shape and material composition. For example, the metal layers can be in the form of a layer covering an area. Any desired metal or metal alloy, such as aluminum, titanium, gold, silver, copper, palladium, platinum, nickel, chromium, or nickel vanadium, can be used as the material.The metal layers do not have to be homogeneous or made of only one material; that is, different compositions and concentrations of the materials contained in the metal layers are possible.

[0011] One or more metal layers in the form of conductive traces (or conductor rails) can be provided and can be electrically coupled to the semiconductor chip. The metal layers can be used, for example, to create a redistribution layer. The conductive traces can be used as wiring layers to establish electrical contact with the semiconductor chips from outside the device and / or with other semiconductor chips and / or components contained within the device. The conductive traces can couple the contact points of the semiconductor chips to the external contact points. The conductive traces can be manufactured with any desired geometric shape and material composition.Any desired material, such as aluminum, nickel, palladium, silver, tin, gold, copper, or metal alloys, can be used. The conductor tracks do not need to be homogeneous or made of only one material; that is, different compositions and concentrations of the materials contained in the conductor tracks are possible. Furthermore, the conductor tracks can be arranged above, below, or between electrically insulating layers.

[0012] The devices described below include external contact points (or external contact elements) that can have any shape and size. The external contact points can be accessible from outside the devices and can therefore allow electrical contact to be established with the semiconductor chips from outside the devices. Furthermore, the external contact points can be thermally conductive and can serve as heat sinks to dissipate the heat generated by the semiconductor chips. The external contact points can be made of any desired electrically conductive material, for example, a metal such as copper, aluminum, or gold, a metal alloy, or an electrically conductive organic material. The external contact points can be formed by sections of the metal layers. A soldering material, such as solder balls or solder bumps, can be deposited on the external contact points.

[0013] The semiconductor chips are encapsulated in a laminate (prepreg). Lamination is used to encapsulate the semiconductor chips with the encapsulation material. Heat and / or pressure can be used to apply the encapsulation material.

[0014] The encapsulation material can be used to create fan-out packages. In a fan-out package, at least some of the external contacts and / or traces connecting the semiconductor chip to the external contacts are located laterally outside the outline of the semiconductor chip or at least intersect the outline of the semiconductor chip. Thus, in fan-out packages, an outer circumferential portion of the semiconductor chip's package is typically used for electrical bonding the package to external applications such as application boards. This outer portion of the package, surrounding the semiconductor chip, effectively increases the package's contact area relative to the semiconductor chip's footprint, consequently reducing restrictions on package contact point size and spacing for subsequent processing, such as second-level assembly.

[0015] Each device has at least one mounting surface. The mounting surface is used to mount the device to another component, for example, a printed circuit board (PCB). External contact elements, and in particular external contact pads, can be arranged on the mounting surface to allow the device to be electrically coupled to the component on which it is mounted. Solder deposits, such as solder balls, or other suitable connecting elements can be used to establish an electrical and, in particular, mechanical connection between the device and the component on which it is mounted.

[0016] Fig. Figure 1 schematically shows a cross-sectional view of a device 100 not according to the invention. The device 100 comprises a first power semiconductor chip 10 with a first surface 11 and a second surface 12 opposite the first surface 11. A first contact point 13 and a second contact point 14 are arranged on the first surface 11, and a third contact point 15 is arranged on the second surface 12 of the first power semiconductor chip 10. The device 100 also comprises a second power semiconductor chip 20 with a first surface 21 and a second surface 22 opposite the first surface 21. A first contact point 23 and a second contact point 24 are arranged on the first surface 21, and a third contact point 25 is arranged on the second surface 22 of the second power semiconductor chip 20.

[0017] In the device 100, the first and second power semiconductor chips 10, 20 are arranged one above the other. The first surface 11 of the first power semiconductor chip 10 faces in a first direction 1, and the first surface 21 of the second power semiconductor chip 20 faces in a second direction 2, which is opposite to the first direction 1. Furthermore, the first power semiconductor chip 10 is arranged laterally, at least partially, outside an outline 27 of the second power semiconductor chip 20.

[0018] Fig. 2A-2O, together Fig. Figure 2 schematically represents an embodiment of a method for manufacturing a device 200, which is described in Fig. 20 is shown. The device 200 is an implementation according to the invention of the in Fig. The details of device 200, described below, can therefore also be applied to device 100. Similar or identical components of devices 100 and 200 are designated with the same reference numerals.

[0019] Fig. Figure 2A schematically depicts a first power semiconductor chip 10 and a second power semiconductor chip 20 in a cross-sectional view. The first power semiconductor chip 10 has a first surface 11 and a second surface 12. A first contact point 13 and a second contact point 14 are located on the first surface 11, and a third contact point 15 is located on the second surface 12 of the first power semiconductor chip 10. The second power semiconductor chip 20 has a first surface 21 and a second surface 22. A first contact point 23 and a second contact point 24 are located on the first surface 21, and a third contact point 25 is located on the second surface 22 of the second power semiconductor chip 20. The first and third contact points 13, 15, 23, 25 of both power semiconductor chips 10 and 20 are load electrodes. The second contact points 14, 24 of both power semiconductor chips 10, 20 are control electrodes.

[0020] Each of the first power semiconductor chip 10 and the second power semiconductor chip 20 is configured as a power transistor, for example, as a power MOSFET, IGBT, JFET, or power bipolar transistor. In the case of a power MOSFET or a JFET, the first contact point 13, 23 is a source electrode, the second contact point 14, 24 is a gate electrode, and the third contact point 15, 25 is a drain electrode. In the case of an IGBT, the first contact point 13, 23 is an emitter electrode, the second contact point 14, 24 is a gate electrode, and the third contact point 15, 25 is a collector electrode. In the case of a power bipolar transistor, the first contact point 13, 23 is an emitter electrode, the second contact point 14, 24 is a base electrode, and the third contact point 15, 25 is a collector electrode.During operation, voltages higher than 5, 50, 100, 500, or 1000 V can be applied between the first and third contact points 13, 15, 23, 25. The switching frequency applied to the second contact point 14, 24 can be in the range of 1 kHz to 100 MHz, but can also be outside this range.

[0021] The power semiconductor chips 10, 20 each comprise a semiconductor substrate 16, 26 made of a suitable semiconductor material, for example Si, SiC, SiGe, or GaAs, and containing n- and / or p-doped regions. Each of the contact points 13-15, 23-25 ​​consists of one or more metal layers deposited onto the semiconductor substrate 16, 26. The metal layers can be manufactured with any desired geometric shape and material composition. For example, the metal layers can be arranged as a layer covering an area. Any desired metal or metal alloy, such as aluminum, titanium, gold, silver, copper, palladium, platinum, nickel, chromium, or nickel vanadium, can be used as the material. Each of the individual metal layers can have a specific function.The function of one of the metal layers is to establish electrical contact with the doped regions of the semiconductor substrate 16, 26. Another of the metal layers acts as a diffusion barrier, protecting the semiconductor substrate 16, 26 during a soldering process. A further function of one of the metal layers is that of an adhesive layer, enabling another metal layer to adhere to the semiconductor substrate 16, 26.

[0022] In one embodiment, the first and second power semiconductor chips 10, 20 are identical in size. In particular, the surface areas of the first surfaces 11, 21 of the first and second power semiconductor chips 10, 20 are identical. Furthermore, the heights of the power semiconductor chips 10, 20 can be approximately 20 µm. In another embodiment, the sizes of the first and second power semiconductor chips 10, 20 are different. For example, the first power semiconductor chip 10, which is later used as a low-side switch, is larger than the second power semiconductor chip 20, which is used as a high-side switch.

[0023] Fig. Figure 2B schematically depicts adhesive carrier films 30, 31. The first and second power semiconductor chips 10, 20 are each detachably attached to the adhesive carrier films 30, 31, with their first surfaces 11, 21 facing the adhesive carrier films 30, 31. Consequently, the first and second contact points 13, 14, 23, 24 adhere to the adhesive carrier films 30, 31. A pick-and-place machine can be used to position the power semiconductor chips 10, 20 on the adhesive carrier films 30, 31.

[0024] Fig. Figure 2C schematically depicts supports 32, 33. The supports 32, 33 can be made of copper or other suitable materials, for example, nickel, steel, stainless steel, laminate, or a stack of materials. Each of the supports 32, 33 has at least one flat surface on which components of the device 200 can be arranged. The shape of the supports 32, 33 is not limited to any geometric shape; for example, the supports 32, 33 are round or square. The supports 32, 33 can each have any suitable size and thickness d1, d2. In one embodiment, the supports 32, 33 have the same thickness d1, d2. In one embodiment, the thicknesses d1, d2 are approximately 70 µm.

[0025] Metal layers 34, 35 are arranged on the supports 32, 33. In one embodiment, the metal layers 34, 35 are copper foils. The metal layers 34, 35 can be attached to the supports 32, 33 by means of an adhesive tape, for example, a double-sided adhesive tape. The metal layers 34, 35 each have a thickness d3, d4. In one embodiment, the metal layers 34, 35 have the same thickness d3, d4. In one embodiment, the thicknesses d3, d4 are approximately 12 µm.

[0026] The adhesive carrier films 30, 31 are arranged over the carriers 32, 33, so that the power semiconductor chips 10, 20 are attached to the metal layers 34, 35, with the second surfaces 12, 22 of the power semiconductor chips 10, 20 facing the metal layers 34, 35.

[0027] In one embodiment, the power semiconductor chips 10, 20 are electrically and mechanically coupled to the metal layers 34, 35 by diffusion soldering. For this purpose, solder material is deposited on the third contact points 15, 25 or, alternatively, on the third contact points 15, 25 and the contact surfaces of the metal layers 34, 35. In one embodiment, the solder material is deposited on the third contact points 15, 25 while the power semiconductor chips 10, 20 are still in the wafer stack, meaning that the solder material is deposited on the semiconductor wafer before the semiconductor wafer is singulated to produce individual semiconductor chips. In one embodiment, the solder material consists of AuSn, AgSn, CuSn, Sn, AuIn, AgIn, AuSi, or CuIn.

[0028] In one embodiment, the power semiconductor chips 10, 20 and the carriers 32, 33, together with the metal layers 34, 35, are arranged in an oven and heated to a suitable temperature to melt the solder material. During the soldering process, the power semiconductor chips 10, 20 can be pressed onto the metal layers 34, 35 for a suitable time. The solder material then forms a metallic bond between the power semiconductor chips 10, 20 and the metal layers 34, 35, which can withstand high temperatures because the solder material forms a temperature-resistant and mechanically very stable intermetallic phase with high-melting-point materials of the third contact points 15, 25 and the metal layers 34, 35. The intermetallic phase has a higher melting point than the solder material used to create it.In this process, low-melting-point solder material is completely transformed, i.e., it transitions entirely into the intermetallic phase. In one embodiment, the power semiconductor chips 10, 20 and the metal layers 34, 35 are exposed to a temperature of approximately 250 °C for 45 minutes.

[0029] In one embodiment, the power semiconductor chips 10, 20 are electrically and mechanically coupled to the metal layers 34, 35 by means of an electrically conductive adhesive. The electrically conductive adhesive can be epoxy resin-based and enriched with gold, silver, nickel, or copper to achieve electrical conductivity. The adhesive can be printed onto the metal layers 34, 35 using a stencil before the power semiconductor chips 10, 20 are positioned over the metal layers 34, 35. The adhesive can be heated to a specific temperature to cure it.

[0030] Fig. Figure 2D schematically depicts the power semiconductor chips 10, 20, each firmly attached to the metal layers 34, 35, after the adhesive carrier films 30, 31 have been removed. Although Fig. If the 2D diagram shows only one first power semiconductor chip 10 and one second power semiconductor chip 20, more first and second power semiconductor chips 10, 20 can be attached to the metal layers 34, 35. For example, more than 50, 100, or 500 first and second power semiconductor chips 10, 20 can be attached to the metal layers 34, 35.

[0031] The exposed surfaces of the metal layers 34, 35 are roughened by an etching process to improve the adhesion of the laminate, which is deposited on the metal layers 34, 35 in the next step.

[0032] Fig. Figure 2E schematically depicts lamination films 40, 41, each attached to the metal layers 34, 35. In one embodiment, the power semiconductor chips 10, 20 are not covered by the lamination films 40, 41. The lamination films 40, 41 each have a thickness d5, d6, which can be identical. In one embodiment, the thicknesses d5, d6 are approximately 35 µm.

[0033] The lamination films 40, 41 consist of a suitable dielectric material, namely a polymer material, which is a prepreg, a combination of a fiber mat, for example, glass or carbon fibers, and a resin, for example, a thermosetting material. Prepreg materials are commonly used for the production of PCBs. Well-known prepreg materials used in the PCB industry that can be used here as polymer materials are: FR-2, FR-3, FR-4, FR-5, FR-6, G-10, CEM-1, CEM-2, CEM-3, CEM-4, and CEM-5. Prepreg materials are two-stage materials that are flexible when applied to the metal layers 34, 35 and are cured during heat treatment. The same or similar process steps as in PCB manufacturing can be used for laminating the prepreg.

[0034] Fig. Figure 2F schematically illustrates that the support 32 is arranged above the support 33 such that the first surface 11 of the first power semiconductor chip 10 faces in a first direction 1, while the first surface 21 of the second power semiconductor chip 20 faces in a second direction 2. In one embodiment, the first direction 1 is perpendicular to the first surface 11 of the first power semiconductor chip 10, the second direction 2 is perpendicular to the first surface 21 of the second power semiconductor chip 20, and the first direction 1 and the second direction 2 form an angle of 180°. In particular, the first surface 11 of the first power semiconductor chip 10 faces in the direction of the first surface 21 of the second power semiconductor chip 20.

[0035] Fig. Figure 2G schematically illustrates that the carrier 32 is subsequently pressed onto the carrier 33. Heat and pressure are applied to laminate the lamination films 40, 41 together, thereby creating a lamination layer 42. The lamination layer 42 encapsulates the power semiconductor chips 10, 20 and covers the first surfaces 11, 21 and the side surfaces of the power semiconductor chips 10, 20. Furthermore, the first power semiconductor chip 10 is arranged laterally, at least partially, outside an outline 27 of the second power semiconductor chip 20. The outline 27 can be defined by the side surfaces 28 of the second power semiconductor chip 20. In one embodiment, therefore, a first section of the first power semiconductor chip 10 is arranged within the outline 27 of the second power semiconductor chip 20 and a second section of the first power semiconductor chip 10 is arranged outside the outline 27 of the second power semiconductor chip 20.In one embodiment, the first power semiconductor chip 10 is arranged laterally completely outside the outline 27 of the second power semiconductor chip 20. The vertical distance between the two power semiconductor chips 10, 20 can be changed by altering the thicknesses d5, d6 of the lamination films 40, 41.

[0036] Fig. Figure 2H schematically illustrates the removal of the supports 32, 33. If the supports 32, 33 were attached to the metal layers 34, 35 using adhesive tapes, the adhesive tapes are also removed.

[0037] Fig. Figure 2I schematically depicts the metal layers 34, 35 after a structuring step to define the position of vias. For this purpose, dry resist films can be applied to the metal layers 34, 35 (in Fig. 2I not shown) are laminated, which are photostructurable. Recesses can be formed in the resist films by exposure to light with a suitable wavelength. A laser beam or exposure through a mask can be used for this purpose. Subsequently, the resist films are developed, and the exposed sections of the metal layers 34, 35 are etched, creating recesses 43 in the metal layers 34, 35. The resist films are then stripped, leaving only the structured metal layers 34, 35, as shown in Fig. 2I is shown.

[0038] Fig. Figure 2J schematically depicts through-holes 44 through the lamination layer 42. The through-holes 44 are created by laser drilling at the positions of the recesses 43 in the metal layers 34, 35. The through-holes 44 expose at least sections of the first and second contact points 13, 14, 23, 24 of the power semiconductor chips 10, 20. At least one of the through-holes 44 extends from a recess 43 in the metal layer 34 through the entire lamination layer 42 to the metal layer 35 and consequently exposes a section of the metal layer 35. The through-holes 44 that expose sections of the first and second contact points 13, 14, 23, 24 of the power semiconductor chips 10, 20 have a diameter d7, which is, for example, approximately 70 µm. The through holes 44, which expose sections of the metal layer 35, have a diameter d8, which is, for example, about 100 µm.

[0039] Fig. 2K schematically represents metal layers 50, 51, each deposited on metal layers 34, 35 using an electroplating process. The material of the metal layers 50, 51 can be any suitable metal or metal alloy, for example, copper or aluminum. The metal layers 50, 51 also fill the vias 44 created in the lamination layer 42. The metal layers 50, 51 form vias in the lamination layer 42 and electrically couple the first and second contact points 13, 14, 23, 24 of the power semiconductor chips 10, 20 to the metal layers 34, 35. The metal layers 50, 51 each have a thickness d9, d 10 on, which can be approximately 38 µm.

[0040] Fig. Figure 2L schematically depicts the metal layers 34, 35, 50, 51 after a structuring step to create the external contact points described below. Furthermore, the metal layers 34, 50 are structured such that the third contact point 15 of the first power semiconductor chip 10 is electrically coupled to the first contact point 23 of the second power semiconductor chip 20. Finally, the exposed surfaces of the metal layers 50, 51 are roughened by an etching process to improve the adhesion of the solder mask, which is deposited onto the metal layers 50, 51 in the next step.

[0041] Fig. 2M schematically depicts solder mask layers 52, 53, each laminated onto the metal layers 50, 51. The solder mask layers 52, 53 are structured to expose sections of the metal layers 50, 51. The exposed sections of the metal layers 50, 51 form external contact points 54-58. The external contact points 54-58 enable electrical contact with the power semiconductor chips 10, 20 from outside the device 200. For this purpose, the external contact points 54 are electrically coupled to the third contact point 15 of the first power semiconductor chip 10 and the first contact point 23 of the second power semiconductor chip 20. The external contact point 55 is electrically coupled to the second contact point 14 of the first power semiconductor chip 10. The external contact point 56 is electrically coupled to the first contact point 13 of the first power semiconductor chip 10.The external contact point 57 is electrically coupled to the third contact point 25 of the second power semiconductor chip 20. The external contact point 58 is electrically coupled to the second contact point 24 of the second power semiconductor chip 20.

[0042] Fig. 2N schematically represents solder bumps 59 which are deposited on the external contact points 54-58 by a pressure and melting process.

[0043] Fig. Figure 2O schematically illustrates that the devices 200 are separated from each other by sawing or cutting. The in Fig. The device 200 shown in Figure 20 has two main surfaces 60, 61. Both main surfaces 60, 61 can be used as mounting surfaces for attaching the device 200 to another component, for example, a printed circuit board (PCB). Due to the manufacturing process of the device 200, the lateral position of the two power semiconductor chips 10, 20 can be selected as desired; consequently, any lateral distance between the power semiconductor chips 10, 20 is possible. The distance between the power semiconductor chips 10, 20, as shown in Figure 20, is determined by the following criteria: Fig. 2O shows that it improves the heat transfer from the power semiconductor chips 10, 20.

[0044] Fig. Figure 3 shows a basic circuit 300 of a half-bridge circuit arranged between two nodes N1 and N2. The half-bridge circuit consists of two switches S1 and S2 connected in series. The power semiconductor chips 20 and 10 of the device 200 can be implemented as switches S1 and S2, respectively. Constant electrical potentials can be applied to nodes N1 and N2. A high potential, such as 10, 50, 100, 200, 500, or 1000 V, or any other potential, can be applied to node N1, and a low electrical potential, such as 0 V, can be applied to node N2. Consequently, the first power semiconductor chip 10 is the low-side switch, whereas the second power semiconductor chip 20 is the high-side switch. Switches S1 and S2 can be switched at frequencies in the range of 1 kHz to 100 MHz, but the switching frequencies can also be outside this range.This means that a variable electrical potential is applied to node N3, located between switches S1 and S2, during operation of the half-bridge. The potential of node N3 varies between the low and high electrical potential range.

[0045] The half-bridge circuit can be implemented, for example, in electronic circuits for converting DC voltages, so-called DC-to-DC converters. DC-to-DC converters can be used to convert an input DC voltage, supplied by a battery or rechargeable battery, into an output DC voltage that is adapted to the requirements of downstream connected electronic circuits. DC-to-DC converters can be implemented as step-down converters, where the output voltage is less than the input voltage, or as step-up converters, where the output voltage is greater than the input voltage. Frequencies of several MHz or higher can be applied to DC-to-DC converters. Furthermore, currents of up to 50 A or even higher can flow through DC-to-DC converters.

[0046] Fig. Figure 4 schematically shows a cross-sectional view of a system 400 comprising the device 200 and a printed circuit board 70. The device 200 is mounted on the printed circuit board 70, with its mounting surface 60 facing the board. The external contact points 55-58 of the device 200 are electrically and mechanically coupled to contact points 71 of the printed circuit board 70 by means of the solder lugs 59. A metallic clamp 72 is also mounted on the surface 61 of the device 200 and electrically couples the external contact points 54 of the device 200 to the printed circuit board 70. Additional components, such as an inductor or a capacitor, may be mounted on the printed circuit board 70. The system 400 can also serve as a sub-module for integration into other systems.

[0047] Although a particular feature or aspect of an embodiment of the invention may have been disclosed with respect to only one of several implementations, such a feature or aspect may also be combined with one or more other features or aspects of the other implementations, as may be desirable and advantageous for any given or specific application. Furthermore, to the extent that the terms "include," "have," "with," or other variations thereof are used in either the detailed description or the claims, such terms shall be understood to mean inclusive in a manner similar to the term "comprise." Moreover, the embodiments of the invention may, of course, be implemented in discrete circuits, partially integrated circuits, fully integrated circuits, or programming devices.The term "exemplary" is meant merely as an example, rather than as the best or optimal solution. It should also be noted that features and / or elements depicted here are shown with specific dimensions relative to each other for the sake of simplicity and ease of understanding, and that the actual dimensions may differ considerably from those shown here.

[0048] explained here

Claims

[1] Device comprising: a first power semiconductor chip (10) having a first surface (11) and a second surface (12) opposite the first surface, wherein a first contact point (13) and a second contact point (14) are arranged on the first surface and a third contact point (15) is arranged on the second surface; and a second power semiconductor chip (20) with a first surface (21) and a second surface (22) opposite the first surface, wherein a first contact point (23) and a second contact point (24) are arranged on the first surface and a third contact point (25) is arranged on the second surface; wherein the first and the second power semiconductor chip are encapsulated in a common lamination layer (42) and arranged such that the first surface (11) of the first power semiconductor chip (10) faces in a first direction and the first surface (21) of the second power semiconductor chip (20) faces in a second direction opposite to the first direction, wherein the common lamination layer (42) contains a prepreg, and wherein the first power semiconductor chip (10) is arranged laterally completely outside an outline of the second power semiconductor chip (20), wherein the device further comprises a first metal layer (34, 50) attached to the second surface (12) of the first power semiconductor chip (10) and to a surface of the common lamination layer (42), and a second metal layer (35, 51) attached to the second surface of the second power semiconductor chip (20), wherein the first metal layer (34, 50) and the second metal layer (35, 51) are arranged on opposite surfaces of the common lamination layer (42). [2] Device according to claim 1, wherein the first metal layer (34, 50) and the second metal layer (35, 51) have the same thickness. [3] Device according to one of the preceding claims, wherein the first metal layer (34, 50) electrically couples the third contact point of the first power semiconductor chip (10) to the first contact point of the second power semiconductor chip (20). [4] Device according to one of the preceding claims, wherein a surface of the first metal layer (34, 50) forms a first external contact point. [5] Device according to one of the preceding claims, wherein a surface of the second metal layer (35, 51) forms a second external contact point. [6] Device according to claim 1, wherein the first, second and third contact points of the first and second semiconductor chip are source, gate and drain electrodes respectively. [7] Device according to claim 1, wherein the first and second power semiconductor chips are each a power MOSFET, an IGBT, a JFET or a power bipolar transistor. [8] Device according to claim 1, wherein the first power semiconductor chip (10) and the second power semiconductor chip (20) are coupled together in a half-bridge circuit. [9] Device according to claim 1, wherein the first power semiconductor chip (10) and the second power semiconductor chip (20) are of the same size. [10] Procedures, including: Providing a first power semiconductor chip (10) having a first surface (11) and a second surface (12) opposite the first surface, wherein a first contact point and a second contact point are arranged on the first surface (11) and a third contact point is arranged on the second surface (12); Attaching a first metal layer (34) to the second surface (12) of the first power semiconductor chip (10); Providing a second power semiconductor chip (20) having a first surface (21) and a second surface (22) opposite the first surface, wherein a first contact point and a second contact point are arranged on the first surface (21) and a third contact point is arranged on the second surface (22); Attaching a second metal layer (35) to the second surface (22) of the second power semiconductor chip (20); Attaching a first lamination film (40) to the first metal layer (34); and Attaching a second lamination film (41) to the second metal layer (35); and Arranging the first and second power semiconductor chips such that the first surface (11) of the first power semiconductor chip (10) faces in a first direction and the first surface (21) of the second power semiconductor chip (20) faces in a second direction opposite to the first direction, and the first power semiconductor chip (10) is arranged laterally completely outside the outline of the second power semiconductor chip (20); Laminating the first lamination film (40) to the second lamination film (41) to create a common lamination layer (42). [11] Method according to claim 10, further comprising generating through-holes in the lamination layer (42). [12] Method according to claim 11, wherein the vias are electrically coupled to the first and second metal layers. [13] Method according to claim 10, wherein the first, second and third contact points of the first and second power semiconductor chip are source, gate and drain electrodes respectively. [14] Method according to claim 10, wherein the first and second power semiconductor chips are each a power MOSFET, an IGBT, a JFET or a power bipolar transistor.

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