Interface with transmit and receive branch

Abstract

Digital interface for a control gear for a lamp, the interface comprising: - a transmitting and a receiving branch, wherein the receiving branch has a current source (Q1, Q2, R2, R3), - one optocoupler (Q5, Q3) each in the transmitting and receiving branch, whereby the current source (Q1, Q2, R2, R3) feeds the primary side of the optocoupler (Q3) in the receiving branch and - an energy storage device (C1) charged via the current source (Q1, Q2, R2, R3), which feeds the secondary side of the optocoupler (Q5) in the transmitting branch, wherein the energy storage device (C1) is connected in a path which is parallel to a path which comprises the primary side of the optocoupler (Q3) of the receiving branch and a non-linear component, preferably a Zener diode (D9), and wherein the charge of the energy storage device (C1) is independent of a signal applied to the receiving branch.

Description

[0001] The present invention relates to an interface for bidirectional communication with an electronic operating device for at least one lamp and a ballast with such an interface.

[0002] From EP 2 837 096 A1 as well as DE 10 2009 016 904 B4, an interface for DALI control signals is known, which has a transmit and a receive channel, both of which can be operated with a common power source. The circuit according to the latter prior art is described in Fig. 1 shown.

[0003] For both receiving and transmitting DALI signals, the known circuit provides corresponding optocouplers U2, U1, each forming part of a transmitting or receiving branch. Both branches are powered by the common current source Q2, Q3, R3, R4. The circuit also features an energy storage device, which is Fig. 1 is shown as capacitor C2.

[0004] The familiar interface is designed for communication according to the DALI standard, in which a predefined DC voltage is applied to the lines when the bus is inactive. This predefined DC voltage is only reduced when a signal is being transmitted, while the constant DC voltage is applied when no signals are being transmitted.

[0005] According to the current state of the art, capacitor C2 is charged by the DC voltage applied to the bus. This makes sense here because when a signal is transmitted according to the DALI standard, the voltage applied to the bus drops to (logical) zero, or to the voltage defined for the low-level voltage. This can be immediately detected in the return channel (transmit branch) of the circuit.

[0006] "Return channel" refers to the channel away from the interface, the channel for the interface's transmit operation. The "transmit branch" is the signal path of the interface used for transmitting signals.

[0007] However, if signals are to be received from the interface instead of DALI signals according to a protocol where the bus voltage is zero (or very low compared to the DALI standard) in the idle state, the existing interface turns out to be unsuitable. An example of such a standard is the so-called DSI standard.

[0008] The reason for this is that, unlike the DALI standard, the DSI standard specifies that no voltage or a low voltage is applied when the bus is inactive (the "low level," i.e., the low value for transmitting a first logical state, e.g., 0, is specified at < 6.5 volts). The voltage on the bus is only increased when a DSI signal is transmitted.

[0009] If a DSI signal arrives at the connection for the operating device, i.e. on the secondary side of the known interface, the voltage increases suddenly from the value for the first logical state, e.g. < 6.5 volts, to a predetermined direct voltage, e.g. 10 - 15 volts (high level, i.e. the voltage value that is interpreted as the second logical value, e.g. 1). It is now necessary for the incoming signal to be recognized immediately to ensure reliable detection of the DSI signal. With DSI, transmission is Manchester-coded, i.e. a data bit is transmitted by a change from low level to high level (logical 0) or a change from high level to low level (logical 1).

[0010] However, the capacitor C2 from the known circuit has an interfering effect, since the falling edge (logical 1) or the first bit of the DSI signal cannot be reliably detected by the known interface.

[0011] This is because capacitor C2 is partially charged after assuming the high level (for approximately 833 µs) as a result of the 2 mA input current source. If the bus voltage drops below 6.5 volts, capacitor C2 continues to charge. This means that current also flows in optocoupler U2 of the return channel (receive branch), and thus the first logical state (e.g. 1) at the optocoupler output of optocoupler U2 cannot be detected immediately after the voltage drops below 6.5 volts. This is because capacitor C2 is still partially charged even after the voltage drops below the low level and, when not or partially charged, bridges Zener diode Z1, which otherwise immediately interrupts the current flow in optocoupler U2 when the Zener voltage falls below the low level.

[0012] It is therefore an object of the invention to provide an interface which makes it possible to use the principle of energy storage also for protocols in which the bus carries no or only a very low voltage in the idle state.

[0013] The invention solves this problem by providing an interface as claimed in claim 1. Advantageous developments of the invention are the subject of the dependent claims.

[0014] In a first aspect, the invention provides a digital interface for an operating device for a lighting device, the interface comprising: a transmitting branch and a receiving branch, the receiving branch comprising a current source, an optocoupler in each of the transmitting and receiving branches, the current source feeding the primary side of the optocoupler in the receiving branch, and an energy store charged via the current source, which energy store feeds the secondary side of the optocoupler in the transmitting branch, characterized in that the energy store is connected in a path which is parallel to a path which comprises the primary side of the optocoupler of the receiving branch and a non-linear component, preferably a Zener diode.

[0015] The charge of the energy storage device is independent of a signal present at the receiving branch.

[0016] The signal on the receiving branch can be a DALI and / or a DSI signal.

[0017] The transmitting and receiving branches can each be galvanically separated, preferably by an optocoupler fed by the power source.

[0018] An input current of 1.6 mA can be divided between the optocoupler and the energy storage device on the receiving branch, e.g. 1 mA for the optocoupler and 600 µA for charging the energy storage device.

[0019] The charge of the energy storage device can be independent of a falling and / or rising edge of the signal applied to the receiving branch.

[0020] The energy storage device can, for example, have a capacity of 1 to 25 µF.

[0021] The interface may have a resistor connected to the lower potential side of the energy storage device, via which a steepness of a falling edge of the signal applied to the receiving branch in the interface can be adjusted.

[0022] The interface may have a capacitor connected to the lower potential side of the energy storage device, via which a steepness of a rising edge of the signal applied to the receiving branch in the interface can be adjusted.

[0023] The higher potential sides of the capacitor connected to the energy storage device and the resistor connected to it can be connected via a further resistor, and a steepness of a rising edge of the signal applied to the receiving branch in the interface can be adjusted via the connected capacitor and the further resistor.

[0024] A capacitance of the capacitor connected to the energy storage device can be selected such that the monotony of a falling edge of the signal applied to the receiving branch in the interface is independent of an influence of a parasitic drain-source capacitance of a field-effect transistor.

[0025] In a further aspect, the invention provides a ballast with an interface as described above.

[0026] Essential aspects of the invention will now be described with reference to the drawings.

[0027] Showing: Fig. 1 a state-of-the-art interface. Fig. 2 a schematic representation of a circuit arrangement according to the invention. Fig. 3 a simulation result for a signal transmission with the circuit arrangement according to the invention according to Fig. 2. Fig. 4 an enlarged section of the simulation result, which is shown in Fig. 3 is shown. Fig. 5 an enlarged section of Fig. 4. Fig. 6 a further schematic representation of a circuit arrangement according to the invention. Fig. 7 a simulation result for the circuit arrangement from Fig. 6. Fig. 8 an enlarged section of the simulation result from Fig. 7. Fig. 9 an enlarged detail from Fig. 8.

[0028] Fig. Figure 2 shows a circuit arrangement according to the invention. In particular, a field-effect transistor (FET, JFET) J1 and a resistor R7 form a current source J1, R7, which provides a charging current of a predetermined magnitude to an energy storage device, which is referred to below as capacitor C1.

[0029] This ensures, on the one hand, that a constant current (input current minus charging current) ultimately flows through optocoupler Q5. On the other hand, the effect of a nonlinear component, in particular a Zener diode D9, is not bypassed by capacitor C1. Therefore, the term "Zener diode" is used below to represent the nonlinear component. The current distribution is preferably chosen such that the charging current for the capacitor is lower than the current through the optocoupler, preferably in a range of 30% to 70% of the optocoupler current.

[0030] The charging current for capacitor C1 is now tapped at the input of the optocoupler Q5 of the receive path (see measurement point I between diode D6 and optocoupler Q5). The capacitor is therefore part of a path connected in parallel with a path containing the primary side of the receive optocoupler.

[0031] The use of the described current source J1, R7 ensures that a falling edge of a DSI signal, especially the first bit of the DSI command (start bit, logic 1, encoded with a falling edge), is detected quickly and reliably. Because capacitor C1 is not discharged after the high level is applied, it is immediately detected when the voltage drops to the low level. Nevertheless, a common current source can also be used for the return channel and forward channel (receive / transmit branch) in the circuit according to the invention.

[0032] In addition to being used for signal reception according to the DSI standard, the interface according to the invention can also be used for signal reception according to the DALI standard. It is important that the arrangement according to the invention enables, in particular, the very rapid detection of incoming signals, even when the idle state of the bus voltage is close to 0 volts or 0 volts.

[0033] The inventive, in Fig. The circuit arrangement shown in Figure 2 is designed to counteract the negative influence of a current source by using a large-sized capacitor (with a capacitance of, for example, 1-6 µF), which is charged to approximately 5.5 volts or more by the current source via FET J1 and resistor R7. Only a parasitic influence of the drain-source capacitance of FET J1 is present, which can, however, be reduced by appropriately dimensioning the capacitance at the gate.

[0034] Fig. Figure 2 shows a schematic representation of the interface according to the invention with a first primary-side control connection and a second primary-side control connection. A DALI control device SDALI is connected to the primary-side control input on the one hand, and a power switch (not shown) on the other.

[0035] In this case, a resistor R1 is arranged in series with the first primary-side control terminal. A rectifier comprising four diodes D1 to D4 is coupled between the resistor R1 and the second primary-side control terminal.

[0036] A switch X1 is coupled between a first and a second rectifier output terminal, specifically its working electrode-reference electrode path. A current source comprising two bipolar transistors Q1, Q2 and two ohmic resistors R2, R3 is also coupled to the rectifier output terminal. A first optocoupler Q3, which is coupled in series with a Zener diode D9, is coupled to the output of the current source. A series circuit comprising a diode D6, the current source J1, R7 consisting of FET J1 and resistor R7, and a capacitor C1 is connected in parallel with the Zener diode D9. A second optocoupler Q5 is supplied via the current source R7, J1.

[0037] The optocoupler Q3 in the transmitting branch can transmit signals via an output of the interface with a first and a second output connection, while the second optocoupler Q5 in the receiving branch is provided for receiving signals via a signal input with a first and a second signal connection.

[0038] The output of optocoupler Q5 is connected to the control electrode of switch X1, with a diode D13 and a resistor R9 connected in series across this path. A parallel circuit of a capacitor C3 and a resistor R11 is connected in parallel to the control electrode of switch X1, acting as a noise filter. Another bipolar transistor Q4 is connected between capacitor C3 and resistor R11, its base coupled to the higher-potential side of resistor R11.

[0039] By using current source J1, R7 to charge capacitor C1 (which essentially corresponds to capacitor C2 in the known circuit), full functionality is ensured even when transmitting signals according to the DSI standard, since capacitor C1 is no longer charged on a falling edge, as well as according to the DALI standard. Consequently, capacitor C1 is always charged, eliminating the need to bypass Zener diode D9 by maintaining a non-charged or partially charged state on a falling edge.

[0040] After switching on the mains voltage and thus applying a DC voltage at a predetermined level according to the DALI standard (DALI Ein ) the capacitor C1 is charged to approximately 5.5 volts or more in about 400 milliseconds, so that a response to a DALI signal can be sent safely after 600 milliseconds (this corresponds to the DALI standard) from the time of switch-on.

[0041] The charging current is limited to 100 µA, for example, by the current source consisting of FET J1 and resistor R7. However, this value can be higher or lower depending on the components used.

[0042] As a result, the optocoupler Q5 is always driven with a defined current, whereby the current through FET J1 is selected so that in the case of a transmission of a DSI signal, the influence on the bit time, ie the time in which a bit can be sent from the transmitter to the receiver, is small.

[0043] The impact on the bit time is in Fig. 3 and is only noticeable in the simulation result shown at 4 microseconds and a threshold of 2.3 volts. This is negligible with respect to the bit time of the DSI standard of 833 microseconds (µs). This means that the first bit(s) according to the DSI standard are always received correctly. Shown in Fig. 3. At the top, a current waveform for the current at diode D6 (measurement point I), in the middle, waveforms for the voltages at capacitor C1 and the gate of switch X1, and below, the voltage waveform at the + and - measurement points of resistor R1 and diode D3. The time range is shown from 0 to 600 milliseconds.

[0044] The Fig. 4 enlarged view of the range from 410 milliseconds to 450 milliseconds from Fig. 3 shows that, for example, a FET X1 can be sufficiently driven with 5 volts, since the FET used in the simulation already has a resistance R at a temperature of 150°C and a gate voltage of more than 4.5 volts. DS(on) of less than 6 ohms. This allows the low level at the interface input to be kept below 4 volts (less than 2.5 volts in the simulation).

[0045] Fig. 5 shows an enlarged section from Fig. 4. It should be noted that the falling edge of the signal applied to the receiving branch (lower simulation window in Fig. 5) can be adjusted by dimensioning capacitor C3 and resistor R9, while the rising edge of the signal applied to the receiving branch can be adjusted by dimensioning resistor R11. The adjustment of the edges is largely independent of each other.

[0046] The Fig. 6-9 show a simulation result of generated edges for long bus lines (for example, per bus line with a length of about 300m), where the circuit in Fig. 6 is largely identical to the circuit in Fig. 2. The Fig. 6 is again a schematic representation of a circuit according to the invention with an equivalent circuit for simulating the line length.

[0047] Fig. Figure 7 shows a simulation result and the falling and rising edges of transmitted DALI signals. Shown at the top is a current waveform for the current at diode D6 (measurement point I), in the middle are waveforms for the voltages at capacitor C1 and the gate of switch X1, and at the bottom is the voltage waveform at the + and - measurement points of resistor R1 and diode D3.

[0048] Fig. Figure 8 shows an enlarged view of the falling edge. It should be noted that the capacitance of capacitor C3 should be chosen such that the influence of the parasitic drain-source capacitance of FET X1 remains small enough to maintain a monotonic slope. However, it should preferably be chosen large enough to ensure the desired level of resistance to a voltage surge.

[0049] Fig. 9 now shows an enlargement of the simulation area from Fig. 7 for a rising edge. The Fig.The oscillation shown in Figure 9 is caused solely by the cable and the selected cable length of approximately 300m. However, this can be counteracted by setting the slope of the edges as low as possible, i.e., by keeping the slope relatively flat.

[0050] The circuits shown according to the invention can be modified as follows. For example, if the drive voltage for FET X1, i.e., the voltage across C1, is to be increased, an optocoupler Q3 with a drive current of approximately 1 milliampere can be used instead of, say, 5 milliamperes (mA). This can be, for example, a TLP621 or TLP624 optocoupler from Toshiba.

[0051] By reducing the optocoupler current to 1 milliampere, more current (e.g., 600 microamperes) can be allowed to charge capacitor C1, allowing the voltage across C1 to reach its setpoint more quickly and thus reach an even higher value at the time of transmission after 600 milliseconds. Furthermore, diodes D6 and D13 can be replaced with Schottky diodes, which allows the control voltage at the gate of switch X1 to be increased by approximately 0.5 volts if necessary. This then allows the use of a smaller FET X1.

Claims

[1] Digital interface for a control gear for a lamp, the interface comprising: - a transmitting and a receiving branch, wherein the receiving branch has a current source (Q1, Q2, R2, R3), - one optocoupler (Q5, Q3) each in the transmitting and receiving branch, whereby the current source (Q1, Q2, R2, R3) feeds the primary side of the optocoupler (Q3) in the receiving branch and - an energy storage device (C1) charged via the current source (Q1, Q2, R2, R3), which feeds the secondary side of the optocoupler (Q5) in the transmitting branch, wherein the energy storage device (C1) is connected in a path which is parallel to a path which comprises the primary side of the optocoupler (Q3) of the receiving branch and a non-linear component, preferably a Zener diode (D9), and wherein the charge of the energy storage device (C1) is independent of a signal applied to the receiving branch. [2] Interface according to claim 1, wherein the signal on the receiving branch is a DALI and / or a DSI signal. [3] Interface according to one of the preceding claims, wherein the transmitting and receiving branches are each galvanically separated, preferably by an optocoupler (Q5, Q3) fed by the current source (Q1, Q2, R2, R3). [4] Interface according to one of the preceding claims, wherein an input current at the receiving branch is divided such that a charging current of the energy storage device (C1) is lower than the current through the primary side of the optocoupler (Q3) of the receiving branch. [5] Interface according to one of the preceding claims, wherein the charge of the energy storage device (C1) is independent of a falling and / or rising edge of the signal applied to the receiving branch. [6] Interface according to one of the preceding claims, wherein the energy storage device (C1) has a capacity of 1 to 25 µF. [7] Interface according to one of the preceding claims, wherein the interface has a resistor (R11) connected to the lower potential side of the energy storage device (C1), via which a steepness of a rising edge of the signal applied to the receiving branch can be adjusted in the interface. [8] Interface according to one of the preceding claims, wherein the interface has a capacitor (C3) connected to the lower potential side of the energy storage device (C1), via which a steepness of a preferably falling edge of the signal applied to the receiving branch can be adjusted in the interface. [9] Interface according to one of the preceding claims, wherein the higher-potential side of the capacitor (C3) connected to the energy storage device (C1) and the resistor (R11) connected thereto are connected via a further resistor (R9), and wherein a steepness of a preferably falling edge of the signal applied to the receiving branch can be adjusted in the interface via the connected capacitor (C3) and the further resistor (R9). [10] Interface according to one of the preceding claims, wherein a capacitance of the capacitor (C3) connected to the energy storage device (C1) is selected such that the monotony of a falling edge of the signal applied to the receiving branch in the interface is independent of an influence of a parasitic drain-source capacitance of a field-effect transistor (X1). [11] Ballast for lamps, in particular gas discharge lamps, LEDs or OLEDs, with an interface according to one of the preceding claims. [12] Luminaire comprising a light source, in particular a gas discharge lamp, LEDs or OLEDs, and a ballast according to claim 11. [13] Building technology bus system, comprising at least one bus subscriber with an interface according to one of claims 1 to 10.

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