SEMICONDUCTOR COMPONENT

Abstract

Semiconductor device comprising: a semiconductor body (100); a source region (13), a body region (14) and a drift region (11) having a first drift region section (111) and a second drift region section (112), wherein the body region (14) is arranged in the semiconductor body (100) between the source region (13) and the drift region (11), and wherein the second drift region section (112) adjoins the first drift region section (111) in a vertical direction of the semiconductor body (100); a gate electrode (21) adjacent to the body region (14) and dielectrically insulated from the body region (14) by a gate dielectric (22), wherein the first drift region section (111) adjoins the gate dielectric (22); a diode region (15) of a semiconductor type complementary to the semiconductor type of the drift region (11) in the semiconductor body (100); and a source electrode (30) electrically connected to the source region (13), the body region (14) and the diode region (15), wherein the source electrode (30) is at least partially arranged in a trench extending adjacent to the source region (13), the body region (14) and the first drift region portion (111) at or into the diode region (15), wherein the diode region (15) is arranged in the drift region (11) in the vertical direction of the semiconductor body (100) below the trench of the source electrode (30), wherein a semiconductor region (16) of the same doping type as the diode region (15) is arranged between the first drift region section (111) and the source electrode (30), and wherein the semiconductor region (16) extends from the diode region (15) to the body region (14).

Description

[0001] The present invention relates to a semiconductor component, in particular a semiconductor component comprising a vertical transistor component and a diode connected in parallel with the transistor component.

[0002] Power transistors, which are transistors with voltage ratings up to several hundred volts and high current carrying capacity, can be implemented as vertical trench transistors. In this case, a gate electrode of the transistor is arranged in a trench extending in a vertical direction in the semiconductor body. The gate electrode is dielectrically insulated from the source, body, and drift regions of the transistor and laterally borders the body region of the semiconductor body. Typically, a drain region borders the drift region, and a source electrode is connected to the source region. Such power transistors are described, for example, in US 2006 / 0 060 916 A1 or US 6 057 558 A.

[0003] In many applications, it is desirable to have a diode connected in parallel with a load path (drain-source path) of the transistor. A body diode of the transistor can be used for this purpose. The body diode is formed by a pn junction between the body region and the drift region. To connect the body diode in parallel with the load path of the transistor, the body region can simply be electrically connected to the source electrode. However, the body diode may have a lower current carrying capacity than desired for some applications.

[0004] Power transistors can be realized using conventional semiconductor materials such as silicon (Si) or silicon carbide (SiC). Thanks to the specific properties of SiC, the use of SiC enables the realization of power transistors with higher dielectric strengths (for a given on-state resistance) than silicon. However, high blocking voltages result in high electric fields in the semiconductor body, particularly at the pn junction between the body region and the drift region. Typically, sections of the gate electrode and the gate dielectric are located near this pn junction. However, problems can arise if the dielectric strength of the gate dielectric is insufficient to achieve the desired dielectric strength of the semiconductor device. In this case, the gate dielectric can break down prematurely.

[0005] STARKE, Ulrich; Non-basal plane SiC surfaces: Anisotropic structures and low-dimensional electron systems. In: Phys. Status Solidi B 246, No. 7, 2009, pp. 1569-1579, describes 4H-SiC and its crystal properties. The object underlying the invention is to provide a semiconductor component with a transistor component and a diode, in which a gate electrode of the transistor is protected from high electric fields and in which the diode has a high current carrying capacity and low losses, as well as to provide a method for producing such a semiconductor component.

[0006] This object is achieved by a semiconductor device according to claim 1, claim 2 or claim 3. Specific embodiments are recited in the dependent claims.

[0007] Examples are explained below using drawings. The drawings serve to illustrate the basic principle, so only those aspects necessary for understanding the basic principle are shown. The drawings are not to scale. In the drawings, the same reference numerals refer to the same features. Fig. 1 illustrates a vertical cross-sectional view of a vertical transistor device according to a first embodiment. Fig. 2 illustrates a top view of the semiconductor device of Fig. 1. Fig. 3 illustrates a modification of the semiconductor device of Fig. 1. Fig. 4 (the Fig. 4A to 4L) illustrates an embodiment of a method for manufacturing a vertical transistor device as described in the Fig. 1 and Fig. 2 is shown. Fig. 5 (the Fig. 5A and Fig. 5B) illustrates a method for providing a semiconductor body as used in the method in Fig. 4A to 4L is used. Fig. 6 illustrates a vertical cross-sectional view of a vertical transistor device according to a second embodiment. Fig. 7 (the Fig. 7A to 7L) illustrates an embodiment of a method for manufacturing a vertical transistor device as described in Fig. 6 is shown. Fig. 8 illustrates a vertical cross-sectional view of a vertical transistor device according to another embodiment. Fig. 9 (the Fig. 9A to 9Q) illustrates an embodiment of a method for manufacturing a vertical transistor device according to Fig. 8.

[0008] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.

[0009] Fig. 1 illustrates a vertical cross-sectional view of a semiconductor device, specifically a vertical semiconductor device and, more specifically, a vertical transistor device with an integrated diode. The semiconductor device comprises a semiconductor body 100. In the semiconductor body 100, the semiconductor device comprises a source region 13, a body region 14, and a drift region 11, wherein the drift region 11 has a first drift region portion 111 and a second drift region portion 112. The source region 13 and the drift region 11 are spaced apart from one another in the vertical direction of the semiconductor body 100, wherein the body region 14 is arranged between the source region 13 and the drift region 11. The second drift region portion 112 adjoins the first drift region portion 111 in the vertical direction of the semiconductor body 100. The “vertical direction” is a direction that is perpendicular to a first (main) surface 101 of the semiconductor body 100.The cutting plane shown in . Fig. 1 is perpendicular to this first surface 101.

[0010] Referring to Fig. 1, the semiconductor component further comprises a gate electrode 21, which is arranged adjacent to the body region 14 and which is dielectrically insulated from the body region 14 by a gate dielectric 22. The gate electrode 21 is arranged in a trench extending from the first surface 101 into the semiconductor body and extends through the source region 13 and the body region 14 to or into the first drift region portion 111.

[0011] Referring to Fig. 1, the semiconductor component further comprises a drain region 12 adjacent to the drift region 11. Optionally, a field stop region (not shown) of the same doping type as the drift region 11 but more highly doped than the drift region 11 can be arranged between the drift region 11 and the drain region 12. The drain region 12 is electrically conductively connected to a drain terminal D (in Fig. 1 only shown schematically), wherein the gate electrode 21 is connected to a gate terminal G and the source region 13 is connected to a source terminal S. The source region 13 is connected to the source terminal S by means of a source electrode 30, which is electrically conductively connected to the source region 13 and the body region 14 of the semiconductor component.

[0012] At least a portion 301 of the source electrode 30 is arranged in a further trench. This trench extends from the first surface 101 through the source region 13, the body region 14, and the first drift region portion 111 to a diode region 15. The diode region 15 is spaced apart from the body region 14 in the vertical direction of the semiconductor body 100, such that the diode region 15 is "buried" in the drift region 11. Furthermore, the diode region 15 has a doping type that is complementary to the doping type of the drift region 11. The trench portion 301 of the source electrode 30 is electrically conductively connected to the source region 13 and the body region 14 via sidewalls of the trench and is electrically conductively connected to the diode region 15 at the bottom of the trench.Optionally, the source electrode 30 is also arranged above the first surface 101 of the semiconductor body 100 and is electrically conductively connected to the source region 13 in the region of the first surface 101. An insulation layer 23 on the gate electrode 21 electrically insulates the source electrode 30 from the gate electrode 21.

[0013] Referring to Fig. 1, a barrier layer insulation is formed between the first drift region section 111 and the source electrode 30 in the trench. For this purpose, a semiconductor region 16 with a doping type complementary to the doping type of the first drift region is arranged between the first drift region section 111 and the source electrode 30. Referring to the illustration in the right-hand section in Fig. 1, this semiconductor region 16 may be provided only in the first drift region section 111. According to a further embodiment shown in the left section in Fig. 1, the semiconductor region 16, which has the same doping type as the body region 14 and the diode region 15, may also be present in the body region 14 and the diode region 15. The semiconductor region 16 may have a higher doping concentration than the body region 14 and the diode region 15 and may help provide ohmic contact between the source electrode 30 and the body region 14 and the diode region 15.

[0014] The first drift region section 111 and the second drift region section 112 may have the same doping concentration or different doping concentrations. According to one embodiment, the first drift region section 111 has a higher doping concentration than the second drift region section 112. The doping concentration of the second drift region section 112 is, for example, between 1E14 cm -3 and 1E16 cm -3. The first drift region section 111 has a doping concentration which is, for example, between the doping concentration of the second drift region section 112 and a few E17 cm -3 such as 5E17 cm -3 .

[0015] Optionally, the drift region 11 may have a third drift region section 114, which adjoins the first drift region section 111 on one side and the second drift region section 112 on the opposite side and which adjoins the diode region 15. The doping concentration of the third drift region section 114 may be in the same range as the doping concentration of the first drift region section 111 (e.g., between 1E14 cm -3 and 1E16 cm -3 ). The doping concentrations of the first and second drift region sections 111, 112 may be the same or different. The doping concentration of the body region 14 is, for example, between 5E16 cm -3and 5E17 cm -3 . The doping concentrations of the source and drain regions 13, 12 are, for example, greater than 1E19 cm -3 The doping concentration of the diode region 15 is, for example, between 1E18 cm -3 and 1E19 cm -3 . The doping concentration of the semiconductor region 16 is, for example, between 1E19 cm -3 and 1E20 cm -3 .

[0016] The transistor component made of Fig. 1 is a MOS transistor component. The transistor component can be implemented as an n-conducting or p-conducting component. In an n-conducting component, the source region 13 and the drift region 11 are n-doped, whereas the body region 14 is p-doped. In a p-conducting component, the source region 13 and the drift region 11 are p-doped, whereas the body region 14 is n-doped. The transistor component can be implemented as an enhancement device or as a depletion device. In an enhancement device, the body region 14 borders the gate dielectric 22. In a depletion device, there is a channel region 17 of the same doping type as the source region 13 and the drift region 11 along the gate dielectric.This channel region 17 extends from the source region 13 to the drift region 11 along a gate dielectric 22 and can be depleted of charge carriers when the transistor component is in the off state. Alternatively, the gate dielectric 22 contains fixed charges that cause the formation of a conductive channel in the body region 14 along the gate dielectric when the gate control voltage (gate-source voltage) is zero. Furthermore, the semiconductor component can be implemented as a MOSFET or as an IGBT. In a MOSFET, the drain region 12 has the same doping type as the source region 13 and the drift region 11, whereas in an IGBT, the drain region 12 has a doping type complementary to the doping type of the drift region 11. In an IGBT, the drain region 12 is also referred to as the collector region.

[0017] In the semiconductor device, which is Fig. As shown in Figure 1, the diode region 15, the drift region 11, and the drain region 12 form a diode connected in parallel to a load path (drain-source path) DS of the MOS transistor. A circuit symbol for this diode is shown in Fig. 1 is also shown (the polarity of the circuit symbol in Fig. 1 refers to an n-type semiconductor device; in a p-type device, the polarity is reversed. This diode blocks when a voltage of a first polarity is applied between the drain and source terminals D, S, and conducts when a voltage of a second polarity is applied between the drain and source terminals D, S. In an n-type semiconductor device, the diode blocks when a positive voltage is applied between the drain and source terminals D, S, and conducts when a negative voltage is applied between the drain and source terminals D, S (which is a positive voltage between the source and drain terminals S, D). The diode is connected in parallel to the body diode of the MOS transistor, the body diode being the diode formed by the body region 14 and the drift region 11.However, unlike the body diode, the properties of the additional diode can be adjusted largely independently of the properties of the MOS transistor. In particular, the additional diode can be implemented to have a high current carrying capacity if the buried diode region 15 is implemented such that the pn junction between the diode region 15 and the drift region 11 has a relatively large area.

[0018] The semiconductor component can be realized with a plurality of identical component cells 10. In Fig. 1, two of these device cells are shown. Each device cell comprises a source region 13, a body region 14, a gate electrode 21, a gate dielectric 22, and a diode region 15, as well as a trench portion 301 of the source electrode 30. Referring to Fig. 1, two adjacent device cells 10 may share a gate electrode 21 and two adjacent device cells may share a trench portion 301 of the source electrode 30 and a diode region 15. In the embodiment in Fig. 1, the component cell is divided into the right section Fig. 1, the gate electrode 21 with the component cell shown in the left section in Fig. 1, and shares the trench section 301 of the source electrode 30 and the diode region 15 with the device cell 10 on the right (this device cell is not completely in Fig. 1). The individual component cells share the drift region 11 and the drain region 12, wherein the first drift region section 111 has several sections separated from each other by the trenches with the source electrode 30, wherein each of these sections is common to two component cells. In the embodiment in Fig. 1, two adjacent component cells are symmetrical with respect to either a central line (axis of symmetry) CL1 (shown as a dotted line in Fig. 1) passing through the gate electrode 21, or a central line CL2 (shown as a dotted line in Fig. 1), which runs through the trench section 301 of the source electrode 30. In the embodiment in Fig. 1, the highlighted component cell (the one designated by reference numeral 10) is symmetrical to the component to its left with respect to the central line CL1, and the component cell is symmetrical to the component cell to its right with respect to the central line CL2.

[0019] The individual component cells are connected in parallel in that the gate electrodes 21 of the individual component cells are connected to the gate terminal G and the source electrode 30 is connected to the source regions 13, the body regions 14 and the diode regions 15 of the individual component cells.

[0020] The semiconductor component made of Fig. 1 can be operated like a conventional MOS transistor by applying a load voltage between the drain and source terminals D, S and a control voltage to the gate electrode G. This operating principle is briefly explained using an n-type semiconductor component. However, this operating principle also applies to a p-type semiconductor component, although in this case the polarity of the voltages, which will be explained below, must be reversed. The semiconductor component is in the forward-biased state when a load voltage is applied between the drain and source terminals D, S, which reverse-biases the body diode and the additional diode. This voltage is a positive voltage for an n-type component.In the forward biased state, the semiconductor device can be switched on and off by the control voltage applied to the gate terminal G, wherein the semiconductor device is switched on when the control voltage applied to the gate terminal G creates a conductive channel 17 in the body region 14 between the source region 13 and the drift region 11, and the semiconductor device is switched off when the conductive channel 17 is interrupted.

[0021] The semiconductor device is in the reverse biased state when a voltage is applied between the drain and source terminals D, S, which forward biases the body diode and the additional diode. In this operating state, the semiconductor device can only be controlled by the polarity of the load voltage, but not by the control voltage applied to the gate terminal G.

[0022] When the semiconductor device is in the forward-biased state and when the semiconductor device is turned off, a pn junction between the diode region 15 and the drift region 11 and a pn junction between the body region 14 and the drift region 11, more precisely the first drift region section 111, are reverse-biased, so that a depletion region spreads in the drift region 11. As the load voltage increases, the depletion region spreads deeper toward the drain region 12 into the drift region 11. As the load voltage increases and the depletion region spreads deeper into the drift region 11, the strength of the electric field at the pn junctions also increases. Since one of these pn junctions, namely the pn junction between the body region 14 and the first drift region section 111, is close to the gate dielectric 22, the gate dielectric 22 may be damaged when high load voltages are applied, so that high field strengths may occur.In the semiconductor device according to . Fig. 1, the diode regions 15 of two adjacent component cells, together with the drift region 11, act as a JFET (Junction Field Effect Transistor). This JFET has a channel region 113 below the gate electrode 21. When the load voltage increases and the electrical potential of the drift region 11 increases, the JFET pinches off the channel region 113, thus preventing a further increase in the field strength of an electric field at the pn junction between the body region 14 and the first drift region section 111 as the load voltage continues to rise. The load voltage at which the channel 113 of the JFET is pinched off depends, for example, on the distance between two adjacent diode regions 15 in the lateral direction of the semiconductor body 100. The "lateral direction" of the semiconductor body 100 is perpendicular to the vertical direction. The distance is, for example, between 0.5 □m and 2 □m or between 0.25 times and 1.5 times the width of the gate electrode 21.In the example shown in . Fig. 1, the diode region 15 of each transistor overlaps the corresponding gate electrode 21 in the horizontal direction, so that the distance between two adjacent diode regions 15 is smaller than the width of the gate electrode 21. In this case, each body region 14 is completely overlapped by a diode region 15. The "width of the gate electrode 21" is the dimension of the gate electrode 21 between two body regions 14.

[0023] The semiconductor body 100 may comprise a conventional semiconductor material, in particular a wide bandgap semiconductor material such as silicon carbide (SiC) or the like. Fig. The component structure illustrated in Figure 1 is particularly suitable for semiconductor components implemented using SiC technology. If the semiconductor body 100 comprises SiC, for example, the gate dielectric 22 can be implemented as silicon oxide (SiO2). A gate dielectric 22 made of SiO2 can be increasingly damaged when exposed to the high field strengths that can occur in high-voltage components. In such components, the JFET formed by the diode regions 15 and the drift region 11 effectively protects the gate dielectric 22 when the semiconductor component is turned off and a high load voltage is applied between the drain and source terminals D, S. In the reverse-biased state, the additional diode, which is directly connected to the source electrode 30, is a highly efficient, low-loss diode connected in parallel with the load path of the MOS transistor.

[0024] Referring to Fig. 2, which shows a horizontal cross-sectional view of the semiconductor body 100 in a horizontal section plane AA, which in Fig. 1, the individual device cells can be realized as elongated device cells. In this case, the source regions 13, the body regions 14, the gate electrode 21, and the trench sections 301 of the source electrode 30 are elongated device structures. Referring to Fig. 2, the individual gate electrodes 21 may be electrically conductively connected to one another by a connecting electrode 28. The connecting electrode 28 may be arranged in a trench that extends perpendicular to the trenches with the gate electrodes 21 and that is electrically connected to the body regions 14 (and the source regions 13, which are outside the view in Fig. 2) is insulated by an insulating layer 29. In this embodiment, the connecting electrode 28 is connected to the gate terminal G.

[0025] Alternatively, the gate electrodes 21 extend with their longitudinal ends to the surface 101 of the semiconductor body 100, where they are connected to the gate terminal G.

[0026] Referring to Fig. 1, the source electrode 30 may comprise multiple electrode layers, such as a first electrode layer 31 in contact with the diode region 15, the body region 14, and the source region 13, and a second electrode layer 32 covering the first electrode layer 31. The first electrode layer 31 contains, for example, titanium (Ti), platinum (Pt), nickel alloys, or the like. The second electrode layer 32 contains, for example, aluminum (Al), copper (Cu), or the like.

[0027] Fig. 3 shows a modification of the semiconductor device according to Fig. 1. In the semiconductor device according to Fig. 3, a Schottky diode is connected in parallel with the body diode 14 and the further diode. The Schottky diode is formed by a Schottky contact between the source electrode 30 and a portion of the drift region 11 that extends through the body region 15 to the bottom of the trench with the source electrode 30. At least at the bottom of the trench section 301, where the trench section 301 touches the drift region 11, the trench section 301 can contain titanium, tungsten, nickel, or platinum to form a Schottky contact with the drift region.

[0028] A first embodiment of a method for producing a semiconductor device according to Fig. 1 is based on Fig. 4A to 4L below. These figures illustrate vertical cross-sectional views of the semiconductor body 100 during various steps of the process.

[0029] Referring to Fig. 4A, a semiconductor body 100 is provided in first method steps. The semiconductor body 100 comprises a first semiconductor layer 11 of a first doping type, a second semiconductor layer 14 of a second doping type complementary to the first doping type of the first semiconductor layer 11, and a third semiconductor layer 13 of the first doping type on the second semiconductor layer 14. The first semiconductor layer 11 forms the drift region of the semiconductor component obtained by the process, the second semiconductor layer 14 forms the body region, and the third semiconductor layer 13 forms the source region. For illustration purposes and for better understanding, the reference numerals of the semiconductor layers correspond to the reference numerals of the semiconductor regions formed by them in the semiconductor component. Referring to Fig. 4A, the semiconductor body 100 further comprises at least one diode region 15 of the second doping type in the first semiconductor layer 11, which is spaced from the second semiconductor layer 14.

[0030] Referring to the Fig. 5A and Fig. 5B, the manufacture of the semiconductor body 100 from Fig. 4A the provision of a semiconductor substrate 110 of the first doping type ( Fig. 5A) and implanting doping atoms of the second doping type into the semiconductor substrate 110 by means of an implantation mask 201, so that the at least one diode region 15 is formed ( Fig. 5B). These regions of the semiconductor substrate 110, which are not doped during the implantation and / or the diffusion process, form the second drift region section 112 of the semiconductor device, wherein the drain region 12 (not shown in Fig. 5A) by an implantation process. Alternatively, the substrate 110, which is shown in Fig. 5A, an epitaxial layer grown on a highly doped semiconductor substrate forming the drain region 12.

[0031] Based on the structure described in Fig. 5B, the semiconductor body can be made of Fig. 4A by forming an intermediate semiconductor layer 111 of the first doping type on the substrate 110 by forming the first layer 14 on the intermediate layer 111 and the second layer 13 on the first layer 14. The intermediate layer 111 forms the first drift region section 111. The optional third drift region section (114 in Fig. 1 and Fig. 3) can be produced by implanting dopant atoms into the semiconductor substrate 110 before or after forming the diode regions 15.

[0032] The semiconductor layers formed on the substrate 110 are, for example, epitaxial layers that can be doped in-situ during the epitaxial process. Alternatively, the second semiconductor layer 13, which forms the source region of the semiconductor device, is formed by an implantation process in the first semiconductor layer, which forms the body region 14. According to a further alternative, the intermediate layer forming the first drift region portion 111 can be omitted if the diode region 15 is formed by an implantation process so that it is located away from a surface 111 of the semiconductor substrate 110. In this case, a semiconductor region of the substrate 110 between the diode region 15 and the surface 111 forms the first drift region portion 111.

[0033] Each of the implantation processes explained above and below requires an activation process that activates the implanted doping atoms. The activation process comprises a temperature process in which at least those regions of the semiconductor body 100 into which doping atoms have been implanted are heated to an activation temperature. For SiC, the activation temperature is, for example, between 1500°C and 1800°C. An activation process can be performed for each implantation process. However, it is also possible to perform an activation process after two or more implantation processes have been performed. According to one embodiment, doping atoms are activated before dielectric layers, such as the gate dielectric layers 22 made of Fig. 1, can be produced.

[0034] Referring to Fig. 4B, at least two trenches 131, 132 are formed in the semiconductor body 100, namely a first trench 131 to form the gate electrode (21 in Fig. 1) and a second trench 132 to form the trench section (301 in Fig. 1) to form the source electrode. The trenches 131, 132 are formed by an etching process using an etching mask 201. The trenches 131, 132 are formed such that they extend from the first surface 101 of the semiconductor body 100 through the source region 13, the body region 14, to or into the first drift region section 111.

[0035] In the next step, which is Fig. As shown in Figure 4C, a protective layer 202 is formed on the bottom and sidewalls of the first trench 131, and the second trench 132 is extended deeper into the semiconductor body 100 such that the second trench 132 reaches or into the diode region 15. To extend the second trench 132 deeper into the semiconductor body 100, an etching process is used, which is, for example, an etching process that etches away the semiconductor material of the semiconductor body 100 and also the etching mask 201. This results in beveled sidewalls of the second trench 132. The protective layer that protects the first trench 131 comprises, for example, a photoresist that is not etched during the etching process. According to one embodiment, the etch mask 201 and the semiconductor material of the semiconductor body 100 are etched with a selectivity of approximately 1:1 in the etching process, which means that these materials are etched equally in this process.In general, the selectivity is between about 2:1 and about 1:2.

[0036] Referring to Fig. 4D, the semiconductor region 16, which forms a pn junction with the first drift region section 111, is formed in the second trench 132. The formation of this semiconductor region 16 may include an implantation process in which doping atoms are introduced at least into the drift region section 111 at the sidewalls of the second trench 132. In the embodiment shown in Fig. 4D, the semiconductor region 16 is formed on the sidewalls and the bottom of the second trench 132 in the source region 13, the body region 14, the first drift region portion 111 and the diode region 15.

[0037] In the next steps of the process, which will be Fig. 4E and Fig. 4F, the etching mask 201 and the protective layer 202 are removed ( Fig. 4E) and a dielectric layer 22' is formed on the semiconductor structure with the first and second trenches 131, 132, namely on the first surface 101 and on the sidewalls and bottoms of the first and second trenches 132. This dielectric layer 22' forms a gate dielectric of the semiconductor device. Furthermore, an electrode layer 21' is deposited on the dielectric layer 22'. The electrode layer 21' completely fills the first and second trenches 131, 132 and covers the dielectric layer 22' above the first surface 101 in the present embodiment. The electrode layer 21' may comprise only one electrode material. According to one embodiment, the electrode layer comprises a plurality of sublayers (not shown) that are deposited one above the other.

[0038] The dielectric layer 22' may comprise an oxide, such as a semiconductor oxide, and may be formed by a deposition process. According to one embodiment, the semiconductor material of the semiconductor body 100 is SiC, whereas the gate dielectric is a silicon oxide (SiO2). The electrode layer comprises an electrically conductive material, such as a metal or a highly doped polycrystalline semiconductor material, such as polysilicon.

[0039] In the next steps of the process, which will be Fig. 4G, the first surface 101 of the semiconductor body 100 is exposed, and an insulation layer 23' is formed above the first surface 101. Exposing the first surface may comprise a planarization process, such as chemical mechanical polishing (CMP), mechanical polishing, or chemical polishing. In this process, the electrode layer 21' is divided into a plurality of electrode sections, and the dielectric layer 22' is divided into a plurality of layer sections. A first layer section 22 of the dielectric layer 22' in the previous first trench 131 forms a gate dielectric, and a first layer section of the electrode layer 21' on the gate dielectric 22 forms the gate electrode. The gate electrode 21 and the gate dielectric 22 remain in the first trench 131, whereas electrode sections 21" and dielectric sections 22" in the second trench 132 represent sacrificial layers that are ultimately removed.

[0040] In the next steps of the process, which will be Fig. 4H, the insulation layer 23' is patterned. Patterning the insulation layer 23' may include forming an etch mask 203 on those portions of the insulation layer 23' that are to remain and etching the insulation layer 23' in the portions not covered by the etch mask 203. Etching the insulation layer 23' may further include etching portions of the semiconductor body 100 that are not covered by the etch mask 203, and of the electrode layer 21" and the dielectric layer 22" in the second trench 132. In the embodiment shown in Fig. 4H, the etching of the semiconductor body 100 comprises etching away the regions of the source regions 13 that are not covered by the etch mask 203 to expose the body region 14 on the first surface 101. The etching process that etches the insulation layer 23' and the etching process that etches the semiconductor body 100 may be anisotropic etching processes, such that at the end of the etching process, a sidewall of the etch mask 203 and sidewalls of the insulation layer 23 of the source region 13 are aligned with each other.

[0041] Referring to Fig. 4l, in the next process steps, the remaining sections 21" of the electrode layer and the dielectric layer are removed from the trenches 132.

[0042] Next steps in the process, which are Fig. 4J to 4L include the fabrication of the source electrode 30. Referring to Fig. 4J, these method steps may include exposing portions of the source region 13 below the etch mask 203. This may include etching the insulation layer 23 using an isotropic etching process. As a result of this process, a portion of the source region 13 adjacent to the first surface 101 is exposed. This process may further include removing the dielectric layer 22" from the bottom and sidewalls of the second trench 132.

[0043] In the next steps of the process, which will be Fig. 4K, the contact layer 31 is formed on the bottom and sidewalls of the second trench 132 and on the source and body regions 13, 14 on the first surface 101. This process may include depositing a first contact layer 311 on those regions not covered by the etch mask. The first contact layer 311 may comprise silicon (Si), polysilicon, nickel, or aluminum (Al). The first contact layer 311 is deposited on the bottom and sidewalls of the second trench 132 and on those portions of the body region 14 not covered by the etch mask 203. Furthermore, a second contact layer 312 is formed on the first contact layer 311. A vapor deposition or sputtering process may be used to form the second contact layer 312. Therefore, the second contact layer 312 is also formed on the source region 13 below the etching mask 203.The second contact layer 312 comprises, for example, Ni. 1-x Al x .

[0044] Finally, the etching mask 203 is removed, and an alloy is formed between the contact layer 31 and the semiconductor material of the semiconductor body 100. The second contact layer 32 is formed on the first contact layer and the insulation layer 32 to complete the source electrode 30. Forming the alloy comprises, for example, an RTP (Rapid Thermal Annealing) process that heats at least the regions where the alloy is formed to temperatures between approximately 800°C and 1000°C for a duration of between approximately 1 minute and 2 minutes. The second contact layer 32 comprises, for example, titanium (Ti) and aluminum (Al).

[0045] Fig. 6 shows a vertical cross-sectional view of a vertical semiconductor device according to another embodiment, which is a modification of the embodiment of Fig. 1. In the embodiment of Fig. 1, gate electrodes 21, body regions 14, and trenches with the source electrode 301 are arranged alternately, so that a gate electrode 21 and each adjacent trench section 301 are separated from each other by a body region 14. In other words, two adjacent device cells 10 are symmetrical with respect to the common gate electrode 21 or symmetrical with respect to the common trench section 301. Body regions 14 border the gate dielectric 22 on both sides of the gate electrode 21.

[0046] In the semiconductor device in Fig. 6, the individual device cells are identical, but neighboring device cells are not symmetrical. Each device cell comprises a source region 13, a body region 14, a first portion 111 of a drift region, a gate electrode 21, and a gate dielectric 22 separating the gate electrode 21 from the body region 14, a diode region 15, and the trench portion 301 of the source electrode 30. In contrast to the embodiment of Fig. 1, a body region 14 adjoins the gate electrode 21 only on one side. The body region 14 is located between the gate electrode 21 of a device cell and the trench and the source electrode of an adjacent device cell. An insulation layer 23 is arranged between the side of the gate electrode 21 facing away from the body region 14 and the source electrode 30. In the semiconductor device of Fig. 6, the channel regions in the body regions have the same orientation in each device cell with respect to the orientation of the semiconductor crystal of the semiconductor body 100. The channel region is the region of the body region 14 that borders the gate dielectric 22.

[0047] According to one embodiment, the semiconductor body 100 comprises SiC, and the channel region is an a-plane of the crystal lattice of the SiC semiconductor body. It is generally known that an a-plane in a SiC semiconductor body is superior to other planes in the SiC crystal lattice with regard to electron mobility. This allows improved device properties to be achieved in a transistor device in which the individual channel regions are arranged in an a-plane compared to conventional transistor devices using SiC technology.

[0048] As with the semiconductor device according to Fig. 1, the trench section 301 of the source electrode 30 extends deeper into the semiconductor body than the gate electrode 21 and is electrically connected to the diode region 15. However, this is only an example. According to a further embodiment (not shown), the gate electrode 21 extends deeper into the semiconductor body 00 than the trench section 301 of the source electrode 30. A pn ​​junction is present between the trench section 301 of the source electrode 30 and the first drift region section 111. Everything that is described with regard to the semiconductor device according to Fig. 1, applies to the semiconductor device according to Fig. 6. In addition, the semiconductor device according to Fig. 6 can be easily modified to include a Schottky diode at the bottom of the trench with the source electrode, as shown in Fig. 3 is explained.

[0049] An embodiment of a method for producing a semiconductor device of the type described in Fig. 6 shown type, is shown below using the Fig. 7A to 7L. Referring to Fig. 7A, the method begins with providing the semiconductor body 100 with the first semiconductor layer 11 of the first doping type, the second semiconductor layer 14 of the second doping type on the first semiconductor layer, and the third semiconductor layer 13 of the first doping type on the second semiconductor layer 14, and with the at least one buried diode region 15 of the second doping type in the first semiconductor layer 11. As in the previously explained embodiment, the first semiconductor layer 11 forms the drift region of the semiconductor component, the second semiconductor layer 14 forms the body region, and the third semiconductor layer 13 forms the source region. The semiconductor body 100 with the first, second, and third semiconductor layers 11, 14, and 13 and with the buried diode region 15 can be formed as described with reference to Fig. 4A, Fig. 5A and Fig. 5B. As in the previously explained embodiment, the drift region 11 may have a more highly doped region 114 in which the diode region 15 is embedded.

[0050] In the next steps, the result of which will be Fig. 7D, first trenches 141 are formed in the semiconductor body 100. The first trenches 141 extend from the first surface 101 of the semiconductor body 100 through the source region 13 and the body region 14 to or into the first drift region portion 111. The first trenches 141 may be formed to have sloped sidewalls, i.e., sidewalls that define an angle α, different from 90°, with the first surface 101 of the semiconductor body 100. According to one embodiment, the angle α is between 91° and 100°, in particular between 92° and 98°. In a semiconductor body 100 comprising SiC, the angle α corresponds to the angle between the 100-plane in the SiC crystal and the c-axis (hexagonal major axis) in the SiC crystal.

[0051] Referring to the Fig. 7B and Fig. 7C, the formation of the first trenches 141 may include an etching process using a first etch mask 301 on the first surface 101 of the semiconductor body 100 and a second etch mask 302 on the first etch mask 301. The first etch mask is, for example, an oxide, while the second etch mask 302 is, for example, a photoresist. First, the second etch mask is patterned, as shown in Fig. 7C. Then, in a first etching process, the first etching mask 301 is structured using the second etching mask 302, such that the second etching mask 301 has sloped sidewalls. The end of this process is shown in Fig. 7D in dashed lines. At the end of this process step, a portion of the first etch mask 301 may remain on the first surface 101 of the semiconductor body 100. Furthermore, corners between the bottom and sidewalls of the first etch mask 301 may be rounded using an etching process. In a second process step, the semiconductor body 100 is then etched down to the first drift region portion 111 using the first etch mask 301. Since the first etch mask 301 has sloped sidewalls, the trench etched into the semiconductor body 100 using the first etch mask 301 also has sloped sidewalls. Each of the first trenches 141 has a first sidewall 1411 and a second sidewall 1412 opposite the first sidewall 1411.

[0052] In the next steps of the process, which Fig. 7E, the first trenches 141 are partially filled with a protective layer 303 covering the sidewalls 1412 and a part of the bottom portion of the trenches 141. The protective layer 303 comprises, for example, a photoresist. This protective layer 303 leaves a portion of the source region 13 on the first surface 101 and portions of the first drift region portion 111 at the bottom of the first trenches 141 uncovered (cf. Fig. 7E).

[0053] Referring to Fig. 7F, a second trench 142 is formed in each first trench 141 by etching the first trench 141 at the bottom down to the diode region 15. In the Fig. 7F, the source region 13 is removed in those portions that are uncovered on the first surface 101. In addition, the semiconductor region 16 of the second doping type is formed on the first sidewalls 1411 at least in the first drift region portion 111. In the embodiment according to Fig. 7, the semiconductor region 16, which forms a pn junction with the first drift region section 111, is formed in the body region 14, the first drift region section 111, and the diode region 15. The doping concentrations of the drift region 11, the drain region 12, the source region 13, and the body region 14 may correspond to the doping concentration of the corresponding device regions explained above.

[0054] Referring to Fig. 7G, the protective layer 303 is removed and a dielectric layer 22' is deposited uniformly on the semiconductor structure, i.e., on the first surface 101 and the bottom and sidewalls of the first and second trenches 141, 142. The first and second trenches 141, 142 adjoin one another in this embodiment. In other words, there is a trench with two trench sections, namely a first trench section in which the gate electrode will be formed, and a second trench section in which the source electrode will be formed, wherein the second trench section may extend deeper into the semiconductor body than the first trench section. According to a further embodiment, the second trench section does not extend deeper into the semiconductor body than the first trench section. An electrode layer 21' is formed on the dielectric layer 22'.

[0055] In the next steps of the process, which Fig. 7H, the electrode layer 21' is etched such that portions of the electrode layer 21 remain along the first sidewall 1411 and the second sidewall 1412, with the electrode portion along the second sidewall forming the gate electrode 21. The dielectric layer 22' along the second sidewall 1412 forms the gate dielectric. Furthermore, an insulation layer 24 is formed, covering the gate electrode 21. The insulation layer 24 may be deposited to completely cover the semiconductor structure.

[0056] Referring to Fig. 7l, an etch mask 304 is formed on the insulating layer 24. The etch mask 304 is formed to leave the insulating layer 24 exposed above the first sidewall 1411 and above portions of the first surface 101 adjacent to the first sidewall 1411. Using the etch mask 304, the insulating layer 24 is removed from the first surface 1411, a bottom portion adjacent to the first sidewall 1411, and above a portion of the first surface 101, and the portion of the electrode layer 21 along the first sidewall 1411 is removed.

[0057] The result of this processing is in Fig. 7J. An etching process for etching the insulating layer 24 may be an isotropic etching process, such that portions of the insulating layer 24 below the etch mask 304 are also removed. In other words, the etch mask 304 is undercut. During this etching process (or a subsequent etching process), the dielectric layer 22' is also removed from the second sidewall 1412, the bottom portion adjacent to the first sidewall 1411, and the first surface 101.

[0058] In the next steps of the process, which Fig. 7K, the first electrode layer 31 is formed on those portions of the surface of the semiconductor body 100 that are not covered by the etching mask 304, while the etching mask is still present. The formation of the first electrode layer 21 may involve the formation of the first and second contact layers 311, 312 with the methods previously described with reference to FIG. Fig. 4K explained procedural steps.

[0059] Referring to Fig. 7L, the etch mask 304 is finally removed and the second electrode layer 32 is formed to complete the source electrode 30.

[0060] Fig. Figure 8 illustrates a modification of the semiconductor device according to Fig. 6. While in the semiconductor device according to Fig. 6 the diode region 15 overlaps the body region 14, the diode region 15 overlaps in the semiconductor device according to Fig. 8, the body region 14 is not. In addition, in the semiconductor device according to Fig. 8, the sidewall of the trench in which the gate electrode 21 is arranged and along which the channel region extends is not beveled, but vertical. However, the semiconductor device according to Fig. 8 can also be manufactured with a bevelled side wall of the gate electrode trench.

[0061] An embodiment of a method for producing the semiconductor device according to Fig. 8 is shown below using the Fig. 9A to 9Q explained.

[0062] Referring to Fig. 9A, a semiconductor body 100 is provided with a first semiconductor layer 11 of a first doping type, a second semiconductor layer 14 of a second doping type on the first semiconductor layer 11, and a third semiconductor layer 13 of the first doping type on the second semiconductor layer 14. The second and third semiconductor layers 14, 12 may be formed using an epitaxial growth process on the first semiconductor layer 11. According to a further embodiment, a semiconductor body with a basic doping of the first semiconductor layer 11 is provided, and the second and third semiconductor layers 13, 14 are formed using implantation and / or diffusion processes. The first semiconductor layer 11 may have two sublayers: a first sublayer forming the second drift region portion 112 and a second sublayer forming the first drift region portion 111.The drift region section 111 can be formed as an epitaxial layer on the second drift region section 112 before forming the second and third semiconductor layers 14, 14. According to a further embodiment, the first drift region section 111 is formed using an implantation process. In this embodiment, the semiconductor body forming the base of the semiconductor body 100 has a basic doping that corresponds to the doping of the second drift region section 112.

[0063] In the next process steps, which are Fig. 9B and Fig. 9C, at least one diode region 15 is formed in the first semiconductor layer 11, which forms the drift region of the semiconductor device. Forming the diode region 15 comprises forming a trench 151 extending through the second and third semiconductor layers 14, 13, which form the body and source regions, to or into the drift region 11. The trench 151 may be formed using an etch mask 401 ( Fig. 9B). After forming the trench 151, dopant atoms are implanted into the bottom of the trench 151. A distance between the bottom of the trench and the diode region 15 can be adjusted via the implantation energy in the implantation process. Optionally, a scattering layer 402, such as an oxide, is formed at least at the bottom of the trench before the dopant atoms are implanted.

[0064] The next steps correspond to those previously described using the Fig. 7E to 7L. These steps include: Producing the protective layer 303 on the first side wall 1511 and a portion of the bottom of the trench 151 ( Fig. 9D); etching the semiconductor body at the bottom of the trench 151 and in those regions of the first surface 101 that are not covered by the protective layer 303 ( Fig. 9E); forming the semiconductor region 16 at least in the drift region portion 111 which is uncovered in the trench ( Fig. 9F); removing the protective layer 303 ( Fig. 9G); and producing the dielectric layer 22' and the electrode layer 21' ( Fig. 9H).

[0065] In contrast to the Fig. 7A to 7L, the gate electrode 21 is formed from its electrode layer 21' using a further etch mask 305 covering those remaining regions of the electrode layer 21'. Using the etch mask 305, the electrode layer 21' is removed above a first surface 1511 of the trench, above those bottom portions of the trench 151 where the trench 151 extends down to the diode region 15, and above portions of the first surface 101. The result of this etching process is shown in Fig. 9J. After the gate electrode 21 has been formed, the etch mask 305 is removed, and the insulation layer 24 is formed on the gate electrode 21. The insulation layer 24 may be deposited anywhere on the semiconductor structure, including the bottom and the first sidewall 1511 of the trench. The dielectric layer 22' may still cover the first sidewall 1511 and the bottom of the trench 151 at this stage of the manufacturing process.

[0066] Referring to Fig. 9M, a further etching mask 304 is added to the previously Fig. 7K. Using this etch mask 304, the insulation layer 24 and the dielectric layer 22' are removed from the bottom portion of the trench adjoining the diode region 15 and from portions of the first surface 101 of the semiconductor body to expose the semiconductor region 16 along the first sidewall 151, and along the bottom of the trench 151 to expose the source region 13 on the first surface 101. In the next method steps, the source electrode 30 is formed. These method steps correspond to the previously described method steps with reference to the Fig. 7K and Fig. 7L and include: producing the first electrode layer 31 with the first and second contact layers 311, 312 ( Fig. 9P) and forming the second electrode layer 32 on the first electrode layer 31 ( Fig. 9Q).

[0067] Some aspects of the above description are summarized below using numbered examples.

[0068] Example 1. A semiconductor component comprising: a semiconductor body; in the semiconductor body: a source region, a body region, and a drift region having a first drift region portion and a second drift region portion, wherein the source region and the drift region are spaced apart in a vertical direction of the semiconductor body, wherein the body region is arranged between the source region and the drift region, and wherein the second drift region portion adjoins the first drift region portion in the vertical direction of the semiconductor body; a gate electrode adjacent to the body region and dielectrically insulated from the body region by a gate dielectric; a diode region of a semiconductor type complementary to the semiconductor type of the drift region, wherein the drift region is arranged in the drift region and spaced apart from the gate electrode in a vertical direction of the semiconductor body;a source electrode electrically connected to the source region, the body region, and the diode region, wherein at least a first portion of the source electrode is disposed in a trench extending adjacent to the source region, the body region, and a first portion of the drift region to the diode region;

[0069] Example 2. Semiconductor device according to Example 1, wherein the diode region overlaps the gate electrode in a lateral direction of the semiconductor body.

[0070] Example 3. Semiconductor device according to Example 1, wherein a semiconductor region of the same doping type as the diode region is arranged between the first portion of the drift region and the first portion of the source electrode.

[0071] Example 4. The semiconductor device of example 1, further comprising: a Schottky contact between the first source electrode portion and the second portion of the drift region.

[0072] Example 5. Semiconductor device according to Example 1, wherein the first drift region section has a higher doping concentration than the second drift region section.

[0073] Example 6. The semiconductor device of example 1, further comprising: a plurality of device cells, each device cell comprising a source region, a body region, a first drift region portion, a gate electrode, a gate dielectric, and a diode region.

[0074] Example 7. The semiconductor device of example 6, wherein two adjacent device cells share a gate electrode and wherein two adjacent device cells share a first source electrode portion.

[0075] Example 8. The semiconductor device according to example 6, wherein the first source electrode portion of each device cell is separated from the gate electrode of the corresponding device cell by an insulating layer.

[0076] Example 9. The semiconductor device according to example 8, wherein the semiconductor body comprises a SiC crystal and wherein an interface between the body region and the gate dielectric is an a-plane of the SiC crystal.

[0077] Example 10. Semiconductor component according to one of the preceding examples, in which the first drift region section and the body region are epitaxially grown semiconductor regions.

[0078] Example 11. The semiconductor device according to Example 10, wherein the source region is an epitaxially grown semiconductor region.

[0079] Example 12. The semiconductor device according to any one of examples 1 to 9, wherein the first drift region portion, the body region, and the source region are implantation regions.

[0080] Example 13. A method for manufacturing a semiconductor device, the method comprising: providing a semiconductor body having a first semiconductor layer of a first doping type, a second semiconductor layer of a doping type complementary to the first doping type on the first semiconductor layer, a third semiconductor layer of the first doping type on the second semiconductor layer, and at least one first semiconductor region of the second doping type in the first semiconductor layer, which is spaced apart from the second semiconductor layer in a vertical direction of the semiconductor body; forming a first trench extending through the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer;Producing a first electrode that is adjacent to at least a portion of the second semiconductor layer in a lateral direction of the semiconductor body and that is dielectrically insulated from this portion of the second semiconductor layer by a dielectric layer; Producing a second trench that extends through the third semiconductor layer, the second semiconductor layer, and a portion of the first semiconductor layer to the at least one first semiconductor region; Producing a second electrode at least in the second trench, wherein the second electrode electrically contacts the at least one first semiconductor region at a bottom of the second trench and the second semiconductor layer at least at one sidewall of the second trench.

[0081] Example 14. The method of Example 13, further comprising: prior to forming the second electrode, forming a second semiconductor layer of the second doping type in regions of the first semiconductor layer exposed at a sidewall of the second trench to form a junction isolation between the second semiconductor layer and the second electrode.

[0082] Example 15. The method of Example 13, wherein providing the semiconductor body comprises: providing a first sublayer of the first semiconductor layer; forming at least one first semiconductor region in the first sublayer; forming a second sublayer of the first semiconductor layer on the first sublayer; forming the second layer on the first semiconductor layer; and forming the third layer on the second semiconductor layer.

[0083] Example 16. The method of Example 15, wherein second and third semiconductor layers are grown epitaxially.

[0084] Example 17. The method of Example 15, wherein forming the second and third semiconductor layers comprises: forming an epitaxial semiconductor layer on the first semiconductor layer; and performing at least one implantation and / or diffusion process to introduce dopant atoms into the epitaxial semiconductor layer to form at least one of the third and second semiconductor layers.

[0085] Example 18. The method of Example 13, wherein providing the semiconductor body comprises: providing the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer before forming the second trench; and forming the at least one first semiconductor region after forming the second trench at the bottom of the second trench and before forming the second electrode.

[0086] Example 19. The method of Example 18, wherein at least one of the second and third semiconductor layers is formed using an implantation and / or diffusion process.

[0087] Example 20. The method of example 13, wherein the first trench and the second trenches are spaced apart in a lateral direction of the semiconductor body.

[0088] Example 21. The method of Example 13, wherein the first and second trenches are formed to be adjacent to each other.

[0089] Example 22. The method of Example 21, wherein an insulating layer is formed between the first electrode and the second electrode.

[0090] Example 23. The method of Example 21, wherein a semiconductor material of the semiconductor body is SiC and wherein the first trench is formed such that a sidewall of the trench adjacent to the portion of the second semiconductor layer lies in an a-plane of a semiconductor crystal of the semiconductor body.

[0091] Example 24. The method of example 21, wherein forming the first and second trenches comprises: forming the first trench; forming the second trench by extending a portion of the first trench deeper into the semiconductor body.

[0092] Of course, features of the various exemplary embodiments described herein may be combined with one another unless otherwise stated.

Claims

[1] Semiconductor device comprising: a semiconductor body (100); a source region (13), a body region (14) and a drift region (11) having a first drift region section (111) and a second drift region section (112), wherein the body region (14) is arranged in the semiconductor body (100) between the source region (13) and the drift region (11), and wherein the second drift region section (112) adjoins the first drift region section (111) in a vertical direction of the semiconductor body (100); a gate electrode (21) adjacent to the body region (14) and dielectrically insulated from the body region (14) by a gate dielectric (22), wherein the first drift region section (111) adjoins the gate dielectric (22); a diode region (15) of a semiconductor type complementary to the semiconductor type of the drift region (11) in the semiconductor body (100); and a source electrode (30) electrically connected to the source region (13), the body region (14) and the diode region (15), wherein the source electrode (30) is at least partially arranged in a trench extending adjacent to the source region (13), the body region (14) and the first drift region portion (111) at or into the diode region (15), wherein the diode region (15) is arranged in the drift region (11) in the vertical direction of the semiconductor body (100) below the trench of the source electrode (30), wherein a semiconductor region (16) of the same doping type as the diode region (15) is arranged between the first drift region section (111) and the source electrode (30), and wherein the semiconductor region (16) extends from the diode region (15) to the body region (14). [2] Semiconductor device comprising: a semiconductor body (100); a source region (13), a body region (14) and a drift region (11) having a first drift region section (111) and a second drift region section (112), wherein the body region (14) is arranged in the semiconductor body (100) between the source region (13) and the drift region (11), and wherein the second drift region section (112) adjoins the first drift region section (111) in a vertical direction of the semiconductor body (100); a gate electrode (21) adjacent to the body region (14) and dielectrically insulated from the body region (14) by a gate dielectric (22), wherein the first drift region section (111) adjoins the gate dielectric (22); a diode region (15) of a semiconductor type complementary to the semiconductor type of the drift region (11) in the semiconductor body (100); and a source electrode (30) electrically connected to the source region (13), the body region (14) and the diode region (15), wherein the source electrode (30) is at least partially arranged in a trench extending adjacent to the source region (13), the body region (14) and the first drift region portion (111) at or into the diode region (15), wherein the diode region (15) is arranged in the drift region (11) in the vertical direction of the semiconductor body (100) below the trench of the source electrode (30), wherein a semiconductor region (16) of the same doping type as the diode region (15) is arranged between the first drift region section (111) and the source electrode (30), and wherein the semiconductor component further comprises a Schottky contact between the first source electrode (30) and the second drift region portion (112). [3] Semiconductor device comprising: a semiconductor body (100); a source region (13), a body region (14) and a drift region (11) having a first drift region section (111) and a second drift region section (112), wherein the body region (14) is arranged in the semiconductor body (100) between the source region (13) and the drift region (11), and wherein the second drift region section (112) adjoins the first drift region section (111) in a vertical direction of the semiconductor body (100); a gate electrode (21) adjacent to the body region (14) and dielectrically insulated from the body region (14) by a gate dielectric (22), which is arranged in a first trench (131), wherein the first drift region section (111) adjoins the gate dielectric (22); a diode region (15) of a semiconductor type complementary to the semiconductor type of the drift region (11) in the semiconductor body (100); and a source electrode (30) electrically connected to the source region (13), the body region (14) and the diode region (15), wherein the source electrode (30) is at least partially arranged in a second trench (132) extending adjacent to the source region (13), the body region (14) and the first drift region portion (111) at or into the diode region (15), wherein the diode region (15) is arranged in the drift region (11) in the vertical direction of the semiconductor body (100) below the trench of the source electrode (30), wherein a semiconductor region (16) of the same doping type as the diode region (15) is arranged between the first drift region section (111) and the source electrode (30), and wherein the first trench (131) with the gate electrode (21) extends deeper into the semiconductor body than the second trench (132) with the source electrode (30). [4] Semiconductor component according to claim 2 or 3, wherein the semiconductor region (16) is further arranged between the body region (14) and the source electrode (30). [5] Semiconductor component according to claim 2 or 3, wherein the semiconductor region (16) extends from the diode region (15) to the body region (14). [6] Semiconductor component according to one of claims 1 to 5, wherein the diode region (15) overlaps the gate electrode (21) in a lateral direction of the semiconductor body (100). [7] A semiconductor device according to claim 1 or 3, further comprising: a Schottky contact between the first source electrode (30) and the second drift region portion (112). [8] Semiconductor component according to one of the preceding claims, wherein the first drift region section (111) has a higher doping concentration than the second drift region section (112). [9] A semiconductor device according to any one of the preceding claims, further comprising: a plurality of component cells (10), each component cell (10) having a source region (13), a body region (14), a first drift region portion (111), a gate electrode (21), a gate dielectric (22) and a diode region (15). [10] A semiconductor device according to claim 9, wherein two adjacent device cells (10) share a gate electrode (21) and wherein two adjacent device cells (10) share a first source electrode portion (311). [11] A semiconductor device according to claim 9, wherein the first source electrode portion (311) of each device cell (10) is separated from the gate electrode (21) of the corresponding device cell (10) by an insulation layer. [12] Semiconductor component according to one of the preceding claims, wherein the semiconductor body (100) comprises a SiC crystal. [13] A semiconductor device according to claim 12, wherein an interface between the body region (14) and the gate dielectric (22) is an a-plane of the SiC crystal. [14] Semiconductor component according to one of the preceding claims, wherein the first drift region section (111) and the body region (14) are epitaxially grown semiconductor regions. [15] Semiconductor component according to claim 12, wherein the source region (13) is an epitaxially grown semiconductor region. [16] Semiconductor component according to one of claims 1 to 12, wherein the first drift region portion (111), the body region (14) and the source region (13) are implantation regions.

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