Device for operating passive infrared sensors

Abstract

Device for operating a passive infrared (PIR) detector with a first connection (IN) and a second connection (IP), the device comprising: - an electrical circuit arrangement (R G ), wherein the electrical circuit arrangement (R G ) forms a leakage resistance between the first terminal (IN) and the second terminal (IP) of the passive infrared detector (PIR) to discharge the first terminal (IN) and the second terminal (IP) of the passive infrared detector (PIR); wherein the electrical circuit arrangement (R G ) includes a switch-capacitor circuit with transfer gates and storage capacities; and the device is set up for this purpose: - the transfer gates of the electrical circuit arrangement (R G) to switch alternately with a first clock (φ1) and a second clock (Φ2), and to advance a charge quantity by one node with each half-clock using the storage capacities, whereby the first clock (φ1) and the second clock (Φ2) do not overlap and, apart from the non-overlap, the first clock (φ1) is the inverse of the second clock (Φ2); and - to switch off the first clock (φ1) and the second clock (Φ2) during a measurement phase, so that the device is in a measurement state and the charge flow through the electrical circuit arrangement (R G ) is prevented.

Description

Introduction

[0001] Various methods are known for measuring infrared radiation. One key sensor principle is the use of passive infrared detectors (PIR detectors).

[0002] These are characterized by their simple and cost-effective manufacturing. Such PIR detectors can be designed as two-terminal devices and can be symbolized in the equivalent circuit diagram by a current source that carries a current I. PIR depending on the change in irradiation and thus the temperature, it delivers a capacity C PIR is connected in parallel. (See also Fig. 1.)

[0003] Several problems can occur when evaluating the signal from a PIR sensor: Firstly, the operating point of the PIR detector can shift due to self-charging. Secondly, the power source I PIRTypically, it only carries a very small current at a relatively high internal resistance. This internal resistance R PIR is in Fig. Figure 1 is shown as an example. These boundary conditions result in the requirement for a large dynamic range and a very high internal resistance for the subsequent amplifier and analog-to-digital converter circuit (evaluation circuit).

[0004] Due to the high internal resistance of an evaluation circuit, once generated, charges cannot dissipate. This can cause the circuit to leave the operating range of the evaluation circuit, as it becomes overloaded.

[0005] Patent application US 2013 / 0082179 A1 describes an object detection device with an I / V conversion circuit comprising an operational amplifier, a capacitive element and a discharge circuit. Object of the invention

[0006] The object of the invention is to provide a device for operating a passive infrared detector that enriches the state of the art.

[0007] This problem is solved by a device according to claim 1. Optional embodiments are the subject of the dependent claims, the description, and the figures. Description of the invention

[0008] A device for operating a passive infrared (PIR) detector with a first terminal and a second terminal is provided. The device comprises an electrical circuit arrangement, wherein the electrical circuit arrangement forms a discharge resistor between the first and second terminals of the passive infrared (PIR) detector for discharging the first and second terminals of the passive infrared (PIR) detector. The electrical circuit arrangement includes a switch-capacitor circuit with transfer gates and storage capacitors.The device is configured to alternately switch the transfer gates of the electrical circuit arrangement with a first clock and a second clock, and to advance a quantity of charge by one node with each half-clock using the storage capacities, whereby the first clock and the second clock do not overlap and, apart from the non-overlap, the first clock is the inverse of the second clock. Furthermore, the device is configured to switch off the first clock and the second clock during a measurement phase, so that the device is in a measurement state and the charge flow through the electrical circuit arrangement is interrupted.

[0009] The circuit arrangement can have two strands and can furthermore be configured to operate the strands of the circuit arrangement offset by one half-cycle, thereby generating a continuous charge outflow.

[0010] The device is optionally designed such that a discharge current through the electrical circuit arrangement during the discharge of the first terminal and the second terminal of the passive infrared detector (PIR) depends on an input voltage between the first terminal and the second terminal of the passive infrared detector (PIR).

[0011] The device can also be configured to control the first clock and / or the second clock for discharging the first terminal and the second terminal of the passive infrared detector (PIR) in such a way that the discharge takes place depending on the input voltage.

[0012] The device can also be configured to switch the switching arrangement into the measuring state before a measurement and to switch the switching arrangement into a state with lower resistance than the measuring state after the measurement has ended.

[0013] The device can also be configured to form a working resistance of the switching arrangement greater than 1 MOhm in the measuring state in order to prevent the flow of charge.

[0014] The device may further include the passive infrared detector (PIR) with the first terminal and the second terminal.

[0015] The device can further comprise a differential amplifier with a first input transistor and a second input transistor, wherein the first terminal of the passive infrared detector (PIR) is connected to the first input transistor and the second terminal of the infrared detector (PIR) is connected to the second input transistor.

[0016] A system according to an optional embodiment is in Fig. Figure 1 shows the passive infrared detector (PIR) connected to a discharge network R via its two connecting leads. GThis is connected to an analog-to-digital converter (ADC). The output of the analog-to-digital converter is connected via a first bus (T) with a first bus bandwidth to a digital filter (DF), whose output (Out) typically has a larger second bus bandwidth than the first bus bandwidth.

[0017] It was recognized that input charging can be a significant obstacle to the correct operation of the system. As will be explained further later, the ΔΣ converter (ADC) can be sensitive to such operating point drift. However, this increased sensitivity of the ΔΣ converter (ADC) can enable particularly efficient suppression of quantization errors by the ΔΣ converter (ADC) comparator. Therefore, the ΔΣ converter and the discharge of the passive infrared detector can be combined using a discharge network (R). G) form a unit. Based on this finding of faulty input charging, a simple solution to this problem can optionally be achieved by discharging the input nodes via a switch when the voltage at the detector reaches the dynamic range. In this case, optionally no evaluation of the voltage at the detector can be performed during and shortly after the discharge. Alternatively, the discharge can optionally be carried out via a leakage resistor between the sensor terminals or from the terminals to reference ground (R). dis_1 , R dis_2This can be done in conjunction with continuous signal attenuation and the detector's inherent noise. Furthermore, it can implement a giga-ohm resistor in a low-cost CMOS technology. During development, it was discovered that discharging the second output through the internal resistance of the PIR sensor's (PIR) current source does not yield satisfactory results. It has been found that, optionally, the resistance value of these leakage resistors should be greater than 1 MΩ and / or preferably greater than 10 MΩ and / or preferably greater than 100 MΩ and / or preferably greater than 1 GΩ and / or preferably greater than 10 GΩ. The optimal leakage value depends on the specific PIR detector and application and should be adjusted accordingly.In the case of large charge displacements due to rapid temperature changes (temperature shock), disproportionately low leakage resistance values ​​would optionally be necessary, which would almost eliminate the signal to be detected.

[0018] It is clear that the leakage resistances of the discharge network (R) GThe leakage resistors should preferably be identical and as symmetrical as possible, or "matched" in technical terms. These leakage resistors can also be more complex circuits that only perform the function of a leakage resistor among other things. It has been found to be advantageous to implement the leakage resistors, at least partially, as switched-capacitor circuits. With such circuits, the potentially required relatively high-impedance leakage resistors can be implemented relatively easily. For the operation of such a switched-capacitor network, it is particularly advantageous if these networks are operated with a non-overlapping two-phase clock. Of course, single-phase and multi-phase clocks can also be used, but these are generally more complex to implement.

[0019] The requirement for reliable discharge of the PIR detector can conflict with the need for the highest possible input resistance of the evaluation circuit. It was therefore recognized that it can be advantageous to make the average equivalent resistance of at least the discharge resistors of the passive infrared detector dependent on whether or not a measurement of the infrared radiation potential is currently being performed using the passive infrared sensor (PIR detector). Before a measurement, the discharge resistors can optionally be switched to a very high-resistance state (measurement state). After the measurement, the discharge resistors can optionally be switched to a state with a lower resistance compared to the measurement state. Alternatively, the state of charge (voltage across the detector) can optionally be measured, and the value of the discharge resistors can optionally be adjusted accordingly.

[0020] It is conceivable that other operating conditions might also optionally require switching. For example, it is possible to discharge the PIR detector in a defined manner via a switch. In such a mode, switching the discharge resistors to high resistance would also be optionally useful. In extreme cases, the measurement state could therefore optionally mean completely disconnecting a discharge resistor.

[0021] The resistance values ​​are optionally based on average values ​​over several clock cycles of the operating clock of the respective switched-capacitor network, provided such a network is used to implement the discharge resistors. The discharge resistors of the PIR detector can assume different values ​​depending on the states of the sensor system; at least the states "measurement" and "no measurement / discharge" should be implemented.

[0022] The ΔΣ converter (ADC) optionally includes a differential amplifier. Unlike conventional differential amplifiers, whose current source is not symmetrically divided between two branches with symmetrical drive of the differential amplifier transistors, this amplifier optionally features a current divider instead of the usual common junction for the transistors in the differential amplifier branches and the operating current source. This current divider distributes the current differently depending on an external control value. It can be assumed that the operating current source has a finite internal resistance. Therefore, the use of a real voltage source is also possible. This current divider is implemented in a device by a resistor network, one end of which is connected to one transistor of the differential amplifier and the other end to the other transistor of the differential amplifier.A multiplexer optionally connects the operating current source to a node of this resistor chain, depending on the external control value. The current divider thus optionally behaves like a digitally controlled potentiometer, whose tap is set by the external parameter.

[0023] This allows for different current feedback to be set for the various branches of the differential amplifier. The current division can be configured such that the gate-source voltages of the transistors adjust themselves through the voltage drop across the resistors of the current divider, ensuring that the sum of the currents through the two branches equals the current of the operating current source. The other terminals of the transistors can each be connected to a load resistor. It has proven particularly advantageous to implement these load resistors as actual current sources, as this results in a particularly high differential load resistance and thus a particularly high differential gain. Capacitors can be connected in parallel with these load resistors to integrate the output signal. The use of Miller capacitors is also conceivable.In the case of the ΔΣ converter, these capacitors perform the summing Σ function of the ΔΣ converter, thus eliminating the quantization error caused by a downstream comparator.

[0024] The following optional method is available for operating a passive infrared detector: Each output of the passive infrared detector is connected to the control input of a corresponding input transistor of the differential amplifier described. One contact of each of these input transistors is connected to a corresponding current divider output of a controllable current divider. This current divider distributes the current from a reference current source (I). refThe current divider outputs are distributed across the transistors depending on a control input. The other contacts of the transistors are each connected to a load resistor, preferably an integrating filter, or a capacitor (C1, C2). The output values ​​of these integrating filters, load resistors, and capacitors are then compared by at least one comparator. This comparator introduces an unavoidable quantization error, which is minimized by the feedback described below. The comparator output signal is connected to a digital integrating filter, which performs a second integration in addition to the aforementioned capacitors. The control input of the current divider, which divides the current from a power source, is connected to the output of the digital integrating filter.If the current divider is controlled analogously, a digital-to-analog converter (DAC) and / or a signal format converter is required to convert the output signal of the digital integrating filter into a suitable format. However, this is not necessary in the example described here, as the multiplexer can be controlled digitally.

[0025] A similar approach may be required when adapting a digital control input for the current divider to the digital output of the digital integrating filter.

[0026] In addition to this two-phase version, a single-phase version of an evaluation circuit can also be used. Here, one output of the passive infrared detector controls at least one second current source. This second current source feeds current into a first node (S). b ) one. This first node (S b) is connected via an integrating filter to the input of a comparator, which measures the signal level of this first node (S). b ) compares with an internal level. The output of this comparator is again directly or indirectly connected to the aforementioned digital integrating filter and thus controls it. The output of this digital integrating filter then controls a digital-to-analog converter (DAC). The output of this digital-to-analog converter then controls a first current source (I1), which in turn also supplies its current to the first node (S). b ) feeds in.

[0027] Unlike the previous version, in this version one terminal of the passive infrared detector is connected to ground, while the other terminal is connected to the previously described evaluation circuit. Such a circuit is also suitable for evaluating thermopiles.

[0028] For both methods, it can be advantageous if the digital integrating filter is implemented as an up / down counter that counts at a predetermined or programmable rate during measurement phases. The counting direction is preferably determined by the comparator output. The counting step size and the time intervals at which counting occurs can also be constant and predetermined or programmable. In some applications, it has proven useful to make the counting step size dependent on the counter value itself, in order to prevent over- or under-counting and thus total malfunction.

[0029] If the counter reading exceeds a critical upper limit, this can be detected, triggering an exit from the measurement state and activating the discharge state of the detector element. This can be particularly useful with the one-handed version, as it is capable of measuring the absolute level of an input signal. The output of the digital integrating filter represents the measured value.

[0030] It can be advantageous to place another digital filter (DF) after the digital integrating filter before using the measured value. This can suppress quantization errors above a certain cutoff frequency.

[0031] It can be shown that the quantization error becomes zero at a frequency of 0 Hz in the interference spectrum and approaches a finite value for infinitely high frequencies. The cutoff frequencies can depend significantly on the aforementioned load capacitances (C1, C2) and the resistance (R). M) of the current divider and thus be properly adjusted.

[0032] It can be advantageous to run significant parts of this process in a signal processor. The input stages can then be implemented in specially designed electronics. Such a device is then optionally capable of carrying out the process described above.

[0033] The following section explains optional embodiments and optional features with reference to the accompanying figures: Fig. Figure 1 shows the basic components of a passive infrared detector device according to an optional embodiment. The device consists of a passive infrared detector (PIR) connected to the discharge network R. GThe discharge network is coupled. Its task is to eliminate charge buildup on the PIR detector and maintain it at an operating point favorable to the subsequent analog-to-digital converter without impacting the system's dynamics. The analog-to-digital converter transforms the discharge network's signal into a first digital signal on a bus T with a first bus width (number of bits). A subsequent digital filter (DF) filters the signal on the first bus T and outputs the data at a higher resolution via an output bus (Out). Therefore, the output bus Out typically has a larger bus width than the first bus T. Fig. Figure 2 shows the unclaimed equivalent circuit of a passive infrared (PIR) detector according to an optional embodiment with an equivalent power source (I). PIR ) and a series circuit of parasitic detector capacitance (C PIR ) and associated loss resistance R PIR_Cas well as the internal resistance of the equivalent current source (R PIR ). This internal resistance of the current source (R PIR ) lies parallel to the power source (I PIR ) and is typically very high. Excessive load on the detector therefore causes the output voltage to collapse. Fig. Figure 3 shows a one-handed version of the analog-to-digital converter (ADC). Fig. 1 according to an optional embodiment. A first controlled current source (I1) (also referred to as the second current source) is controlled by the feedback path and feeds into the first node (Sb). A second controlled current source (I2) (also referred to as the current source) is controlled by an output of the passive infrared detector and also feeds into the first node (Sb). b ) the sum of the two current source currents charges a capacitor (C). 1b) charges or discharges them. If the control loop is stable, the second current source (I2) supplies a current with the opposite sign but the same magnitude as the first current source (I1). The comparator (CP) b ) is connected to its input via this capacitor (C 1b ) connected and compares the voltage value across this capacitor and thus at the first node (S b ) with an internal comparison value. The enumerator / counter (Int) b In this example, ) now counts either up or down by one with each system clock cycle, depending on whether the input of the comparator (CP) b ) above or below the switching threshold of the comparator (CP) b ) is located. 6 bits of the counter value of the up / down counter (Int bThese 6 bits are used, for example, for feedback. In this example, these 6 bits are converted into an analog signal by a digital-to-analog converter (DAC), which controls the other current source (I1). A digital filter (DF) filters the counter value of the up / down counter (Int b ) to the output signal (Out), which is the output bus of the digital filter DF. Fig. Figure 4 also shows a one-handed version of the analog-to-digital converter (ADC). Fig. 1 according to an optional embodiment. However, instead of the controllable current source, the single source of the single reference signal is now implemented such that the counter reading (Val) of the up / down counter (Int) b ) now the tap (IN FB ) at a resistance cascade (R FB) controlled by individual resistors (not shown). This tap can then be fed to a differential transconductance amplifier, which has a current output (CS). The current outputs each charge and discharge a capacitor (C1, C2). The resulting voltages across the capacitors (C1, C2) are compared by a comparator (CP), which in turn controls the counter (Int). b ) controls. Fig. Figure 5 shows a controllable current divider according to an optional embodiment as part of a differential stage according to an optional embodiment consisting of the resistor chain of n resistors R M1 to R Mn , which are typically, but not necessarily, implemented identically. Of the n+1 taps of the resistor chain in this example, one is selected by an analog multiplexer (MUX) and connected to the operating current source (I). refThe bus width of the control bus (Val) of the analog multiplexer (Mux) must be chosen to be sufficiently large and should typically be greater than the logarithm of the n-base 2. The current divider, the current source, and the transistors (T1, T2) form a differential stage. Fig. 6 Shows the difference level Fig. 5 with two work resistors (R L1 , R L2 ) according to an optional embodiment. It is obvious that the current divider resistors (R M1 to R Mn This results in different current feedback for the two branches of the differential amplifier. This different current feedback is set by the control signal (Val). In this example, two example outputs (ON, OP) are shown. Fig. 7 shows the difference level from Fig. 6 as part of a construction accordingly Fig. 3 according to an optional embodiment. Instead of the operating resistances (R L1 , R L2 ) out of Fig. Six capacitors (C1, C2) are each connected in parallel with a load resistor (R1, R2). The passive infrared sensor (PIR) is connected to terminals IN and IP according to the Fig. 1 and Fig. 2 connected. Fig. 8 corresponds Fig. 7 with the difference that the resistors (R1, R2) are replaced by real current sources (I W1 , I W2) are replaced. This has the advantage that they exhibit increased differential resistance. When implemented as an integrated semiconductor circuit, this design represents a robust solution against parametric fluctuations. The design is very simple and therefore consumes very little power. At the same time, it exhibits a very high input resistance. Since the source connections follow the respective gate voltages (on average) via the negative feedback through the current divider, the gate-source voltages do not fluctuate. Therefore, the complex input impedances are very high. The gate-source capacitances do not need to be significantly recharged. The quantization noise of the analog-to-digital converter decreases with an increasing number n of resistors R. Mi less. The points mentioned above represent significant advantages over the state of the art. Fig. Figure 9 shows a possible implementation of the discharge circuit RG out of Fig. 1 or the discharge resistors (R dis_1 , R dis_2 ) in Fig. 1 according to an optional embodiment. These resistors optionally have a relatively high resistance value and are optionally as similar as possible. The ones in this Fig. The switch-capacitor implementation shown in Figure 9 uses transfer gates that are alternately switched by one of two non-overlapping clocks (ϕ1, ϕ2). Apart from the non-overlap, one clock is the inverse of the other. The storage capacitors each transfer a certain amount of charge one node with each half-clock cycle. The figure shows two strands. The strands are operated with a half-clock offset. This results in a continuous discharge of charge. When the clocks are switched off, as is the case during the measurement phases, no current flows. The resulting load resistance becomes high. If the discharge clock is chosen to be dependent on the input voltage, the discharge can be controlled, for example, so that it is greater for larger input voltage differences and smaller for smaller input voltage differences, and disappears within a predefined range. Fig. Figure 10 shows another example of an unloading network R G as an active network. Transistors T3 and T4 are switched on depending on the difference in input voltage between IP and IN. The differential amplifier calculates the magnitude of this difference at its inputs OP and ON and switches transistors T3 and T4 on according to a predefined function, depending on this difference. Since the characteristic curve of the transistors is not linear, this results in a zero conductance of transistors T3 and T4 when the difference in input voltage between IP and IN is zero. Fig. Figure 11 shows another possible implementation of an unloading network R. GA first current source supplies current I to MOS diodes T9 and T14, each receiving half of its value. The current through MOS diode T14 is reduced by T13. The current through MOS diode T9 is reduced by T11. A second current source supplies a current that is typically 80% of the value of the current from the first current source. Since transistor T11 forms a current mirror with MOS diode T12, and transistor T13 forms a current mirror with the same MOS diode T12, an offset current, typically 80% of current I, is attracted by the currents through T9 and T14, respectively. If the inputs IP and IN are biased differently, this leads to an unbalanced current distribution through the differential stage consisting of T5 and T6. This manifests itself in that additional current can flow through the MOS diodes T9 or T14, which causes transistors T7 and T15 or T8 and T16 to turn on, thus discharging the input nodes IP and IN. Fig. Figure 12 shows an exemplary discharge resistance characteristic of a circuit according to Fig. 11. By appropriately choosing the current mirror and transistor ratios, it is possible to achieve a characteristic curve of the input resistance that has an extremely high-impedance region A, in which the input resistance is practically only determined by the leakage current of the circuit, a region B in which voltage limiting takes effect, and a region C in which the input resistance is very low.

[0034] The two terminals are thus discharged by this electrical circuit arrangement, whose equivalent resistance at an operating point in area A is significantly larger than at an operating point in areas B or C.

[0035] This allows a passive infrared detector to be operated such that the electrical terminals are discharged via a current path when the voltage is outside a predetermined range A. The discharge current through this circuit depends on the input voltage between the electrical terminals IP and IN. Within the input voltage range A, defined by the component values, the discharge current vanishes, except for the leakage current of the transistors. Outside this range A, the discharge current increases with increasing deviation of the input voltage from the input range A. The input resistance RIN(IP-IN) depends on the differential voltage V(IP-IN) between the inputs IP and IN of the network R. GThe input resistance considered here can be assumed to be located either between terminals IP and IN, or between a terminal IP or IN on one side and the reference potential, e.g., ground, on the other. The behavior in Fig. 12 should preferably be similar in each of these two cases. Reference symbol list A voltage range in which the discharge network has high resistance ADC Analog to Digital Converter B Voltage range in which the discharge network exhibits a medium conductivity C voltage range in which the discharge network exhibits higher conductivity C1 First Capacity C 1b First integrating filter (third capacity) C2 Second Capacity CP Comparator CP b Comparator CPO comparator output C PIRParasitic capacity of the PIR sensor PIR CS current output of the differential transconductance amplifier DAC Digital-to-Analog Converter DF Downstream digital filter I1 Additional power source I2 power source I a1 First current divider output I a2 Second current divider output IN First connection for the PIR sensor Int Integrating Filter (in the simplest case an up / down counter) Int b Integrating filter (in the simplest case an up / down counter) IP Second connection for the PIR sensor IN FB Tapping at a resistor cascade (R) FB ) from individual resistors I PIR Power source of the equivalent circuit of the PIR sensor I ref Reference current source IW1 First power source used as a work resistor IW2 Second power source, used as a work resistor MUX Analog 1:(n-1) or 1:n or 1:(n+1) multiplexer. Here, n preferably has a value greater than three and / or four. Values ​​of n = (2) are particularly advantageous. m -2) with m>2 or m>3. In the present example, m=6 is chosen. ON First output of the differential stage OP Second output of the differential stage Output bus of the digital filter DF (=downstream filter DF) φ1 First clock cycle of the SC network to form a discharge resistor Φ Z Second clock cycle of the SC network for the formation of a discharge resistor. This clock cycle is essentially the inverse of φ1 and does not overlap with φ1. PIR sensor R1 First work resistor R2 Second work resistor R dis_1First unfavorable discharge resistance in the prior art. This leads to a load on the output IP and a reduction in the output signal. R dis_2 A second unfavorable discharge resistance in the prior art. This leads to a load on the output IN and a reduction in the output signal. R FB A resistor cascade consisting of individual resistors. A control signal (Val) controls the tap of the output signal IN. FB The resistor cascade thus behaves like a potentiometer controlled by the value Val. Its implementation is similar to that of the current divider consisting of a multiplexer MUX and a resistor cascade R. M1 to R Mn . R G Discharge network. This discharge network prevents the PIR sensor from charging to ground as well as the PIR sensor terminals from charging to each other. RIN(IP-IN) Input resistance of the network R, dependent on the differential voltage V(IP-IN) between inputs IP and IN G The input resistance can be assumed to be located either between terminals IP and IN, or between a terminal IP or IN on one side and the reference potential, e.g., ground, on the other. The behavior in Fig. 12 should preferably be similar in each of these two cases. R L1 First work resistance R L2 Second work resistance R M Resistance of the current divider. This is the sum of the resistance values ​​of the resistance chain R. M1 to R Mn consisting of n resistors. R M1 to R Mn Resistances of the resistor chain consisting of n resistors of the current part of the differential stage R PIR Internal resistance of the PIR sensor PIR, which is in parallel to the outputs of the PIR sensor (see Fig. 1) R PIR_C Series resistance of the parasitic capacitance C PIR . S b First knot T ADC output with typically a smaller bit width than the bus output T1 First transistor of the differential stage T2 Second transistor of the differential stage T3 Third Transistor T4 Fourth Transistor T5 to T16 transistors of an exemplary further discharge network. Val Control input of the multiplexer MUX V(IP-IN) Voltage between the outputs of the PIR sensor and thus between the inputs of the discharge network R G V ref Reference voltage

Claims

[1] Device for operating a passive infrared (PIR) detector having a first terminal (IN) and a second terminal (IP), the device comprising: - an electrical circuit arrangement (R G ), wherein the electrical circuit arrangement (R G ) forms a leakage resistance between the first terminal (IN) and the second terminal (IP) of the passive infrared detector (PIR) to discharge the first terminal (IN) and the second terminal (IP) of the passive infrared detector (PIR); wherein the electrical circuit arrangement (R G ) includes a switch-capacitor circuit with transfer gates and storage capacities; and the device is set up for this purpose: - the transfer gates of the electrical circuit arrangement (R G) to switch alternately with a first clock (φ1) and a second clock (Φ2), and to advance a charge quantity by one node with each half-clock using the storage capacities, whereby the first clock (φ1) and the second clock (Φ2) do not overlap and, apart from the non-overlap, the first clock (φ1) is the inverse of the second clock (Φ2); and - to switch off the first clock (φ1) and the second clock (Φ2) during a measurement phase, so that the device is in a measurement state and the charge flow through the electrical circuit arrangement (R G ) is prevented. [2] Device according to claim 1, wherein the electrical circuit arrangement (R G ) has two strands and is further configured to connect the strands of the electrical circuit arrangement (R G ) to operate each half-cycle offset, thereby generating a continuous charge outflow. [3] Device according to claim 1 or 2, wherein the device is configured such that a discharge current is passed through the electrical circuit arrangement (R G ) when discharging the first terminal (IN) and the second terminal (IP) of the passive infrared detector (PIR) depends on an input voltage between the first terminal (IN) and the second terminal (IP) of the passive infrared detector (PIR). [4] Device according to claim 3, wherein the device is further configured to control the first clock (φ1) and the second clock (Φ2) for discharging the first terminal (IN) and the second terminal (IP) of the passive infrared detector (PIR) such that the discharge takes place depending on the input voltage. [5] Device according to one of the preceding claims, wherein the device is further configured to pre-measure the electrical circuit arrangement (R G) to switch to the measurement state and, after the measurement has ended, to switch the electrical circuit arrangement (R G ) to switch to a state that has a lower resistance compared to the measured state. [6] Device according to one of the preceding claims, wherein the device is further configured to measure the leakage resistance of the electrical circuit arrangement (R) in the measuring state G ) to form a resistance greater than 1 MOhm in order to prevent the flow of charge. [7] Detection device comprising: - a passive infrared (PIR) detector with a first terminal (IN) and a second terminal (IP); and - a device according to one of the preceding claims for operating the passive infrared detector (PIR). [8] Detection device according to claim 7, further comprising a differential amplifier with a first input transistor (T1) and a second input transistor (T2), wherein the first terminal (IN) of the passive infrared detector (PIR) is connected to the first input transistor (T1) and the second terminal (IP) of the infrared detector (PIR) is connected to the second input transistor (T2).

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