Charge pump supply with clock phase interpolation

Abstract

Voltage generator (300) comprising: a plurality of sets of delay lines (310, 320, 330), each having a predetermined number of delay stages (312.1-312.N, 322.1-322.N, 332.1-332.N) connected in series, a plurality of charge pumps (110-130) having triggering inputs coupled to a corresponding delay stage (312.1-312.N, 322.1-322.N, 332.1-332.N), and a phase controller (350) comprising a plurality of phase control stages interconnecting delay lines (310, 320, 330), each phase control stage comprising a plurality of capacitors (352-356), and a pair of capacitors (352, 354) of the plurality of capacitors (352-356) connected in series are arranged between a first input terminal of a first delay stage (312.1) of a first delay line (310), a second input terminal of a first delay stage (322.1) of a second delay line (320), and the second input terminal and a third input terminal of a first delay stage (332.1) of a third delay line (330).

Description

GENERAL STATE OF THE ART

[0001] In modern integrated circuit (IC) designs, there is often a requirement to generate voltage levels that are higher than the available supply voltages (V DD ) or lower than ground. For this purpose, voltage generators are built from charge pumps. A charge pump typically charges a capacitor to the available supply voltage V DD and drives either the low potential side of the capacitor to V DD or its high-potential plate to GND to generate a boosted voltage at an output node (either 2*V DD or -V DD). In practice, multiple charge pump cells of a common size are typically coupled to the output node to achieve an estimated load current that causes the boosted voltage to drain. These charge pump cells are typically controlled by a single clock source. The voltage at the output node may include a "ripple" effect when the charge pumps inject charge into the output node at the clock-controlled rate and when load devices draw current from the output node.

[0002] In a clock-controlled charge pump setup, the voltage waveform may have a fundamental frequency based on the clock source and a magnitude proportional to: ILOAD*TCLK / CLOAD, based, where I LOAD represents a drain current from the output node, C LOAD represents a capacity of a load device and T CLKrepresents a period of a drive timer. In certain applications, a significant voltage ripple can cause chip malfunctions or significantly degrade a circuit's performance. For high-power applications, for example, a large backup capacitor often needs to be added to a charge pump output to reduce ripple. Sometimes a linear low-dropout regulator is required to further reduce ripple. However, these techniques come at a cost: large backup capacitors can occupy significant chip area, and the dropout associated with the linear regulator can make it unsuitable for certain low-voltage applications. Another way to reduce ripple would be to reduce the clock period, but there are many other constraints on selecting the clock frequency, making this method less practical.

[0003] U.S. Patent Application Serial No. 13 / 214,904, assigned to the assignee of the present invention and the disclosure of which is incorporated herein, describes a system in which multiple clock stages of a ring oscillator or delay line drive respective charge pumps. The transitions of each charge pump are offset from the others due to the delays associated with each element in the delay line. Thus, the voltage drop rate for a common number N of charge pumps can be reduced by N / 2. A further advantage is that the fundamental frequency of the voltage waveform is N / 2 times the clock frequency and is limited only by the associated delay in a pair of inverters of the ring oscillator. This system achieves a significant improvement in ripple reduction compared to a drive system with a single clock phase.However, the design is limited by the unit delay in the delay chain and may not be sufficient for some applications. US 5 036 229 A discloses a charge pump comprising substantially parallel connections of low capacitance charge pumps, each of the low capacitance charge pumps being controlled by a clock signal. WO 2006 / 126733 A1 discloses a coupled ring oscillator comprising n ring oscillators each comprising m inverter circuits and a phase-locking loop in which mxn phase-locking circuits are interconnected, each of which couples signal phases at two points in a specific phase mode to form a loop. From US 2009 / 0 261 911 A1 a multiphase oscillator is known which includes a plurality of ring oscillators, each having a plurality of output terminals and each formed by connecting an odd number of inverters in a ring. US 2009 / 0 251 225 A1 discloses a digital fractional PLL which introduces an accumulated phase offset in front of the digital VCO using a digital accumulator to achieve the fraction of the division ratio. In US 2010 / 0 271 100 A1 a digital voltage regulator with a large dual rail delay chain feeding forward cross-coupled inverters is disclosed. US 2010 / 0 176 889 A1 discloses an oscillator comprising a first ring oscillator with a first plurality of inverters and a first plurality of capacitors. US 2008 / 0 180 181 A1 provides an apparatus for generating multi-phase clock signals with a ring oscillator, comprising a first-stage phase mixing module and a second-stage phase mixing module.

[0004] Accordingly, the inventors see a need in the art to reduce the effects of ripples in voltage generators with multi-stage charge pumps. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] They show: Fig. 1 is a functional block diagram of a voltage generator according to an embodiment of the present invention. Fig. 2 is a simplified block diagram illustrating relationships between delay lines and phase control stages according to an embodiment of the present invention. Fig. 3 shows a voltage generator according to another embodiment of the present invention. Fig. 4 a voltage generator according to another embodiment of the present invention. Fig. 5 shows a voltage generator according to another embodiment of the present invention. Fig. 6 a voltage generator according to another embodiment of the present invention. Fig. 7 is a circuit diagram of a charge pump according to an embodiment of the present invention. DETAILED DESCRIPTION

[0006] Embodiments of the present invention provide a voltage generator having the features of claim 1. In this way, the voltage generator can reduce ripple effects of prior art designs.

[0007] An alternative design may provide a voltage generator having the features of claim 16. In this way, the voltage generator may reduce ripple effects of prior art designs.

[0008] Fig. 1 is a functional block diagram of a voltage generator 100 according to an embodiment of the present invention. The voltage generator 100 may include multiple arrays 110-130 of charge pumps, multiple delay lines 140-160, and a phase control formed by phase control stages 170, 180, and 190. Each array 110, 120, 130 may include a common number N of charge pumps 110.1-110.N, 120.1-120.N, 130.1-130.N, each having an input (represented as "FIRE") for a corresponding control signal. Control signals TRG1.1-TRG1.N, TRG2.1-TRG2.N, TRG3.1-TRG3.N for each charge pump 110.1-110.N, 120.1-120.N, and 130.1-130.N can be taken from the respective positions of their associated delay lines 140, 150, and 160. Accordingly, control signals TRG1.1-TRG1.N for charge pumps 110.1-110.N can be taken from delay line 140, and control signals TRG2.1-TRG2.N for charge pumps 120.1-120.N can be taken from the delay line 150, and so on. The outputs of the charge pumps 110.1-110.N, 120.1-120.N, and 130.1-130.N can be connected to a common output terminal V. OUT of the voltage generator 100.

[0009] The delay lines 140, 150, 160 may have similar architectures and be constructed from the same component types. The control signals TRG1.1-TRG1.N may be taken from the same positions in a first delay line 140 as their counterparts TRG2.1-TRG2.N, TRG3.1-TRG3.N, etc., in the other delay lines 150, 160. If the delay lines 140, 150, 160 receive a common input signal and no phase control contribution (and no process variations between the components), the control signals TRG.1-TRG1.N of the first delay line 140 would be in phase with their corresponding control signals TRG2.1-TRG2.N, TRG3.1-TRG3.N from the other delay lines 150, 160.

[0010] The phase control may be coupled between the delay lines 140-160 to induce phase offsets between the control signals TRG1.1-TRG1.N, TRG2.1-TRG2.N, TRG3.1-TRG3.N, etc. Couplings of the phase control stages 170-190 to the delay lines 140-160 may form a "ring" between the delay lines 140-160. In the Fig. For example, in the embodiment illustrated in Figure 1, delay line 150 is illustrated as being coupled to delay line 140 through a first phase control stage 170, delay line 160 is coupled to delay line 150 through a second phase control stage 180, and delay line 140 is coupled to delay line 160 through a third phase control stage 190.

[0011] The phase control stages 170, 180, 190 may have inputs coupled to control signal outputs at a common position between the delay lines 140, 150, 160. For example, the phase control stages 170, 180, 190 in the Fig. 1, the phase control stages 170, 180, 190 have inputs coupled to the control signals TRG2.2, TRG3.2, and TRG1.2, respectively, which can be taken over by the second stages (not shown) in each delay line 140, 150, 160. Outputs of the phase control stages 170, 180, 190 can be coupled to different stages of an adjacent line. One of the phase control stages can have an output coupled to a stage of another delay line that is different from its input stage. The other phase control stages can have outputs coupled to a line stage that corresponds to the stage of their input. Accordingly, the phase control stage 180 in the example of Fig. 1 has an input coupled to the TRG3.2 output, which corresponds to a second stage (not shown) in delay line 160, but has an output coupled to a third stage (also not shown) in delay line 150. The other phase control stages 170, 190 are shown as having their outputs coupled to the second stage of their respective delay lines 140, 160.

[0012] Fig. 1 shows a phase controller provided as a single ring of phase control stages 170-190. Other embodiments of the present invention, described below, may include additional phase control stages (not shown) coupled between different stages of the delay lines 140-160. Indeed, in some embodiments, the phase controller may include a network of phase control stages coupling each stage of a delay line to stages of two adjacent delay lines. Such embodiments have been described in Fig. 1 have been omitted to avoid cluttering the illustration, but are shown in other figures herein.

[0013] Embodiments of the present invention provide various architectures for delay lines 140-160. In a first embodiment, for example, delay lines 140-160 may have inputs coupled to a common clock signal CLK. The delay lines may include a series of buffers provided in series. In another embodiment, delay lines 140-160 may be provided as ring oscillators that generate their own clocks.

[0014] The example from Fig. 1 shows three sets of charge pump arrays 110-130 and delay lines 140-160, but the principles of the present invention can be extended to any number M of charge pump arrays and delay lines, where M ≥ 3. Thus, a voltage generator 100 of the present invention can include M sets of charge pump arrays and delay lines with N charge pumps and delay stages in each set. As part of the implementation, circuit designers can select appropriate numbers for M and N to meet their design requirements.

[0015] Fig. Figure 2 is a simplified block diagram illustrating relationships between delay lines and phase control stages according to one embodiment of the present invention. Delay lines 210, 220, etc., may each include a plurality of delay stages 212.1-212.N, 222.1-222.N, etc., coupled in series. Outputs TRG1.1-TRG1.N, TRG2.1-TRG2.N, etc., of delay lines 210, 220, etc., may be taken from intermediate nodes between delay stages 212.1-212.N, 222.1-222.N, etc.

[0016] The phase control 250 may include a plurality of phase control stages 252-260 forming a ring between the delay stages. In this example, as shown in Fig. 1, inputs of the phase control stages 252-260 may each be connected to an input of a third delay stage 212.3, 222.3, 232.3, 242.3, etc. of the respective delay lines 210-240. An output of one of the phase control stages 254 may be connected to an input of a line stage that is different from the stage to which its input is connected (in the example from Fig. 2 an input of the fourth line stage 232.4). Outputs of the other phase control stages 252, 256-260 can be coupled to inputs of line stages 212.3, 222.3, 242.3 at the same level to which their inputs are connected (e.g., inputs and outputs of the phase control stages are coupled to inputs of the third line stages).

[0017] The phase control may include additional phase control stages and connections between lines 210-240. Fig. Figure 2 schematically shows additional phase control stages 262-268 that may form a second ring between lines 210-240. As with the first ring, the second phase control stages 262-268 may each have inputs and outputs coupled to the delay lines 210-240 at a common depth in each line, except that an output of one of the phase control stages (stage 262 in the example of Fig. 2) may be coupled to an input of another stage in line 220 at a level different from stage 212.5, where its input is connected to another line 210.

[0018] Fig. Figure 3 shows a voltage generator 300 according to another embodiment of the present invention. In this embodiment, the voltage generator 300 is illustrated as including a plurality of delay lines 310-330, an associated charge pump arrangement 340, and a phase controller 350. The charge pump arrangement 340 may comprise an array of M x N charge pump stages (not individually described in Fig. 3), where M represents the number of delay lines 310-330 and N represents the number of stages in each delay line 310-330.

[0019] In the embodiment from Fig. 3, the delay lines 310-330 are provided as ring oscillators. Each ring oscillator 310, 320, 330 may have an odd number of inverter stages 312.1-312.5, 322.1-322.5, and 332.1-332.5 coupled in series in a ring. Trigger signals TRG1.1-TRG1.5, TRG2.1-TRG2.5, and TRG3.1-TRG3.N5 for the charge pump arrangement 340 may be taken from intermediate nodes that occur between the inverter stages 312.1-312.5, 322.1-322.5, and 332.1-332.5. The inverters 312.1, 312.3, 312.5, etc. in odd positions of the delay lines can generate outputs corresponding to a first subset of the trigger signals TRG1.1-TRG1.3, and the inverters 312.2, 312.4 in even positions of the delay lines can generate outputs corresponding to a remainder of the trigger signals TRG1.4-TRG1.5.

[0020] The phase control 350 is shown as including a plurality of capacitors 352-356 connected between the ring oscillators 310-330. In the Fig. In the embodiment shown in Figure 3, capacitors 352-356 are coupled to inputs of the first stage of inverters 312.1, 322.1, 332.1 between the ring oscillators, with one exception. Here, one terminal of a capacitor 356 is coupled to an input of another stage 312.3 of one of the ring oscillators.

[0021] During operation, each ring oscillator 310, 320, 330 generates its own clock signal, which propagates through the inverters of each oscillator. Taking ring oscillator 310 as an example, an inverter 312.1 may generate a rising edge signal at its output, which would cause a charge pump connected to the TRG1.1 output (not individually shown in array 340) to fire. The rising edge signal from inverter 312.1 may be inverted by inverter 312.2 and inverted again by inverter 312.3. If inverter 312.3 generates a rising edge signal, it may cause a charge pump connected to the TRG1.2 output (again not individually shown) to fire. The rising edge signal from inverter 312.3 can be inverted by inverter 312.4 and inverted again by inverter 312.5, which can generate a rising edge signal that can be connected to the TRG1.3 output can cause the charge pump to fire.

[0022] The rising edge signal from inverter 312.5 can be fed back to inverter 312.1, which can generate a falling edge signal. Inverter 312.2 can generate a rising edge signal from the output of inverter 312.1, which can cause a charge pump connected to the TRG1.4 output to fire. The rising edge signal from inverter 312.2 can be inverted by inverter 312.3 and inverted again by inverter 312.4, which can generate a rising edge signal that can cause a charge pump connected to the TRG1.5 output to fire. Accordingly, the ring oscillator 310 generates a "ripple" on rising and falling transitions that loop through the ring's inverters 312.1-312.5 and produce trigger signal outputs TRG1.1-TRG1.5 that can be output to the charge pump arrangement 340.The operation of the ring oscillators 320-330 may function in a similar manner to the operation of the first ring oscillator 310.

[0023] The timing of the trigger signals TRG1.1-TRG1.5, TRG2.1-TRG2.5, TRG3.1-TRG3.5 from the ring oscillators 310-330 can be determined by the propagation delays of signals through the inverters 312.1-312.5 and by a contribution from the phase control 350. In the embodiment of Fig. 1, a voltage transition on a first terminal of cross-connected capacitor 356 can force a corresponding voltage transition on a second terminal of capacitor 356. Accordingly, when a voltage transition occurs at an input of inverter 332.1 in a ring oscillator 330, capacitor 356 can drive a corresponding transition to the input of inverter 312.3 in an adjacent ring oscillator 310. When a transition occurs at the input of inverter 312.1 in ring oscillator 310, capacitor 352 can drive a corresponding transition to the input of inverter 322.1 in ring oscillator 320. Similarly, when a transition occurs at the input of inverter 322.1 in ring oscillator 320, capacitor 354 may drive a corresponding transition to the input of inverter 332.1 in ring oscillator 330.

[0024] Under stable operating conditions, ring oscillators 310-330 are expected to generate trigger signals TRG1.1-TRG1.5, TRG2.1-TRG2.5, and TRG3.1-TRG3.5 that are denser than would be possible with a single ring oscillator. In a single ring oscillator, the time between a pair of consecutive trigger signals would be defined by a propagation delay D between a pair of inverters, for example, inverters 312.2 and 312.3 of ring oscillator 310, which is a predetermined minimum time determined by the process, voltage, and temperature conditions that govern the operation of ring oscillator 310.However, using an array of parallel ring oscillators 310-330 networked by a phase controller 350 can cause each of the ring oscillators 310-330 to generate trigger signals that share a common delay characteristic but are phase-shifted by a time PD less than the number D of transitions in a single ring oscillator. Thus, if a single ring oscillator 310 generates a single trigger signal in a period D, an array of M ring oscillators 310-330 can generate trigger signals in the same period DM. Each ring oscillator 310, 320, 330 can generate a single trigger signal during the period D, but the trigger signals are phase-shifted from each other. Thus, charge pumps (not shown) can fire within the period DM, resulting in improved control of the output voltage V. OUT contributes.

[0025] In other embodiments, the phase controller 350 may include multiple sets of capacitors (shown schematically) networked between different stages of the ring oscillators 310-330. Fig. 3 shows an embodiment in which phase controller 350 provides a network of interconnections in which three of five inverters (roughly half) each have inputs coupled to the inputs of the inverters of two adjacent ring oscillators via capacitors. Other embodiments may use different numbers of interconnections. For example, other embodiments may provide coupling capacitors to interconnect the input of each inverter to inverters of a pair of adjacent ring oscillators. Another variation would be to couple a different fraction of the inverters (e.g., one-third, one-quarter, etc.) to inverters of the other ring oscillators.

[0026] In other embodiments, the phase control may consist of various types of delay elements. For example, phase control may be composed of inverters and resistors. Fig. Figure 4 shows a voltage generator 400 according to another embodiment of the present invention, in which a phase control 450 is composed of resistors 452-456 connected in a ring between stages of a plurality of ring oscillators 410-430. In this example, the voltage generator 400 has a similar architecture to that of Fig. 3, in which ring oscillators 410-430 each have inverters 412.1-412.5, 422.1-422.5, 432.1-432.5 that generate trigger signals TRG1.1-TRG1.5, TRG2.1-TRG2.5, TRG3.1-TRG3.5 to a charge pump arrangement 440. The phase controller 450 can impose phase shifts between trigger signals between the ring oscillators 410-430 such that each ring oscillator generates a trigger signal in the delay period of a pair of inverters offset from each other by a time determined by the phase controller 450.

[0027] As noted, the phase control 450 may include a plurality of resistors 452-456 connected between the ring oscillators 410-430. In the Fig. In the embodiment shown in Figure 4, resistors 452-456 are, without exception, coupled to inputs of the first stage of inverters 412.1, 422.1, and 432.1 between the ring oscillators. Here, an output terminal of a resistor 456 can be coupled to an input of another stage 412.2 of the associated ring oscillator 410.

[0028] Fig. Figure 4 also schematically illustrates another embodiment that may include a network of resistors interconnecting stages of the various ring oscillators 410-430. As in previous embodiments, the present invention provides variations for implementing such a network. A network may interconnect inputs of each inverter to a pair of adjacent ring oscillators, or it may connect the input of a fraction of the inverters (e.g., half, one-third, or one-quarter of the inverters) to the adjacent ring oscillators.

[0029] Fig. 5 shows a voltage generator 500 according to another embodiment of the present invention. The voltage generator 500 can accept a drive clock signal CLK from an external source. In this embodiment, the voltage generator 500 can include various delay lines 510-550, an associated charge pump arrangement 560, and a phase controller 570. The charge pump arrangement 560 can be an array of M x N charge pump stages (in Fig. 5 not shown individually), where M represents the number of delay lines 510-550 and N represents the number of stages in each delay line 510-550.

[0030] In the embodiment from Fig. 5, the delay lines 510-550 may be provided as chains of series-connected inverters. Each delay chain 510-550 may include any number N of inverter stages 512.1-512.4, 522.1-522.4, ..., 552.1-552.4. Trigger signals (not shown individually) may be acquired from intermediate nodes located between the inverter stages 512.1-512.4, 522.1-522.4, ..., 552.1-552.4. The inverters 512.1, 512.3, etc., in odd positions of the chains 510-550 may generate outputs corresponding to a first subset of trigger signals, and the inverters 512.2, 512.4, etc., in even positions of the delay lines may generate outputs corresponding to a remainder of the trigger signals.

[0031] The phase control 570 may include a plurality of interconnected capacitors 572.1-572.5, 574.2-574.5, 576.1-576.5, 578.1-578.3. The CLK signal may be input directly to a first delay chain 510 of the voltage generator 500. Input nodes of the remaining delay chains 520-540 may be coupled to the CLK input via the interconnecting capacitors 572.1, 574.1, 576.1, etc.

[0032] Fig. Figure 5 shows a network of capacitors 572.1-572.5, 574.2-574.5, 576.1-576.5, 578.1-578.3, in which the input of each inverter of the intermediate delay chains 520-550 is connected by a pair of capacitors to an inverter of adjacent delay chains. As in previous embodiments, it is not necessary for every node to be connected in this manner. Other embodiments provide a variation in which a predetermined fraction (again, half, one-third, one-quarter, etc.) of the inverters are connected to their neighbors in this manner.

[0033] During operation, as the state of the CLK signal changes, alternating rising and falling edges of the CLK signal may be input to the first delay chain 510. The rising and falling transitions may cause corresponding transitions at inputs of the remaining delay chains 520-550 through the cross-linking capacitors 572.1, 574.1, 576.1, 578.1. Thus, the first-stage inverters 512.1, 522.1, 532.1, 542.1, 552.1 may transition at times offset from each other. Other cross-linking capacitors provided in later stages of the delay chains 510-550 may also contribute to maintaining the phase shift between the chains.

[0034] In a circuit implementation from Fig. 5, the delay lock loop (generally DLL) may be provided to the circuit 500 to ensure that the total delay of an inverter series is one cycle of the LCK signal.

[0035] Fig. 6 shows a voltage generator 600 according to another embodiment of the present invention. The voltage generator 600 may include a delay line 610 having a plurality of N delay stages 612.1-612.5, a charge pump arrangement 620 having twice the number (2*N) of charge pumps (not shown) as the stages in the delay line 610, a plurality of trigger signal drivers 630, and a phase controller 640. The trigger driver 630 may have twice as many trigger drivers 632.1-632.5, 634.1-634.5 as delay stages in the delay line 610. A first set of the trigger drivers 632.1-632.5 may have inputs coupled to inputs and / or outputs of the delay lines' delay stages 612.1-612.5. A second number of trigger drives 634.1-634.5 may have inputs coupled to structures within the phase control 640. In the example from Fig. 6 is N=5.

[0036] The phase control 640 may be provided as a cascaded series of phase control stages 642.1-642.10 with twice as many stages as charge pumps in the charge pump arrangement 620. The phase control stages 642.1-642.10 may be provided as a plurality of connected pairs (e.g., stages 642.1 and 642.2, stages 642.3 and 642.4, etc.), in which an intermediate node in each pair may be connected to an input of the second set of trigger drives 634.1, 643.2, etc. External terminals of each pair (e.g., stages 642.1 and 642.2) may each be connected to input and output terminals of a common line delay unit 612.1.

[0037] During operation, a clock signal CLK may be propagated through delay stages 612.1-612.5 of delay line 610. Consider an event where a voltage at the input of a respective delay stage 612.2 is initially high, but transitions to low when reached by a new phase of the CLK signal. Immediately before the falling transition, both the voltages at the input and output of delay stage 612.2 may be high. When a falling transition is input to delay stage 612.2 from the preceding delay stage 612.1, the falling transition may also be input to trigger driver 632.2 and capacitors 642.2 and 642.3. In response, trigger driver 632.2 may change state, producing a rising transition at its output, which is provided to charge pump arrangement 620. The falling transition from delay stage 612.1 may also trigger a charge redistribution event between capacitors 642.3 and 642.4, which may cause trigger driver 634.2 to generate an output with a rising transition. The transitions from the outputs of drivers 632.2 and 634.2 may have offset timing relative to each other based on delays introduced by the response of capacitors 642.3 and 642.4. Finally, delay stage 612.2 may generate an output with a falling transition in response to the falling transition after a delay triggered by components therein.

[0038] The falling transition can be output from delay stage 612.2 to the next delay stage 612.3 in delay line 610, to trigger driver 632.3, and to capacitors 642.4 and 642.5 of the phase control. The falling transition can trigger a rising transition from trigger driver 632.3. It can also trigger another charge redistribution event in capacitors 642.3 and 642.4, causing trigger driver 634.2 to produce a rising transition output. This operation can cascade through the remaining delay stages 612.4 and 612.5 of delay line 610.

[0039] In the Fig. In the embodiment illustrated in Figure 6, the phase control stages 642.1-642.10 are depicted as capacitors, however, the principles of the present invention are also applicable to other circuit structures, including resistors and inverters. Similarly, the trigger drivers 632.1-632.5 and 634.1-634.5 are depicted as inverters, however, the principles of the present invention are also applicable to non-inverting buffers.

[0040] Fig. Figure 7 is a circuit diagram of a charge pump 700 according to an embodiment of the present invention. The charge pump 700 may be used as a charge pump stage in any of the voltage generators described above. The charge pump 700 may include a capacitor 710 and a pair of switches 720, 730. A first switch 720 may be connected to the capacitor 710 at a first terminal and selectively connect the first terminal of the capacitor 710 to a reference voltage V REF(for example the supply voltage V DD ) or ground. The second switch 730 may be connected to the capacitor 710 at a second terminal and may connect the second terminal to a V REF -terminal or the V OUT -Output node. Both switches can be controlled by a trigger signal TRG.

[0041] During operation, when the TRG signal is in a first state (e.g., TRG is low), the switch 720 may connect the first terminal of the capacitor 710 to ground GND and the switch 730 may connect the second terminal of the capacitor to the reference voltage V REF Therefore, the capacitor 710 can provide a voltage V REF When the TRG signal transitions to a second state (TRG goes high), the switch connections may change. Switch 720 may connect the first terminal of capacitor 710 to the reference voltage V REFand the switch 730 can connect the second terminal of the capacitor 710 to the output terminal V OUT In response, the voltage at the output node V OUT to approximately 2*V REF Charge from capacitor 710 can be applied to the output terminal V OUT be injected.

[0042] The charge pump 700 can be modified to provide a voltage lower than ground. In particular, the switch 730 can be connected between ground and the output terminal V OUT back and forth. In a first phase of operation, the TRG signal can cause switch 720 to connect the first terminal of capacitor 710 to V REF and the switch 730 can connect the second terminal of the capacitor to ground. Accordingly, the capacitor 710 can have a voltage of -V REFWhen the TRG signal transitions to a second state (TRG goes high), switch 720 may couple the first terminal of capacitor 710 to ground GND and switch 730 may couple the second terminal of capacitor 710 to the output terminal V OUT In response, the voltage at the output node V OUT to approximately -V REF Charge from capacitor 710 can be increased according to this voltage from the output terminal V OUT drain away.

[0043] In the above description, delay line and charge pump arrays were presented with relatively small sizes. In an implementation, the number of delay lines, the number of delay stages, and the number of charge pumps in an array may be much larger than illustrated. For example, in certain implementations, it may be practical to provide systems that have 24 delay lines with 21 delay stages within them, resulting in 504 charge pumps in an array. Other numbers of delay lines, delay stages, and charge pumps may be selected for other circuit implementations, depending on what is convenient for the circuit designer.

[0044] Several embodiments of the invention are specifically illustrated and / or described herein. However, it should be understood that modifications and variations of the invention are covered by the above teachings and fall within the scope of the appended claims without departing from the spirit and intended scope of the invention.

Claims

[1] Voltage generator (300) comprising the following: several sets of delay lines (310, 320, 330), each having a predetermined number of delay stages connected in series (312.1-312.N, 322.1-322.N, 332.1-332.N), a plurality of charge pumps (110-130) having triggering inputs coupled to a corresponding delay stage (312.1-312.N, 322.1-322.N, 332.1-332.N), and a phase control (350) comprising a plurality of phase control stages connecting delay lines (310, 320, 330) together, each phase control stage comprising a plurality of capacitors (352-356), and wherein a pair of capacitors (352, 354) of the plurality of capacitors (352-356) connected in series are arranged between a first input terminal of a first delay stage (312.1) of a first delay line (310), a second input terminal of a first delay stage (322.1) of a second delay line (320), and the second input terminal and a third input terminal of a first delay stage (332.1) of a third delay line (330). [2] Voltage generator (300) according to claim 1, wherein networking of the phase control stages forms a ring of connections between the delay lines (310, 320, 330). [3] Voltage generator (300) according to claim 1, wherein networking of the phase control stages forms a network of connections between the delay lines (310, 320, 330). [4] Voltage generator (300) according to one of claims 1 to 3, wherein at least one phase control stage has a first terminal connected to a first delay line (310) at a first position therein and a second terminal connected to a second delay line (320) at a second position therein, which differs from the first position. [5] Voltage generator (300) according to claim 2, wherein other phase control stages have first terminals and second terminals which are connected to common positions in corresponding input and output delay lines. [6] Voltage generator (300) according to one of the preceding claims, wherein the delay lines (310, 320, 330) are contained in one or more ring oscillators. [7] Voltage generator (300) according to one of the preceding claims, wherein the delay lines (310, 320, 330) comprise a chain of inverters (312.1-312.5, 322.1-322.5, 332.1-332.5). [8] Voltage generator (300) according to claim 7, wherein the voltage generator (300) has an input for an externally provided clock signal, the voltage generator (300) includes an inverter which has an input coupled to the clock input, wherein a first chain has an input coupled to the clock input, and a second chain has an input coupled to an output of the inverter. [9] Voltage generator comprising the following: an arrangement of M x N charge pumps (110-130), a set of M delay lines (310, 320, 330) each having N stages (312.1-312.N, 322.1-322.N, 332.1-332.N), wherein the stages of each line are connected to corresponding charge pumps from the arrangement, and Means for offsetting outputs between the delay lines (310, 320, 330), wherein the means for offsetting comprise a plurality of capacitors (352-356), and wherein a pair of capacitors (352, 354) connected in series are arranged between a first input terminal of a first stage of a first delay line (310) and a second input terminal of a first stage of a second delay line (320) and the second input terminal and a third input terminal of a first stage of a third delay line (330). [10] Voltage generator according to claim 9, wherein the means for the offset comprise a ring of delay elements connected between the delay lines (310, 320, 330). [11] Voltage generator according to claim 9, wherein the means for the offset comprise a network of delay elements connected between the delay lines (310, 320, 330). [12] Voltage generator according to one of claims 9 to 11, wherein the means for the offset comprise a plurality of capacitors (352, 354, 456) connected between the delay lines (310, 320, 330), wherein at least one capacitor has a first terminal connected to a first delay line (310) at a first position therein and a second terminal connected to a second delay line (320) at a second position therein, which differs from the first position. [13] Voltage generator according to one of claims 9 to 12, wherein the delay lines (310, 320, 330) are contained in one or more ring oscillators. [14] Voltage generator according to any one of claims 9 to 13, wherein the delay lines (310, 320, 330) comprise corresponding chains of inverters. [15] Voltage generator according to any one of claims 9 to 14, wherein the voltage generator has an input for an externally provided clock signal, the voltage generator includes an inverter which has an input coupled to the clock input, wherein a first chain has an input coupled to a clock input, and a second chain has an input coupled to an output of the inverter. [16] Voltage generator (600) comprising the following: a predetermined number of charge pumps that have outputs coupled to a common node, a delay line (610) having a predetermined number of delay stages, wherein intermediate nodes between the delay stages are coupled to triggering inputs of a subset of the charge pumps, a phase control (640) comprising a plurality of phase control stages (642.1-642.10) each coupled between the intermediate nodes of the delay line (610), wherein intermediate nodes of the phase control stages (642.1-642.10) are coupled to triggering inputs of another subset of the charge pumps, wherein the phase control stages (642.1-642.10) each comprise a pair of capacitors (642.1-642.10) connected in series between an input terminal and an output terminal of a common delay stage (612.1-612.5). [17] Voltage generator (600) according to claim 16, wherein the delay line (610) is contained in a ring oscillator. [18] Voltage generator (600) according to claim 16 or 17, wherein the delay line (610) comprises a chain of inverters.

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