Multiphase ground-referenced single-end signaling

Abstract

GRS system (100), comprising a control circuit (602) configured to generate a first set of control signals (610) based on a first phase of a clock signal (CLK), to generate a second set of control signals (612) based on a second phase of the clock signal (CLK), and to generate a third set of control signals (614) based on a third phase of the clock signal (CLK); a first ground-referenced single-end signaling GRS driver circuit (400(4)) configured to: precharging a first capacitor to store a first charge based on the first set of control signals (610) during at least one phase of the clock signal (CLK) other than the first phase of the clock signal (CLK); and driving an output signal (616) relative to a ground network (107) by discharging the first charge during the first phase of the clock signal (CLK) by coupling either a first output node or a second output node to the output signal (616) to convey a first input (D0); a second GRS driver circuit (400(5)) configured to: precharging a second capacitor to charge a second charge based on the second set of control signals (612) during at least one phase of the clock signal (CLK) other than the second phase of the clock signal (CLK); and driving the output signal (616) relative to the ground network (107) by discharging the second charge during the second phase of the clock signal (CLK) to convey a second input (D1); and a third GRS driver circuit (400(6)) configured to: precharging a third capacitor to store a third charge based on the third set of control signals (614) during at least one phase of the clock signal (CLK) other than the third phase of the clock signal (CLK); and driving the output signal (616) relative to the ground network (107) by discharging the third charge during the third phase of the clock signal (CLK) to convey a third input (D2).

Description

FIELD OF THE INVENTION

[0001] The present invention relates to digital signaling and, more particularly, to ground-referenced single-ended signaling. BACKGROUND

[0002] Successive generations of computer systems typically require higher performance and, in many cases, reduced size and overall power consumption. A typical computing system includes a central processing unit, a graphics processing unit, and a high-capacity memory subsystem, such as one or more dynamic random access memory (DRAM) devices. Conventional computing systems integrate one or more central processing unit cores and one or more graphics processing unit cores on a single processor system chip, which is coupled to one or more DRAM chips. In certain highly integrated computing systems, the processor system chip is packaged with one or more DRAM chips in a multi-chip module (MCM), which includes interconnect traces to couple the processor system chip to the DRAM chips.

[0003] Differential signaling is typically preferred over single-end signaling for high-speed channels within the MCM because conventional differential signaling can be implemented to dissipate less power, generate less supply noise, and exhibit superior noise rejection characteristics when compared to conventional single-end signaling. Differential signals require two input / output pads on each interconnected chip and well-matched interconnect traces per digital signal. In contrast, single-end signals require one signal pad per digital signal. However, conventional single-end drivers draw a data-dependent supply current, resulting in symbol-rate simultaneous switching noise (SSN) on an associated power supply network.SSN is proportional to signal level and can be overcome by reducing a power supply inductance, a relatively costly solution that typically requires additional input / output arrays. Conventional single-channel signaling is also highly susceptible to electromagnetic noise because such noise is indistinguishable relative to an incoming signal.

[0004] Conventional differential signaling exhibits excellent noise characteristics but is expensive in terms of interconnect resources. While conventional single-end signaling requires fewer signal traces and fewer input / output fields, conventional single-end drivers generate more SSN, and conventional single-end receivers have poor noise tolerance, especially at the lower voltage swings required for low-power operation. Thus, conventional single-end and differential signaling both have disadvantages. US 2011 / 0 199 122 A1 discloses a sampling circuit with discrete timing circuits. DE 602 19 767 T2 discloses a data receiving circuit with a conversion circuit.

[0005] Thus, there is a need to improve signaling and / or other problems associated with the current state of the art. In particular, one objective is to eliminate switching noise. SUMMARY

[0006] This object is achieved by the features of the independent claims. A system for transmitting a ground-referenced single-ended signal (GRS) according to claim 1 is provided. The system comprises, among other things, a control circuit and a first, a second and a third GRS driver circuit. The control circuit is configured to generate a first set of control signals based on a first phase of a clock signal, to generate a second set of control signals based on a second phase of the clock signal, and to generate a third set of control signals based on a third phase of the clock signal. The first GRS driver circuit is configured to pre-charge a first capacitor.pre-charge a second capacitor to store a first charge based on the first set of control signals during at least one phase of the clock signal other than the first phase of the clock signal, and drive an output signal relative to a ground network by discharging the first charge during the first phase of the clock signal. The second GRS driver circuit is configured to pre-charge a second capacitor to store a second charge based on the second set of control signals during at least one phase of the clock signal other than the second phase of the clock signal, and drive the output signal relative to the ground network by discharging the second charge during the second phase of the clock signal.A third GRS driver circuit is configured to precharge a third capacitor to store a third charge based on the third set of control signals during at least one phase of the clock signal other than the third phase of the clock signal and to drive the output signal relative to the ground network by discharging the third charge during the third phase of the clock signal. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A illustrates a ground-referenced single-ended signaling (GRS) system implementing a GRS transmitter based on a flying capacitor charge pump, in accordance with one embodiment; Fig. 1B illustrates operation of a data driver in a pre-load state and in two different data-dependent driver states in accordance with one embodiment; Fig. 1C illustrates a GRS system implementing a GRS transmitter based on a two-capacitor charge pump, in accordance with one embodiment; Fig. 1D illustrates operation of a data driver in a pre-load state in accordance with one embodiment; Fig. 1E illustrates operation of a data driver in various data-dependent driver states in accordance with one embodiment; Fig. 1F illustrates operation of a ground-referenced single-ended data driver based on a flying capacitor charge pump in accordance with one embodiment; Fig. 1G illustrates operation of a ground-referenced single-end data driver based on a two-capacitor charge pump in accordance with one embodiment; Fig. 2A illustrates an exemplary ground-referenced single-end receiver in accordance with one embodiment; Fig. 2B illustrates an exemplary ground-referenced single-end receiver configured to demultiplex incoming data, in accordance with one embodiment; Fig. 3 illustrates an exemplary transceiver pair configured to implement ground-referenced single-end signaling, in accordance with one embodiment; Fig. 4A illustrates an exemplary ground-referenced single-ended data driver including CMOS circuitry, in accordance with one embodiment; Fig. 4B illustrates a ground-referenced single-ended data driver in a pre-charge state associated with driving a data value of zero, in accordance with one embodiment; Fig. 4C illustrates a ground-referenced single-ended data driver in a pre-charge state associated with driving a data value of one, in accordance with one embodiment; Fig. 4D illustrates a ground-referenced single-ended data driver in a driver state in accordance with one embodiment; Fig. 5A illustrates a ground-referenced single-ended transmitter having two instances of a ground-referenced single-ended data driver, in accordance with one embodiment; Fig. 5B illustrates timing for a ground-referenced single-ended transmitter having two ground-referenced single-ended data drivers, in accordance with one embodiment; Fig. 5C illustrates a flowchart of a method for generating a ground-referenced single-ended signal, in accordance with one embodiment; Fig. 6A illustrates timing for a multi-phase ground-referenced single-ended transmitter having four ground-referenced single-ended data drivers, in accordance with one embodiment; Fig. 6B illustrates a multi-phase ground-referenced single-ended transmitter having four instances of a ground-referenced single-ended data driver, in accordance with one embodiment; Fig. Figure 6C illustrates an instance of a GRS data driver from Fig. 6B corresponding to a phase of the clock signal, in accordance with one embodiment; Fig. 6D illustrates a four-phase ring oscillator circuit in accordance with one embodiment; Fig. 7A and Fig. 7B illustrates a flowchart of a method for generating a multi-phase ground-referenced single-ended signal in accordance with one embodiment; Fig. 8A illustrates a multi-phase ground-referenced single-end receiver having four instances of a ground-referenced single-end data receiver, in accordance with one embodiment; Fig. 8B and Fig. 8C illustrates a flowchart of a method for receiving a multi-phase ground-referenced single-ended signal in accordance with one embodiment; Fig. 9A illustrates timing for a multi-phase ground-referenced single-ended transmitter having three ground-referenced single-ended data drivers, in accordance with one embodiment; Fig. 9B illustrates a three-phase ring oscillator circuit in accordance with one embodiment; and Fig. 10 illustrates an exemplary system in which the various architecture and / or functionality of the various previous embodiments may be implemented. DETAILED DESCRIPTION

[0007] A technique is provided for high-speed, single-ended signaling between a processor and memory devices. A ground-referenced driver transmits a pulse having a polarity determined by a corresponding logic state. The pulse traverses a signal path and is received by a ground-referenced amplifier, which amplifies the pulse for interpretation as a conventional logic signal. A set of ground-referenced drivers and ground-referenced amplifiers implements a high-speed interface within the processor and a corresponding interface within one or more memory devices coupled to the processor.The high-speed interface advantageously improves memory bandwidth within the processor, enabling higher performance and higher-density systems than those provided by conventional memory signaling techniques.

[0008] Embodiments of the present invention implement a multi-phase system having multiple transmitter circuits and corresponding receiver circuits operating over different phases of a clock signal to transmit data during each of the phases. Transmitting data over multiple phases enables data transmission at higher rates. Some multi-phase systems may suffer from fixed-pattern jitter resulting from timing mismatches between the different phases. Signals encoding the different phases of the clock signal may be passed along with the data and used to sample the data to mitigate the effects of fixed-pattern jitter.

[0009] A ground-referenced single-end signaling (GRS) link implements a charge pump driver configured to transmit a ground-referenced pulse on an associated signal line. In one implementation, a pulse of positive charge indicates a logic one, while a pulse of negative charge indicates a logic zero. The charge pump driver eliminates simultaneous switching noise (SSN) commonly associated with single-end signaling by forcing a transient signal current and a ground current to be locally balanced and by drawing a constant amount of charge from the power supply every half clock cycle, regardless of the data being transmitted. The pulse is received and amplified by a common-gate amplifier stage configured to use a local ground signal as an input reference.This configuration provides substantial immunity to common-mode noise, the dominant source of transmission errors in single-ended signaling. A second amplifier stage translates a given received pulse to full-swing logic voltages, allowing the received pulse to be correctly interpreted as one or two logic states by conventional logic circuitry. In one embodiment, a GRS receiver includes a common-gate amplifier stage, the second amplifier stage, and two storage elements, such as flip-flops, configured to capture received data during alternate clock phases.

[0010] A GRS transceiver comprises a GRS data driver and a GRS receiver. The GRS transceiver transmits outbound data through the GRS data driver and receives inbound data through the GRS receiver. An isochronous GRS transceiver can also transmit clock information that has a fixed phase relationship to the outbound data and receive clock information that has a fixed phase relationship to the inbound data.

[0011] Fig. 1A illustrates a ground-referenced single-end signaling (GRS) system 100 implementing a GRS transmitter 110 based on a flying capacitor charge pump, in accordance with one embodiment. GRS system 100 includes GRS transmitter 110, a transmission path including a signal line 105 and a ground network 107, and a GRS receiver 130. In one embodiment, GRS transmitter 110 includes two data drivers 112, 114. Input data signals D0 and D1 are presented to GRS transmitter 110 based on a clock signal CLK. Data driver 112 is configured to detect a logic state associated with input D0 and drive output signal Vout 116 on signal line 105 with a pulse corresponding to the logic state of input D0 while CLK is low.Similarly, data driver 114 is configured to detect a logic state associated with input D1 and drive output signal Vout 116 on signal line 105 with a pulse corresponding to the logic state of D1 while CLK is high. A sequence of pulses is formed along signal line 105 corresponding to a sequence of input data from inputs D0 and D1. The sequence of pulses is referenced to ground with a voltage swing that may be lower than conventional logic voltage swings. GRS receiver 130 is configured to amplify an incoming sequence of pulses from signal line 105 and translate the pulses to a conventional logic voltage swing so that the pulses can be correctly interpreted as logic signals on amplifier output signal 132.For example, the sequence of pulses along signal line 105 may have a nominal amplitude of plus or minus 100 mV, while the amplifier output signal 132 may have a corresponding voltage swing of 1200 mV to zero volts with respect to ground when logic coupled to amplifier output signal 132 operates on a 1200 mV positive supply rail.

[0012] In one embodiment, the GRS transmitter 130 is fabricated on a transmitter chip, and the GRS receiver 130 is fabricated on a receiver chip different from the transmitter chip. Pads 120 include bonding pads configured to couple the output signal Vout 116 from the transmitter chip to the signal line 105 fabricated as an impedance-controlled trace within the multi-chip module (MCM) package 190. Pads 122 include bonding pads configured to couple a local ground signal within the transmitter chip to the ground network 107 fabricated within the MCM package 190.Similarly, pads 124 comprise binding pads configured to couple signal line 105 to an input signal for the GRS receiver 130 within the receiver chip, and pads 126 comprise binding pads configured to couple the ground network 107 to a local ground within the receiver chip. A termination resistor RTx is coupled between the output signal Vout 116 and the local ground within the transmitter chip to absorb incoming signals, such as reflections or induced noise signals. A termination resistor RRx is coupled across inputs to the GRS receiver 130 to similarly absorb incoming signals at the receiver chip.

[0013] Data driver 112 includes capacitor C0 and switches S01 through S06. Switch S01 allows a first node of capacitor C0 to be coupled to a positive supply rail, while switch S02 allows a second node of capacitor C0 to be coupled to a local ground net. Switches S01 and S02 are active (closed) during a pre-charge state for data driver 112, defined when CLK is equal to a logic "1" value. Switch S03 allows the first node of capacitor C0 to be coupled to GND, while switch S06 allows the second node of capacitor C0 to be coupled to GND. Switch S04 allows the first node of capacitor C0 to be coupled to Vout 116, while switch S05 allows the second node of capacitor C0 to be coupled to Vout 116.When CLK equals a logic "0" value, switches S04 and S06 are active when data driver 116 drives a logic "1" value to Vout 116, or switches S02 and S05 are active when data driver 112 drives a logic "0" value to Vout 116. Data driver 114 has essentially identical circuit topology, with an inverted sense for CLK, such that data driver 114 is in a pre-charge state when CLK equals a logic "0" value and drives Vout 116 when CLK equals a logic "1" value.

[0014] In one embodiment, switches S01 through S06 and switches S11 through S16 are fabricated using monolithic complementary metal oxide semiconductor (CMOS) devices, such as enhancement-mode n-channel and p-channel field-effect transistors. Any technically feasible logic circuit topologies may be implemented to drive switches S01 through S06 and switches S11 through S16 to individual active or inactive states without departing from the scope and spirit of embodiments of the present invention.

[0015] Fig. 1B illustrates operation of a data driver 112 in a pre-charge state and in two different data-dependent driver states in accordance with one embodiment. As shown, when CLK is equal to a logic "1" value, data driver 112 is in a pre-charge state, with switches S01 and S02 active and capacitor C0 charging to a voltage approximately corresponding to a positive supply rail, such as a "VDD" supply rail. All of switches S03-S06 are inactive (open) during the pre-charge state. When CLK is equal to a logic "0" value, two of switches S03-S06 are configured to couple capacitor C0 to Vout 116 to transmit a pulse having a polarity corresponding to a logic value for D0. To drive a logic “0” value, switches S03 and S05 are actively driven to thereby couple a negative charge relative to ground to Vout 116.To drive a logic “1” value, switches S04 and S06 are actively driven to thereby couple a positive charge relative to ground to Vout 116.

[0016] Fig. 1C illustrates a GRS system 102 implementing a GRS transmitter 150 based on a two-capacitor charge pump, in accordance with one embodiment. GRS system 102 includes GRS transmitter 150, a transmission path including a signal line 105 and a ground network 107, and a GRS receiver 130. In one embodiment, GRS transmitter 150 includes two data drivers 152 and 154. Operation of GRS system 102 is substantially identical to the operation of GRS system 100 described above in Fig. 1A and Fig. 1B, with the exception of the internal topology and the operation of data drivers 152 and 154.

[0017] Data driver 152 includes capacitors C0A and C0B, and switches S0A through S0H. Switch S0A allows a first node of capacitor C0A to be coupled to a positive supply rail, while switch S0C allows a first node to be coupled to a local ground net. Switch S0B allows a second node of capacitor C0A to be coupled to Vout 116, while switch S0D allows the second node to be coupled to the local ground net. Similarly, switch S0E allows a first node of capacitor C0B to be coupled to the positive supply rail, while switch S0G allows a first node to be coupled to the local ground net. Switch S0F allows a second node of capacitor C0B to be coupled to Vout 116, while switch S0H allows the second node to be coupled to the local ground net.

[0018] A pre-charge state for data driver 152 is defined when CLK is equal to a logic "1" value. During the pre-charge state, switches S0A, S0D, S0G, and S0H are actively driven, which pre-charges capacitor C0A to a voltage corresponding to the positive supply rail relative to a local ground network, and which pre-charges capacitor C0B to have approximately no charge. When CLK is equal to a logic "0" value, either capacitor C0A is coupled to Vout 116 to generate a negative pulse, or capacitor C0B is coupled to Vout 116 to generate a positive pulse, as discussed below in connection with Fig. 1E. Data driver 154 has a substantially identical circuit topology, with an inverted sense of CLK such that data driver 154 is in a pre-charge state when CLK equals a logic "0" value and drives Vout 116 when CLK equals a logic "1" value.

[0019] In one embodiment, switches S0A through S0H and switches S1A through S1H are fabricated using monolithic CMOS devices, such as boost-mode n-channel and p-channel FETs. Any technically feasible logic circuit topologies may be implemented to drive switches S0A through S0H and switches S1A through S1H to individually active or inactive states without departing from the scope and spirit of embodiments of the present invention.

[0020] Fig. 1D illustrates operation of data driver 152 in a pre-charge state in accordance with one embodiment. As shown, when CLK is equal to a logic "1" value, switch S0A is active, coupling a first node of capacitor C0A to a positive supply rail, and switch S0D is active, coupling a second node of capacitor C0A to a local ground net. At the same time, switch S0G is active, coupling a first node of capacitor C0B to ground, and switch S0H is active, coupling a second node of capacitor C0B to ground. At the end of this pre-charge state, capacitor C0B is substantially discharged.

[0021] Fig. 1E illustrates operation of data driver 152 in various data-dependent driver states in accordance with one embodiment. As shown, when CLK is equal to a logic "0" value and D0 is equal to a logic "0" value, switches S0C and S0B are configured to couple capacitor C0A to Vout 116 to transmit a pulse having a negative polarity. Alternatively, when CLK is equal to a logic "0" value and D0 is equal to a logic "1" value, switches S0E and S0F are configured to couple capacitor C0B to Vout 116 to transmit a pulse having a positive polarity. Here, it is assumed that the positive supply rail has adequate high frequency capacitive coupling to the local ground network to force a transient flyback current through the local ground network associated with driving Vout 116 with a positive pulse.

[0022] Illustrative information will now be set forth with regard to various optional architectures and features with which the foregoing framework may or may not be implemented, according to the wishes of a designer or user. It should be clearly noted that the following information is set forth for illustrative purposes and should not be interpreted as limiting in any way. Any of the following features may be optionally incorporated with or without the exclusion of other described features.

[0023] Fig. 1F illustrates operation of a ground-referenced single-ended data driver 162 based on a flying capacitor charge pump, in accordance with one embodiment. One or more instances of data driver 162 may be configured to operate as data drivers within a GRS transmitter. For example, an instance of data driver 162 may be configured to operate as data drivers within GRS transmitter 110 instead of data driver 112. Fig. 1A. Similarly, an instance of data driver 162 may be configured to operate instead of data driver 114.

[0024] Data driver 162 includes capacitor C2 and switches S20, S21, S22, S23, and S24, which are configured to precharge capacitor C2 during a pre-charge phase and discharge capacitor C2 into Vout 116 during a data output phase. In one embodiment, a first instance of data driver 162 is configured to operate in a pre-charge phase when a clock signal is in a logic "0" state and to operate in a data output phase when the clock signal is in a logic "1" state. A second instance of data driver 162 is configured to operate in a pre-charge phase when the clock signal is in a logic "1" state and to operate in a data output phase when the clock signal is in a logic "0" state.

[0025] When each instance of data driver 162 is in a pre-charge phase, when D0 is in a logic "1" state, then switches S22 and S21 are active, while switches S20, S23, and S24 are inactive. During the pre-charge phase, when D0 is in a logic "0" state, then switches S20 and S23 are active, while switches S21, S22, and S24 are inactive. During a data output phase, switches S21 and S24 are active, while switches S20, S22, and S23 are inactive. In summary, the flying capacitor C2 is pre-charged with either a positive or negative polarity charge during the pre-charge phase. The charge is then discharged through ground and Vout 116 during the data output phase.

[0026] Fig. 1G illustrates operation of a ground-referenced single-ended data driver 172 based on a two-capacitor charge pump in accordance with one embodiment. One or more instances of data driver 172 may be configured to operate as data drivers within a GRS transmitter. For example, an instance of data driver 172 may be configured to operate as data drivers within GRS transmitter 110 instead of data driver 112. Fig. 1A. Similarly, an instance of data driver 162 may be configured to operate instead of data driver 114.

[0027] Data driver 172 includes capacitors C3, C4 and switches S30, S31, S32, S33, S40, S41, and S42 configured to precharge capacitors C3 and C4 during a precharge phase and discharge one of capacitors C3, C4 in Vout 116 during a data output phase. In one embodiment, a first instance of data driver 172 is configured to operate in a precharge phase when a clock signal is in a logic "0" state and in a data output phase when the clock signal is in a logic "1" state. A second instance of data driver 172 is configured to operate in a precharge phase when the clock signal is in a logic "1" state and in a data output phase when the clock signal is in a logic "0" state.

[0028] When each instance of data driver 172 is in the pre-charge phase, switches S30, S33, S40, and S41 are active, and switches S31, S32, and S42 are inactive. During the data output phase, when D0 is in a logic "0" state, switches S31 and S32 are active, allowing capacitor C3 to discharge a negative polarity charge into Vout 116. At the same time, switches S30, S33, and S40-S42 are inactive. During the data output phase, when D0 is in a logic "1" state, switches S41 and S42 are active, allowing capacitor C4 to discharge a positive polarity charge into Vout 116. At the same time, switches S40 and S30-S33 are inactive.

[0029] Fig. 2A illustrates an exemplary GRS receiver 130 in accordance with one embodiment. As shown, GRS receiver 130 receives input signals Vin 264 and GRef 266 and generates an amplifier output signal 132. In one embodiment, an incoming pulse at Vin 264 having a positive voltage with respect to GRef 266 represents a logic "1," and an incoming pulse at Vin 264 having a negative voltage with respect to GRef 266 represents a logic "0." GRS receiver 130 amplifies a differential voltage between input signals Vin 264 and GRef 266 to generate a corresponding difference signal 262. In one embodiment, the GRS receiver 130 is configured to bias the difference signal 262 to be centered around a switching threshold for the inverter inv3, which amplifies the difference signal 262 to produce an amplifier output signal 132 according to conventional logic voltage levels.

[0030] In one embodiment, GRS receiver 130 includes resistors R1 through R4, inverters inv1 through inv3, capacitor C5, and field-effect transistors n1 and n2. Resistors R2 and R4 may be implemented as variable resistors using any technically feasible technique. An exemplary implementation of a variable resistor provides digital control of a resistance value and includes a set of n-channel FETs connected in a parallel configuration. Each n-channel FET is controlled by a different digital control signal from a control word used to establish the resistance value. If the control word is defined to be a binary number, a corresponding resistance value for the set of n-channel FETs may be monotonic if the n-channel FETs are appropriately sized.In a practical implementation, resistors R2 and R4 are finely tuned to balance the termination of incoming pulses and current injected into Vin 264 and GRef 266 via GRS receiver 130. A monotonic mapping from a binary codeword to a resistance value simplifies any necessary digital trimming required to achieve balanced termination. Any technically feasible technique can be implemented to adjust resistors R2 and R4 to achieve balanced termination.

[0031] Resistors R1 and R3 can also be implemented using any technically feasible technique. For example, resistors R1 and R3 can be implemented as appropriately biased p-channel FETs. Inverters inv1 and inv2 provide gain, while capacitor C5 serves to stabilize a loop formed by inverters inv1 and inv2 in conjunction with resistor R1 and FET n1.

[0032] Fig. 2B illustrates an exemplary GRS receiver unit 270 configured to demultiplex incoming data, in accordance with one embodiment. GRS receiver unit 270 includes GRS receiver 130 and storage elements configured to capture the logic state of amplifier output signal 132 on alternating phases to demultiplex input data represented as incoming pulses on input signal Vin 264, referenced to input signal GRef 266. Each output signal D0 284 and D1 282 presents captured input data at half the frequency of the incoming data pulses.

[0033] In one embodiment, the storage elements include a positive-edge-triggered flip-flop 274 and a negative-edge-triggered flip-flop 272. As shown, the positive-edge-triggered flip-flop 274 is configured to capture D0 during the rising edge of a clock signal CLK 268, while the negative-edge-triggered flip-flop 272 is configured to capture D1 during a falling edge of CLK 268. Such a configuration assumes that CLK 268 and amplifier output signal 132 transition together and that flip-flops 272 and 274 require more setup time than hold time. In alternative embodiments, D0 is captured on a falling edge of CLK 268, while D1 is captured on a rising edge of CLK 268. In other alternative embodiments, the memory elements comprise level-sensitive latches instead of flip-flops.

[0034] Fig. Figure 3 illustrates an exemplary transceiver pair 300 configured to implement GRS signaling, in accordance with one embodiment. As shown, transceiver pair 300 includes a transceiver unit 310 coupled to transceiver unit 370 by signal lines 352, 354, 356, and 358. Signal lines 352, 354, 356, and 358 may be implemented as controlled impedance traces embedded within an MCM packet 190. Transceiver 310 is configured to receive a reference clock 312 operating at one-half the data transmission rate for the signal lines. Adjustable phase delay 332 may introduce an adjustable phase delay before transmitting reference clock 312 to GRS transmitter 322, GRS transmitter 324, and serializer 334.

[0035] As shown, GRS transmitter 322 is configured to transmit a sequential "01" pattern to GRS receiver 382 through fields 342, signal line 352, and fields 362. In one embodiment, this "01" pattern is transmitted at substantially the same phase as data transmitted from GRS transmitter 324 to GRS receiver 384 through fields 344, signal line 354, and fields 364. Serializer 334 receives transmit data 314 at a lower frequency than reference clock 312, but at a correspondingly wider parallel width. For example, if reference clock 312 is configured to operate at 10 GHz and serializer 334 is configured to multiplex a 16-bit word of 2 bits for transmission by GRS transmitter 324, then 16-bit words may arrive at a rate of 10 GHz divided by 8 or 1.25 GHz.Here, a transmission data clock 313 may be generated by serializer 334 to operate at 1.25 GHz for timing transmissions of incoming transmission data 314. In this example, reference clock 312 has a 100 pS period, and each distinct bit transmitted by GRS transmitters 322 and 324 has a unit interval of 50 pS.

[0036] GRS receiver 382 receives a phase-delayed version of reference clock 312 through signal line 352 and generates a local reference clock 383, which may be coupled to GRS receiver 384 for capturing incoming pulses on signal line 354. Local reference clock 383 may also be coupled to serializer 394 for capturing and demultiplexing data from GRS receiver 384. Extending the above example, GRS receiver 384 may capture incoming pulses on alternating clock phases from local reference clock 383, which operates at 10 GHz, to generate 2 bits every 100 pS. Deserializer 394 is configured to demultiplex sequential data comprising 2 bits from GRS receiver 384 and generate corresponding 16-bit words at a rate of 1.25 GHz. The 16-bit words are presented as receive data 374. Deserializer 394 may generate receiver data clock 373 to reflect appropriate clocking for receive data 374.Receive data 374 represents a local copy of transmit data 314. In one embodiment, deserializer 394 is configured to align incoming data along word boundaries. Those skilled in the art will understand that serialization and deserialization of parallel data may require alignment of the parallel data along word boundaries, and that well-known techniques of the art may be implemented using receiver unit 370 or associated logic without departing from the scope and spirit of embodiments of the present invention.

[0037] Serializer 396 captures incoming transmit data 376 and serializes the data for transmission by GRS transmitter 386 through signal line 356. In one embodiment, serializer 396 generates transmit data clock 375 based on local reference clock 383 as a timing reference for incoming transmit data 376. GRS receiver 326 captures the data arriving from signal line 356, and deserializer 336 demultiplexes the data into words, presented as receive data 316. GRS transmitter 388 is configured to transmit a sequential "01" pattern to GRS receiver 328 through fields 368, signal line 358, and fields 348. In one embodiment, this "01" pattern is transmitted at substantially the same phase as data transmitted from GRS transmitter 386 to GRS receiver 326 through fields 366, signal line 356, and fields 346.GRS receiver 328 and adjustable phase delay 338 generate a receive clock 318 based on the sequential "01" pattern. In one embodiment, receive data clock 315 is generated by serializer 336 to reflect appropriate timing for receive data 316.

[0038] Determining a correct phase delay value for adjustable phase delay 332 and adjustable phase delay 338 may be performed using any technically feasible technique. For example, the phase delay values ​​for adjustable phase delay 332 and adjustable phase delay 338 may be swept over a range of phase delay values ​​during a link training phase, thereby determining phase delays corresponding to a substantially minimal bit error rate during training and used for normal link operation.

[0039] Although an isochronous clock model is illustrated herein for communicating data between transceiver unit 310 and transceiver unit 370, any technically feasible clock model may be implemented without departing from the scope and spirit of embodiments of the present invention.

[0040] Fig. Figure 4A illustrates a GRS data driver 400 comprising a CMOS circuit, in accordance with one embodiment. As shown, the CMOS circuit illustrates a circuit topology that can be used to implement the data driver 162 of Fig. 1F using CMOS circuit elements. In particular, switches S20 and S22 are implemented as p-channel FET p40 and p-channel FET p42, respectively; and switches S21, S23, and S24 are implemented as n-channel FET n41, n-channel FET n43, and n-channel FET n44, respectively. A reference node 410 is coupled to a capacitor C7, p-channel FET p40, and n-channel FET n41. An output node 412 is coupled to an opposite side of capacitor C7, as well as to p-channel FET p42, n-channel FET n43, and n-channel FET n44.

[0041] Control signal g40 is coupled to a gate node of p-channel FET p40. When control signal g40 is driven to a logic 0 level, p-channel FET p40 turns on, pulling node 410 to a voltage level associated with VDD. Control signal g41 is coupled to a gate node of n-channel FET n41. When control signal g41 is driven to a logic 1 level, n-channel FET n41 turns on, pulling node 410 to a voltage level associated with GND. Similarly, p-channel FET p42 responds to control signal g42 to selectively pull node 412 to VDD, while n-channel FET n43 responds to control signal g43 to selectively pull node 412 to GND. Control signal g44 is coupled to a gate node of n-channel FET n44. When control signal g44 is driven to a logic 0 level, n-channel FET n44 essentially isolates node 412 from node Vout 416.However, when control signal g44 is driven to a logic 1 level, n-channel FET n44 forms a low-impedance path between node 412 and Vout 416. As discussed below in connection with . Fig. As described in Figure 4D, this low-impedance path allows Vout 416 to be driven with a suitable signal.

[0042] GRS data driver 400 primarily operates in three different states, including a first pre-charge state for successively driving a data value of zero, a second pre-charge state for successively driving a data value of one, and a drive state for driving a signal line, such as signal line 105, with a signal corresponding to a previous pre-charge state. These states are described below in Fig. 4B-4D. Transitions between pre-charge states and the driver state are orchestrated by control signals g40 to g44.

[0043] Fig. 4B illustrates GRS data driver 400 in the first pre-charge state, which is associated with driving a data value of zero, in accordance with one embodiment. As shown, in the first pre-charge state, control signal g40 is set to zero to turn on p-channel FET p40, thereby coupling node 411 to VDD. At the same time, control signal g43 is set to one (1) to turn on n-channel FET n43, thereby coupling node 412 to GND. Also, control signal g42 is set to one to turn off p-channel FET p42, and control signals g41 and g44 are set to zero to turn off n-channel FET n41 and n-channel FET n44, respectively. In this first pre-charge state, capacitor C7 is charged with a positive charge at node 410 and a negative charge at node 412, which is electrically isolated from node Vout 416.

[0044] Fig. 4C illustrates GRS data driver 400 in the second pre-charge state, which is associated with driving a data value of one, in accordance with one embodiment. As shown, in the second pre-charge state, control signal g42 is set to zero to turn on p-channel FET p42, thereby coupling node 412 to VDD. At the same time, control signal g41 is set to one to turn on n-channel FET n41, thereby coupling node 410 to GND. Also, control signal g40 is set to one to turn off p-channel FET p40, and control signals g43 and g44 are set to zero to turn off n-channel FET n43 and n-channel FET n44, respectively. In this second pre-charge state, capacitor C7 is charged with a negative charge on node 410 and a positive charge on node 412, which is electrically isolated from node Vout 416.

[0045] Fig. Figure 4D illustrates GRS data driver 400 in a drive state in accordance with one embodiment. As shown, control signal g41 is set to one, coupling node 410 to ground, and control signal g44 is set to one, coupling node 412 to node Vout 416. Control signals g40 and g42 are set to one to turn off p-channel FET p40 and p-channel FET p42, respectively. Additionally, control signal g43 is set to zero to turn off n-channel FET n43. In this state, capacitor C7 discharges into node Vout 416. If a negative charge has been accumulated in capacitor C7 in a previous pre-charge state, then C7 discharges the negative charge into node Vout 416 with respect to ground. Otherwise, if a positive charge has been accumulated in capacitor C7 in a previous pre-charge state, then C7 discharges a positive charge into node Vout 416 with respect to GND.Current passing through node Vout 416 is essentially balanced with a corresponding ground current passing through GND.

[0046] Capacitor C7 may be implemented using any technically feasible technique without departing from the scope and spirit of embodiments of the present invention. In one embodiment, capacitor C7 is implemented using n-channel FETs according to one embodiment. For example, a gate node of a first n-channel FET may be connected to node 412 of Fig. 4A to form a back-to-back metal-oxide-transistor capacitor. Additionally, the source and drain nodes of the first n-channel FET may be coupled to node 410. A gate node of a second n-channel FET may be coupled to node 410, while the source and drain nodes of the second n-channel FET may be coupled to node 412. Gate capacitance is relatively area-efficient compared to other capacitor structures available within a CMOS process. However, gate capacitance varies significantly with charge polarity. To compensate for polarity-dependent gate capacitance, two n-channel devices are symmetrically configured to store charges of opposite polarities. In this way, a positive pulse discharged into node Vout 416 has a substantially equal magnitude relative to a negative pulse discharged into Vout 416.

[0047] In another embodiment, capacitor C7 may be implemented using traces in adjacent metal layers. For example, traces in sequential metal layers may be configured to provide plate capacitance (Cp) and edge capacitance (Ce) between nodes 410 and 412. Unlike gate capacitance, plate and edge capacitance between metal structures embedded within conventional dielectric materials are stable with respect to polarity. However, a capacitor formed using metal layer traces may require more die area compared to a capacitor formed using gate capacitance for an equivalent capacitance value.While two parallel traces on two adjacent layers may be used to implement capacitor C7, one skilled in the art will understand that such a metal oxide metal (MOM) capacitor may be realized using more than two layers and more than two adjacent traces on each layer.

[0048] Fig. 5A illustrates a GRS transmitter 550 comprising two instances of a GRS data driver 400, in accordance with one embodiment. As shown, GRS transmitter 550 receives data input signals D0 and D1 synchronized to clock signal CLK. Control logic 502 receives signals D0, D1, and CLK and, in response, generates driver control signals 510 and driver control signals 512. In one embodiment, driver control signals 510 comprise control signals g40 through g44 for instance 400(0) of GRS data driver 400, and driver control signals 512 comprise control signals g40 through g44 for instance 400(1) of GRS data driver 400.

[0049] In one embodiment, when CLK is in a logic one state, control logic 502 configures instance 400(0) to operate in a pre-load state. If D0 is in a logic zero state, then instance 400(0) enters the pre-load state, which is associated with driving a data value of zero, illustrated previously in Fig. 4B. Here, driver control signals 510 are generated such that g40=0, g41=0, g42=1, g43=1, and g44=0. If, instead, D0 is in a logic one state, then instance 400(0) enters the pre-load state, which is associated with driving a data value of one, illustrated previously in Fig. 4C. Here, driver control signals 510 are generated such that g40=1, g41=1, g42=0, g43=0, and g44=0. When CLK is in a logic zero state, control logic 502 configures instance 400(0) to operate in a driver state previously in Fig. 4D. Here, driver control signals 510 are generated such that g40=1, g41=1, g42=1, g43=0, and g44=1.

[0050] If CLK is in a logic zero state, control logic 502 configures instance 400(1) to operate in a pre-load state. If D1 is in a logic zero state, then instance 400(1) enters the pre-load state, which is associated with driving a data value of zero, previously in Fig. 4B. Here, driver control signals 512 are generated such that g40=0, g41=0, g42=1, g43=1, and g44=0. If, instead, D1 is in a logic one state, then instance 400(1) enters the pre-load state, which is associated with driving a data value of one, previously illustrated in Fig. 4C. Here, driver control signals 512 are generated such that g40=1, g41=1, g42=0, g43=0, and g44=0. When CLK is in a logic one state, control logic 502 configures instance 400(1) to operate in the driver state previously in Fig. 4D. Here, driver control signals 510 are generated such that g40=1, g41=1, g42=1, g43=0, and g44=1.

[0051] The Vout 416 signal for each instance 400(0), 400(1) is coupled to a common Vout 516 signal, which is further coupled to an array 520. In one embodiment, Vout 516 is coupled to array 522 via resistor RTx. Array 522 is coupled to a circuit ground node, which is GND in Fig. 4A-4D.

[0052] In one embodiment, GRS transmitter 550 is configured to receive GRS transmitter 110 from Fig. 1A. Here, fields 520 couple Vout 516 to signal line 105 and field 522 couples GND to ground network 107. In such a configuration, GRS receiver 130 receives data from GRS transmitter 550. In certain embodiments, GRS transmitter 550 includes GRS Tx 322, GRS Tx 324, GRS Tx 386 and GRS Tx 388 of Fig. 3 on.

[0053] Fig. 5B illustrates timing for a GRS transmitter 550 in accordance with one embodiment. As shown, a bit of data from input D0 is transmitted to Vout 516 during time k+1 when CLK is in a logic zero state, and a bit of data from input D1 is transmitted to Vout 516 during time k+2 when CLK is in a logic one state. In one embodiment, inputs D0 and D1 are synchronized with and updated on the rising edge of CLK. In such an embodiment, instance 400(1) is in a data-driving state when inputs D0 and D1 change in response to a rising edge of CLK, which occurs at time k. On the rising edge of CLK, which occurs at time k, instance 400(0) enters a pre-present state to thereby sample data on D0.On the falling edge of CLK, which leaves time k and enters time k+1, instance 400(0) enters a data-driving state and drives the captured data from D0 to Vout 516. On the falling edge of CLK, which enters time k+1, instance 400(1) enters a pre-load state to thereby sample data onto D1. On the rising edge of CLK, leaving time k+1 and entering time k+2, instance 400(1) enters a data-driven state and drives the captured data from D1 to Vout 516. In this way, data comprising D0 and D1 can be presented to GRS transmitter 550 using conventional logic having conventional single-edge synchronous timing, while GRS transmitter 550 time-multiplexes the data for transmission at twice the data rate. In other words, two data transfers occur in each period or clock of CLK.In a preferred embodiment, D0 is latched when CLK is low to ensure that D0 is stable while used to control the pre-charging of instance 400(0). Similarly, D1 is latched when CLK is high to ensure that D1 is stable while used to control the pre-charging of instance 400(1).

[0054] In other embodiments, a GRS transmitter having more than two instances of GRS data driver 400 is configured to receive one data bit per instance of GRS data driver 400 and time-multiplex the data at a correspondingly higher data rate. In such embodiments, multiple clock signals may be required to provide appropriate timing for pre-charging and driving data to time-multiplex the data.

[0055] Fig. 5C illustrates a flowchart of a method 560 for generating a ground-referenced single-ended signal in accordance with one embodiment. Although method 560 is described in the context of Fig. 4A-5B to implement a two-to-one time-multiplexing ratio of input data to output data, those skilled in the art will understand that any system performing method 560 is within the scope and spirit of embodiments of the present invention.

[0056] Method 560 begins at step 565, where a first data driver, such as instance 400(0) of GRS data driver 400, samples a first bit of data by pre-charging a first capacitor for a first time k. The first capacitor is charged to have a polarity corresponding to a logic level of the first bit of data. In step 570, a second data driver, such as instance 400(1) of GRS data driver 400, samples a second bit of data by pre-charging a second capacitor for a time k+1. The second capacitor is charged to have a polarity corresponding to a logic level of the second bit of data.

[0057] In step 575, the first data driver drives an output signal, such as Vout 416 of Fig. 4A-4D or Vout 516 from Fig. 5A, to reflect the first bit of data by coupling the first capacitor to the output signal during time k+1. Here, the first capacitor is coupled between a ground network and the output signal. The polarity of charge on the first capacitor, established in step 565, is based on the logic level for the first bit of data. When coupled to the output signal, the first capacitor therefore reflects the logic level for the first bit of data.

[0058] In step 580, the second data driver drives the output signal to reflect the second bit of data by coupling the second capacitor to the output signal for a time k+2. Here, the second capacitor is coupled between a ground network and the output signal. The polarity of charge on the second capacitor, established in step 570, is based on the logic level for the second bit of data. Therefore, when coupled to the output signal, the second capacitor reflects the logic level for the first bit of data. Method 560 terminates after driving the output signal to reflect the second bit of data.

[0059] In other embodiments, a time-multiplexing ratio greater than two may be implemented and at least one additional phase-related clock may be provided to orchestrate operation of more than three instances of GRS data driver 400. Multi-phase ground-referenced signaling

[0060] An alternative to time-multiplexing the outputs of two or more instances of the GRS data driver 400 to increase the data rate is to transmit data over three or more phases of a clock signal. Specifically, when four phases of the clock signal are used, data can be transmitted at twice the rate compared to a system configured to perform 2-to-1 multiplexing. For example, when four phases are used, each of four transmitters and corresponding receiver circuits operates at 1 / 4 the bit rate compared to 1 / 2 the bit rate for a 2-to-1 multiplexed implementation. Instead of precharging the capacitor(s) in each transmitter circuit during 1 / 2 of the clock cycle, when four phases are used, 3 / 4 of each clock cycle (three phases) is available to precharge the capacitor(s) in each transmitter circuit.

[0061] Fig. 6A illustrates timing 600 for a multi-phase GRS transmitter having four GRS data drivers, in accordance with one embodiment. A clock signal, represented by an in-phase clock signal iCLK and a quadrature clock signal qCLK, is used to generate each of the four phases P0, P1, P2, and P3. The P0 signal, corresponding to the first phase of the clock signal, may be generated as the AND of inverted iCLK and inverted qCLK. The P1 signal, corresponding to the second phase of the clock signal, may be generated as the AND of iCLK and inverted qCLK. The P2 signal, corresponding to the third phase of the clock signal, may be generated as the AND of iCLK and qCLK. The P3 signal, which corresponds to the fourth phase of the clock signal, can be generated as the AND of qCLK and inverted iCLK.

[0062] The transmitter circuits M0, M1, M2, and M3 correspond to the data drivers that generate the output signals for each of the phases P0, P1, P2, and P3, respectively. As shown in the waveforms, an M0 transmitter circuit drives the output during a first phase when signal P0 is asserted. In one embodiment, a first capacitor in a first transmitter circuit M0 is discharged during the first phase to drive the output signal, and the first capacitor is precharged during at least one phase other than the first phase (e.g., the second, third, and / or fourth phase). Similarly, a second capacitor in a second transmitter circuit M1 is discharged during the second phase to drive the output signal, and the second capacitor is precharged during at least one phase other than the second phase (e.g., the first, third, and / or fourth phase).A third capacitor in a third transmitter circuit M2 is discharged during the third phase to drive the output signal, and the third capacitor is precharged during at least one phase other than the third phase (e.g., the first, second, and / or fourth phase). A fourth capacitor in a fourth transmitter circuit M3 is discharged during the fourth phase to drive the output signal, and the fourth capacitor is precharged or precharged during at least one phase other than the fourth phase (e.g., the first, second, and / or third phase).

[0063] Fig. 6B illustrates a multi-phase GRS transmitter 650 comprising four instances of a GRS data driver 400, in accordance with one embodiment. As shown, the GRS transmitter 650 receives data input signals D0, D1, D2, and D3 synchronized to a clock signal. An oscillator 605 generates one or more signals that encode the clock signal. For example, the oscillator 605 may provide in-phase and quadrature clock signals iCLK and qCLK, and inverted versions of iCLK and qCLK, to control logic 602.

[0064] Control logic 602 receives the one or more signals encoding the clock signal and the data input signals D0, D1, D2, and D3 and, in response, generates driver control signals 610, 612, 614, and 618. In one embodiment, driver control signals 610 include control signals g40 through g44 for instance 400(4) of GRS data driver 400, driver control signals 612 include control signals g40 through g44 for instance 400(5) of GRS data driver 400, driver control signals 614 include control signals g40 through g44 for instance 400(6) of GRS data driver 400, and driver control signals 618 include control signals g40 through g44 for instance 400(7) of GRS data driver 400.

[0065] In one embodiment, if P0 is in a logic zero state during one or more of phases P1, P2, and P3, control logic 602 configures instance 400(4) to operate in a pre-charge state. If D0 is in a logic zero state, then instance 400(4) enters the pre-charge state, which is associated with driving a data value of zero, which was previously in Fig. 4B. Here, driver control signals 610 are generated such that g40=0, g41=0, g42=1, g43=1, and g44=0. If, instead, D0 is in a logical one state, then instance 400(4) enters the pre-load state, which is associated with driving a data value of one, which was previously in Fig. 4C. Here, driver control signals 610 are generated such that g40=1, g41=1, g42=0, g43=0, and g44=0. When P0 is in a logical one state, control logic 602 configures instance 400(4) to operate in the driver state, which was previously Fig. 4D. Here, driver control signals 610 are generated such that g40=1, g41=1, g42=1, g43=0, and g44=1.

[0066] In one embodiment, when P1 is in a logic zero state during one or more of phases P0, P2, and P3, control logic 602 configures instance 400(5) to operate in a pre-charge state. If D1 is in a logic zero state, then instance 400(5) enters the pre-charge state, which is associated with driving a data value of zero, as previously described in Fig. 4B. Here, driver control signals 612 are generated such that g40=0, g41=0, g42=1, g43=1, and g44=0. If, instead, D1 is in a logic one state, then instance 400(5) enters the pre-charge state, which is associated with driving a data value of one, as previously described in Fig. 4C. Here, driver control signals 612 are generated such that g40=1, g41=1, g42=0, g43=0, and g44=0. When P1 is in a logic one state, control logic 602 configures instance 400(5) to operate in the driver state previously configured in Fig. 4D. Here, driver control signals 612 are generated such that g40=1, g41=1, g42=1, g43=0, and g44=1.

[0067] In one embodiment, if P2 is in a logic zero state during one or more of phases P0, P1, and P3, control logic 602 configures instance 400(6) to operate in a pre-charge state. If D0 is in a logic zero state, then instance 400(6) enters the pre-charge state, which is associated with driving a data value of zero, previously in Fig. 4B. Here, driver control signals 614 are generated such that g40=0, g41=0, g42=1, g43=1, and g44=0. If, instead, D2 is in a logic one state, then instance 400(6) enters the pre-charge state, which is associated with driving a data value of one, as previously described in Fig. 4C. Here, driver control signals 614 are generated such that g40=1, g41=1, g42=0, g43=0, and g44=0. When P2 is in a logic one state, control logic 603 configures instance 400(6) to operate in the driver state previously configured in Fig. 4D. Here, driver control signals 614 are generated such that g40=1, g41=1, g42=1, g43=0, and g44=1.

[0068] In one embodiment, if P3 is in a logic zero state during one or more of phases P0, P1, and P2, control logic 602 configures instance 400(7) to operate in a pre-charge state. If D3 is in a logic zero state, then instance 400(7) enters the pre-charge state, which is associated with driving a data value of zero, previously in Fig. 4B. Here, driver control signals 618 are generated such that g40=0, g41=0, g42=1, g43=1, and g44=0. If, instead, D3 is in a logic one state, then instance 400(7) enters the pre-load state, which is associated with driving a data value of one, previously in Fig. 4C. Here, driver control signals 618 are generated such that g40=1, g41=1, g42=0, g43=0, and g44=0. When P3 is in a logic one state, control logic 602 configures instance 400(7) to operate in the driver state previously configured in Fig. 4D. Here, driver control signals 618 are generated such that g40=1, g41=1, g42=1, g43=0, and g44=1.

[0069] The Vout 416 signal of each instance 400(4), 400(5), 400(6), 400(7) is coupled to a common Vout 616 signal, which is further coupled to a field 620. In one embodiment, Vout 616 is coupled to field 622 via resistor RTx. Fields 622 may be connected to a circuit ground node corresponding to GND in Fig. 4A-4D must be coupled.

[0070] In one embodiment, GRS transmitter 650 is configured to receive GRS transmitter 110 from Fig. 1A. Here, field 620 couples Vout 616 to signal line 105 and field 622 couples GND to ground network 107. In such a configuration, GRS receiver 130 receives data from GRS transmitter 650. In certain embodiments, GRS transmitter 650 includes GRS Tx 322, GRS Tx 324, GRS Tx 386 and GRS Tx 388 of Fig. 3 on.

[0071] In one embodiment, each instance 400(4), 400(5), 400(6), 400(7) is associated with an instance of data driver 112 of Fig. 1A and Fig. 1B replaced, data driver 152 from Fig. 1C, Fig. 1D and Fig. 1E or data driver 172 from Fig. 1G. When data driver 112 is used, driver control signals 610, 612, 614, and 618 comprise control signals S01 through S06 for each instance of GRS data driver 112. For the GRS data driver 112 corresponding to the first phase, when P0 is in a logic zero state during one or more of phases P1, P2, and P3, control logic 602 configures the GRS data driver 112 corresponding to the first phase to operate in a pre-charge state, which was previously in Fig. 1B. Here, driver control signals 610 are generated such that S01=1, S02=1, and S03-S06=0. For the GRS data driver 112 corresponding to the first phase, when P0 is in a logic one state, control logic 602 configures the GRS data driver 112 corresponding to the first phase to operate in a driver state, which was previously described in Fig. 1B. If D0 is in a logic zero state, then the GRS data driver 112 corresponding to the first phase enters the drive state associated with driving a data value of zero. Here, drive control signals 610 are generated such that S01=S02=0, S03=1, S04=0, S05=1, and S06=0. If, instead, D0 is in a logic one state, then the GRS data driver 112 corresponding to the first phase enters the drive state associated with driving a data value of one. Here, drive control signals 610 are generated such that S01=S02=0, S03=0, S04=1, S05=0, and S06=1. The data drivers 112, which correspond to phases P1, P2 and P3, are controlled in a respective manner by means of the driver control signals 612, 614 and 618.

[0072] When data driver 152 is used in GRS transmitter 650, driver control signals 610, 612, 614, and 618 comprise control signals S0A through S0H for each instance of GRS data driver 152. For the GRS data driver 152 corresponding to the first phase, when P0 is in a logic zero state during one or more of phases P1, P2, and P3, control logic 602 configures the GRS data driver 152 corresponding to the first phase to operate in a pre-charge state, which was previously described in Fig. 1D. Here, driver control signals 610 are generated such that S0A=1, S0B=0, S0C=0, S0D=1, S0E=0, S0F=0, S0G=1, and S0H=1. For the GRS data driver 152 corresponding to the first phase, when P0 is in a logic one state, control logic 602 configures the GRS data driver 152 corresponding to the first phase to operate in a driver state as previously described in Fig. 1E. If D0 is in a logic zero state, then the GRS data driver 152, corresponding to the first phase, enters the drive state associated with driving a data value of zero. Here, drive control signals 610 are generated such that S0A=0, S0B=1, S0C=1, S0D=0, and S0E=H=0. If, instead, D0 is in a logic one state, then the GRS data driver 152, corresponding to the first phase, enters the drive state associated with driving a data value of one. Here, drive control signals 610 are generated such that S0A=0, S0E=1, S0F=1, S0G=0, and S0H=0. The data drivers 152, which correspond to phases P1, P2 and P3, are controlled in a respective manner by means of the driver control signals 612, 614 and 618.

[0073] If data driver 172, which is in Fig. 1G, in which GRS transmitter 650 is used, driver control signals 610, 612, 614, and 618 comprise control signals S30-S33 and S40-S42 for each instance of GRS data driver 172. For the GRS data driver 172 corresponding to the first phase, when P0 is in a logic zero state during one or more of phases P1, P2, and P3, control logic 602 configures the GRS data driver 172 corresponding to the first phase to operate in a pre-charge state. Here, driver control signals 610 are generated such that S30=1, S31=0, S32=0, S33=1, S40=1, S41=1, and S42=0. For the GRS data driver 172 corresponding to the first phase, when P0 is in a logic one state, control logic 602 configures the GRS data driver 172 corresponding to the first phase to operate in a driver state.If D0 is in a logic zero state, then the GRS data driver 172, corresponding to the first phase, enters the drive state associated with driving a data value of zero. Here, driver control signals 610 are generated such that S30=0, S31=1, S32=1, S33=0, S40=0, S41=0, and S42=0. If, instead, D0 is in a logic one state, then the GRS data driver 172, corresponding to the first phase, enters the drive state associated with driving a data value of one. Here, driver control signals 610 are generated such that S30=0, S31=0, S32=0, S33=0, S40=0, S41=1, and S42=1. The data drivers 172, which correspond to phases P1, P2 and P3, are controlled by the driver control signals 612, 614 and 618 in a respective manner.

[0074] Fig. 6C illustrates an instance of a GRS data driver 400 of Fig. 6B, which corresponds to a phase of the clock signal, in accordance with one embodiment. As previously described in connection with Fig. 4A-4D, capacitor C7 is precharged with a positive or negative voltage depending on the input data, and capacitor C7 is discharged in the same direction. The input data Di (e.g., D0, D1, D2, and D3) is acquired during phase Pi (e.g., P0, P1, P2, and P3) so that the input data is held stable during the precharge state. Logic gates N0, N1, N2, and N3 are configured to precharge capacitor C7, and logic gate N0 is configured to discharge capacitor C7 in a drive state to drive Vout 416. Specifically, capacitor C7 is precharged in the positive direction when Di is a logic one and p-channel FET p42 and n-channel FET n41 are both turned on, as shown in Fig. 4C. The capacitor C7 is precharged in the negative direction with Di being a logic zero and the p-channel FET p40 and the n-channel FET n43 are both turned on, as shown in Fig. 4B. When Pi is a logical one, the n-channel FET n41 and the n-channel FET n44 are both turned on to discharge the capacitor C7 between Vout 416 and ground, as shown in Fig. 4D is illustrated.

[0075] Fig. Figure 6D illustrates a four-phase ring oscillator circuit 605 in accordance with one embodiment. The four-phase ring oscillator circuit 605 can be used to generate the signals that encode the clock signals, iCLK and qCLK, as well as the inverted clock signals, iCLKN and qCLKN, respectively.

[0076] A cross-coupling of the inverters, which are in Fig. 6D can be implemented to exclude the stable states of the dynamic circuit and ensure that the circuit will oscillate. In one embodiment, the oscillator circuit 605 is operated as a voltage-controlled oscillator (VCO) of a phase-locked loop (PLL) by modulating the power supply of the oscillator circuit 605. In one embodiment, the oscillator circuit 605 may be followed by a duty-factor correction circuit configured to adjust each output so that both iCLK and qCLK have a 50% duty-factor. In one embodiment, the oscillator circuit 605 is followed by a phase correction circuit that adjusts the phase of the qCLK output so that times between which P1 and P2 are logic ones have substantially identical durations and the times between which P0 and P3 are logic ones have substantially identical durations.

[0077] The two signals iCLK and qCLK, which encode the clock signal, can be forwarded to the destination to reduce the effects of fixed-pattern jitter. At a receiver, the forwarded clock signals can be used to sample the received data signals using an integrating or point-sampling receiver, as described in further detail in connection with Fig. 8A, Fig. 8B and Fig. 8C. In one embodiment, the iCLK signal may be transmitted with the data by configuring a multi-phase GRS transmitter 650 with the data input sets at D3=0, D2=1, D1=1, and D0=0. In one embodiment, the qCLK signal may be transmitted with the data by configuring a multi-phase GRS transmitter 650 with the data input set at D3=0, D2=0, D1=1, and D0=1. In one embodiment, a phase rotator circuit is inserted in the clock path from the oscillator 605 to the multi-phase GRS transmitters 650 and / or the two multi-phase GRS transmitters 650 configured to generate the propagated clock signals to enable adjustment of the relative phase between the data and the propagated clock signals iCLK and qCLK.

[0078] Fig. 7A and Fig. 7B illustrate a flowchart of a method 700 for generating a multi-phase GRS signal in accordance with one embodiment. Although method 700 is described in the context of Fig. 6A-6D, implementing an N-phase transmitter, where N=4, those skilled in the art will understand that any system performing method 700 is within the spirit and scope of embodiments of the present invention. In particular, method 700 may be extended to perform multi-phase signaling for three phases, as described in connection with Fig. 9A and Fig. 9B, or for more than four phases.

[0079] Method 700 begins in step 710, where a controller, such as control logic 602 of GRS transmitter 650, generates N sets of control signals, each set of control signals corresponding to one of N phases of a clock signal. A first set of control signals 610 is generated based on a first phase of a clock signal, P0. The controller generates a second set of control signals 612 based on a second phase of the clock signal, P1. The controller generates a third set of control signals 614 based on a third phase of the clock signal, P2. The controller generates a fourth set of control signals 618 based on a fourth phase of the clock signal, P3.

[0080] In one embodiment, the first set of control signals 610 is generated based on a first input data signal D0 and a first clock phase signal P0, the second set of control signals 612 is generated based on a second input data signal D1 and a second clock phase signal P1, the third set of control signals 614 is generated based on a third input data signal D2 and a third clock phase signal P2, and the fourth set of control signals 618 is generated based on a fourth input signal D3 and a fourth clock phase signal P3.

[0081] In step 715, a first data driver, such as instance 400(4) of GRS data driver 400 within GRS transmitter 650, drives an output signal relative to a ground network based on a first charge during a first phase of the clock signal, wherein the output signal is a GRS signal. The first charge is stored by pre-charging a first capacitor in the first data driver based on the first set of control signals during at least one phase of the clock signal other than the first phase of the clock signal. In one embodiment, the first capacitor is coupled between the first output node and a first reference node. As in Fig. As shown in Figure 6A, during the first phase, when P0 is a logic one, M0, corresponding to instance 400(4), drives the output signal.

[0082] In step 720, a fourth data driver, such as instance 400(7) of GRS data driver 400 within GRS transmitter 650, samples a fourth bit of data by precharging a fourth capacitor during at least one phase starting at the first phase. As in Fig. As shown in Figure 6A, when P0 is a logical one, M3, corresponding to instance 400(7), is in the pre-charge state.

[0083] In step 725, a second data driver, such as instance 400(5) of GRS data driver 400 within GRS transmitter 650, drives the output signal relative to the ground network based on a second charge during a second phase of the clock signal. The second charge is stored by pre-charging a second capacitor in the second data driver based on the second set of control signals during at least one phase of the clock signal other than the second phase of the clock signal. As shown in Fig. As shown in Figure 6A, during the second phase, when P1 is a logic one, M1, corresponding to instance 400(5), drives the output signal.

[0084] In step 730, the first data driver samples the first bit of data by precharging the first capacitor during at least one phase starting at the second phase. As in Fig. As shown in Figure 6A, during the second phase, when P1 is a logic one, M0, corresponding to instance 400(4), is in the pre-charge state.

[0085] In step 735, a third data driver, such as instance 400(6) of GRS data driver 400 within GRS transmitter 650, drives the output signal relative to the ground network based on a third charge during a third phase of the clock signal. The third charge is stored by pre-charging a third capacitor in the third data driver based on the third set of control signals during at least one phase of the clock signal other than the third phase of the clock signal. As shown in Fig. As shown in Figure 6A, during the third phase, when P2 is a logic one, M2, corresponding to instance 400(6), drives the output signal.

[0086] In step 740, the second data driver samples the second bit of data by precharging the second capacitor during at least one phase starting at the third phase. As in Fig. As shown in Figure 6A, during the third phase, when P2 is a logic one, M1, corresponding to instance 400(5), is in the pre-charge state.

[0087] In step 745, the fourth data driver drives the output signal relative to the ground network based on a fourth charge during a fourth phase of the clock signal. The fourth charge is stored by pre-charging a fourth capacitor in the fourth data driver based on the fourth set of control signals during at least one phase of the clock signal other than the fourth phase of the clock signal. As in Fig. As shown in Figure 6A, during the fourth phase, when P3 is a logic one, M3, corresponding to instance 400(7), drives the output signal.

[0088] In step 750, the third data driver samples the third bit of data by precharging the third capacitor during at least one phase starting at the fourth phase. As in Fig. As shown in Figure 6A, during the fourth phase, when P3 is a logic one, M2, corresponding to instance 400(6), is in the pre-charge state.

[0089] Fig. 8A illustrates a multi-phase GRS receiver 850 comprising four instances of a GRS data receiver 800, in accordance with one embodiment. A four-phase GRS signal 833 is separated into four bits of data, D0, D1, D2, and D3, by the four GRS data receivers 800(0)-800(3) using iCLK and qCLK. The clock signals can be communicated with Vout 616 and used to capture and store the logic state of signal 833 generated by a GRS receiver 130 (illustrated in Fig. 2A) on the different clock phases P0, P1, P2 and P3 to demultiplex input data represented as incoming pulses on input signal Vin 864, referenced to input signal GRef 866. Each output signal D0, D1, D2 and D3 generated by the GRS data receivers 800 is captured input data for one of the four phases.

[0090] In one embodiment, GRS data receivers 800 include a negative-edge-triggered flip-flop. As shown, a negative-edge-triggered flip-flop is configured to capture signal 833 during the falling edge of a signal that is the AND of iCLKN and qCLKN to generate D0, where iCLKN is the inverted iCLK and where qCLKN is the interverted qCLK. In alternative embodiments, signal 833 is captured on a rising edge of the signal that is the AND of iCLKN and qCLKN to generate D0. In other alternative embodiments, the storage elements include level-sensitive latches instead of flip-flops. As shown, a negative-edge triggered flip-flop within GRS data receiver 800(1) is configured to capture signal 833 during the falling edge of a signal that is the AND of iCLK and qCLKN to generate D1.A negative-edge triggered flip-flop within GRS data receiver 800(2) is configured to capture signal 833 during the falling edge of a signal that is the AND of iCLK and qCLK to generate D2. A negative-edge triggered flip-flop within GRS data receiver 800(3) is configured to capture signal 833 during the falling edge of a signal that is the AND of iCLKN and qCLK to generate D3.

[0091] In one embodiment, GRS data receivers 800 are integrating receivers that integrate signal 833 during a respective one of the phases to generate a characterized output signal, which is detected during a subsequent phase. The sensing circuitry is then precharged during one or more remaining phases. For example, GRS data receiver 800(0) may be configured to integrate signal 833 during the first phase P0 to generate a first characterized output signal, sense the first characterized output signal during the second phase P1, and precharge the detection circuitry during the third and / or fourth phases P3 and / or P4.

[0092] In another embodiment, the GRS data receivers 800 are sampling receivers that sample the signal 833 at a particular time during each of the phases to generate the output signals. The particular time at which the signal 833 is sampled may be determined by interpolating between the rising and falling edges that define a phase. The sampling logic may be preloaded during one or more remaining phases when the signal 833 is not sampled. For example, the GRS data receiver 800(0) may be configured to interpolate between the rising and falling edges of the signal generated as the AND of iCLKN and qCLKN, which define the first phase P0, to determine a particular sampling time for subsequent first phases.

[0093] Fig. 8B and Fig. 8C illustrate a flowchart of a method 860 for receiving a multi-phase GRS signal in accordance with one embodiment. Although method 860 is described in the context of Fig. 8A describes implementing an N-phase receiver, where N=4, those skilled in the art will understand that any system performing method 860 is within the scope and spirit of embodiments of the present invention. In particular, method 860 may be extended to receive multi-phase signals for three phases or for more than four phases.

[0094] Method 860 begins in step 810, wherein transmitted signals encoding N phases of a clock signal are received. As in Fig. For example, as shown in Figure 8A, signals iCLK and qCLK encode in-phase and quadrature clock signals, and four separate signals, each corresponding to a different phase P0, P1, P2, and P3, can be decoded using iCLK and qCLK.

[0095] In step 815, a first GRS data receiver, such as instance 800(0) of GRS data receiver 800 within multi-phase GRS receiver 850, receives a GRS output signal 833 and characterizes the received GRS output signal 833 during a first phase of the clock signal after pre-loading detection circuitry in the first GRS data receiver during at least one phase of the clock signal other than the first phase of the clock signal. In step 820, during the first phase, a characterized signal corresponding to the fourth phase is detected by detection circuitry within a fourth GRS data receiver to generate the fourth output, D3.

[0096] In step 825, a second GRS data receiver, such as instance 800(1) of GRS data receiver 800 within multi-phase GRS receiver 850, receives GRS output signal 833 and characterizes the received GRS output signal 833 during a second phase of the clock signal after pre-charging the detection circuitry in the second GRS data receiver during at least one phase of the clock signal other than the second phase of the clock signal. In step 830, during the second phase, the characterized signal corresponding to the first phase is detected by the detection circuitry within the first GRS data receiver to generate the first output, D0.

[0097] In step 835, a third GRS data receiver, such as instance 800(2) of GRS data receiver 800 within multi-phase GRS receiver 850, receives GRS output signal 833 and characterizes the received GRS output signal 833 during a third phase of the clock signal after pre-charging the detection circuitry in the third GRS data receiver during at least one phase of the clock signal other than the third phase of the clock signal. In step 840, during the third phase, the characterized signal corresponding to the second phase is detected by the detection circuitry within the second GRS data receiver to generate the second output, D1.

[0098] In step 845, the fourth GRS data receiver, such as instance 800(3) of GRS data receiver 800 within multi-phase GRS receiver 850, receives GRS output signal 833 and characterizes the received GRS output signal 833 during the fourth phase of the clock signal after pre-charging the detection circuitry in the fourth GRS data receiver during at least one phase of the clock signal other than the fourth phase of the clock signal. In step 850, during the fourth phase, the characterized signal corresponding to the third phase is detected by detection circuitry within the third GRS data receiver to generate the third output, D2.

[0099] Fig. 9A illustrates timing 900 for a multi-phase GRS transmitter having three GRS data drivers, in accordance with one embodiment. In the context of the following description, signals x0, x1, and x2 may each have a 50% duty factor and a 120° phase offset relative to each other and may be direct outputs of an oscillator. Signals x0, x1, and x2 may be used to generate the three phase signals P0, P1, and P2.

[0100] The P0 signal, which corresponds to the first phase of the clock signal, can be generated as the AND of x0 and inverted x2. The P1 signal, which corresponds to the second phase of the clock signal, can be generated as the AND of x2 and x1. The P2 signal, which corresponds to the third phase of the clock signal, can be generated as the AND of inverted x0 and inverted x1.

[0101] As with four phases, for each phase Pi, there is a GRS data driver and a GRS data receiver for each phase. Each GRS data driver can be configured to discharge a capacitor on the signal line during one phase and precharge the capacitor during at least one of the other two phases. Each GRS data receiver can be configured to integrate during one phase to generate a characterized signal, sense the characterized signal during another phase, and precharge a detection circuit during the remaining phase. In another embodiment, each GRS data receiver can be configured to sample the signal during one phase to generate a characterized signal, output the characterized signal during another phase, and precharge the detection circuit during the remaining phase.

[0102] Signals encoding the three-phase clock signal should be propagated to generate the appropriate phases at the multi-phase GRS data receiver and reduce the effects of fixed-pattern flicker. In one embodiment, the three signals x0, x1, and x2 are transmitted to the multi-phase GRS data receiver with the output signal. In another embodiment, the three phases P0, P1, and P2 are transmitted to the multi-phase GRS data receiver with the output signal.

[0103] In one embodiment, the P0 signal with the data can be transmitted by configuring a three-phase GRS transmitter with the data input set at D2=1, D1=0, and D0=0. In one embodiment, the P1 signal with the data can be transmitted by configuring a three-phase GRS transmitter with the data input set at D2=0, D1=1, and D0=0. In one embodiment, the P2 signal with the data can be transmitted by configuring a three-phase GRS transmitter with the data input set at D2=0, D1=0, and D0=1.

[0104] In one embodiment, only a signal encoding one phase of the three-phase clock is transmitted to the multi-phase GRS data receiver, and the remaining two phases are generated at the multi-phase GRS data receiver by phase locking or injection locking a three-phase ring oscillator to the forwarded phase. However, if only one phase is transmitted, the multi-phase GRS data receiver is not necessarily able to reject timing noise due to phase mismatches.

[0105] Fig. 9B illustrates a three-phase ring oscillator circuit 905 in accordance with one embodiment. The signals x0N, x1N, and x2N are the inverted versions of signals x0, x1, and x2, respectively. In one embodiment, the oscillator circuit 905 may be followed by a turn-on factor correction circuit configured to adjust each output so that x0, x1, and x2 each have a 50% turn-on factor. In one embodiment, the oscillator circuit 905 is followed by a phase correction circuit that adjusts the phase of x0, x1, and / or x2 so that times during which P0, P1, and P2 are logical ones have substantially identical durations.

[0106] Fig. 10 illustrates an exemplary system 1000 in which the various architectures and / or functionality of the various previous embodiments may be implemented. As shown, a system 1000 is provided that includes at least one central processor 1001 connected to a communications bus 1002. The communications bus 1002 may be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI Express, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communications protocol(s). The system 1000 also includes a main memory 1004. Control logic (software) and data are stored in the main memory 1004, which may take the form of random access memory (RAM).

[0107] The system 1000 also includes input devices 1012, a graphics processor 1006, and a display 1008, e.g., a conventional CRT (cathode ray tube), LCD (liquid crystal display), LED (light-emitting diode), plasma display, or the like. User input may be received from the input devices 1012, e.g., a keyboard, mouse, touchpad, microphone, and the like. In one embodiment, the graphics processor 1006 may include a plurality of shading modules, a raster module, etc. Each of the foregoing modules may even be located on a single semiconductor platform to form a graphics processing unit (GPU).

[0108] In this specification, a single semiconductor platform refers to a single unitary semiconductor-based integrated circuit or chip. It should be noted that the term single semiconductor platform can also refer to multi-chip modules with enhanced connectivity that simulate on-chip operations and provide significant improvements over using a conventional central processing unit (CPU) and bus implementation. Of course, the various modules can also be situated separately or in various combinations of semiconductor platforms according to the user's wishes.

[0109] The system 1000 may also include secondary storage 1010. The secondary storage 1010 includes, for example, a hard disk drive and / or a removable storage drive, which may represent a floppy disk drive, a magnetic tape drive, a compact disc drive, a digital versatile disk (DVD) drive, a recording drive, or a universal serial bus (USB) flash memory. The removable storage drive reads from and / or writes to a removable storage device in a well-known manner. Computer programs or computer control logic algorithms may be stored in the main memory 604 and / or the secondary storage 610. Such computer programs, when executed, enable the system 600 to perform various functions. The memory 604, storage 610, and / or any other memory are possible examples of computer-readable media.

[0110] In one embodiment, the architecture and / or functionality of the various previous figures may be implemented in the context of the central processor 1001, graphics processor 1006, and integrated circuit (not shown) enabled by at least a portion of the capabilities of both the central processor 1001 and the graphics processor 1006, a chipset (i.e., a group of integrated circuits configured to operate and be sold as a unit for performing respective functions, etc.), and / or any other integrated circuit for that purpose.

[0111] Still further, the architecture and / or functionality of the various previous figures may be implemented in the context of a general-purpose computer system, a circuit board system, a game console system dedicated for entertainment purposes, an application-specific system, and / or any other desired system. For example, system 1000 may take the form of a desktop computer, laptop computer, server, workstation, game console, embedded system, and / or any other type of logic. Still further, system 1000 may take the form of various other devices, including, but not limited to, a personal digital assistant (PDA) device, a mobile phone device, a television, etc.

[0112] Furthermore, while not shown, the system 1000 may be coupled to a network (e.g., a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, or the like) for communication processes.

[0113] In one embodiment, certain signals within bus 1002 are implemented as GRS signals, as described above in Fig. 1A-9B.

Claims

[1] GRS system (100), comprising a control circuit (602) configured to generate a first set of control signals (610) based on a first phase of a clock signal (CLK), to generate a second set of control signals (612) based on a second phase of the clock signal (CLK), and to generate a third set of control signals (614) based on a third phase of the clock signal (CLK); a first ground-referenced single-end signaling GRS driver circuit (400(4)) configured to: precharging a first capacitor to store a first charge based on the first set of control signals (610) during at least one phase of the clock signal (CLK) other than the first phase of the clock signal (CLK); and driving an output signal (616) relative to a ground network (107) by discharging the first charge during the first phase of the clock signal (CLK) by coupling either a first output node or a second output node to the output signal (616) to convey a first input (D0); a second GRS driver circuit (400(5)) configured to: precharging a second capacitor to charge a second charge based on the second set of control signals (612) during at least one phase of the clock signal (CLK) other than the second phase of the clock signal (CLK); and driving the output signal (616) relative to the ground network (107) by discharging the second charge during the second phase of the clock signal (CLK) to convey a second input (D1); and a third GRS driver circuit (400(6)) configured to: precharging a third capacitor to store a third charge based on the third set of control signals (614) during at least one phase of the clock signal (CLK) other than the third phase of the clock signal (CLK); and driving the output signal (616) relative to the ground network (107) by discharging the third charge during the third phase of the clock signal (CLK) to convey a third input (D2). [2] The GRS system (100) of claim 1, wherein the control circuit (602) is further configured to generate the first set of control signals (610) based on the first input (D0), generate the second set of control signals (612) based on the second input (D1), and generate the third set of control signals (614) based on the third input (D2). [3] The GRS system (100) of claim 1, wherein the first capacitor (C7) stores the first charge between the first output node (412) and a first reference node (410), and wherein a polarity of the first charge is based on a logic state of the first input (D0). [4] The GRS system (100) of claim 1, wherein the first charge is a constant voltage during the at least one phase of the clock signal (CLK) other than the first phase of the clock signal (CLK), and wherein the first capacitor is discharged with a polarity based on a logic state of the first input (D0). [5] The GRS system (100) of claim 1, wherein the first set of control signals (610) is configured to precharge the first capacitor with a negative charge when the first input (D0) is in a logic zero state during the at least one phase of the clock signal (CLK) other than the first phase of the clock signal (CLK). [6] The GRS system (100) of claim 5, wherein the first capacitor (C7) stores the first charge between the first output node (412) and a first reference node (410), and wherein the first set of control signals (610) is configured to couple the first reference node (410) to a supply node (VDD) through a first p-channel field-effect transistor (p40), p-FET, and to couple the first output node (412) to the ground network (107) through a first n-channel field-effect transistor (n43), n-FET, to precharge the first capacitor (C7) with a negative charge. [7] The GRS system (100) of claim 1, wherein the first set of control signals (610) is configured to precharge the first capacitor (C7) with a positive charge when the first input (D0) is in a logic one state during the at least one phase of the clock signal (CLK) other than the first phase of the clock signal (CLK). [8] The GRS system (100) of claim 7, wherein the first capacitor (C7) stores the first charge between the first output node (412) and a first reference node (410), and wherein the first set of control signals (610) is configured to couple the first reference node (410) to the ground network (107) through a first n-channel field-effect transistor (g41), n-FET, and to couple the first output node (412) to a supply node (VDD) through a first p-channel field-effect transistor (g42), p-FET, to precharge the first capacitor (C7) with the positive charge. [9] The GRS system (100) of claim 1, wherein the first capacitor (C7) stores the first charge between the first output node (412) and a first reference node (410), and wherein the first set of control signals (610) is configured to drive the output signal (416) by coupling the first reference node (410) to the ground network (107) and to couple the first output node (412) to the output signal (416) during the first phase of the clock signal (CLK). [10] The GRS system (100) of claim 9, wherein the first set of control signals (610) is configured to couple the first reference node (410) to the ground network (107) through a first n-channel field effect transistor (g41), n-FET, and to couple the first output node (412) to the output signal (416) through a second n-FET (g44) during the first phase of the clock signal (CLK) to drive the output signal (416). [11] The GRS system (100) of claim 1, wherein a set of signals (x0, x1, x2; P0, P1, P2; iCLK, qCLK) encoding the first phase of the clock signal, the second phase of the clock signal, and the third phase of the clock signal are transmitted with the output signal (616). [12] GRS system (100) according to claim 11, wherein the set of signals (x0, x1, x2; P0, P1, P2; iCLK, qCLK) comprises an in-phase clock signal (iCLK) and a quadrature clock signal (qCLK). [13] GRS system (100) according to claim 11, wherein the set of signals (x0, x1, x2; P0, P1,P2; iCLK, qCLK) comprises a first clock phase signal (P0) representing the first phase of the clock, a second clock phase signal (P1) representing the second phase of the clock signal, and a third clock phase signal (P2) representing the third phase of the clock. [14] The GRS system (100) of claim 1, further comprising a first GRS receiver circuit (800(0)) coupled to the output signal (833) and configured to characterize the output signal (833) during the first phase of the clock signal. [15] The GRS system (100) of claim 14, wherein the characterized output signal is generated by integrating the output signal (833) during the first phase of the clock signal. [16] The GRS system (100) of claim 14, wherein the first GRS receiver circuit (800(0)) is further configured to: detect the characterized output signal during the second phase of the clock signal; and Precharge detection circuit during at least one phase of the clock signal other than the first phase and the second phase of the clock signal. [17] The GRS system (100) of claim 14, wherein the characterized output signal is generated by sampling the output signal (833) during the first phase of the clock signal. [18] The GRS system (100) of claim 17, further comprising determining a time at which the output signal (833) is sampled by interpolating between a rising edge and a falling edge defining the first phase of the clock signal. [19] The GRS system (100) of claim 1, wherein the control circuit (602) is further configured to generate a fourth set of control signals (618) based on a fourth phase of the clock signal (CLK), and further comprising: a fourth GRS driver circuit (400(7)) configured to: precharging a fourth capacitor to store a fourth charge based on the fourth input signal (D3) during at least one phase of the clock signal (CLK) other than the fourth phase of the clock signal (CLK); and driving the output signal relative to the ground network (107) by discharging the fourth charge during the fourth phase of the clock signal (CLK). [20] A method of generating an output signal (616), comprising: Pre-charging a first capacitor to store a first charge during at least one phase of the clock signal (CLK) other than the first phase of the clock signal (CLK); and Driving the output signal (616) relative to a ground network (107) by discharging the first charge during a first phase of the clock signal (CLK) by coupling either a first output node or a second output node to the output signal (616), wherein the output signal (616) is a ground-referenced single-ended signal; Pre-charging a second capacitor to store a second charge during at least one phase of the clock signal (CLK) other than a second phase of the clock signal (CLK); and Driving the output signal (616) relative to the ground network (107) by discharging the second charge during the second phase of the clock signal (CLK); and Pre-charging a third capacitor to store a third charge during at least one phase of the clock signal (CLK) other than a third phase of the clock signal (CLK); and Driving the output signal (616) relative to the ground network (107) by discharging the third charge during the third phase of the clock signal (CLK). [21] The method of claim 20, further comprising generating a first set of control signals (610) based on the first phase of a clock signal (CLK), a second set of control signals (612) based on the second phase of the clock signal (CLK), and a third set of control signals (614) based on the third phase of the clock signal (CLK), wherein the first capacitor is precharged based on the first set of control signals (610), the second capacitor is precharged based on the second set of control signals (612), and the third capacitor is precharged based on the third set of control signals (614). [22] The method of claim 20, wherein driving the output signal (416; 616) during the first phase of the clock signal (CLK) comprises coupling the first output node (412) associated with the first capacitor (C7) to the output signal (416; 616), and coupling a first reference node (410) associated with the first capacitor (C7) to a ground network (107). [23] The method of claim 20, further comprising transmitting a set of signals (x0, x1, x2; P0, P1, P2; iCLK, qCLK) encoding the first phase of the clock signal (CLK), the second phase of the clock signal (CLK), and the third phase of the clock signal (CLK) with the output signal (416; 616).

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