Three-dimensional memory with split word routing

Abstract

Three-dimensional 3D circuit (60) comprising: a first layer (61-1) comprising at least one first memory cell (65-0); a second layer (62-1) above the first layer (61-1), wherein the second layer (62-1) comprises at least one second memory cell (64-0), the second layer (62-1) being arranged in a vertical stack with the first layer (61-1) above the first layer (61-1); a third layer (61-X) below the first layer (61-1), wherein the third layer (61-X) comprises at least one third memory cell (65-4, 65-5, 65-6, 65-7) arranged below the first layer (61-1); a fourth layer (62-Y) above the second layer (62-1), wherein the fourth layer (62-Y) comprises at least one fourth memory cell (64-4, 64-5, 64-6, 64-7) which is arranged above the second layer (62-1);and a word line (63-1) shared by the first memory cell (65-0), the second memory cell (64-0), the third memory cell (65-4, 65-5, 65-6, 65-7) and the fourth memory cell (64-4, 64-5, 64-6, 64-7), wherein the word line (63-1) is a horizontal word line, the horizontal word line extending in a horizontal direction perpendicular to the direction of the vertical stack; and wherein the horizontal word line is arranged vertically between the first memory cell (65-0) and the second memory cell (64-0).

Description

FIELD OF DISCLOSUREThe disclosed circuits and methods relate to semiconductor memories. More particularly, the disclosed circuits and methods relate to three-dimensional semiconductor memories sharing word lines.BACKGROUNDStatic random access memory ("SRAM") includes multiple cells arranged in rows and columns to form an array. SRAM cells include multiple transistors connected to bit lines and word lines used to read and write a data bit in the memory cell. In two-dimensional memories, memory cells and word lines are in the same location. The length of the word lines increases as the word width increases. As a result of a longer wordline length, power consumption increases and overall performance degrades. EP 0043786 A2 discloses a stereoscopic semiconductor memory formed by stacking a plurality of semiconductor layers. US 2012 / 0263003 A1 discloses an apparatus comprising a plurality of memory circuits having a plurality of memory cells and a control circuit configured to control data refresh operations on one or more of the memory cells. US 2008 / 0291767 A1 discloses a three-dimensional integration multi-port register file in which multiple active circuit layers are vertically stacked and vertically aligned interconnects are used to connect one device of one of the stacked layers to another device in another stacked layer. US 2012 / 0091427 A1 discloses a multilayer memory structure having a first memory cell and a second memory cell formed over the first memory cell, the first and second memory cells being mirror-symmetrical to one another, and having a common word line and different bit lines.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a perspective view of an example of a three-dimensional semiconductor integrated circuit having bit cells on different vertical layers sharing the same word line, in accordance with some embodiments. FIG. 1A is a circuit diagram of bit cells of different vertical layers sharing the same word line, in accordance with some embodiments. FIG. 2 is a perspective view of a three-dimensional semiconductor integrated circuit where adjacent bit cells are in the same layer and bit cells on different layers share the same word line, in accordance with some embodiments. FIG. 3 is a perspective view of a three-dimensional semiconductor integrated circuit where bit cells on different vertical layers share the same word line, similar to FIG. 1, and in accordance with some embodiments. FIG. 4 is a perspective view of a three-dimensional semiconductor integrated circuit where bit cells on two different vertical layers are below a shared word line, in accordance with some embodiments. FIG. 5 is a perspective view of a three-dimensional semiconductor integrated circuit where bit cells on a predetermined number of different vertical layers are below a shared word line, in accordance with some embodiments. FIG. 6 is a perspective view of a three-dimensional semiconductor integrated circuit according to the invention, wherein bit cells are located on a predetermined number of different vertical layers above and below a divided word line, in accordance with some embodiments. FIG. 7 is a flow diagram of an example of a method of forming a three-dimensional semiconductor memory, in accordance with some embodiments.DETAILED DESCRIPTIONThis description of the exemplary embodiments is intended to be read in conjunction with the accompanying drawings, which are to be considered part of the entire specification.The disclosed circuits of claims 1 to 14 advantageously reduce problems that conventional two-dimensional semiconductor memories can address by reducing resistance and capacitance due to reduced word line lengths. In addition, the disclosed circuits of claims 1 to 14 improve the performance of a semiconductor memory (e.g., power, speed, and area).FIG. 1 shows an example of a three-dimensional ("3D") semiconductor integrated circuit ("IC") 10. the 3D IC 10 includes multiple layers, such as layers 11 and 12, vertically stacked on each other in the z-direction. In some embodiments, layers 11 and 12 are individual dies that are interconnected by at least one through substrate via ("TSV") or inter-layer via ("ILV") (not shown). In some embodiments, 3D IC 10 is such a 3D IC that each layer 12 forms a corresponding "plane", where each plane includes a corresponding active device layer and a corresponding interconnect structure that may include multiple conductive layers (e.g., M 1, M 2, etc.). Interlayer dielectric ("ILD") layers (not shown) may be disposed between directly adjacent levels, as one of ordinary skill in the art can understand.The 3D IC 10 includes an array of bit cells arranged over the two layers 11 and 12. The bit cells 15-0 to 15-3 and 17-0 to 17-3 are arranged on the first layer 11, and the bit cells 15-4 to 15-7 and 17-4 to 17-7 are arranged on the second layer 12. The bit cells 15-0 to 15-3 and 15-4 to 15-7 share the same word line 13 arranged between vertically adjacent bit cells in respective layers 11 and 12. In some embodiments, the word line 13 may be embedded in a portion of the layer 11 and in other embodiments, the word line may be embedded in a portion of the layer 12. In some embodiments, word line 13 may be disposed between layers 11 and 12 as a separate layer. Similarly, bit cells 17-0 to 17-3 and 17-4 to 17-7 share the same word line 14 disposed between vertically adjacent bit cells in the respective layers 11 and 12. The 3D IC further includes multiple bit lines (BL[0] through BL[m-1], where m is the number of bit cells in a word). The 3D IC 10 may also include multiple complementary bit lines (BLB). Bit lines 16- 0 to 16- 3 may drive bit cells 15- 0 to 15- 3 and / or bit cells 17- 0 to 17- 3, respectively. The bit lines 16- 4 to 16- 7 may drive the bit cells 15- 4 to 15- 7 and / or the bit cells 17- 4 to 17- 7, respectively.FIG. 1A shows further details of an example of a pair of vertically stacked bit cells 15- 7 and 15- 3 as shown in FIG. 1, in accordance with some embodiments. Bit cell 15-3 is a mirror image of bit cell 15-7, therefore for simplicity bit cell 15-3 is described below. Bit cell 15-3 includes a pair of pass transistors 128-1, 128-2, each having a respective gate connected to the same word line 13 at node 130, and having its respective drain connected to latch 132. The source of transistor 128- 1 is connected to a bit line, BL[n], at node 134, and the source of transistor 128- 2 is connected to the complementary bit line, BLB[n], at node 136. Latch 132 includes a pair of cross-coupled inverters 138-1 and 138-2 arranged such that the output of inverter 138-1 is connected to the input of inverter 138-2 at node 124, and the output of inverter 138-2 is connected to the input of inverter 138-1 at node 142. Node 142 is also connected to the drain of transistor 128- 1.As shown in FIG. 1A, in some embodiments, inverters 138- 1, 138- 2 each include a pair of transistors. For example, inverter 138- 1 includes transistors 144- 1 and 146- 1, and inverter 138- 2 includes transistors 144- 2 and 146- 2. In some embodiments, transistors 144- 1, 144- 2 are PMOS transistors and transistors 146- 1, 146- 2 are NMOS transistors. However, transistors 144- 1, 144- 2, 146- 1, 146- 2 may be implemented as other types of transistors.The source of transistor 144- 1 is connected to a node that, in some embodiments, is connected to a power supply node at VDD. The drain of transistor 144-1 is connected to node 124, and the gate of transistor 144-1 is connected to node 142, which serves as the input of inverter 138-1. Transistor 146-1 has its drain connected to node 124, its source connected to ground or VSS, and its gate connected to node 142.The source of transistor 144-2 of inverter 138-2 is connected to a node connected to VDD, its drain is connected to node 142, and its gate is connected to node 124. Node 142 is connected to the drain of transistor 128- 1 and is configured as an output of inverter 138- 2 and an input of inverter 138- 1. The source of transistor 146-2 of inverter 138-2 is connected to ground or VSS, its drain is connected to node 142, and its gate is connected to node 124. Although the bit cell 15- 3 shown in FIG. 1A is shown as a six-transistor ("6T") bit cell, one of ordinary skill in the art will understand that the bit cell 15- 3 (as well as the bit cell 15- 7) may have other implementations with fewer or more transistors. Note that the illustrated embodiments generally relate to and are not limited to SRAM cells. Some embodiments include other types of memory, such as DRAM cells, that include multiple transistors connected to bit lines and word lines used to read and write a bit of data in the memory cell.FIG. 2 shows an example of a 3D IC 20 including multiple layers, such as layers 21 and 22, vertically stacked on each other in the z direction. In some embodiments, layers 21 and 22 are individual dies electrically connected to each other by at least one through substrate via ("TSV") or intermediate layer via ("ILV") or intermediate device via ("IDV") (not shown). In some embodiments, 3D IC 20 is such a 3D IC that each of layers 21 and 22 is a corresponding "plane", where each plane includes a corresponding active device layer and a corresponding interconnect structure that may include multiple conductive layers (e.g., M 1, M 2, etc.). Interlayer dielectric ("ILD") layers (not shown) may be disposed between directly adjacent levels, as will be understood by one of ordinary skill in the art.The 3D IC 20 includes an array of bit cells arranged over two layers 21 and 22. The bit cells 25-0 to 25-1 and 27-0 to 27-1 are arranged on the first layer 21, and the bit cells 25-2 to 25-3 and 27-2 to 27-3 are arranged on the second layer 22, as shown. The bit cells 25-0 to 25-3 share the same vertical word line 23. similarly, the bit cells 27-0 to 27-3 share the same vertical word line 24. the 3D IC 20 further includes multiple bit lines. The bit line 26-0 drives the bit cells 25-0 and 27-o, the bit line 26-1 drives the bit cells 15-1 and 27-1, the bit line 26-2 drives the bit cells 25-2 and 27-2, and the bit line 26-3 drives the bit cells 25-3 and / or 27-3, respectively.FIG. 3 is a perspective view of a three-dimensional semiconductor integrated circuit 30, wherein bit cells are formed on different vertical layers 31 and 32 sharing the same word lines 36 and 38, and wherein bit cells are formed on still further vertical layers 33 and 34 sharing the same word lines 37 and 39, in accordance with some embodiments. In this embodiment, adjacent bit cells that lie on separate stacked layers and are disposed above and below a word line share the same word line. For example, bit cells 35- 0 through 35- 3 of layer 31 share the same wordline 36 with corresponding bit cells 35- 4 through 35- 7 of layer 32. Note that in some embodiments, wordline 36 may be embedded in layer 31 or layer 32 as long as wordline 36 is connected to corresponding sets of bit cells formed in other layers. The bit cells 35- 8 to 35- 11 of layer 33 share the same word line 37 with the corresponding bit cells 35- 12 to 35- 15 of layer 34. the word lines 37 and 39 similarly share bit cells on an opposite side of the 3D IC 30. The 3D IC 30 further includes multiple bit lines. Bit lines 36-0 through 36-15 are connected to cells 35-0 through 35-15 and a corresponding set of bit cells connected to word line 38 or word line 39. This embodiment illustrates memory or bit cell sharing over layers above and below (or above or below in the z-direction) a shared horizontal (x- and y-directions) wordline.FIG. 4 illustrates a 3D IC 40 having bit cells formed on two different vertical layers disposed below a shared word line (43 or 44), in accordance with some embodiments. The 3D IC 40 includes multiple layers, such as the layers 41 and 42, vertically stacked on each other in the z direction. In some embodiments, as described above, layers 41 and 42 are individual dies electrically connected to each other by at least one of through substrate via ("TSV"), inter-layer via ("ILV"), or inter-device via ("IDV") (not shown). In some embodiments, each of the layers 41 and 42 of the 3D IC 40 is a corresponding "plane", where each plane includes a corresponding active device layer and a corresponding interconnect structure that may include multiple conductive layers (e.g., M 1, M 2, etc.). Interlayer dielectric ("ILD") layers (not shown) may be disposed between directly adjacent levels, as one of ordinary skill in the art can understand.The 3D IC 40 includes an array of bit cells arranged over the two layers 41 and 42. The bit cells 45- 0 to 45- 3 and 47- 0 to 47- 3 are disposed on the first layer 41, and the bit cells 45- 4 to 45- 7 and 47- 4 to 47- 7 are disposed on the second layer 42. Bit cells 45-0 through 45-3 and 45-4 through 45-7 respectively share the same word line 43 overlying bit cells 45-0 through 45-7. The bit cells 47-0 to 47-7 share the same word line 44 that is disposed over the bit cells 47-0 to 47-7. In some embodiments, word lines 43 and 44 may be embedded in layer 41 (as part of a metal layer M 1, M 2, M 3, etc.), or alternatively may be disposed over layer 41. The bit lines 46- 0 to 46- 3 are connected to the bit cells 45- 0 to 45- 3 and / or the bit cells 47- 0 to 47- 3. The bit lines 46- 4 to 46- 7 are connected to the bit cells 45- 4 to 45- 7 and / or the bit cells 47- 4 to 47- 7.FIG. 5 illustrates a 3D IC 50 having bit cells on a number X of different vertical layers, the bit cells being arranged under a shared word line (58 or 59), in accordance with some embodiments. The 3D IC 50 includes multiple layers, such as the layers 51- 1, 51- 2 to 51-X, vertically stacked on each other in the z direction. In some embodiments, as described above, layers 51- 1, 51- 2 to 51-X are individual dies electrically connected to each other by at least one TSV, ILV, or IDV (not shown). In some embodiments, 3D IC 50 is such a 3D IC that each of layers 51- 1, 51- 2 through 51-X form a corresponding "plane", where each plane includes a corresponding active device layer and a corresponding interconnect structure that may include multiple conductive layers (e.g., M 1, M 2, etc.). ILD layers (not shown) may be disposed between directly adjacent planes, as one of ordinary skill in the art can understand.The 3D IC 50 includes an array of bit cells arranged across the number X of layers under the word lines 58 and 59. Bit cells 55-0 to 55-3 and 57-0 to 57-3 are arranged on the first layer 51-1, bit cells 55-4 to 55-7 and 57-4 to 57-7 are arranged on the second layer 51-2, and bit cells 55-8 to 55-11 and 57-8 (not shown) to 57-11 are arranged on the X-th layer 51-X. Bit cells 55-0 through 55-3, 55-4 through 55-7, and 55-8 through 55-11 respectively share the same word line 58 overlying bit cells 55-0 through 55-11. The bit cells 57-0 to 57-3, 57-4 to 57-7, and 57-8 to 57-11 respectively share the same word line 59 disposed over the bit cells 57-0 to 57-11. In some embodiments, word lines 58 and 59 may be embedded in layer 51- 1, or alternatively may be disposed over layer 51- 1. Bit lines 56- 0 to 56- 3 may respectively drive or be driven by bit cells 55- 0 to 55- 3 and / or bit cells 57- 0 to 57- 3. Bit lines 56- 4 to 56- 7 may drive bit cells 55- 4 to 55- 7 and / or bit cells 57- 4 to 57- 7, respectively. The bit lines 56- 8 to 56- 11 may respectively drive or be driven by the bit cells 55- 8 to 55- 11 and / or the bit cells 57- 8 to 57- 11.FIG. 6 illustrates a 3D IC 60 of the present invention having bit cells on a number X of different vertical layers below a shared wordline and bit cells on a number Y of different vertical layers above a shared wordline, in accordance with some embodiments. The 3D IC 60 includes multiple layers, such as layers 61- 1 to 61-X vertically stacked on each other in the z direction, under the divided word line, and multiple layers, such as layers 62- 1 to 62-Y vertically stacked over the divided word line. In some embodiments, as described above, layers 61- 1 to 61-X and 62- 1 to 62-Y are single dies electrically connected to each other by at least one of TSV, TDV, and ILV (not shown). In some embodiments, each of the layers of the 3D IC 60 is a corresponding "level," where each level includes a corresponding active device layer and a corresponding interconnect structure that may include multiple conductive layers (e.g., M 1, M 2, etc.). ILD layers (not shown) may be disposed between directly adjacent planes, as one of ordinary skill in the art can understand.The 3D IC 60 includes an array of bit cells arranged over the number X of layers among the word lines 63- 1 and 63- 2 and over the number Y of layers over the word lines 63- 1 and 63- 2. The bit cells 65- 0 to 65- 3 connected to the word line 63- 1 and another corresponding set of bit cells connected to the word line 63- 2 are arranged on the layer 61- 1, and the bit cells 65- 4 to 65- 7 connected to the word line 63- 1 and another corresponding set of bit cells connected to the word line 63- 2 are arranged on the layer 61- X. Bit cells 64-0 through 64-3 connected to word line 63-1 and another corresponding set of bit cells connected to word line 63-2 are disposed on layer 62-1, and bit cells 64-4 through 64-7 connected to word line 63-1 and another corresponding set of bit cells connected to word line 63-2 are disposed on layer 62-Y.Bit cells 65-0 through 65-3 and bit cells 65-4 through 65-7 respectively share the same word line 63-1 overlying bit cells 65-0 through 65-7. Further, the bit cells 64-0 to 64-3 and the bit cells 64-4 to 64-7 respectively share the same word line 63-1 that is among the bit cells 64-0 to 64-7. Another set of bit cells respectively share the word line 63-2 in a similar arrangement. The 3D IC 60 further includes a number of bit lines. Bit lines 66- 0 through 66- 3 may drive bit cells 65- 0 through 65- 3, respectively, to store a logical zero or a logical one in a storage node 124, 142 (FIG. 1A ), or may be connected to storage nodes 124, 142 to read a logical zero or a logical one from one of the storage nodes. The bit lines 66- 4 to 66- 7 (FIG. 6 ) may drive the bit cells 65- 4 to 65- 7, respectively, to store a logical zero or a logical one in the storage nodes 124, 142 (FIG. 1A ), or may be connected to the storage nodes 124, 142 to read a logical zero or a logical one from the storage nodes. Bit lines 67- 0 to 67- 3 (FIG. 6 ) may drive bit cells 64- 0 to 64- 3, respectively, to store a logic zero or a logic one in storage nodes 124, 142 (FIG. 1A ), or may be connected to storage nodes 124, 142 to read a logic zero or a logic one from the storage nodes, and bit lines 67- 4 to 67- 7 (FIG. 6 ) may drive bit cells 64- 4 to 64- 7, respectively, to store a logic zero or a logic one in storage nodes 124, 142 (FIG. 1A ), or may be connected to storage nodes 124, 142 to read a logic zero or a logic one from the storage nodes.FIG. 7 is a flow diagram of an example of a method 70 of manufacturing a three-dimensional semiconductor memory, in accordance with some embodiments. At block 72, circuits are formed in and / or on a first layer. For example, the active devices of the bit or memory cells (e.g., transistors 128, 144, 146) of a bit cell array are formed in a semiconductor substrate (not shown) using semiconductor processing technology. In some embodiments, the bit cells are formed using complementary metal oxide semiconductor ("CMOS") semiconductor processing technology.At block 74, circuits are formed in and / or on the second layer. For example, the active devices including a second bit or memory cell or set of memory or bit cells (e.g., transistors 128, 128, 144, 146) are formed in another semiconductor substrate (not shown) using semiconductor processing technology. In some embodiments, the bit cells or memory cells are formed using CMOS semiconductor processing technology.At block 75, the first and second layers are bonded together. For example, if the first and second layers 11 and 12 of FIG. 1 are separate semiconductor chips, the layers 11 and 12 are vertically stacked on, aligned, and bonded to each other. In some embodiments, such as embodiments in which layers 11 and 12 are planes, the layers are stacked on top of each other to produce a 3D-stacked CMOS IC. One skilled in the art will recognize that one or more layers may be disposed between layers 11 and 12, in some embodiments.At block 76, the portion of the circuits formed in either the first layer or the second layer includes a word line of the word used to share the first memory cell and the second memory cell, where the first memory cell and the second memory cell are formed on separate layers. In some embodiments, the word line and other conductive traces in metal layers (e.g., M 1, M 2, etc.) are embedded in either layer 11 or layer 12 (FIG. 1 ) or formed between layer 11 and layer 12 to connect corresponding bit cells via a word line 13 or a word line 14 (FIG. 1 ). In some embodiments, the conductive traces are TSVs or ILVs.The disclosed circuits and methods described herein advantageously reduce problems that can relate to conventional two-dimensional semiconductor memories by reducing the resistance and capacitance as a result of reduced word line lengths. The implementation of a stacked bit cell array sharing word lines further improves the efficiency of area consumption. Additionally, the disclosed circuits and methods improve the performance of a semiconductor memory with respect to performance and speed.In some embodiments, a 3D IC includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a word line shared by the first memory cell and the second memory cell. The second layer is arranged in a vertical stack with the first layer.In some embodiments, the first memory cell and the second memory cell are horizontally adjacent memory cells connected to different bit lines.In some embodiments, the first memory cell and the second memory cell are vertically adjacent memory cells connected to different bit lines. In some embodiments, the different bit lines include a first bit line in the first layer and a second bit line in the second layer.In some embodiments of the invention, the first layer comprises a plurality of first memory cells, the second layer comprises a plurality of second memory cells, and the word line is shared by the plurality of first memory cells and the plurality of second memory cells. In some embodiments, the word line extends horizontally across either the first layer or the second layer and is shared with the plurality of first memory cells disposed vertically above the word line and the plurality of second memory cells disposed vertically below the word line.In some embodiments, the word line extends horizontally across either the first layer or the second layer and is shared by the plurality of first memory cells and the plurality of second memory cells, both of which are disposed vertically below the word line.In some embodiments, the 3D circuit includes a plurality of first memory cells disposed in the first layer, a plurality of second memory cells disposed in the second layer, and a plurality of corresponding memory cells disposed in respective adjacent layers below the first and second layers, wherein the word line extends horizontally through and across the plurality of first memory cells and is shared by the plurality of first memory cells, the plurality of second memory cells, and the plurality of corresponding memory cells, all of which are disposed vertically below the word line.In some embodiments of the invention, the 3D circuit further comprises a plurality of first memory cells disposed over the first layer in respective layers over the first layer and a plurality of second memory cells disposed under the second layer in respective layers under the second layer, wherein the word line is a horizontal word line disposed between the first layer and the second layer, and the horizontal word line is shared by the plurality of first memory cells and the plurality of second memory cells.In some embodiments, the first memory cell and the second memory cell are adjacent static memory cells.In some embodiments, the word line extends vertically from the first layer to the second layer and is shared by memory cells on separate layers, the memory cells including the first memory cell arranged horizontally on the left side of the word line and memory cells arranged horizontally on the right side of the word line.In some embodiments, a semiconductor memory includes a bit cell array including a first memory cell of the bit cell array arranged in a first layer and a second memory cell of the bit cell array arranged in a second layer. A word line is shared between the first memory cell and the second memory cell of the bit cell array. The first and second layers are arranged in a vertical stack.In some embodiments, the first memory cell and the second memory cell are vertically adjacent memory cells connected to different bit lines. In some embodiments, the different bit lines include a first bit line in the first layer and a second bit line in the second layer.In some embodiments, a method includes the steps of forming circuits on a first layer, the circuits on the first layer including a first memory cell, forming circuits on a second layer, the circuits of the second layer including a second memory cell, and forming a word line such that the word line is shared between the first memory cell and the second memory cell.In some embodiments, the first memory cell and the second memory cell are formed as horizontally adjacent memory cells connected to different bit lines. In some embodiments, the first memory cell and the second memory cell are formed as vertically adjacent memory cells connected to different bit lines.In some embodiments, the method further comprises coupling the first layer and the second layer.In some embodiments, the method includes connecting the first memory cell and the second memory cell via the word line using through-silicon vias.In some embodiments, the first layer includes a plurality of first memory cells for the word, the second layer includes a plurality of second memory cells for the word, and the word line for the word is shared by the plurality of first memory cells and the plurality of second memory cells.

Claims

A three-dimensional 3D circuit (60) comprising: a first layer (61-1) comprising at least one first memory cell (65-0); a second layer (62-1) over the first layer (61-1), the second layer (62-1) comprising at least one second memory cell (64-0), the second layer (62-1) being arranged in a vertical stack with the first layer (61-1) over the first layer (61-1); a third layer (61-X) under the first layer (61-1), the third layer (61-X) comprising at least one third memory cell (65-4, 65-5, 65-6, 65-7) arranged under the first layer (61-1); a fourth layer (62-Y) over the second layer (62-1), the fourth layer (62-Y) comprising at least a fourth memory cell (64-4, 64-5, 64-6, 64-7) disposed over the second layer (62-1); and a word line (63-1) shared by the first memory cell (65-0), the second memory cell (64-0), the third memory cell (65-4, 65-5, 65-6, 65-7) and the fourth memory cell (64-4, 64-5, 64-6, 64-7), wherein the word line (63-1) is a horizontal word line, wherein the horizontal word line extends in a horizontal direction that is perpendicular to the direction of the vertical stack; and wherein the horizontal word line is vertically disposed between the first memory cell (65-0) and the second memory cell (64-0).The 3D circuit of claim 1, wherein the first memory cell (65-0) and the second memory cell (64-0) are connected to different bit lines (66-0, 67-0), respectively.The 3D circuit of claim 2, wherein the different bit lines comprise a first bit line (66-0) in the first layer (61-1) and a second bit line (66-0, 67-0) in the second layer (62-1).The 3D circuit (60) of any preceding claim, wherein the first memory cell (65-0) and the second memory cell (64-0) are vertically adjacent memory cells.The 3D circuit (60) of claim 1, wherein the first layer (61-1) comprises a plurality of first memory cells (65-0, 65-1, 65-2, 65-2), the second layer (62-1) comprises a plurality of second memory cells (64-0, 64-1, 64-2, 64-2), and the word line (63-1) is shared by the plurality of first memory cells (65-0, 65-1, 65-2, 65-2) and the plurality of second memory cells (64-0, 64-1, 64-2, 64-2).The 3D circuit (60) of claim 5, wherein the word line (63-1) extends horizontally across the first layer (61-1) and is shared with the plurality of first memory cells (65-0) disposed vertically below the word line (63-1) and the plurality of second memory cells (64-4, 64-5, 64-6, 64-7) disposed vertically above the word line (13).The 3D circuit (60) of claim 1, further comprising a plurality of first memory cells (65-0, 65-1, 65-2, 65-2) disposed in the first layer (61-1), a plurality of second memory cells (64-4, 64-5, 64-6, 64-7) disposed in the second layer (62-1), and a plurality of third memory cells (65-4, 65-5, 65-6, 65-7) disposed in the third layer (61-X) below the first (61-1) and second layers (62-1), wherein the word line (63-1) extends horizontally across and overlies the plurality of first memory cells (65-0, 65-1, 65-2, 65-2).The 3D circuit (60) of claim 1, further comprising a first plurality of third memory cells (65-4, 65-5, 65-6, 65-7) disposed below the first layer (61-1) in the third layer (61-X) and a second plurality of fourth memory cells (64-4, 64-5, 64-6, 64-7) disposed above the second layer (62-1) in the fourth layer (62-Y), wherein the horizontal word line (63-1, 63-2) is further shared by the first plurality of third memory cells (65-4, 65-5, 65-6, 65-7) and the second plurality of fourth memory cells (64-4, 64-5, 64-6, 64-7).The 3D circuit (60) of claim 1, wherein the first memory cell (65-0) and the second memory cell (64-0) are adjacent static memory cells.A semiconductor memory comprising: a bit cell array comprising: a first bit cell array memory cell (65-0) disposed in a first layer (61-1); a second bit cell array memory cell (64-0) disposed in a second layer (62-1), wherein the second layer (62-1) is disposed with the first layer (61-1) in a vertical stack over the first layer (61-1); a third bit cell array memory cell (65-4, 65-5, 65-6, 65-7) disposed in a third layer (61-X) under the first layer (61-1); a fourth memory cell (64-4, 64-5, 64-6, 64-7) of the bit cell array arranged in a fourth layer (62-Y) above the second layer (62-1); and a word line (63-1) shared by the first memory cell (65-0), the second memory cell (64-0), the third memory cell (65-4, 65-5, 65-6, 65-7) and the fourth memory cell (64-4, 64-5, 64-6, 64-7); wherein the word line (63-1) is a horizontal word line, the horizontal word line extending in a horizontal direction that is perpendicular to the direction of the vertical stack; and wherein the horizontal word line is vertically arranged between the first memory cell (65-0) and the second memory cell (64-0).The semiconductor memory of claim 10, wherein the first memory cell (65-0) and the second memory cell (64-0) are vertically adjacent memory cells connected to different bit lines (66-0, 67-0).The semiconductor memory of claim 11, wherein the different bit lines comprise a first bit line (66-0) in the first layer (61-1) and a second bit line (67-0) in the second layer (62-1).A method comprising: forming circuits on a third layer (61-X), the circuits on the third layer (61-X) comprising a third memory cell (65-4, 65-5, 65-6, 65-7); forming (72) circuits on a first layer (61-1) over the third layer (61-X), the circuits on the first layer (61-1) comprising a first memory cell (65-0); forming (74) circuits on a second layer (62-1) over the first layer (61-1), the circuits on the second layer (62-1) comprising a second memory cell (64-0), the first layer (61-1) and the second layer (62-1) being arranged in a vertical stack; forming circuits on a fourth layer (62-Y) over the second layer (62-1), the circuits on the fourth layer (62-Y) comprising a fourth memory cell (64-4, 64-5, 64-6, 64-7); and forming (76) a word line (63-1) shared by the first memory cell (65-0), the second memory cell (64-0), the third memory cell (65-4, 65-5, 65-6, 65-7) and the fourth memory cell (64-4, 64-5, 64-6, 64-7); wherein the word line (63-1) is a horizontal word line, the horizontal word line extending in a horizontal direction that is perpendicular to the direction of the vertical stack; and wherein the horizontal word line is vertically disposed between the first memory cell (65-0) and the second memory cell (64-0).The method of claim 13, wherein the first memory cell (65-0) and the second memory cell (64-0) are connected to different bit lines (66-0, 67-0).The method of claim 13 or claim 14, wherein the first memory cell (65-0) and the second memory cell (64-0) are formed as vertically adjacent memory cells.The method of any of claims 13 to 15, wherein the method further comprises electrically connecting (75) the first layer (61-1) and the second layer (62-1).The method of any of claims 13 to 16, wherein the method comprises connecting the first memory cell (65-0) and the second memory cell (64-0) via the word line (63-1) via through-silicon vias.The method of any of claims 13 to 17, wherein the first layer comprises a plurality of first memory cells (65-0) for the word, the second layer comprises a plurality of second memory cells (64-0) for the word, and the word line (63-1) for the word is shared by the plurality of first memory cells and the plurality of second memory cells.

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