Method for producing a self-adjusting contact

Abstract

Method for establishing a source / drain contact, comprising the following steps: Fabrication of a pair of gate structures (104) in a first dielectric material (108) on a surface of a substrate (102); Forming a deck material (210) on the pair of gate structures (104) and the first dielectric material (108); Forming a mask material (224, 110) on each gate structure by implanting areas of the cover material (210) with dopants and Removing the first dielectric material (108) in the areas not covered by the mask material (110); the formation of the mask material (110) comprising the following steps: Forming an etch stop material (106) on a pair of gate structures (104); Formation of a first dielectric material (108) on the etch stop material at a position between the pair of gate structures (104); Forming a planar surface (202) comprising the etch stop material (106) on each gate structure and the first dielectric material (108); Forming a non-planar surface by performing a first selective etching process (206) on the planar surface (202) with a first selective etchant (206) that removes the etch stop material (106) on each gate structure (104); and Forming the cover material (210) on the non-planar surface, which has a recessed area (212) over each gate structure (104) resulting from the topology of the non-planar surface.

Description

Background of the invention

[0001] Device downsizing at advanced semiconductor nodes, such as those at 10 nm and higher, has reduced the CPP (contacted poly pitch; the minimum center-to-center spacing between gates of adjacent transistors) to less than about 100 nm. Contacts to the source or drain of these transistors must fit into the gap between adjacent gates without having to shorten a gate to the source or drain. To achieve this, techniques such as double- or triple-patterning of source / drain contacts have been used. However, these multiple-patterning techniques require additional masks and manufacturing overhead.The use of additional masks can also degrade the over-coverage control (OVL) between these contacts, the transistor source or drain to which the contact is aligned, and neighboring elements, such as the transistor gate, from which the contact must remain electrically isolated to ensure performance. Other techniques, such as self-aligned contact (SAC) fabrication, can mitigate the OVL degradation associated with multi-patterning techniques, but require additional layers in the transistor-device stack for proper contact fabrication.

[0002] US 2013 / 0288468 A1 relates to a method comprising performing at least one angled ion implantation process to implant at least one etch-inhibiting species into less than an entirety of the etch stop layer. Short description of the drawings The Fig. 1A-1D show cross-sectional views of some embodiments of a semiconductor device having a source / drain contact disposed between a pair of gate structures. The Fig. 2A - 2J show cross-sectional views of some embodiments of the fabrication of source / drain contacts. The Fig. 3A-3D show cross-sectional views of some embodiments for creating a surface topology of a substrate by selective etching. The Fig. 4A-4F show cross-sectional views of some embodiments for using the surface topology of a substrate to fabricate a pattern of a mask material. Fig. 5 shows some embodiments of a method for using the surface topology of a substrate to fabricate a pattern of a mask material. Fig. 6 shows some embodiments of a method for creating the surface topology of a substrate by selective etching. Detailed description

[0003] The invention is evident from the independent claims. The dependent claims relate to corresponding developments. The description is made with reference to the drawings, in which like reference numerals are generally used to designate like elements throughout and in which the various structures are not necessarily drawn to scale. In the following description, for the purpose of explanation, numerous specific details are described in order to facilitate understanding. However, it will be apparent to one skilled in the art that one or more aspects described herein may be utilized with a lesser amount of such specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate understanding.

[0004] Some SAC fabrication methods use a hard mask (HM) material to define a structure with an opening that is etched to create a recess and filled with a conductive material to create the SAC (e.g., a source / drain contact, a gate contact, a metal contact, etc.). For source / drain SAC fabrication on a transistor, an electrically inactive material is deposited on a top surface of the transistor (e.g., on the gate, source, and drain). The electrically inactive material serves both to separate the gate from the source / drain SAC and as an etch stop layer for the etching of the source / drain recess. A dielectric material is then deposited over the transistor and the electrically inactive material to electrically isolate the transistor from its surroundings.The dielectric material is then etched over the source and drain of the transistor to create a recess for the source / drain SAC.

[0005] Etching the source / drain SAC is a selective etch that uses an etchant with a high degree of selectivity between the electrically inactive material and the dielectric material (i.e., it etches the dielectric material at a significantly higher rate than the electrically inactive material). This allows the dielectric material to be completely etched away while leaving the electrically inactive material essentially intact. This forms the recess for the source / drain SAC while keeping the gate electrically separate from the recess (i.e., it does not touch the recess). Although the electrically inactive material is etched at a significantly slower rate than the dielectric material, it is still etched. In addition, HM misalignment due to OVL variations can cause the HM opening to shift from over the transistor's source / drain to over the gate.Due to the misalignment, the electrically inactive material above the gate (particularly at the corner of the gate) is exposed to a larger amount of etchant than intended in the normal process, and is subsequently etched more deeply than intended in the normal process. This can expose the gate to the recess. As a result, the source / drain SAC comes into contact with the gate and is electrically shorted to the gate when the recess is filled with the conductive material.

[0006] Therefore, some embodiments of the present invention relate to a method of fabricating a source / drain SAC for a transistor. The method comprises forming a pair of gate structures in a first dielectric material on a surface of a substrate, separated from the first dielectric material by an etch stop material. A cap material is formed on the pair of gate structures and the first dielectric material. A pattern of a mask material is formed by implanting dopants into portions of the cap material. Then, the implanted portions of the cap material are removed by selective etching, creating the pattern of mask material on each gate structure. The pattern of mask material is configured to protect each gate structure during a subsequent etch step to avoid shorting the gate structure to the SAC.In some embodiments, the implanted regions of the capping material are defined by the surface topology of the substrate. In some embodiments, the implantation creates the etch selectivity by converting the capping material from a crystalline phase to an amorphous phase. Further embodiments are described.

[0007] Fig. 1A shows a cross-sectional view of a semiconductor device 100 being fabricated on a surface of a substrate 102. The semiconductor device 100 includes a pair of gate structures 104 disposed beneath an etch stop material 106 in a first dielectric material 108; and a mask material 110 disposed over each gate structure 104. The source / drain contact 118 is disposed on the etch stop material 106 between the pair of gate structures 104 and a portion of each etch mask 110 over each gate structure 104. The semiconductor device 100 also includes a second dielectric material 112 disposed over each mask material 110 in a region where the source / drain contact 118 is not located.Each gate structure 104 includes a gate electrode 114 disposed between spacers 116 that provide electrical isolation between the gate electrode 114 and the source or drain of the semiconductor device 100. In some embodiments, the gate electrodes 114 include polysilicon. In some embodiments, the gate electrodes 114 include a replacement metal gate (RGM). In various embodiments, the etch stop material 106 includes silicon nitride (SiN).

[0008] The semiconductor device 100 has a first interface layer 122 formed between the mask material 110 and the source / drain contact 118. Fig. 1B shows a cross-sectional view of some embodiments of a first region 100B of the first interface 122, in which a surface of the source / drain contact 118 forms a concave apex 124 with the mask material 110 along the first interface 122. The mask material 110 disposed over each gate structure 104 has a first height h1 below the source / drain contact 118 and a second height h2 below the second dielectric material 112 that is greater than the first height h1 (i.e., h2 > h1), where h1 and h2 are in the range of approximately 10 nm (100 angstroms) to 50 nm (500 angstroms). This height "step" of the mask material 110 results from the method for forming the source / drain contact 118, which will be described in subsequent embodiments.

[0009] Fig. 1C shows a cross-sectional view of some embodiments of a second region 100C of the first interface 122, in which the height step of the mask material 110 also results in the surface of the source / drain contact 118 forming a convex vertex 126 with the mask material 110 along the first interface 122. Fig. 1D shows a cross-sectional view of some embodiments of a third region 100D of the first interface layer 122, in which the first interface layer 122 terminates. The first interface layer 122 terminates at a second interface layer 130 between the hard mask material 110 and the second dielectric material 112. The first interface layer 122 lies in the same plane as a third interface layer 132 formed between the second dielectric material 112 and the source / drain contact 118 at an end point 128 of the first interface layer 122. It should be noted that in the embodiments in the Fig. 1A-1D, the concave vertex 124 and the convex vertex 126 are illustrated as forming a 90° angle. However, in reality, these vertices are rounded due to the corner rounding of the mask material 110 and the source / drain contact 118.

[0010] It should be noted that the semiconductor device 100A of the Fig. 1A-1D does not represent a final configuration on the wafer of the semiconductor device 100A. The semiconductor device 100A is planarized using a CMP (chemical mechanical polishing) process to remove the mask material 110 and the second dielectric material 112 above the source / drain contact 118 for subsequent middle-of-line (MOL) and back-end-of-line (BEOL) processing, as in the embodiments of the Fig. 2A - 2J is shown.

[0011] The Fig. 2A - 2J show cross-sectional views of some embodiments for the manufacture of the source / drain contact. Fig. 2A shows a cross-sectional view of a semiconductor substrate 200A on which a pair of gate structures 104 is formed in a first dielectric material 108. An etch stop material 106 is formed on the pair of gate structures 104 and beneath the first dielectric material 108. After forming these structures, a CMP process is performed to create a planar surface 202 of the semiconductor substrate 200A.

[0012] Fig. 2B shows a sectional view of a semiconductor substrate 200B, which is the semiconductor substrate 200A, in which a non-planar surface 204 is formed by a first selective etching process on the planar surface 202 of Fig. 2A. In the first selective etch process, a first selective etchant 206 is used to remove the etch stop material 106 over each gate structure 104 to form a recess 208 over each gate structure 104. The first selective etchant 206 is configured to etch the etch stop material 106 at a significantly higher rate (e.g., about 10 times) than the first dielectric material 108. The first selective etch process is followed by a hardening step.

[0013] Fig. 2C shows a cross-sectional view of a semiconductor substrate 200C, which is semiconductor substrate 200B, in which a capping material 210 is deposited over the non-planar surface 204. In various embodiments, depositing the capping material 210 comprises depositing amorphous silicon (a-Si) by atomic layer deposition (ALD) or another suitable epitaxial process. In these embodiments, after deposition of the capping material 210, the semiconductor substrate 200B is annealed to transition from the a-Si phase to a crystalline silicon (c-Si) phase. In some embodiments, the thermal conditions for the annealing are a temperature in the range of about 250°C to about 750°C and a duration in the range of about 5 minutes to about 5 hours.The resulting cap material 210 has a substantially uniform thickness to conform to the topology of the non-planar surface 204, thereby forming a recessed region 212 over each gate structure.

[0014] Fig. 2D shows a cross-sectional view of a semiconductor substrate 200D, which is the semiconductor substrate 200C, in which a photoresist (PR) material 214 is deposited on the capping material 210. The deposition of the PR material 214 may be performed in a spin-on coating system, in which the PR material 214 is spun onto a top surface 216 of the capping material 210, and then excess PR material 214 is removed from the top surface. The removal of the excess PR material 214 may be achieved by curing the PR material 214 and subsequently etching the excess PR material 214 on the top surface 216. As a result, the remaining PR material 214 is located in the recessed areas 212 above each gate structure 104. Furthermore, the combination of the remaining PR material 214 and the cap material 210 forms a substantially planar top surface (see 218 of Fig. 2E). In some embodiments, the cover material 210 contains silicon.

[0015] Fig. 2E shows a cross-sectional view of a semiconductor substrate 200E, which is the semiconductor substrate 200D, in which the semiconductor substrate 200D undergoes an implantation 220 with dopants through the substantially planar top surface 218. The implanted dopants are absorbed by first regions 222 of the capping material 210, but are prevented from reaching second regions 224 of the capping material 210. In some embodiments, the dopants are arsenic, boron, germanium, oxygen, phosphorus, or a combination thereof. In some embodiments, the dopants are implanted with an energy in the range of about 1 keV to about 100 keV. In some embodiments, the dopants are implanted with a dose in the range of about 1e13 cm -3 up to about 1e17 cm -3 implanted.

[0016] Fig. 2F shows a cross-sectional view of a semiconductor substrate 2000F, which is the semiconductor substrate 200E, in which the PR material 214 has been removed from the recessed regions 212. The implantation 220 of the cap material 210 creates an etch selectivity between the implanted first regions 222 and the non-implanted second regions 224. In some embodiments, the implantation 220 causes the first regions 222 to become amorphous (e.g., a-Si) while the second regions remain crystalline (e.g., c-Si). In these embodiments, a suitable etchant with a high etch selectivity between the amorphous first regions 222 and the crystalline second regions 224 is then used to remove the amorphous first regions 222 of the cap material 210.

[0017] Fig. 2G shows a cross-sectional view of a semiconductor substrate 200G, which is the semiconductor substrate 200F, in which a second selective etch process is performed on the cap material 210 with a second selective etchant 226 that removes the first regions 222 and creates a pattern of the mask material 110 (from the second regions 224). In some embodiments, the second selective etch process is a wet etch process, and the second selective etchant 226 is ammonia (NH3), water (H2O), or a combination thereof. In some embodiments, the second selective etch process is a dry etch process, and the second selective etchant 226 is chlorine (Cl2), nitrogen trifluoride (NF3), or a combination thereof.

[0018] Fig. 2H shows a cross-sectional view of a semiconductor substrate 200H, which is the semiconductor substrate 200G, in which a second dielectric material 112 is formed on the first dielectric material 108 and the pattern of the mask material 110. Then, a PR structure is formed, having an opening 228 in a PR material 230 between the pair of gate structures 104. In some embodiments, the PR material 230 is a three-layer photoresist comprising a carbon-containing layer formed on the second dielectric material 112, an HM layer formed on the carbon-containing layer, and a PR layer formed on the HM layer. Then, the PR layer is patterned by photolithography, and the pattern is transferred to the HM layer and the carbon-containing layer, forming the opening 228.

[0019] Fig. 2I shows a cross-sectional view of a semiconductor substrate 200I, which is the semiconductor substrate 200H, in which an etching process has been performed on the first dielectric material 108 through the opening 228 in the PR material 230 to form a contact recess 232. Etching the first dielectric material 108 removes the first dielectric material 108 between the pair of gate structures 104, using the PR material 230 and the mask material 110 to prevent the pair of gate structures 104 from being etched.

[0020] Fig. 2J shows a cross-sectional view of a semiconductor substrate 200J, which is the semiconductor substrate 200I, in which the contact recess 232 has been filled with a conductive material to form a source / drain contact 118. The semiconductor substrate 200J is then planarized using a CMP process to remove the mask material 110 and the second dielectric material 112, forming a planar surface 234 on the source / drain contact 118. The semiconductor substrate 200J is subsequently subjected to MOL and BEOL processing to complete the fabrication of the semiconductor device.

[0021] The Fig. 3A-3D show cross-sectional views of some embodiments for creating a surface topology of a substrate by selective etching. Fig. 3A illustrates a cross-sectional view of some embodiments of a device structure 300A including a substrate 302 on which a plurality of structures 304 (e.g., gate structures) are deposited, creating the surface topology of the substrate 302. The device structure 300A also includes a first material 306 (e.g., an etch stop material) having a first uniform thickness t1 deposited on the plurality of structures 304.

[0022] Fig. 3B illustrates a cross-sectional view of some embodiments of a device structure 300B, which is the device structure 300A in which a second material 308 (e.g., a dielectric material) has been deposited on the first material at a position above and between the plurality of structures 304. Fig. 3C shows a cross-sectional view of some embodiments of a device structure 300C, which is the device structure 300B, in which a planar surface 310 is created using a CMP or other planarization process. The planar surface 310 includes the first material 306 and the second material 308. Fig. 3D shows a cross-sectional view of some embodiments of a device structure 300D, which is the device structure 300C, in which the planar surface 310 is selectively etched. For the selective etching, an etchant 312 is used that etches the first material 306 at a substantially higher speed (e.g., in the range of about 5 times to about 10 times the speed) than the second material 308 to form a first recess 314 in the planar surface 310. Thus, the selective etching forms a surface topology of a substrate having the first recesses 314 (see 402 in Fig. 4A) is generated.

[0023] The Fig. 4A-4D show cross-sectional views of some embodiments for using the surface topology of a substrate to create the structure of a mask material. Fig. 4A shows a cross-sectional view of some embodiments of a substrate 400A with the device structure 300D. The substrate 400A has a first surface topology 402 having the first recesses 314 formed by the selective etching in the embodiments of Fig. were produced in 3D.

[0024] Fig. 4B shows a cross-sectional view of some embodiments of a substrate 400B, which is the substrate 400A, on which a capping material 404 is formed, wherein the capping material 404 has a second surface topology 406 that is the same as the first surface topology 402. The second surface topology 406 also has second recesses 408 formed over the first recesses 314.

[0025] Fig. 4C shows a cross-sectional view of some embodiments of a substrate 400C, which is the substrate 400B on which a PR material 410 is formed in the second recesses 408 of the second surface topology 406 to form a planar surface 412 comprising the cap material 404 and the PR material 410.

[0026] Fig. 4D shows a cross-sectional view of some embodiments of a substrate 400D, which is substrate 400C, in which a first region 416 of the cap material 404 undergoes a dopant implantation 414. At the same time, second regions 418 of the cap material 404 are protected from the implantation 414 under the PR material 410. The implantation 414 creates etch selectivity between the first region 416 and the second regions 418 of the cap material 404. In some embodiments, the cap material 404 initially has a crystalline phase (e.g., c-Si). In these embodiments, the implantation 414 creates the etch selectivity between the first region 416 and the second regions 418 by converting the cap material 404 in the first region 416 from the crystalline phase to an amorphous phase (e.g., a-Si), while leaving the cap material 404 in the second regions 418 in the crystalline phase.

[0027] Fig. 4E shows a cross-sectional view of some embodiments of a substrate 400E, which is substrate 400D, in which the PR material 410 has been removed and the first region 416 of the cap material 404 has been etched away. The removal of the first region 416 of the cap material is performed using a selective etch process that removes the implanted cap material 404 in the first region 416 at a significantly higher rate than the non-implanted cap material 404 in the second regions 418. This creates a structure formed by the remaining cap material 404 in the second regions 418.

[0028] Fig. 4F illustrates a cross-sectional view of some embodiments of a substrate 400F, which is the substrate 400E, in which the non-implanted cap material in the second regions 418 is used as a mask material (e.g., 110) in a subsequent etching process. In the subsequent etching process, an etchant 420 is used to form recesses 422 in the regions of the substrate 400F that are not protected by the mask material in the second regions 418.

[0029] Fig. 5 illustrates some embodiments of a method 500 for using a surface topology of a substrate to create a pattern of a mask material. While the method 500 and a subsequent method 600 are described as a sequence of steps or operations, it should be understood that the illustrated order of these steps or operations is not intended to be limiting. For example, some steps or operations may occur in different orders than those illustrated and / or described herein and / or concurrently. Furthermore, not all illustrated steps may be required to implement one or more aspects or embodiments of the present description. Furthermore, one or more of the steps described herein may be performed in one or more separate steps and / or phases.

[0030] In step 502, a capping material is formed on a substrate, wherein the capping material has the same surface topology as the substrate.

[0031] In step 504, a photoresist material is formed in recesses of the surface topology of the capping material to form a planar surface comprising the capping material and the photoresist material.

[0032] In step 506, first regions of the capping material are implanted with dopants, while second regions of the capping material are protected from the dopants under the photoresist material. The implantation creates etch selectivity between the first and second regions of the capping material.

[0033] In step 508, the photoresist material is removed.

[0034] In step 510, the first regions of the capping material are removed by performing a selective etching process with an etchant configured to remove the implanted capping material in the first regions at a significantly higher rate than the non-implanted capping material in the second regions. The selective etching results in a structure formed by the remaining capping material in the second regions.

[0035] In step 512, the non-implanted cap material in the second regions is used as a mask material in one or more subsequent etching steps.

[0036] Fig. 6 shows some embodiments of a method for creating a surface topology of a substrate by selective etching.

[0037] In step 602, a first material is formed on one or more structures deposited on a surface of the substrate, wherein the one or more structures create the surface topology of the substrate.

[0038] In step 604, a second material is formed on the first material at a position between the one or more structures.

[0039] In step 606, a planar surface is formed comprising the first material on the one or more structures and the second material.

[0040] In step 608, a selective etching process is performed on the planar surface to etch the first material to create depressions in the planar surface on the one or more structures.

[0041] It should be understood that appropriate changes and / or modifications may occur to one skilled in the art upon reading and / or understanding the specification and upon reviewing the accompanying drawings. The present invention includes all such changes and modifications and is generally not intended to be limited thereby. Moreover, although a particular feature or aspect may be described for only one of several implementations, that feature or aspect may, if desired, be combined with one or more other features and / or aspects of other implementations. Furthermore, as used herein, the terms "includes," "has," "with," and / or variations thereof, are intended to have an inclusive meaning—such as "comprises." Likewise, "exemplary" is intended to mean only one example, not the best.It should also be understood that for convenience and clarity, features, layers and / or elements described herein are depicted with particular dimensions and / or orientations relative to one another, and that actual dimensions and / or orientations may vary substantially from those depicted.

[0042] Some embodiments of the present invention relate to a method of fabricating a source / drain SAC for a transistor. The method comprises forming a pair of gate structures in a first dielectric material on a surface of a substrate, separated from the first dielectric material by an etch stop material. A cap material is formed on the pair of gate structures and the first dielectric material. A pattern of mask material is created by implanting portions of the cap material with dopants. Then, the implanted portions of the cap material are removed by selective etching, creating the pattern of mask material on each gate structure. The pattern of mask material is configured to shield each gate structure during a subsequent etch step to prevent shorting the gate structure to the SAC.In some embodiments, the implanted regions of the capping material are defined by a surface topology of the substrate. In some embodiments, the implantation creates the etch selectivity by converting the capping material from a crystalline phase to an amorphous phase.

[0043] In some embodiments, the present invention relates to a method for using the surface topology of a substrate to create a pattern of a mask material on the substrate. The method comprises forming a capping material on a substrate, wherein the capping material has the same surface topology as the substrate. The method further comprises forming a photoresist material in recesses of the surface topology of the capping material, thereby forming a planar surface comprising the capping material and the PR material. The method further comprises implanting dopants into first regions of the capping material while protecting second regions of the capping material beneath the photoresist material from the dopants, wherein the implantation creates etch selectivity between the first and second regions of the capping material.

[0044] In some embodiments, the present invention relates to a method of fabricating a source / drain contact, comprising creating a pair of gate structures in a first dielectric material on a surface of a substrate. The method further comprises forming a capping material on the pair of gate structures and the first dielectric material. The method further comprises forming a mask material on each gate structure by implanting dopants into portions of the capping material and removing the implanted portions of the capping material. The method further comprises the steps of removing the first dielectric material in the portions not covered by the mask material to form a recess; and filling the recess with a conductive material to form the source / drain contact.

[0045] In some embodiments, the present invention relates to a method of forming a source / drain contact, comprising the steps of forming an etch stop material on a pair of gate structures and forming a first dielectric material on the etch stop material at a position between the pair of gate structures. The method further comprises creating a planar surface comprising the etch stop material on each gate structure and the first dielectric material. The method further comprises performing a first selective etch process on the planar surface with a first selective etchant that removes the etch stop material on each gate structure, thereby creating a non-planar surface.The method further comprises forming a cap material on the non-planar surface having a recessed region above each gate structure resulting from the topology of the non-planar surface.

Claims

[1] Method for producing a source / drain contact, comprising the following steps: forming a pair of gate structures (104) in a first dielectric material (108) on a surface of a substrate (102); Forming a capping material (210) on the pair of gate structures (104) and the first dielectric material (108); Forming a mask material (224, 110) on each gate structure by implanting regions of the cover material (210) with dopants and Removing the first dielectric material (108) in the areas not covered by the mask material (110); wherein the formation of the mask material (110) comprises the following steps: Forming an etch stop material (106) on a pair of gate structures (104); Forming a first dielectric material (108) on the etch stop material at a position between the pair of gate structures (104); Forming a planar surface (202) comprising the etch stop material (106) on each gate structure and the first dielectric material (108); Forming a non-planar surface by performing a first selective etching process (206) on the planar surface (202) with a first selective etchant (206) that removes the etch stop material (106) on each gate structure (104); and Forming the capping material (210) on the non-planar surface having a recessed region (212) above each gate structure (104) resulting from the topology of the non-planar surface. [2] The method of claim 1, wherein the cover material (210) contains silicon. [3] The method of claim 1, further comprising the steps of: depositing a photoresist material (214) in the recessed area over each gate structure (104); performing an implantation of dopants (220) into first regions of the covering material (222) while preventing the dopants from reaching second regions of the covering material (224); and Performing a second selective etching process on the cover material with a second selective etchant (226) that removes the first regions and creates a pattern of the mask material (110) from the second regions (224). [4] The method of claim 3, wherein the second selective etchant (226) comprises ammonia, water, or a combination thereof. [5] The method of claim 3, wherein the second selective etchant (226) contains chlorine, nitrogen trifluoride, or a combination thereof. [6] The method of claim 3, further comprising the steps of: Forming the capping material (210) by depositing an amorphous material on the pair of gate structures and the first dielectric material (108) and annealing the amorphous material to produce a crystalline material; and Implanting the crystalline material (210) with the dopants (220) to create etch selectivity between the first and second regions (222, 224). [7] The method of claim 6, wherein the implanting (220) causes the first regions (222) to transition to an amorphous phase while the second regions (224) remain in the crystalline phase, thereby creating etch selectivity between the amorphous and crystalline regions. [8] The method of claim 1, wherein removing the first dielectric material (108) further comprises the steps of: Etching the first dielectric material (108) between the pair of gate structures (104) to create a recess (232) exposing the surface of the substrate, wherein the mask material (110) is used to prevent the pair of gate structures (104) from being etched; and Producing the source / drain contact (118) which is electrically connected to the surface of the substrate (102) by filling the recess with a conductive material. [9] The method of claim 8, wherein etching the first dielectric material (108) comprises the following steps: Forming a second dielectric material (112) on the first dielectric material (108) and second regions (110) of the cover material (210); Producing a photoresist structure (230) having an opening (228) in a photoresist material (230) between the pair of gate structures (104) and Etching through the opening in the photoresist structure, wherein the photoresist structure (230) and the mask material (110) are used to prevent the pair of gate structures (104) from being etched. [10] The method of claim 1, wherein the dopants (220) are arsenic, boron, germanium, oxygen, phosphorus, or a combination thereof. [11] A method for producing a source / drain contact (118), comprising the following steps: Forming an etch stop material (106) on a pair of gate structures (104); Forming a first dielectric material (108) on the etch stop material (106) at a position between the pair of gate structures (104); forming a planar surface (202) comprising the etch stop material (106) on each gate structure and the first dielectric material (108); Performing a first selective etching process (206) on the planar surface with a first selective etchant that removes the etch stop material (106) on each gate structure (104) to form a non-planar surface (204); and Forming a cap material (210) on the non-planar surface (204) having a recessed region (212) over each gate structure (104) to form a topology of the non-planar surface (216). [12] The method of claim 11, further comprising the steps of: Forming a photoresist material (214) in the recessed region (212) over each gate structure (104); performing an implantation (220) of first regions (222) of the covering material (210) with dopants, wherein the dopants are prevented from reaching second regions (224) of the covering material (210); and Performing a second selective etching process (226) on the cover material (210) with a second selective etchant that removes the first regions (222) and creates a pattern of the mask material (110) from the second regions (224). [13] The method of claim 12, further comprising the steps of: Forming the capping material (210) by depositing an amorphous material on the pair of gate structures (104) and the first dielectric material (108) and annealing the amorphous material to produce a crystalline material; and Performing an implantation (220) of the crystalline material with the dopants to create an etch selectivity between the first and second regions (222, 224), wherein the implantation causes the first regions (222) to transition to an amorphous phase while the second regions (224) remain in the crystalline phase, thereby creating an etch selectivity between the amorphous and crystalline regions. [14] The method of claim 13, wherein removing the first dielectric material (108) further comprises the steps of: Forming a second dielectric material (112) on the first dielectric material (108) and second regions of the cover material (110); Producing a photoresist structure (230) having an opening (228) in a photoresist material between the pair of gate structures (104) and Etching through the opening (228) in the photoresist structure (230) to etch away the first dielectric material (108), wherein the photoresist structure (230) and the mask material (110) are used to prevent etching of the pair of gate structures.

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