Chip with protective function and method for manufacturing

Abstract

Chip with varistor function, - comprising a zinc oxide varistor layer (VS) - with a multi-layer electrode structure that realizes a varistor function in the varistor layer - with at least two solderable or bondable external contacts (AK) on a first main surface of the varistor layer (VS) - with a glass layer (GS) applied to the first main surface, leaving only the external contacts uncovered - wherein the glass layer comprises as main component oxides of Si and / or Ge, B and K, which in total comprise at least 70 wt.% of the components of the glass layer, - where the content of Al, Ga, Cr and Ti is less than one percent by weight based on the total glass composition.

Description

[0001] The application concerns a chip with a protective function and a low profile that is surface-mountable.

[0002] Discrete components with varistor functionality can be used to protect sensitive systems, components, and networks against ESD (electrostatic discharge). These are nonlinear components whose resistance drops significantly when a certain applied voltage is exceeded. Varistors are therefore suitable for safely dissipating overvoltage pulses. Varistors are made of a zinc oxide ceramic with a grain structure.

[0003] Varistors are difficult to integrate into multilayer ceramics and are therefore typically used as discrete components. Surface-mount varistors require solderable or bondable metallizations, which must then be applied to the zinc oxide surface of the varistor. However, the production of these contacts presents the problem that good-quality solderable and bondable contacts can only be produced with electroplating. However, the commonly used electroplating baths are acidic or basic and therefore suitable for dissolving the zinc oxide of the varistors.

[0004] A galvanic coating for the production of solderable or bondable contacts of zinc oxide varistors therefore requires a suitable protective layer for the zinc oxide surface that is not to be coated.

[0005] DE 103 59 264 A1 discloses a multilayer varistor with a glass layer applied beneath its electrodes. Varistors are known from DE 10 2008 024 479 A1 and JP 2007 - 088 173 A. DE 10 2004 005 664 A1 discloses an electrical component with a circumferential passivation layer.

[0006] Glass-based protective coatings have already been proposed that enable the structured production of contacts. However, it has been shown that varistors with a glass coating exhibit degradation, which manifests itself in an increasing leakage current, also known as reverse current. Circuits containing such varistors exhibit power consumption that exceeds the permissible value. Furthermore, the degradation can manifest itself as an increase in grain resistance and lead to an increase in the terminal voltage. While the problem of degradation leads to only relatively minor degradation in thick varistor components, the degradation becomes even more pronounced in thinner varistor components.

[0007] The object of the present invention is therefore to provide a surface-mountable chip with a protective function, which has a low overall height and at the same time a low blocking current while complying with the requirements for U Cand to the varistor voltage U V According to a further subtask, a substrate for electrical components with high heat generation is to be specified.

[0008] This object is achieved according to the invention with a chip having a varistor function and the features of claim 1. Advantageous embodiments of the invention and a method for producing the chip can be found in further claims.

[0009] It has been found that the above-mentioned degradation effects in varistor components are attributable to certain ions that diffuse from the protective glass layer into the ceramic and impair the varistor function. Furthermore, it has been found that the problem can be solved by using a protective glass layer whose main components are oxides of silicon and / or germanium, boron, and potassium, and which is essentially free of interfering additives such as aluminum, gallium, chromium, and titanium. Essentially free means a content that is significantly less than one percent by weight, preferably less than half a percent by weight, based on the total glass composition. Proportions of these interfering additives close to 1 wt.% and above otherwise result in noticeable changes in UC and IC. The main components make up at least 70 wt.% of the glass layer.It is also possible that the glass layer used consists exclusively of the main components mentioned.

[0010] On a zinc oxide varistor layer with a glass layer of the above-mentioned composition as a protective and masking layer, metallization applied directly to the varistor layer can be easily reinforced electrolytically or electrolessly in a standard electroplating bath without attacking the zinc oxide surface. The glass layer also does not cause any degradation in the varistor layer.

[0011] The chips with varistor function and a sufficiently thick metallization for the solderable and / or bondable external contacts and connection pads are stable over the long term and show no deterioration in their properties, and in particular, no unacceptable increase in leakage current. This demonstrates that the use of a glass layer of the above-mentioned composition can successfully prevent the diffusion of interfering ions and the resulting electrical degradation of the varistors.

[0012] The varistor function is realized in a conventional and known manner by a multi-layer electrode structure within the varistor layer, which is electrically connected to the external contacts.

[0013] In one embodiment of the invention, the varistor layer has electrical connection pads on a second main surface that are suitable for connecting an electrical component. The connection pads are designed, in particular, for surface mounting an electrical component on the second main surface.

[0014] The electrical connection pads are electrically connected to the electrode structure in the varistor layer and thus to the varistor itself. At least one further connection pad is connected to the external contacts on the first main surface of the varistor layer via corresponding connecting lines. In this way, the external contacts make contact with both the varistor and the component mounted on it. The chip serves as a carrier for the electrical component. Due to its high thermal conductivity of λ > 30 W / mK, the chip's varistor layer is particularly suitable for dissipating any heat loss generated by the component through the varistor layer.If the chip, and thus the component mounted on the chip, is mounted in a circuit environment, in particular on a printed circuit board or printed circuit board, the component's waste heat can be effectively dissipated through the chip without causing the component to overheat. Since absolute heat dissipation is indirectly proportional to the layer thickness of the substrate, or in this case the chip, a sufficiently thin chip offers the further advantage of improved thermal conductivity. The chip or varistor layer can have a maximum layer thickness of 1,000 µm, a maximum of 500 µm, and in particular approximately 250 µm, without the varistor function or mechanical stability being unduly impaired by a decreasing layer thickness.

[0015] The protective function that a varistor such as the one implemented in the chip according to the invention can provide increases with the electrode area in the varistor. The larger the electrode area, the greater the current dissipation capacity in the event of overvoltage. For a given chip size, the electrode area can be increased by increasing the number of electrode layers. A chip according to the invention therefore has at least four electrode layers arranged one above the other and alternately connected to the two external contacts. However, the highest possible number of electrode layers is generally desired in order to ensure maximum current dissipation capacity for a given layer thickness.A reduced distance between different electrode layers for a given layer thickness can be compensated by suitable doping and graining of the zinc oxide material, so that a desired varistor voltage can be set at the desired level even if the number of electrode layers is increased.

[0016] Furthermore, it has been found that certain other additives usable in a glass layer according to the invention also lead to disadvantages or undesirable degradation of the varistor function and should therefore be avoided in the glass layer according to the invention on the varistor layer. It is advantageous, for example, if the glass layer is free of zinc oxide and bismuth oxide. Zinc oxide and bismuth oxide impair, among other things, the glass stability in basic or acidic electroplating baths.

[0017] The thickness of the glass layer is usually chosen to be significantly thinner than the thickness of the varistor layer, since the thermal conductivity of the glass layer is significantly poorer than that of the varistor layer. In one embodiment, fillers with better thermal conductivity than SiO2 are added to the glass layer.

[0018] Filler particles made of zirconium oxide ZrO2 improve the thermal conductivity of the glass layer and are suitable as fillers in a glass layer according to the invention. Furthermore, the filler particles do not impair the protective function of the glass layer or its adhesion to the zinc oxide layer.

[0019] In addition to the main components Si and / or Ge, B, and K, the glass layer may contain other components that neither impair the protective function of the glass layer nor adversely affect the varistor function. Other permitted components are metal oxides selected from lithium, sodium, magnesium, calcium, strontium, and barium. Metal oxides of lithium and sodium may be present in the glass layer in amounts up to a maximum of 5 wt.% each without adversely affecting the desired properties. Metal oxides of magnesium, calcium, strontium, and barium may be added without adverse effects in quantities sufficient to achieve a desired glass transition temperature of the glass layer.

[0020] The glass layer may also contain small amounts of yttrium and other lanthanides. Yttrium oxide can be present in quantities of up to approximately 7.5 wt.% and is a preferred filler for the glass layer due to its low diffusion in the varistor layer and its good thermal conductivity.

[0021] For the external contacts and, if present, the connection surfaces on the varistor layer, an existing base metallization is preferably reinforced by electroplating. Preferred metals for producing or thickening the external contacts and connection surfaces include at least one of nickel, silver, and gold. These materials are preferably used in acidic or basic electroplating baths, against which the varistor layer is reliably protected by the glass layer according to the invention.

[0022] As with other ceramics, the base metallization can be created by printing and firing a conductive paste.

[0023] In a preferred embodiment, the component mounted on the chip is a light-emitting diode (LED). LEDs generate relatively high waste heat and are also sensitive to excessive temperatures, so that good heat dissipation via the substrate is particularly required. A chip with a varistor layer used as the substrate according to the invention advantageously fulfills this task. In addition, the chip can be manufactured with a suitably thin layer thickness, simultaneously providing a protective component against overvoltages that could damage the component, particularly during assembly, and allowing for a low overall height for the chip-LED arrangement.

[0024] To produce a chip with varistor function, the varistor layer is first created. To do this, a stack is created by stacking green foils printed with electrode material. The green foils are made from zinc oxide particles that are finely ground, doped, homogenized, and processed with a solvent such as water and a binder to form a slurry for foil production. Vias through individual zinc oxide green foils can be created by punching holes, called vias, which are then filled with electrode material. The electrode material is also used in the form of a printable paste, which also contains finely divided components (metal particles), a binder, and a solvent.

[0025] By appropriately structuring the individual green foils and arranging them on top of each other, the desired interconnection via the vias and electrode layers is created in the stack. The green foil stack is then sintered into a monolithic varistor layer with a multilayer electrode structure.

[0026] Metallizations for the external contacts and the connection pads are then applied to the finished varistor layer, e.g., by printing a metallization paste onto the first and / or second main surface of the varistor layer. Screen printing, for example, is a suitable printing process. The printed metallization paste on the main surfaces of the varistor layer defines the external contacts and / or connection pads, thereby creating a base metallization in the desired areas.

[0027] To structure the desired external contacts and / or connection surfaces, a glass paste according to the invention is now applied to the main surfaces over the base metallization in such a way that the areas intended for the external contacts and / or connection surfaces remain uncovered.

[0028] To create the glass layer, the components intended for the glass layer—in particular the oxides and / or carbonates of silicon and / or germanium or other suitable starting materials, as well as boron and potassium—are preferably melted and deep-fried to form a glass. The glass is then ground and mixed until homogeneous. The powder is then produced from the powder in the manner described above and subsequently printed.

[0029] The glass paste is then fired or sintered to create a glass layer. It is possible to sinter the metallization layer beneath the glass layer together with the printed glass paste. However, it is also possible to first sinter the base metallization, then print the glass paste, and then sinter the arrangement again.

[0030] In a galvanic or electroless metallization bath, the base metallization can now be reinforced in the areas not covered by the glass layer to a desired layer thickness or a desired current carrying capacity.

[0031] The invention is explained in more detail below using exemplary embodiments and the associated figures. The figures serve only to illustrate the invention and are therefore not drawn to scale. Therefore, neither absolute nor relative dimensions can be derived from the figures.

[0032] They show: Fig. 1 a simple embodiment of a chip according to the invention in schematic cross-section, Fig. 2 shows a chip with external contacts and connection areas, Fig. 3 shows a chip with vias, Fig. 4a shows another embodiment of a chip, Fig. 4b shows a variant of Fig. 4a, Fig. 5 shows a chip with an electrical component mounted on the second main surface, Fig. 6 shows various green foils, some of which are printed with electrode material, from which a varistor layer can be produced, Fig. 7 shows a varistor layer after stacking the green foils and sintering the stack, Fig. 8 shows the arrangement after the application of external contacts, Fig. 9 shows the arrangement after applying a glass layer, Fig. 10 shows the finished chip after thickening the metallization for the external contacts and Fig. 11a and Fig. 11b shows two possible connections of a chip with varistor function with an electrical component to be protected.

[0033] Fig. 1 shows a simple embodiment of a chip CH. This chip has an integrated multi-layer electrode structure in which several electrode layers ES are arranged overlapping one above the other within the varistor layer VS so that they can be connected to different electrodes or different contacts. In the embodiment shown, the electrode layers ES are alternately assigned to a first and second external contact AK and are each connected to the corresponding external contact AK via a via DK1, DK2. The regions of the first main surface of the varistor layer VS not covered by the external contact AK are covered with a glass layer GS. Accordingly, the first main surface has either a glass layer covering or a metallization patterned to form an external contact AK. The varistor layer itself, which comprises zinc oxide, is not visible on the first main surface.The second main surface of the varistor layer VS opposite the first main surface can also be covered with a glass layer GS' in order to protect it against aggressive baths, such as those used for electroplating.

[0034] Fig. Figure 2 shows a further embodiment of a chip in which, in contrast to Fig. 1 In addition to an external contact AK on the first main surface, there is also a connection surface AF on the second main surface, which is connected to at least part of the electrode structure inside the varistor layer. In the illustrated embodiment, the varistor can thus be contacted via a connection surface AF and an external contact AK, which are arranged on different main surfaces. A glass layer GS' is also arranged on the second main surface, which only leaves out the connection surface AF and thus protects the varistor layer against aggressive media.

[0035] Fig. 3 shows a further embodiment of a chip in which, similar to Fig. 2 both external contacts AK and connection areas AF are provided, which contact the electrode structure of the varistor via vias DK1 and DK2 once from the first and once from the second main surface. Two further vias DK' and DK'' each connect an external contact on the first main surface with a connection area AF', AF'' on the second main surface. The connection area AF' is not directly connected to the electrode structure of the varistor, so that an electrical connection is made from the first to the second main surface via the external contact, which enables the connection of another component. The connection area AF'' is connected to the electrode structure of the varistor via the via. All connections of the varistor and the component connected to it are thus possible via the external contacts on the first main surface.Areas of the two main surfaces not occupied by external contacts and connection surfaces AF are covered by a glass layer GS, thus protecting the varistor layer.

[0036] Fig. 4a shows a chip similar Fig. 1, in which the vias DK1 and DK2 external contacts AK are connected both to the electrode structure of the varistor and, here, also to connection pads AF on the second main surface. The connection pads AF and the external contacts AK are shown here with a greater layer thickness than the glass layer GS. This means that there are two connection pads AF on the second main surface suitable for connecting a component, via which an electrical component with varistor function can be connected in parallel to the chip and then protects it against overvoltages. Additional connection pads AF and the external contacts AK are possible but not required for simple components. A voltage pulse acting on the component or on the connection pads AF that exceeds the varistor voltage can then be harmlessly diverted via the electrode structure to the external contact AK.

[0037] Fig. 4b shows a chip similar Fig. 4a, in which the connection pads AF and the external contacts AK are implemented as two- or multi-layer metallization. It is possible for the upper sublayer of the two- or multi-layer metallization, facing away from the chip, to have a larger surface area than the bottom sublayer and partially overlap the glass layer. This has the advantage that a larger surface area is available for soldering or bonding to the component or to a circuit environment, and that this larger surface area has a higher current-carrying capacity. The strength of a solder or other bond connection is also increased.

[0038] Fig. 5 shows the chip of Fig. 3, in which an electrical component BE is now mounted on the connection pads AF using a connecting material on the second main surface. Mounting can be achieved, for example, via solder contacts LK, as shown in the figure. This creates simultaneous electrical and mechanical contact between the chip and the component BE. The chip CH can thus serve as a carrier for the component BE, and the component can be connected to a circuit environment via the external contacts AK of the chip CH. The varistor function integrated in the chip serves as protection for the component BE.

[0039] Fig. Figure 6 shows three different green sheets GF1, GF2, and GF3 based on a zinc oxide material, from which a chip according to the invention can be assembled. The topmost green sheet GF1 shown has no patterning or metallization. The two lower green sheets behave, for example, like an image and mirror image and serve to connect the metallization, each of which comprises an electrode layer, to one of two different vias. The vias are punched out in the green sheets GF, for example, and the holes are then filled with conductive paste.

[0040] To produce this green film, a zinc oxide powder is finely ground, mixed with a dopant, and then mixed and ground again until homogeneous. If necessary, a glass former is added to adjust the sintering temperature to a desired value. An organic binder ensures a certain degree of formability and cohesion of the green film. The green film can be formed by film drawing, casting, or any other conventional technique.

[0041] The second green film GF2 is printed with an electrode material that can be sintered to form an electrode layer ES2. Furthermore, this green film contains at least two vias DK, which are created, for example, by punching holes into the green film. The vias are then filled with a conductive compound, usually the electrode material.

[0042] The third green foil GF3 shown is similar to the second green foil, but the vias and the structure of the printed electrode material in both green foils GF2, GF3 are applied horizontally mirrored in order to connect the respective electrode layer ES in the varistor with different vias and thus with different contacts.

[0043] Fig. 7 shows the Fig. 6 are stacked on top of each other to form a varistor layer VS. Only two inner electrode layers ES are shown in the figure to illustrate the alternating arrangement of the electrode layer.

[0044] To achieve the required current-carrying capacity, a suitable varistor, i.e., a chip with a varistor function, typically comprises a plurality of electrode layers alternately connected to different contacts. In the stack shown, the electrode layers are alternately assigned to two vias, which are arranged congruently or overlappingly in the stack to ensure continuous conduction to a main surface, in this case, the first main surface. A green film without any vias and without an electrode layer is applied as the top layer, which serves to cover the inner electrode layers ES.

[0045] Of course, green foils with through-holes can also be used, which also allow access from the second main surface to internal electrode layers or the later external contacts on the first main surface.

[0046] In the next step, the stack of superimposed and, if necessary, pressed green foils is sintered, resulting in the chip as a solid, monolithic composite of the originally separate green foils. The binder burns out completely, leaving metallic electrode layers, the ceramic varistor layer, and purely metallic vias.

[0047] The varistor layer VS obtained after sintering is now provided with a metallization M for the external contacts AK. For this purpose, a metallization paste is printed onto the corresponding main surface in such a way that the metallization is in contact with a respective via DK. Fig. Figure 8 shows the arrangement at this stage of the process.

[0048] Subsequently, a layer of a glass-containing paste with the aforementioned specifications is printed onto the first main surface in such a way that only the metallizations M intended for the external contacts remain uncovered by the glass paste layer. This can be done by screen printing or another spatially resolved process. The entire assembly is then subjected to another sintering process, resulting in a firmly adhering metallization and the now dense and also firmly adhering glass layer GS.

[0049] Alternatively, the metallization paste can be fired before applying the glass paste and the glass layer GS can be fired separately in a further sintering process.

[0050] Fig. Figure 9 shows the arrangement with fired metallizations M for external contacts and fired glass layer GS.

[0051] In the next step, the previously printed and baked metallizations M are reinforced electrolytically or electrolessly to create solderable surfaces. Conventional standardized electroplating baths, which are usually alkaline or acidic, are used for this purpose.

[0052] Suitable depositable metals for the external contacts AK, which can also be used for the connection pads AF, include nickel and gold or nickel and silver layers. However, other metallizations with other metals and, if necessary, additional layers can also be applied galvanically or electrolessly without compromising the properties of the CH chips, especially the varistor function.

[0053] Fig. Figure 10 shows the arrangement after the thickening or completion of the external contacts AK. Depending on the desired application, the thickness of the external contacts AK can exceed the thickness of the glass layer GS. The glass layer and metallization, or the external contacts and the glass layer, can also be flush with each other. It is also possible to connect the external contacts AK and the connection surfaces AF (in the Fig. 6-10 not shown) into the glass layer GS so that they are deeper than the surface of the glass layer.

[0054] Although only the production of external contacts AK, i.e. solderable metallizations on a first main surface of the chip, has been described in the figures, connection areas AF can also be produced on the second main surface of the chip in the same way and parallel to the external contacts AK.

[0055] In one embodiment, a glass paste with the following composition is selected for the production of the glass layer GS: 78 wt.% SiO2, 19 wt.% B2O3, and 3 wt.% K2O. Such a glass has a softening point of 775 °C and, after sintering, a thermal expansion coefficient of approximately 2.8 ppm / K. However, first, a glass paste is produced from the glass powder or the finely distributed and homogeneously mixed oxides. In parallel, a varistor layer VS is heated to the Fig. The process is carried out in the process step shown in Figure 8, i.e., up to the production of the first metallization M before the application of the glass layer GS. At this stage, the varistor properties are determined for comparison purposes. Subsequently, the glass paste is printed and fired, and the varistor is measured again.

[0056] It can be seen that the varistor voltage remains unchanged and that the leakage current does not exceed the permissible currents and is less than 0.1 µA in the example embodiment.

[0057] Electroplating is then performed on the test components to thicken the metallizations M to the desired layer thickness of the external contacts AK or connection pads AF. Further determination of the varistor values ​​at this stage of the process shows that electroplating had no negative impact on the varistor properties.

[0058] This proves that the varistor function is neither negatively influenced by the printed and baked glass layer, nor that the varistor layer is damaged by the subsequent electroplating bath.

[0059] In a parallel experiment, a glass paste is used in which 15 vol.% zirconium oxide powder is added to the glass composition as a filler. This glass layer is also fired at approximately 850 °C. Electrical measurements of the chip show that the varistor function or the electrical varistor properties are not adversely affected.

[0060] With the chip according to the invention, a varistor can be realized which, with a size of, for example, 1.2 x 1.2 mm 2 and a layer thickness of 250 µm has a varistor voltage in the range of approximately 10 V. The clamping voltage U CThe residual voltage is typically a maximum of 100 V at a standardized 8 kV pulse. This demonstrates that the chip with the varistor function can provide excellent protection even at this small size. Due to its high thermal conductivity, small size, and easily patternable contacts, the chip can be used as a substrate for electrical components such as LEDs.

[0061] Fig. 11a and Fig. 11b shows various possibilities how the chip with varistor function can be connected to an electrical component and in particular to a light-emitting diode.

[0062] In Fig. 11a, the varistor V is connected in parallel with the component BE. If the varistor voltage is exceeded, the current can flow through the varistor V, effectively short-circuiting the component until the damaging voltage is dissipated.

[0063] In Fig. 11b, the varistor V is connected in parallel with the component BE to ground. If the varistor voltage is exceeded, the damaging overvoltage or current can be diverted to ground through the varistor V. In both cases, the component remains protected from damaging overvoltages exceeding the varistor voltage.

[0064] In this circuit, which is preferably arranged in accordance with Fig. 5, the chip according to the invention is designed to safely dissipate excess waste heat or heat loss such as that of the LED component through the varistor layer to the external contacts, where it can be harmlessly dissipated at a heat sink within a PCB (printed circuit board).

[0065] The invention is not limited to the structures and methods illustrated in the exemplary embodiments. In particular, the electrode structure of the varistor layer can have any number of electrode layers and any desired patterning. The number of green films, vias, external contacts, and connection pads can also be arbitrarily selected and adapted to the requirements of a desired application. Only external contacts or both external contacts and connection pads can be provided, which may or may not be individually and independently connected to the electrode structure. List of reference symbols AF connection surface AK External Contact BE Electrical component CH Chip DK through-hole plating ES electrode layer GF green film GS glass layer LK solder contact M Metallization VS Varistor shield V Varistor

Claims

[1] Chip with varistor function, - comprising a zinc oxide varistor layer (VS) - with a multi-layer electrode structure that realizes a varistor function in the varistor layer - with at least two solderable or bondable external contacts (AK) on a first main surface of the varistor layer (VS) - with a glass layer (GS) applied to the first main surface, leaving only the external contacts uncovered - wherein the glass layer comprises as main component oxides of Si and / or Ge, B and K, which in total comprise at least 70 wt.% of the components of the glass layer, - where the content of Al, Ga, Cr and Ti is less than one percent by weight based on the total glass composition. [2] Chip according to claim 1, with electrical connection surfaces (AF) on a second main surface of the varistor layer (VS) for connecting an electrical component (BE). [3] Chip according to claim 1 or 2, wherein the electrode structure comprises at least 4 electrode layers (ES) arranged one above the other and alternately connected to the two external contacts (AK). [4] Chip according to one of claims 1-3, wherein the glass layer (GS) is free of ZnO and Bi2O3. [5] Chip according to one of claims 1-4, wherein the glass layer (GS) contains a filler which is a better thermal conductor than quartz. [6] Chip according to claim 5, wherein the glass layer (GS) comprises solid filler particles of ZrO2. [7] Chip according to one of claims 1-6, in which the glass layer (GS) contains as further components oxides of metals selected from Li, Na, Mg, Ca, Sr and Ba in which these components Li and Na are contained in proportions of up to a maximum of 5 wt.% each, and the remaining components in proportions of up to a maximum of 15 wt.% each. [8] Chip according to one of claims 1-7, wherein the external contacts (AK) and optionally the connection surfaces (AF) are galvanically deposited and comprise at least one selected from Ni, Ag and Au. [9] Chip according to one of claims 2-8, in which an electrical component (BE) is mounted on the second main surface of the varistor layer (VS) and is electrically connected to the connection surfaces (AF), in which the electrical component (BE) is connected to the electrode structure and to the external contacts (AK). [10] Chip according to one of claims 1-9, the thickness of which is at most 1000µm, or 500µm or in particular 250µm. [11] Chip according to claim 9, wherein the component (BE) is an LED. [12] Method for producing a chip (CH) with varistor function, - Creating a stack by stacking green foils (GF) printed with electrode material from a ZnO composition - Sintering of the stack with green foils (GF) to form a varistor layer (VS) with a multilayer electrode structure - Printing a metallization paste onto a first and / or second main surface of the varistor layer (VS) to define external contacts (AK) and / or connection surfaces (AF) - structured printing of a glass paste (GP) on it in such a way that areas intended for the later external contacts and / or connection surfaces remain uncovered - Firing and sintering of the metallization paste and the glass paste to produce a metallization (M) and a structured glass layer (GS) - Galvanic or electroless reinforcement of the areas of the metallization (M) intended for the external contacts (AK) and / or connection surfaces (AF) and not covered by the glass layer (GS), - wherein glass paste (GP) is printed and fired, and comprises as main component oxides of Si and / or Ge, B and K, which in total comprise at least 70 wt.% of the components of the glass layer, - where the content of Al, Ga, Cr and Ti is less than one percent by weight based on the total glass composition.

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