Non-volatile storage devices, storage systems and related control methods

Abstract

A non-volatile memory device (120) comprising: a cell array (121) comprising a plurality of cell strings extending on a substrate (11) in a vertical direction, wherein memory cells in each of the cell strings are connected by a plurality of word lines (WL <0> to WL <7> ) and a plurality of bit lines (BL <0> to BL <2> ) controlled; a page buffer (123) connected to the plurality of bit lines (BL <0> to BL <2> ) and configured to store sample data of the cell array (121) in a sample operation; a voltage generator (127) configured to generate voltages for the plurality of word lines (WL <0> to WL <7> ) and the plurality of bit lines (BL <0> to BL <2> ) shall be provided; an input / output buffer (125) configured to temporarily store the sample data received in a data buffer from the page buffer (123) and to output the temporarily stored data to an external device; and a control logic (126) configured to set a status of the non-volatile memory device (120) to a ready state after the scan data is latched in the input / output buffer (125) and before the regeneration of the cell array (121) from a bias of the scan operation is completed, wherein the control logic (126) is further configured to control the input / output buffer (125) to output the sample data stored during the regeneration of the voltage of the cell array (121) to the outside in response to a read enable signal (RE) from an external memory controller (110), wherein the memory controller (110) is configured to send a more urgent command than the output of the scan data from the non-volatile memory device (120) to the non-volatile memory device (120) before the scan data is output from the non-volatile memory device (120) and after a reference time has elapsed after the time at which the status changes to the ready state and the regeneration of the voltage of the cell array (121) is completed, and wherein, when the more urgent command is sent to the non-volatile memory device (120), the non-volatile memory device (120) receiving the more urgent command performs an internal operation corresponding to the more urgent command before outputting the sample data.

Description

BACKGROUND

[0001] The inventive concepts described herein relate to semiconductor memories, and more particularly to a non-volatile memory device, a memory system including a non-volatile memory device, and a method for controlling a memory system including a non-volatile memory device.

[0002] Semiconductor memory devices can be volatile or non-volatile. Volatile semiconductor memory devices are generally characterized by the loss of stored contents in a power-off state, whereas non-volatile semiconductor memory devices are generally characterized by the retention of stored contents in a power-off state.

[0003] Flash memory is an example of a non-volatile storage device widely used in the electronics industry. Flash memory can be used to store large amounts of voice, audio, image, and other data in information devices such as computers, mobile phones, PDAs, digital cameras, camcorders, voice recorders, MP3 players, handheld PCs, game machines, fax machines, scanners, printers, and the like.

[0004] Meanwhile, in an effort to meet the continuing demand for highly integrated memory devices, research has focused on the development of non-volatile memory devices (hereinafter referred to as three-dimensional non-volatile memory devices) in which memory cells are arranged in three dimensions. Due to the relatively large associated stresses of three-dimensional non-volatile memory devices, challenges are encountered in realizing devices that exhibit high operating speeds.

[0005] US 2006 / 0146612 A1 shows flash memory devices configured to output data without waiting for recovery of a bit line and word line, and methods of operation thereof.

[0006] US 2012 / 0265928 A1 shows non-volatile memory devices, methods for operating non-volatile memory devices and systems incorporating them. SUMMARY

[0007] It is therefore an object of the invention to provide a non-volatile memory device, a memory system, and a control method for a memory system that can avoid the disadvantages of the prior art. Advantageous embodiments are recited in the subclaims.

[0008] One aspect of embodiments of the inventive concept is directed to providing a non-volatile memory device comprising a cell array having a plurality of cell strings extending on a substrate in a vertical direction, wherein memory cells in each of the cell strings are controlled by a plurality of word lines and a plurality of bit lines.The non-volatile memory device further includes a page buffer connected to the plurality of bit lines and configured to store sensing data of the cell array in a sensing operation, a voltage generator configured to provide voltages to the plurality of word lines and the plurality of bit lines, and an input / output buffer configured to temporarily store the sensing data received in a data dump from the page buffer and output the temporarily stored data to an external device.The non-volatile memory device further comprises control logic configured to set a status of the non-volatile memory device to a ready state after the scan data is applied to the input / output buffer and before regeneration of the cell array from a bias of the scan operation is completed.

[0009] Another aspect of the embodiments of the inventive concept is directed to providing a memory system including a non-volatile memory device configured to sample and latch data from selected memory cells in response to a read command, output the latched data as read data, and set a ready / busy signal to a ready state before a regeneration operation on the selected memory cells is completed. The memory system further includes a memory controller configured to control the non-volatile memory device based on the ready / busy signal such that the read data is output and a next command is issued after a reference time elapses from a time when the ready / busy signal is set to the ready state.

[0010] Yet another aspect of embodiments of the inventive concept is directed to providing a control method of a non-volatile memory device, which includes providing a first command to the non-volatile memory device, detecting a timing when a ready / busy signal of the non-volatile memory device transitions from a busy state to a ready state, and providing a second command to the non-volatile memory device. Issuance of the second command to the non-volatile memory device is inhibited before a reference time elapses from the timing at which the ready / busy signal transitions from the busy state to the ready state.

[0011] Yet another aspect of embodiments of the inventive concept is directed to providing a control method of a memory system, in which the memory system comprises a memory controller and a non-volatile memory device. The control method comprises transmitting a read command from the memory controller to the non-volatile memory device, transitioning a busy / ready state signal of the non-volatile memory device from a ready state to a busy state, sampling data of a memory cell array of the non-volatile memory device by latching the data into a page buffer of the non-volatile memory device, and storing or storing the data.Storing the data from the page buffer to an input / output buffer of the non-volatile memory device, performing a regeneration operation of the memory cell array, and transitioning the busy / ready status signal of the non-volatile memory device from the busy state to the ready state before completing the regeneration operation of the memory cell array. SHORT DESCRIPTION OF THE CHARACTERS

[0012] The above and other aspects and features will become apparent from the detailed description which follows with reference to the accompanying drawings, wherein like reference numerals refer to like parts throughout the several figures unless otherwise specified, and wherein: Fig. 1 is a perspective view of a memory block BLKi of a non-volatile memory device according to an embodiment of the inventive concept; Fig. 2 is a schematic diagram of a memory block selection architecture according to an embodiment of the inventive concept; Fig. 3 is a block diagram schematically illustrating a memory system according to an embodiment of the inventive concept; Fig. 4 is a timing diagram schematically showing an example of operation of the memory system of Fig. 3 illustrates; Fig. 5 is a block diagram schematically illustrating a non-volatile memory device according to an embodiment of the inventive concept; Fig. 6 is a timing diagram schematically showing an example of a read operation of a non-volatile memory device of the Fig. 5 illustrates; Fig. 7 is a block diagram schematically showing an example of a status generator of the non-volatile memory device of Fig. 5 illustrates; Fig. 8 is a flowchart for reference in describing an operation of a non-volatile memory device according to an embodiment of the inventive concept; Fig. 9 is a flowchart for reference in describing an operation example applicable to the non-volatile memory device of the Fig. 5 is assigned; Fig. 10 is a table showing examples of minimum wait times with respect to the data size of data that can be processed by a memory controller of the Fig. 9 are requested to read, illustrated; Fig. 11 is a flowchart for reference in describing a control method of the non-volatile memory device of Fig. 5 according to another embodiment of the inventive concept; Fig. 12 is a flowchart for reference in describing an operation of a non-volatile memory device according to another embodiment of the inventive concept; Fig. 13 is a block diagram schematically illustrating a memory system according to another embodiment of the inventive concept; Fig. 14 is a timing diagram schematically illustrating an example of a response of a non-volatile memory device to a first read command; Fig. 15 is a timing diagram schematically illustrating an example of a response of a non-volatile memory device to a second read command; Fig. 16 is a block diagram schematically illustrating a control system according to still another embodiment of the inventive concept; Fig. 17 is a flowchart for reference in describing an operation example of the storage system of Fig. 16 is; Fig. 18 is a block diagram illustrating a user device having a solid-state drive according to an embodiment of the inventive concept; and Fig. 19 is a block diagram illustrating a memory card according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0013] Embodiments will be described in detail with reference to the accompanying drawings. However, the inventive concept may be embodied in various different forms and should not be considered limited only to the illustrated embodiments. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the concept of the inventive concept to those skilled in the art. Accordingly, well-known operations, elements, and techniques with respect to some embodiments of the inventive concept will not be described. Unless otherwise noted, like reference numerals designate like elements throughout the accompanying drawings and description, and thus descriptions will not be repeated. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0014] It will be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Accordingly, a first element, component, region, layer, or section discussed below could be referred to as a second element, component, region, layer, or section without departing from the teachings of the inventive concept.

[0015] Spatially relative terms such as "beneath," "under," "lower," "beneath," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientations illustrated in the figures. For example, if the device is inverted in the figures, elements described as being "below" or "beneath" or "under" other elements or features would then be oriented "above" the other elements or features. Accordingly, the exemplary terms "below" and "below" can encompass both an above and below orientation.The device may be oriented differently (rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein will be interpreted accordingly. Additionally, it will also be understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or one or more intermediate layers may also be present.

[0016] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. When used herein, the singular forms "a" and "an" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will further be understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Likewise, the term "exemplary" is intended to refer to an example or illustration.

[0017] It will be understood that when an element or layer is referred to as being "on," "connected to," "coupled to," or "adjacent to" another element or layer, it may be directly on, connected to, coupled to, or adjacent to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," or "immediately adjacent to" another element or layer, no intervening elements or layers are present.

[0018] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or the present description, and should not be interpreted in an idealized or overly formal sense, unless expressly defined otherwise herein.

[0019] Below, features and functions of the inventive concept will be described by way of example using a flash memory device as a non-volatile storage medium. However, the inventive concept is not limited thereto. For example, the storage medium may be formed of a PRAM, an MRAM, a ReRAM, an FRAM, a NOR flash memory, or the like. In addition, the inventive concept can be applied to semiconductor devices that are supplied with a high voltage from an external device.

[0020] The inventive concept can be implemented by or applied to various embodiments. Furthermore, the detailed description can be modified or changed according to aspects and applications without departing from the scope, spirit, and other objects of the inventive concept. The inventive concept will be described below with reference to the accompanying drawings.

[0021] Fig. 1 is a perspective view of a memory block BLKi of a non-volatile memory device according to an embodiment of the inventive concept. Referring to Fig. 1, a memory block BLKi may have structures extending in axial directions x, y and z.

[0022] A plurality of doping regions 12a, 12b, 12c, and 12d may be formed on a substrate 11 in the length direction along the x-direction. A plurality of insulating materials 18, which also extend in the y-direction, may be arranged sequentially in the z-direction and formed on the substrate between the first and second doping regions 12a and 12b. A plurality of insulating materials 18 may also be similarly arranged between the second and third doping regions 12b and 12c, and between the third and fourth doping regions 12c and 12d. As shown, the insulating materials 18 may be formed such that they are spaced apart from each other along the z-direction.

[0023] On the substrate 11, pillars 13 can be arranged sequentially in the y-direction between the first and second doping regions 12a and 12b and formed so that they penetrate the insulating materials 18 along the z-direction. Here, the pillars 13 can also be formed on the substrate 11 between the second and third doping regions 12b and 12c and on the substrate 11 between the third and fourth doping regions 12c and 12d.

[0024] A surface layer 13a of the pillar 13 may comprise a silicon material of the same type as that of the substrate 11. An inner layer 13b of the pillar 13 may be formed from an insulating material. For example, the inner layer 13b of the pillar 13 may comprise an insulating material such as silicon oxide.

[0025] An insulating film or insulating layer 15 may be provided between the first and second doping regions 12a and 12b along exposed surfaces of the insulating materials 18, the pillars 13, and the substrate 11. In exemplary embodiments, the insulating layer 15 is provided on an exposed surface (e.g., exposed in the z-direction) of the last insulating material 18 provided along the z-direction.

[0026] First conductive materials 14a to 14i may be provided on the exposed surface of the insulating layer 15, between the first and second doping regions 12a and 12b, respectively. For example, a first conductive material 14a extending along the y-direction may be provided between the substrate 11 and an insulating layer 15 adjacent to the substrate 11. In detail, the first conductive material 14a extending along the x-direction may be provided between the substrate 11 and an insulating layer 15 on a lower surface of the insulating material 18 adjacent to the substrate 11.

[0027] The same structure as that between the second doping region 12a and 12b may be provided between the second and third doping regions 12b and 12c, and the same structure as that between the first and second doping regions 12a and 12b may be provided between the third and fourth doping regions 12c and 12b.

[0028] Drains 16 may be provided on the pillars 13. The drains 16 may be formed of an n-type silicon material. Second conductive materials 17a to 17c, which extend along the x-direction, may be provided on the drains 16. The second conductive materials 17a to 17c may be arranged sequentially along the y-direction. The second conductive materials 17a to 17c may be connected to the drains 16 at corresponding surfaces. For example, the drains 16 and the second conductive material 17c, which extends along the x-direction, may be connected to each other by contact plugs.

[0029] Here, the first conductive materials 14a to 14i may form word lines and selection lines. The first conductive materials 14b to 14h used as word lines may be formed such that conductive materials belonging to the same layer are connected to each other. The memory block BLKi may be selected by selecting all of the first conductive materials 14a to 14i. The inventive concept is not limited by the number of first conductive materials 14a to 14i, which may be selected by way of an example in Fig. 1. That is, the number of first conductive materials 14a to 14i can be changed as desired, for example, by process techniques and / or control techniques employed.

[0030] Fig. 2 is a schematic diagram of a memory block selection architecture according to an embodiment of the inventive concept. Referring to Fig. 2, a memory block may comprise a plurality of cell strings. The memory block may be provided with a plurality of string selection lines SSL <0> up to SSL <2> to select a plurality of cell strands.

[0031] One of the memory blocks can be selected by activating a block selection signal BLKWL, which is provided for a memory block to be selected. Pass transistors 20 and 30 of a decoder can be turned on or off by the block selection signal BLKWL. Selection signals SS <0> to SS <2> can be used for strand selection lines SSL <0> up to SSL <2> transmitted through the pass transistor 20. Driver signals S <0> to S <7> and GS can be converted to word lines WL <0> to WL <7> and a ground selection line GSL through the pass transistor 30.

[0032] When the selection signal SS <00> activated, cell strands that are connected to the strand selection line SSL <0> are electrically connected to bit lines BL <0> to BL <2> Under this condition, memory cells contained in a memory unit 40 can be accessed by applying the drive signals S <0> to S <7> . When the selection signal SS <1> activated, cell strands that are connected to the strand selection lines SSL <1> are electrically connected to the bit lines BL <0> to BL <2> Under this condition, memory cells contained in a memory unit 50 can be programmed. When the selection signal SS <2> is activated, cell strands that are connected to the strand selection lines SSL <2> are electrically connected to the bit lines BL <0> to BL <2> Under this condition, memory cells contained in a memory unit 60 can be programmed.

[0033] The selection signals SS <j>, the driver signals S <k>and the block selection signals BLKWL may be provided through the pass transistors 20 and 30 to select a memory block and to select a specific word line of the selected memory block.

[0034] For simplification, Fig. 2 Examples of control signals for selecting a word line. However, it will be understood that various other signals and voltages may be applied, such as voltages applied to a bulk, to bit lines, to common source lines, etc. After a given memory operation, a regeneration operation may be required to discharge applied voltages before a next operation can be performed. The associated regeneration time of the three-dimensional non-volatile memory device used in Fig. 2, may increase due to relatively large resistive and capacitive components. This may adversely delay the execution of the next memory operation.

[0035] As will be described below, embodiments of the inventive concept relate to techniques for eliminating problems associated with the increase in regeneration time discussed above.

[0036] Fig. 3 is a block diagram schematically illustrating a memory system according to an embodiment of the inventive concept. Referring to Fig. 3, a memory system 100 may include a memory controller 110 and a non-volatile memory device 120.

[0037] The memory controller 110 may control the non-volatile memory device 120 in response to a request from a host. The memory controller 110 may provide an interface between the host and the non-volatile memory device 120. The memory controller 110 may control a write operation of the non-volatile memory device 120 in response to a write request from the host. The memory controller 110 may control a read operation of the non-volatile memory device 120 in response to a read request from the host.

[0038] The memory controller 110 may access the non-volatile memory device 120 based on a ready / busy signal RnB or status data from the non-volatile memory device 120. For example, when the ready / busy signal RnB has a ready state (e.g., a high level), the memory controller 110 may provide a read command to the non-volatile memory device 120. In response to an input of the read command, the ready / busy signal RnB of the non-volatile memory device 120 may transition from the high level to a busy state (e.g., a low level) to perform a read operation. When the read operation is complete, the non-volatile memory device 120 may set the ready / busy signal RnB to the high level. The memory controller 110 may provide a read enable signal.provide a read enable signal / RE to the non-volatile memory device 120 in response to a low-to-high transition of the read enable signal / RE, and the non-volatile memory device 120 may output read data.

[0039] In response to the read command, the non-volatile memory device 120 may generate a bias voltage for sensing selected memory cells. The non-volatile memory device 120 may sense the selected memory cells based on the generated bias voltage. The sensed data may be read from a page buffer (in Fig. 3 not shown) of the non-volatile memory device 120 to an output buffer (in Fig. 3 (not shown) therefrom. When the read data is dumped to the output buffer, the non-volatile memory device 120 may set the ready / busy signal RnB to a high level before or during a regeneration operation. At the same time, the non-volatile memory device 120 may perform the regeneration operation to discharge a current or bias voltage provided to the memory cells selected for access.

[0040] As will be explained herein, even if the ready / busy signal RnB transitions from a low level (busy state) to a high level (ready state) some time after the read command is provided to the non-volatile memory device 120, the memory controller 110 may not issue the next command for a predetermined time after the transition. That is, the memory controller 110 may issue the next command after the elapse of the time required to complete a regeneration operation of the non-volatile memory device 120.

[0041] With the memory system 100 of the inventive concept, the non-volatile memory device 120 can output a high level (ready state) of the ready / busy signal RnB or output ready status data before the regeneration operation is completed. Nevertheless, the memory controller 110 cannot issue the next command until a predetermined time has elapsed thereafter.

[0042] Fig. 4 is a timing diagram schematically showing an operation example of the storage system of the Fig. 3. As explained with reference to Fig. 4, a memory controller 110 may retrieve read data before core recovery of a non-volatile memory device 120 is complete.

[0043] During a high-level (ready state) period of a ready / busy signal RnB, the memory controller 110 may issue a read command (00h, ADD, 30h) through input / output terminals I / Oi for the non-volatile memory device 120. When input of the read command is completed, the non-volatile memory device 120 may transition the ready / busy signal RnB to a low level (busy state). Alternatively, the non-volatile memory device may respond to a status read command received through the input / output terminals I / Oi to transmit ready / busy status data to the memory controller 110.

[0044] The non-volatile memory device 120 may generate a word line voltage to be provided for a selected memory area in response to the read command, and the word line voltage may be applied to the selected memory area. This operation may be a word line setup interval corresponding to a time section T0 to T1 of the Fig. 4. Then, the non-volatile memory device 120 may sample and latch cells of the selected memory area. This operation may be a sampling interval corresponding to a time section T1 to T2 of the Fig. 4. The sampled data can be buffered in an output buffer. This operation can be a buffer interval or dump interval, which corresponds to a time section T2 to T3 of the Fig. 4 corresponds.

[0045] The non-volatile memory device 120 may perform a core regeneration operation at time T3 when the latching of the sensing data to the output buffer is completed. Here, the core regeneration operation may be performed to discharge a bulk, word lines, bit lines, select lines, a common source line, etc., associated with the selected memory cells. Likewise, the non-volatile memory device 120 may set a ready / busy signal RnB to a high level (ready state) at time T3 when the latching of the sensing data to the output buffer is completed. Outputting data of the non-volatile memory device 120 to an external device may be possible from a time when the ready / busy signal RnB transitions to a high level.When the memory controller 110 provides a read enable signal / RE to the non-volatile memory device 120 in response to a low-to-high transition of the ready / busy signal RnB, the non-volatile memory device 120 may output the output data.

[0046] Here, it is necessary to define a time when the sampled data is output during the execution of the core regeneration operation. Although the ready / busy signal RnB is set to a high level, an external command should not be provided to the non-volatile memory device 120 during a time section T3 to T4 when the core regeneration operation of the non-volatile memory device 120 is being performed. In this case, even if a command is provided from the memory controller 110 to the non-volatile memory device 120, an abnormal operation may be generated because the core regeneration operation is not completed. Therefore, even though data output is completed, command input may be prohibited during a time section tRC between a time when the ready / busy signal RnB is set to a high level and a time when the core regeneration operation is completed.Hereinafter, the time section tRC may be referred to as a command wait time. During an access operation of the non-volatile memory device 120, the memory controller 110 may issue a next command for a read, program, and erase operation after the command wait time tRC elapses.

[0047] Fig. 5 is a block diagram schematically illustrating a non-volatile memory device according to an embodiment of the inventive concept. Referring to Fig. 5, a non-volatile memory device 120 may include a cell array 121, a row decoder 122, a page buffer 123, a column gating circuit 124, an input / output buffer 125, control logic 126, and a voltage generator 127.

[0048] Cell array 121 may be connected to row decoder 122 via word lines and select lines. Cell array 121 may be connected to page buffer 123 via bit lines BL. Cell array 121 may include a plurality of NAND cell strings, each of which forms a vertical or horizontal channel. The word lines of cell array 121 may be stacked in a vertical direction.

[0049] During a read operation, cell array 121 may be provided with a word line voltage and a select line voltage from row decoder 122. The bit lines of cell array 121 may be provided with a precharge voltage from page buffer 123. Likewise, during the read operation, a well or common source line of cell array 121 may be provided with a voltage from voltage generator 127. Furthermore, during the read operation, various core voltages may be applied to selected memory cells and peripheral circuits.

[0050] Row decoder 122 may select one of the memory blocks of cell array 121 in response to an ADD address. Row decoder 122 may select one of the word lines of the selected memory block. Row decoder 122 may provide the word line voltage and the select line voltage for the selected memory block. During a read operation, row decoder 122 may transmit a select read voltage to a selected word line and a non-select read voltage to a non-selected word line.

[0051] The page buffer 123 can act as a write driver or a sense amplifier according to an operating mode. During a read operation, the page buffer 123 can sense data from selected memory cells through bit lines according to control of the control logic 126. The page buffer 123 can precharge bit lines of selected memory cells according to control of the control logic 126. The page buffer 123 can sense bit lines or sense nodes of the selected memory cells in response to sense enable signals S_EN from the control logic 126. The sensed data can be stored in latches of the page buffer 123. Likewise, the page buffer 123 can output the latched data to the input / output buffer 125 through the column gate circuit 124 in response to a dump signal from the control logic 126.

[0052] The column gate circuit 124 may sequentially select read data stored at the latch or in the latch (e.g., a cache latch) of the page buffer 124 according to control of the control logic 126.

[0053] Input / output buffer 125 may temporarily store data provided by an external device. Input / output buffer 125 may temporarily store read data or internal status data of non-volatile memory device 120 to be output to the external device through input / output lines at a specified time. For example, input / output buffer 125 may temporarily store a command, address, and data provided through input / output lines from the external device. An rCMD command may be provided to control logic 126, an address for row decoder 122 or control logic 126, and data for page buffer 123.

[0054] Status data provided by control logic 126 may be temporarily stored, and the temporarily stored status data may be output to the external device through the input / output lines. Input / output buffer 125 may output read data output from page buffer 123 in response to an output enable signal Out_EN from control logic 126.

[0055] Control logic 126 may control page buffer 123, column gate circuit 124, input / output buffer 125, and voltage generator 127 in response to the rCMD command or a control signal from the external device. Control logic 126 may perform an overall control operation including a word line setup operation, a data sensing operation, an output operation, and a core regeneration operation on selected memory cells in response to a read command. During a read operation, control logic 126 may output a ready / busy signal RnB that has a low-to-high transition soon after the output operation is completed. At this time, when a status command is received from the external device, control logic 126 may control input / output buffer 125 to output a ready state.

[0056] The control logic 126 may include a status generator 126a for outputting a high level of the ready / busy signal RnB during the execution of the core regeneration operation. After the read command rCMD is provided, the status generator 126a may generate the ready / busy signal RnB and / or status data based on whether data is being sensed from selected memory cells and whether outputting or accumulating the sensed data is complete. The status generator 126a may generate the ready / busy signal RnB and status data regardless of whether the core regeneration operation of the non-volatile memory device 120 is complete. That is, when outputting the sampled data is completed during the execution of the core regeneration operation, the status generator 126a may set the ready / busy signal RnB to a high level and the status data to a ready state.

[0057] Voltage generator 127 may generate wordline voltages to be provided to wordlines under control of control logic 126. Also under control of control logic 126, voltage generator 127 may generate a voltage to be provided to a bulk (or well) region where memory cells are formed. The wordline voltages to be provided to wordlines may include a programming voltage, a pass voltage, a select voltage, a non-select voltage, etc. Voltage generator 127 may also generate select line voltages to be provided to select lines SSL and GSL during read and program operations.

[0058] The non-volatile memory device 120 of the inventive concept can output data to an external device in response to a read command. Specifically, the non-volatile memory device 120 can output data before a core regeneration operation following a cache operation is completed. Thus, input of a next command can be prohibited during a time when the core regeneration operation is being performed. A time when command input is prohibited.

[0059] Fig. 6 is a timing diagram schematically showing an example of a read operation of the non-volatile memory device of the Fig. 5. Referring to Fig. 6, a non-volatile memory device 120 may sequentially perform a word line setup operation, a sense operation, an accumulation operation, and a core regeneration operation in response to a read command (e.g., 00h-ADD-30h).

[0060] When the read command is received during a high level interval of a ready / busy signal RnB, the non-volatile memory device 120 may set the ready / busy signal RnB to a low level and start an overall operation or procedure for scanning selected memory cells.

[0061] At t0, the memory device 120 may perform the word line setup operation. A high level of the string select signal may be applied to a string select line SSL of a selected memory block in the non-volatile memory device 120, and a non-select read voltage Vread may be applied to a non-selected word line.

[0062] At t1, non-volatile memory device 120 may sense the selected memory cells. To sense the selected memory cells, a select read voltage Vrd may be applied to a selected word line. Although not shown, bit lines of memory cells may be precharged to a specific level for a sense operation. Under this condition, in response to a sense enable signal S_EN from control logic 126, a page buffer 123 may sense bit lines or sense nodes supplied with bit line precharge voltages. That is, page buffer 123 may store sense data in a latch therein according to levels of the sense nodes.

[0063] At t2, control logic 126 may provide a dump latch signal to page buffer 123. In response to the dump latch signal, page buffer 123 may output sample data from the latch to an input / output buffer 125. The sample data output from page buffer 123 may be stored at or in a latch unit of input / output buffer 125. This latch operation may be performed until t3.

[0064] At t3, control logic 126 may control cell array 121, row decoder 122, page buffer 123, voltage generator 127, etc., so that they discharge any voltages or currents intended for a read operation. That is, a core regeneration operation may be performed at t3 to restore a bias state of cell array 121 to a state prior to the read operation. Additionally, control logic 126 may set ready / busy signal RnB to a high level at t3 when the latch operation is completed. Alternatively or additionally, if a status read command is received within such an interval, control logic 126 may output a ready state. An output enable signal Out_EN of read data stored at or in the input / output buffer 125 may be activated at a time when the ready / busy signal RnB has a low-to-high transition.

[0065] During a command wait time tRC, when the ready / busy signal RnB is at a high level, the non-volatile memory device 120 may perform the core regeneration operation. For example, in the core regeneration operation, a power supply voltage of the string selection line SSL may be discharged to a ground voltage (e.g., 0 volts), and word line voltages applied to the selected and unselected word lines may be discharged to a ground voltage. The command wait time tRC may be decided by considering the start and end timings of the core regeneration operation. During the command wait time tRC, as described above, command input may be prohibited after the ready / busy signal RnB transitions to a high level.

[0066] Voltage curves of lines WL, SSL and BL during the core regeneration operation (for example, at a time section t3 to t4) are not limited to the examples shown in Fig. 6. This means that the voltage waveforms or curve progressions of the Fig. 6 are only examples. Various modifications, variations, and changes to the voltage waveforms of lines WL, SSL, and BL during the core regeneration operation (for example, during a time period t3 to t4) can be made.

[0067] Fig. Figure 7 is a block diagram schematically showing a status generator of the Fig. 5. Referring to Fig. 7, a status generator 126a may generate a ready / busy signal RnB or status data Status in response to a read command rCMD, a buffer signal Dump, and a scan enable signal S_EN.

[0068] The status generator 126a may decide a level of the ready / busy signal RnB of the inventive concept following an input of the read command rCMD. The status generator 126a may output the ready / busy signal RnB, which has a high-to-low transition, after the read command rCMD is received. During a low level of the ready / busy signal RnB, a non-volatile memory device 120 may perform a word line setup operation, a sensing operation, and a latch operation. The sensing enable signal S_EN may be activated when the word line setup operation is completed. The latch signal Dump may be activated when the sensing operation, which is activated by the sensing enable signal S_EN, is completed.The status generator 126a may output the ready / busy signal RnB, which has a low-to-high transition, at a time when the latch operation is completed. The status data may be output as a ready state from this time.

[0069] Fig. 8 is a flowchart for reference in describing an example of an operation of a non-volatile memory device according to an embodiment of the inventive concept. As described with reference to Fig. 8 will be explained, a non-volatile memory device 120 (refer to Fig. 5) Output data before a core regeneration operation is completed on a read operation.

[0070] In operation S110, non-volatile memory device 120 may receive a read command through an input / output buffer 125. The read command rCMD may be provided using a read command sequence (e.g., 00h-ADD-30h) transmitted from a memory controller 110 to the input / output buffer 125 via input / output lines. The read command rCMD, temporarily latched by the input / output buffer 125, may be transmitted to control logic 126. An address temporarily latched by the input / output buffer 125 may be transmitted to the control logic 126 or a row decoder 122.

[0071] In operation S120, the non-volatile memory device 120 may set a ready / busy signal RnB to a low level in response to the read command rCMD. A status generator 126a of the control logic 126 may set a logic value of a register for setting the ready / busy signal RnB to "0" in response to the read command rCMD. Likewise, the status generator 126a of the control logic 126 may set a value of a status register to be output to the input / output lines to a "ready" state in response to the read command rCMD.

[0072] In operation S130, non-volatile memory device 120 may set a read bias voltage for a read operation. For example, control logic 126 may control row decoder 122, a page buffer 123, and a voltage generator 127 to generate a word line voltage, a select line voltage, a bulk voltage, a bit line voltage, etc., for a read operation. All voltages thus generated may be referred to as a read bias voltage. When generating the read bias voltage, control logic 126 may provide the generated voltages for a bit line, a word line, and a select line.

[0073] In operation S140, the non-volatile memory device 120 may sense voltage variations of bit lines connected to selected memory cells. For example, the page buffer 123 may precharge bit lines connected to selected memory cells and transfer precharged voltages of the bit lines to sense nodes SO. The page buffer 123 may determine logic levels of the sense nodes SO to store a sense result at sense latches designated for a sense operation. Thereafter, sense data stored at the sense latches of the page buffer 123 may be transferred to cache latches of the page buffer 123 to perform a caching operation.

[0074] In operation S150, the non-volatile memory device 120 may perform a latch operation to transfer the sampled data latched by the page buffer 123 to the input / output buffer 125. The control logic 126 may activate a latch signal Dump such that data stored in the cache latches of the page buffer 123 is latched to output latches of the input / output buffer 125. During the latch operation, the control logic 126 may control a column gate circuit 124 such that the sampled data is transferred from the page buffer 123 to the input / output buffer 125 through an input / output unit.

[0075] In operation S160, when the latch operation is completed, the non-volatile memory device 120 may set the ready / busy signal RnB to a high level. When the latch operation is completed, a status generator 126a of the control logic 126 may set a logic value of a register for setting the ready / busy signal RnB to "1," regardless of whether a core regeneration operation is completed. Likewise, in response to a status read command, the status generator 126a may change a value of a status register to be output to input / output lines from a "busy" state to a "ready" state.

[0076] In operations S170a, S170b, and S170c, the non-volatile memory device 120 may perform the core regeneration operation and output the sampled data at the same time. In other words, the output of the sampled data may be performed at least partially in parallel with the execution of the core regeneration operation. When the latch operation is completed, in operation S170a, the core regeneration operation may be performed at the same time as the ready / busy signal RnB transitions from a low level to a high level. The sampled data latched in the input / output buffer 125 may be output independently of the core regeneration operation (S170a). In operation S170b, the control logic 126 may detect whether a read enable signal / RE is provided from the memory controller 110.If the read enable signal / RE is not provided for a predetermined time, the method may be terminated. If the read enable signal / RE is provided, the control logic 126 may activate an output enable signal Out_EN such that the sampled data temporarily stored in the input / output buffer 125 is output to the external device.

[0077] A read operation of the non-volatile memory device 120 of the inventive concept will be described. The non-volatile memory device 120 can scan a selected memory area in response to a read command. The non-volatile memory device 120 can output scanned data by setting a ready / busy signal RnB to a high level before a core regeneration operation following a scan operation is completed. Thus, if the scanned data is output during the execution of the core regeneration operation, a high-speed read operation can be implemented.

[0078] Fig. 9 is a flowchart for reference in describing an example of a control method of a non-volatile memory device of the Fig. 5. With reference to Fig. 9, a memory controller 110 (refer to Fig. 3) not issue a next command during a command wait time tRC, even if a ready / busy signal RnB of a non-volatile memory device 120 transitions from a low level to a high level. This will be described more fully below.

[0079] In operation S210, the memory controller 110 may issue a command (e.g., a read command) to the non-volatile memory device 120. The read command rCMD may be provided using a read command sequence (e.g., 00h-ADD-30h) to the non-volatile memory device 120 through input / output lines of the Fig. 4. However, the inventive concept is not limited to this. For example, a command accompanying an operation of applying specific voltages to bit lines or word lines connected to memory cells of the non-volatile memory device 120 may be provided in the same manner as the read command of the inventive concept.

[0080] In operation S220, the memory controller 110 may detect a ready / busy signal RnB to check an internal operation of the non-volatile memory device 120 according to the transmitted command. Alternatively, the memory controller 110 may provide a status read command to check an internal operation of the non-volatile memory device 120 according to the transmitted command. If the ready / busy signal RnB is low, indicating a busy state, or status data is output as "busy," the memory controller may proceed to check an internal operation of the non-volatile memory device 120. If the ready / busy signal RnB is high, indicating a ready state, or status data is output as "ready," the method may proceed to operation S230.

[0081] In operation S230, the memory controller 110 may retrieve scan data from the non-volatile memory device 120. For example, the memory controller 120 may toggle a read enable signal / RE and retrieve the scan data output in synchronization with the read enable signal / RE.

[0082] In operation S240, the memory controller may compare a size of the sample data output from the non-volatile memory device 120 with a reference size (e.g., N bytes). Here, the reference size may mean a size of data capable of being output during a command wait time tRC. If a size of data read-requested by the memory controller 110 is equal to or greater than the reference size, the process may proceed to operation S250. On the other hand, if a size of data read-requested by the memory controller 110 is less than the reference size, the process may proceed to operation S260.

[0083] In operation S250, since a size of data read-requested by the memory controller 110 is equal to or greater than the reference size, the memory controller 110 may wait until data output is completed. That is, a size of data read-requested by the memory controller 110 being equal to or greater than the reference size may mean that the sample data continues to be output even if the command wait time tRC elapses. Thus, the memory controller 110 may wait until data output is completed. Here, the memory controller 110 may predict a wait time according to a size of data to be output. When one data output cycle is completed, the process may proceed to operation S270.

[0084] Since a size of data read-requested by memory controller 110 is smaller than the reference size, data output may be completed in operation S260 before the command wait time tRC elapses. Memory controller 110 may check whether the command wait time tRC elapses, not whether data output is complete. Memory controller 110 may wait if the command wait time tRC does not elapse. If the command wait time tRC elapses, the process may proceed to operation S270.

[0085] In operation S270, the memory controller 110 may issue a next command to the non-volatile memory device 120. Since the read-requested data is all output or a command wait time tRC for executing the core regeneration operation elapses, reliability may not be reduced even if a command is issued.

[0086] Fig. 10 is a table schematically showing examples of minimum waiting times according to sizes of data processed by a memory controller of the Fig. 9 read-requested, illustrated. Referring to Fig. 10, a minimum wait time can be varied or changed according to a size of data being read-requested and a clock frequency of a memory controller 110. Here, it is assumed that a non-volatile memory device 120 outputs data at the same speed regardless of a clock frequency of the memory controller 110.

[0087] For example, in the case where read-requested data has a size of 4 KB, a time required to output the read-requested data may be approximately 10 µs. If read-requested data has a size of 8 KB, a time required to output the read-requested data may be approximately 20 µs. A time of approximately 40 µs may be required to output 16 KB of data. Here, a command wait time tRC may have a fixed value at a time point after a ready / busy signal RnB transitions from a low level to a high level. The command wait time tRC may be longer or shorter than a time required to output data.

[0088] Fig. 11 is a flowchart for reference in describing an example of a control method of a non-volatile memory device of the Fig. 5 according to another embodiment of the inventive concept. As described below with reference to Fig. 11, although a ready / busy signal RnB transitions from a low level to a high level in a read operation, a memory controller 110 (refer to Fig. 3) do not issue a next instruction during an instruction wait time tRC.

[0089] In operation S310, the memory controller 110 may issue a command (e.g., a read command) to a non-volatile memory device 120. The read command may be provided to the non-volatile memory device 120 through input / output lines of the Fig. 4 using a read command sequence (e.g., 00h-ADD-30h). However, the inventive concept is not limited thereto. For example, a command accompanying an operation of applying specific voltages to bit lines or word lines connected to memory cells of the non-volatile memory device 120 may be provided in the same manner as the read command of the inventive concept.

[0090] In operation S320, the memory controller 110 may detect a ready / busy signal RnB to check an internal operation of the non-volatile memory device 120 corresponding to the transmitted command. Alternatively, the memory controller 110 may provide a status read command to check an internal operation of the non-volatile memory device 120 corresponding to the transmitted command. If the ready / busy signal RnB is low, indicating a busy state, or status data is output as "busy," the memory controller may proceed to check an internal operation of the non-volatile memory device 120. If the ready / busy signal RnB is high, indicating a ready state, or status data is output as "ready," the method may proceed to operation S330.

[0091] In operation S330, the memory controller 110 may decide a next operation of the non-volatile memory device 120. For example, the memory controller 110 may control the non-volatile memory device 120 to output sampled data. In this case, the process may proceed to operation S340. On the other hand, if the output of a command is more urgently needed than the output of the sampled data after the memory controller 110 issues a read command, the process may proceed to operation S350.

[0092] In operation S340, the memory controller may toggle a read enable signal / RE and may retrieve the scan data output in synchronization with the read enable signal / RE.

[0093] In operation S350, the memory controller 110 may wait until a command wait time tRC elapses for input of a next command. If the command wait time tRC does not elapse, the memory controller 110 may wait until a counted time reaches the command wait time tRC. When the command wait time tRC elapses, the memory controller 110 may issue a next command to the non-volatile memory device 120.

[0094] A method is described for applying an instruction wait time tRC when a next instruction must be issued without a data output operation after a read instruction is scheduled.

[0095] Fig. 12 is a flowchart for reference in describing an operation example of a non-volatile memory device according to an embodiment of the inventive concept. Referring to Fig. 12, a non-volatile memory device 120 (refer to Fig. 5) ignore a command that is scheduled before a command wait time tRC.

[0096] In operation S410, the non-volatile memory device 120 may receive a read command through an input / output buffer 125.

[0097] In operation S420, the non-volatile memory device 120 may set a ready / busy signal RnB to a low level in response to the read command rCMD. A status generator 126a of the control logic 126 may set a logic value of a register for setting the ready / busy signal RnB to "0" in response to the read command rCMD. Likewise, the status register 126a may change a value of a status register to be output to the input / output lines from a "ready" state to a "busy" state.

[0098] In operation S430, the non-volatile memory device 120 may generate a read bias voltage for a read operation and sense selected memory cells based on the generated read bias voltage. The non-volatile memory device 120 may sense voltage variations of bit lines connected to the selected memory cells. The non-volatile memory device 120 may store the sensed data at the sense latches of a page buffer 123. The sensed data stored at the sense latches of the page buffer 123 may be transferred to cache latches thereof for a latching operation. The sensed data stored at the cache latches may be later latched in an input / output buffer 125.

[0099] In operation S440, when the latch operation is completed, the non-volatile memory device 120 may set the ready / busy signal RnB to a high level. When the latch operation is completed, the status generator 126a may set a logic value of a register for setting the ready / busy signal RnB to "1," regardless of whether a core regeneration operation is completed. Likewise, the status register 126a may change a value of a status register to be output to the input / output lines from a "busy" status to a "ready" status. In addition, when the latch operation is completed, the non-volatile memory device 120 may perform the core regeneration operation.

[0100] In operation S450, the non-volatile memory device 120 may detect a control operation of the memory controller 110 while performing the core regeneration operation. For example, the non-volatile memory device 120 may determine whether the memory controller 110 activates a control signal (e.g., a read enable signal / RE) for outputting the accumulated data or whether the memory controller 110 issues another command. If the read enable signal / RE is activated, the process may proceed to operation S460. On the other hand, if another command is received without data output, the process may proceed to operation S470.

[0101] In operation S460, the non-volatile memory device 120 may output the sampled data to the memory controller 110.

[0102] In operation S470, the non-volatile memory device 120 may determine whether the command wait time tRC elapses based on a time when the ready / busy signal RnB transitions from a low level to a high level. If the command wait time tRC does not elapse, the process may proceed to operation S480, in which an input command is ignored. Thereafter, the process may proceed to operation S470, in which it is continuously detected whether the command wait time tRC elapses. If the command wait time tRC elapses, the process may proceed to operation S490, in which an input command is executed. In operation S490, the non-volatile memory device 120 may perform an internal operation corresponding to the input command.

[0103] Fig. 13 is a block diagram schematically illustrating a memory system according to another embodiment of the inventive concept. Referring to Fig. 13, a storage system 200 may include a controller 210 and a non-volatile storage device 220.

[0104] The memory controller 210 may issue first and second read commands rCMD and rCMD' to the non-volatile memory device 220. In response to the first read command rCMD, the non-volatile memory device 220 may set a ready / busy signal RnB to a high level after a core regeneration operation is completed. Thus, in a read operation corresponding to the first read command rCMD, sampled data may be output after a core regeneration operation is completed.

[0105] In response to the second read command rCMD', the non-volatile memory device 220 may set the ready / busy signal RnB to a high level when a latch operation of sampled data is completed, regardless of whether the core regeneration operation is completed. Thus, the non-volatile memory device 220 may output the sampled data during the execution of the core regeneration operation.

[0106] With the above description, the memory system 200 can perform a core regeneration operation and a data output operation simultaneously or separately based on a read command type. When the second read command rCMD' is intended for the non-volatile memory device 220, the memory controller 210 cannot issue the next command for a predetermined time even if the ready / busy signal RnB is set to a high level or status data indicates "ready."

[0107] Fig. 14 is a timing diagram schematically illustrating an example of a response of a non-volatile memory device to a first read command. Referring to Fig. 14, a memory controller may control a non-volatile memory device 220 such that data output is possible after a core regeneration operation is completed.

[0108] During a high section of a ready / busy signal RnB, the memory controller 210 may provide a read command sequence 00h-ADD-30h to the non-volatile memory device 220. Here, the read command sequence 00h-ADD-30h may correspond to a first read command rCMD. The non-volatile memory device 220 may set a ready / busy signal RnB to a low level in response to the first read command rCMD. Alternatively or additionally, when a status read command is received, the non-volatile memory device 220 may output data indicating a busy state.

[0109] During a wordline setup section T0 to T1, the non-volatile memory device 220 may respond to the first read command rCMD to generate a wordline voltage to be provided for a selected memory region. During a sense section T1 to T2, the non-volatile memory device 220 may sense and latch cells of the selected memory region. During a latch section T2 to T3, the sensed data may be latched to an output buffer. During a core regeneration section T3 to T4, which follows the latch section, the non-volatile memory device 220 may perform a core regeneration operation to discharge a bulk, wordlines, bitlines, select lines, a common source line, etc., associated with the selected memory cells.

[0110] After the core regeneration operation is completed, the non-volatile memory device may set the ready / busy signal RnB to a high level. Data output may be possible from the time the ready / busy signal RnB transitions from a low level to a high level. When the memory controller 210 activates a read enable signal / RE based on the ready / busy signal RnB, the non-volatile memory device 220 may output the latched data.

[0111] A read mode is described in which data output is possible after a core regeneration operation is completed in response to the first read command rCMD.

[0112] Fig. 15 is a timing diagram schematically illustrating a response of a non-volatile memory device to a second read command. Referring to Fig. 15, a memory controller 210 may retrieve data from a non-volatile memory device 220 even if a core regeneration operation corresponding to a second read command rCMD' is not completed.

[0113] During a high section of a ready / busy signal RnB, the memory controller 210 may provide a read command sequence 02h-ADD-30h to the non-volatile memory device 220. Here, the read command sequence 02h-ADD-30h may correspond to a second read command rCMD'. The non-volatile memory device 220 may set a ready / busy signal RnB to a low level in response to the second read command rCMD'.

[0114] During a word line setup section T0 to T1, the non-volatile memory device 220 may respond to the first read command rCMD to generate a word line voltage to be provided for a selected memory region. During a sense section T1 to T2, the non-volatile memory device 220 may sense and latch cells of the selected memory region. During a latch section T2 to T3, the sensed data may be latched to an output buffer. The ready / busy signal RnB may transition from a low level to a high level when the latch operation is completed. During a core regeneration section T3 to T4, the non-volatile memory device 220 may perform a core regeneration operation to discharge a bulk, word lines, bit lines, select lines, a common source line, etc., associated with the selected memory cells.

[0115] In a read operation corresponding to the second read command rCMD', when a sampled data latch operation is completed during the latch section T2 to T3, the ready / busy signal RnB may transition from a low level to a high level. Output of the sampled data that is latched may be possible from a time when the ready / busy signal RnB transitions from a low level to a high level. At this time, if the memory controller 210 activates a read enable signal / RE, the latched data may be output from the non-volatile memory device 220.

[0116] In a read mode in which the second read command rCMD' is provided, sampled data may be output while a core regeneration operation of the non-volatile memory device 220 is being performed. Although the ready / busy signal RnB is at a high level, output of a next command to the non-volatile memory device 220 may be inhibited during a command wait time tRC when a core regeneration operation is being performed. In the case where the second read command rCMD' is received, input of a next command may be inhibited during a command wait time tRC even though the ready / busy signal RnB is at a high level.

[0117] In the Fig. 14 and Fig. 15, a control method of a non-volatile memory device is described in which a core regeneration operation and a data output operation are performed simultaneously or separately depending on the type of read command received.

[0118] Fig. 16 is a block diagram schematically illustrating a memory system according to yet another embodiment of the inventive concept. Referring to Fig. 16, a memory system 300 may include a memory controller 310 and a non-volatile memory device 320. The memory controller 310 may set a read mode of the non-volatile memory device 320 using a setting feature command.

[0119] The memory controller 310 may set a setting characteristic of the non-volatile memory device 320 to set a read mode. A setting characteristic of the non-volatile memory device 320 may be set such that a core regeneration operation and a data output operation are performed simultaneously or separately during a read operation of the non-volatile memory device 320. In the case where a setting characteristic of the non-volatile memory device 320 is set such that a core regeneration operation and a data output operation are performed simultaneously, input of a next command to the non-volatile memory device 320 may be inhibited during a command wait time tRC even though a ready / busy signal RnB is high during a read operation.

[0120] Fig. 17 is a flowchart for reference in describing an operation example of a storage system of the Fig. 16. As explained with reference to Fig. 17, a non-volatile memory device 320 (refer to Fig. 16) refer to a setting feature to perform a read operation under the control of a memory controller 310. Here, it is assumed that a read mode of the non-volatile memory device 320 is set in advance by a setting feature command.

[0121] In operation S510, the non-volatile memory device 320 may receive a read command from a memory controller 310. A read command sequence provided to the non-volatile memory device 320 may not include information for selecting a read mode.

[0122] In operation S520, the non-volatile memory device 320 may check a previously decided read mode to execute the received read command. The non-volatile memory device 320 may check whether the previously decided read mode corresponds to a first read mode tRC_En or a second read mode tRC_Dis. If the previously decided read mode corresponds to the first read mode tRC_En, the method may proceed to operation S530. On the other hand, if the previously decided read mode corresponds to the second read mode tRC_Dis, the method may proceed to operation S540.

[0123] In operation S530, the non-volatile memory device 320 may read a read-requested memory area according to the first read mode tRC_En and may output the sampled data. The first read mode may correspond to a read mode in which a command wait time tRC is enabled when a data output operation and a core regeneration operation are performed to the same page.

[0124] In operation S540, the non-volatile memory device 320 may scan a read-requested memory area according to the second read mode tRC_Dis and may output the scanned data. The second read mode may correspond to a read mode in which a command wait time tRC is disabled when a data output operation and a core regeneration operation are performed separately.

[0125] Fig. 18 is a block diagram illustrating a user device having a solid-state drive according to an embodiment of the inventive concept. Referring to Fig. 18, a user device 1000 may include a host 1100 and a solid-state drive (hereinafter referred to as SSD) 1200. The SSD 1200 may include an SSD controller 1210, a buffer memory 1220, and a non-volatile storage device 1230.

[0126] The SSD controller 1210 may provide a physical connection between the host 1100 and the SSD 1200. The SSD controller 1210 may provide an interface with the SSD 1200 according to a bus format of the host 1100. In particular, the SSD controller 1210 may decode a command provided by the host 1100 to access the non-volatile storage device 1230 based on the decryption result. The bus format of the host 1100 may include USB (Universal Serial Bus), SCSI (Small Computer System Interface), PCI Express, ATA, PATA (Parallel ATA), SATA (Serial ATA), SAS (Serial Attached SCI), and the like.

[0127] Buffer memory 1220 may temporarily store write data provided by host 1100 or data read from non-volatile storage device 1130. When data existing in non-volatile storage device 1230 is cached, upon a read request from host 1100, buffer memory 1220 may support a caching function to directly provide cached data to host 1100. Typically, a data transfer speed of a bus format (e.g., SATA or SAS) of host 1100 may be higher than that of a storage channel SSD 1200. That is, when an interface speed of host 1100 is relatively fast, a reduction in performance due to a speed difference can be minimized by providing buffer memory 1220 with a large storage capacity.

[0128] The non-volatile storage device 1230 can be used as a storage medium of the SSD 1200. The non-volatile storage device 1230 can be formed from a vertical NAND flash memory with a mass storage capacity. The non-volatile storage device 1230 can be formed from a plurality of storage devices. In this case, the storage devices of the non-volatile storage device 1230 can be connected to the SSD controller 1210 through the channel unit. An example is described in which the non-volatile storage device 1230 is formed as a storage medium from a NAND flash memory. However, the non-volatile storage device 1230 is not limited to a NAND flash memory device. For example, a storage medium of the SSD 1200 can be formed from a PRAM, an MRAM, a ReRAM, an FRAM, a NOR flash memory, and the like.Furthermore, the inventive concept can be applied to a storage system that uses different types of storage devices in combination. Each storage device of the non-volatile memory device 1230 can be configured the same as the one described with reference to FIG. 3.

[0129] In the SSD 1200, the non-volatile storage device 1230 can perform a core regeneration operation and a data output operation simultaneously or separately. If the core regeneration operation and the data output operation are performed simultaneously, the SSD controller 1210 cannot issue a next command during a command wait time tRC, even if a ready / busy signal RnB of the non-volatile storage device 1230 is high.

[0130] Fig. 19 is a block diagram illustrating a memory card according to an embodiment of the inventive concept. Referring to Fig. 19, a memory card system 2000 may include a host 2100 and a memory card 2200. The host 2100 may include a host controller 2110 and a host connection unit 2120. The memory card 2200 may include a card connection unit 2210, a card controller 2220, and a flash memory 2230.

[0131] Each of the host connection unit 2120 and the card connection unit 2210 may be formed of a plurality of pins. Such pins may include a command pin, a data pin, a power pin, etc. The number of pins may vary according to a type of memory card 2200. In exemplary embodiments, an SD card may have nine pins.

[0132] The host 2100 may be configured to write data to the memory card 2200 or to read data stored in the memory card 2200. The host controller 2110 may send a command (e.g., a write command), a clock signal CLK generated within a clock generator (not shown) of the host 2100, and data to the memory card 2200 via the host connection unit 2120.

[0133] Card controller 2220 may operate in response to a write command received via card connection unit 2210 and may store data in memory 2230 in synchronization with a clock signal generated by a clock generator (not shown) of card controller 2220. Memory 2230 may store data transmitted from host 2100. For example, if host 2100 is a digital camera, memory 2230 may store image data.

[0134] The flash memory 2230 of the inventive concept may include memory cells stacked in a direction perpendicular to a substrate. The non-volatile memory device 2230 may perform a core regeneration operation and a data output operation simultaneously or separately. When the core regeneration operation and the data output operation are performed simultaneously, the card controller 2220 may not issue a next command during a command wait time tRC, even if a ready / busy signal RnB of the non-volatile memory device 2230 is high.

[0135] The card connection unit 2210 may be configured to communicate with an external device (e.g., a host) using one of various interface protocols such as USB, MMC, PCI-E, SAS, SATA, PATA, SCSI, ESDI, IDE, and the like.

[0136] A non-volatile memory device and / or a memory controller may be packaged according to any of various packaging technologies such as PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDI2P), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package (WSP), and the like.< / k> < / j>

Claims

[1] A non-volatile memory device (120) comprising: a cell array (121) comprising a plurality of cell strings extending on a substrate (11) in a vertical direction, wherein memory cells in each of the cell strings are connected by a plurality of word lines (WL <0> to WL <7> ) and a plurality of bit lines (BL <0> to BL <2> ) controlled; a page buffer (123) connected to the plurality of bit lines (BL <0> to BL <2> ) and configured to store sample data of the cell array (121) in a sample operation; a voltage generator (127) configured to generate voltages for the plurality of word lines (WL <0> to WL <7> ) and the plurality of bit lines (BL <0> to BL <2> ) shall be provided; an input / output buffer (125) configured to temporarily store the sample data received in a data buffer from the page buffer (123) and to output the temporarily stored data to an external device; and a control logic (126) configured to set a status of the non-volatile memory device (120) to a ready state after the scan data is latched in the input / output buffer (125) and before the regeneration of the cell array (121) from a bias of the scan operation is completed, wherein the control logic (126) is further configured to control the input / output buffer (125) to output the sample data stored during the regeneration of the voltage of the cell array (121) to the outside in response to a read enable signal (RE) from an external memory controller (110), wherein the memory controller (110) is configured to send a more urgent command than the output of the scan data from the non-volatile memory device (120) to the non-volatile memory device (120) before the scan data is output from the non-volatile memory device (120) and after a reference time has elapsed after the time at which the status changes to the ready state and the regeneration of the voltage of the cell array (121) is completed, and wherein, when the more urgent command is sent to the non-volatile memory device (120), the non-volatile memory device (120) receiving the more urgent command performs an internal operation corresponding to the more urgent command before outputting the sample data. [2] The non-volatile memory device (120) of claim 1, wherein the control logic (126) is configured to provide the page buffer (123) with a latch signal such that the sample data is latched or stored from the page buffer (123) to the input / output buffer (125). [3] The non-volatile memory device (120) of claim 2, wherein the control logic (126) comprises: a status generator (126a) configured to set the status to the ready state in response to the latch signal. [4] The non-volatile memory device (120) of claim 1, wherein the bias voltage is a read bias voltage applied to at least one of a word line (WL <0> to WL <7> ), a selection line, a bulk area, a bit line (BL <0> to BL <2> ) and a common source line of the cell array (121). [5] The non-volatile memory device (120) of claim 1, wherein the status is set by controlling a ready / busy signal indicating whether the non-volatile memory is in a busy state or a ready state. [6] The non-volatile memory device (120) according to claim 1, wherein the status is set by controlling a content of status data output in response to a status read command from the external device. [7] Storage system (100, 200, 300) comprising: a non-volatile memory device (120) configured to sample data from selected memory cells in response to a read command and to latch to output the latched data as read data, and to set a ready / busy signal to a ready state before a regeneration operation on the selected memory cells is completed; and a memory controller (110, 210, 310) configured to control the non-volatile memory device (120) based on the ready / busy signal such that the read data is output, and to issue a next command after a reference time elapses from a time when the ready / busy signal is set to the ready state, wherein the memory controller (110, 210, 310) is further configured to switch a read enable signal (RE) at the non-volatile memory device (102) when the read data is to be output from the non-volatile memory device (120) during the regeneration operation, and when the input of a more urgent command to the non-volatile memory device (120) is required instead of outputting the read data from the non-volatile memory device (120), and wherein the memory controller (110, 210, 310) issues the more urgent command to the non-volatile memory device after the reference time has elapsed from the time the ready / busy signal transitions to the ready state and the regeneration of the voltage of a cell array (121) is completed before the read data is output. [8] The memory system (100, 200, 300) of claim 7, wherein the read command is a second type of read command, wherein, when a first type of read command is received, the non-volatile memory device (120) sets the ready / busy signal to the ready state after the regeneration operation is completed, and wherein, when the second type of read command is received, the non-volatile memory device (120) sets the ready / busy signal to the ready state before the regeneration operation is completed. [9] The memory system (100, 200, 300) of claim 8, wherein, when the second type of read command is received, the non-volatile memory device (120) sets the ready / busy signal to a ready state after the read data is latched from a page buffer (123) to an input / output buffer (125). [10] The memory system (100, 200, 300) of claim 8, wherein, after the second type of read command is provided to the non-volatile memory device (120), the memory controller (110, 210, 310) issues a next command after a reference time elapses from a time when the ready / busy signal transitions from a busy state to the ready state. [11] The storage system (100, 200, 300) according to claim 10, wherein the reference time is a time required to perform the regeneration operation. [12] The memory system (100, 200, 300) of claim 10, wherein the memory controller (110, 210, 310) determines a timing to issue the next command based on a size of read-requested data or the reference time. [13] The memory system (100, 200, 300) according to claim 12, wherein, when a time required to output the read-requested data is shorter than the reference time, the memory controller (110, 210, 310) outputs the next command to the non-volatile memory device (120) after output of the read-requested data is completed. [14] The memory system (100, 200, 300) of claim 7, wherein the regeneration operation comprises an operation for resetting at least one of a word line voltage, a bit line voltage, a common source line voltage, a bulk voltage, a charge pump voltage, and select line voltages generated in the non-volatile memory device (120). [15] A control method for a memory system (100, 200, 300), the memory system (100, 200, 300) comprising a memory controller (110, 210, 310) and a non-volatile memory device (120), the method comprising: transmitting a read command from the memory controller (110, 210, 310) to the non-volatile memory device (120); transitioning a busy / ready signal of the non-volatile memory device (120) from a ready state to a busy state; sampling data of a memory cell array (121) of the non-volatile memory device (120) by loading the data into a page buffer (123) of the non-volatile memory device (120); caching the data from the page buffer (123) in an input / output buffer (125) of the non-volatile memory device; performing a regeneration operation of the memory cell array (121); and transitioning the busy / ready status signal of the non-volatile memory device (120) from the busy state to the ready state before completion of the regeneration operation of the memory cell array (121), wherein, when the Ready / Busy signal transitions to the Ready state, a control logic (126) controls the input / output buffer (125) to transmit the data of the input / output buffer (125) to the memory controller (110, 210, 310), and where, if it is necessary to enter a command that is more urgent than the output of the sampled data, after a reference time from the time, at which the ready / busy signal transitions to the ready state and the regeneration of the voltage of the memory cell array (121) is completed, has elapsed before the sampled data is output, the memory controller (110, 210, 310) is configured to provide the more urgent command to the non-volatile memory device (120). [16] The control method of claim 15, further comprising the memory controller (110, 210, 310) delaying transmission of a next command to the non-volatile memory device (120) until a reference time elapses after the busy / ready status signal transitions from the busy state to the ready state. [17] The control method according to claim 16, wherein the reference time is a time required to perform the regeneration operation. [18] The control method of claim 15, further comprising transferring the data from the input / output buffer (125) to the memory controller (110, 210, 310) when the busy / ready status signal transitions to the ready state. [19] The control method according to claim 18, wherein the regeneration operation comprises an operation of resetting at least one of a word line voltage, a bit line voltage, a common source line voltage, a bulk voltage, a charge pump voltage, and select line voltages generated in the non-volatile memory device (120). [20] The control method according to claim 15, wherein the memory cell array (121) of the non-volatile memory device (120) is a three-dimensional memory cell array (121).

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