Semiconductor device

Abstract

Semiconductor device comprising: a first external power supply connection (P1) to which a power supply voltage (VD) is applied; a second external power supply connection (P3) which is set to a reference potential (GND); an anomaly detection circuit (14, 14A, 14B, 24A to 24D) that performs an anomaly detection operation to output a signal (S14, S14A, S14B, S14A to S14D) of the detection of a specific anomaly, indicating whether a specific anomaly to be detected occurs; and an anomaly tracking unit (13, Q2, R2) which includes a fuse (13, 13A, 13B, 19) which is provided between the first and the second external power supply terminal and which performs an anomaly tracking operation to allow current flow through the fuse in order to disconnect the fuse when the signal of detection of a specific anomaly indicates the occurrence of the specific anomalous phenomenon, wherein the semiconductor device is able to continue operating after the anomaly trajectory adjustment unit (13, Q2, R2) has performed the anomaly trajectory operation.

Description

[0001] The invention relates to the field of semiconductor devices such as IPMs (Intelligent Power Modules), and more particularly to a semiconductor device having a function for tracking the history of occurrence of an abnormal phenomenon.

[0002] A conventional semiconductor device such as an IPM generally has a shutdown protection function for shutting down (turning off) a semiconductor element to be protected and outputting a fault signal to the outside to protect a power supply chip on which a semiconductor element such as an IGBT (insulated gate bipolar transistor) is mounted upon the occurrence of an abnormality (fault) such as high temperature generation and overcurrent. Examples of such a semiconductor device with a shutdown protection function include an IPM disclosed in JP 2003-88093.

[0003] The conventional IPM with the shutdown protection function shuts down the semiconductor element to be protected and outputs a fault signal to the outside, but leaves no trace of whether an abnormal phenomenon occurred that caused the IPM to shut down. Thus, it is extremely difficult to determine the cause after the IPM is shut down due to a problem such as various abnormal phenomena. Specifically, the conventional IPM with the shutdown protection function poses a problem in that no appropriate action can be taken after the shutdown because the IPM cannot detect the reason for the shutdown.

[0004] The shutdown protection function of conventional semiconductor devices consistently performs a shutdown protection operation when the abnormal phenomenon exceeds a certain prescribed level. Specifically, the conventional semiconductor device shuts down the semiconductor element to be protected without determining whether the abnormal phenomenon causing the shutdown is at a notable level or at a fatal failure level. Thus, the conventional semiconductor device poses a problem of being user-unfriendly.

[0005] EP 1 630 923 A1 describes an electric heating device with an improved safety concept. For this purpose, the function of a power semiconductor used to adjust the current of a heating stage with PTC heating elements is monitored. As soon as the power semiconductor supplies current to the heating stage without appropriate control, the current path to the power semiconductor is permanently interrupted by blowing a fuse installed in the current path. This reliably permanently deactivates the faulty load switch, preventing subsequent damage to the heater.

[0006] The invention has for its object to provide a semiconductor device which leaves a history of whether a specific abnormal phenomenon to be detected has occurred and which can take appropriate action for a failure.

[0007] This object is achieved according to the invention by a semiconductor device according to claim 1. Advantageous developments of the invention are specified in the dependent claims.

[0008] The abnormality history setting unit includes a fuse between the first and second external power supply terminals and performs an abnormality history operation of disconnecting the fuse by allowing a current to flow through the fuse when the specific abnormality detection signal indicates the occurrence of the specific abnormal phenomenon.

[0009] The semiconductor device according to the invention can detect a history of whether the specific abnormal phenomenon to be detected has occurred from a state of whether the fuse has been blown by the abnormality history operation performed by the abnormality history setting unit. As a result, the semiconductor device can promptly analyze and take appropriate measures after the occurrence of the specific abnormal phenomenon. Accordingly, by using the semiconductor device, the service life of the semiconductor device can be extended with appropriate failure prevention measures.

[0010] Further features and advantages of the invention will become apparent from the description of embodiments of the invention with reference to the figures. The figures show: Fig. 1 is a circuit diagram of an abnormality history setting unit in an IPM in accordance with a first preferred embodiment of the invention; Fig. 2 is a circuit diagram of an abnormality history setting unit in an IPM in accordance with a second preferred embodiment of the invention; Fig. 3 is a circuit diagram of an abnormality history setting unit in an IPM in accordance with a third preferred embodiment of the invention; Fig. 4 is an explanatory schematic diagram of a turn-off control system for an IGBT to be protected by an IGBT turn-off signal; Fig. 5 is a circuit diagram of an abnormality history setting unit in an IPM in accordance with a fourth preferred embodiment of the invention; Fig. 6 is a circuit diagram of an abnormality history setting unit in an IPM in accordance with a fifth preferred embodiment of the invention; Fig. 7 is a circuit diagram of an abnormality history setting unit in an IPM in accordance with a sixth preferred embodiment of the invention; Fig. 8 is a circuit diagram of an abnormality history setting unit in an IPM in accordance with a seventh preferred embodiment of the invention; Fig. 9 is a circuit diagram of an abnormality history setting unit in an IPM in accordance with an eighth preferred embodiment of the invention; Fig. 10 is a circuit diagram of an abnormality history setting unit in an IPM in accordance with a ninth preferred embodiment of the invention; Fig. 11 is an explanatory view of an anomaly history operation and first to third anomaly detection operations of the IPM according to a ninth preferred embodiment in the form of a table; and Fig. 12 is a circuit diagram of an abnormality history setting unit in an IPM in accordance with a tenth preferred embodiment of the invention. First preferred embodiment

[0011] Fig. 1 is a schematic diagram of an anomaly output unit and an anomaly history setting unit of an IPM 1 and its peripherals in accordance with a first preferred embodiment of the invention.

[0012] The IPM 1 includes an external terminal P1 (first external power supply terminal) to which a power supply voltage VD (a positive electrode of a power supply 21) is applied as an external terminal, an external terminal P3 (second external power supply terminal) set to a ground voltage GND (a negative electrode of the power supply 21) which is a reference potential, and an external terminal P2 (external detection terminal) which outputs an error output signal (FO) (false output).

[0013] The anomaly output unit includes an (NPN bipolar) transistor Q1 for detecting the FO and a resistor R1 for the FO. Resistor R1 and transistor Q1 are connected in series between external terminals P2 and P3. Specifically, one end of resistor R1 is connected to external terminal P2, the other end of resistor R1 is connected to a collector of transistor Q1, and an emitter of transistor Q1 is connected to external terminal P3.

[0014] The transistor Q1 receives at its base an abnormality detection signal SF from an abnormality detection circuit 14. Generally, the abnormality detection signal SF assumes an H level (level of power supply voltage VD) to bring the transistor Q1 into an on-state when at least one of a plurality of abnormal phenomena occurs, while it assumes an L level (level of ground voltage GND) to bring the transistor Q1 into a blocking state during a normal state in which none of the plurality of abnormal phenomena occurs.

[0015] On the other hand, an optocoupler 22 includes a light-emitting diode D22 and a phototransistor Q22. An anode of the light-emitting diode D22 is connected to a positive electrode of the power supply 21, while a cathode is connected to the external terminal P2. When the light-emitting diode D22 emits light with an intensity at least equal to a reference value, the phototransistor Q22 is turned on.

[0016] Thus, when transistor Q1, which is the anomaly output unit, is turned on, external terminal P2 and external terminal P3 are electrically connected via resistor R1 and transistor Q1. As a result, the anomaly output signal FO from external terminal P2 is set to the L level, creating a potential difference between the anode and the cathode, which can emit light. Accordingly, light-emitting diode D22 emits light with an intensity at least equal to a reference value. Therefore, by detecting whether phototransistor Q22 is in the on or off state, it can be externally detected whether the error output signal FO is output.

[0017] A fuse 13, a resistor R2, and an (NPN bipolar) transistor Q2, which serve as an anomaly history setting unit, are connected in series between the external terminal P1 and the external terminal P3. Specifically, one end of the fuse 13 is connected to the external terminal P1, the other end is connected to one end of the resistor R2, the other end of the resistor R2 is connected to a collector of the transistor Q2, and an emitter of the transistor Q2 is connected to the external terminal P3.

[0018] The transistor Q2 receives at its base a specific abnormality detection signal S14 from the abnormality detection circuit 14. When a specific abnormal phenomenon to be detected occurs, the specific abnormality detection signal S14 assumes an H level (level of power supply voltage VD) to turn the transistor Q2 on, while it assumes an L level (level of ground voltage GND) to turn the transistor Q2 off when the specific abnormal phenomenon does not occur.

[0019] When the transistor Q2 is brought into an on-state by the specific abnormality detection signal S14 at the H level indicating the occurrence of the specific abnormal phenomenon to be detected, the thus configured abnormality history setting unit (the fuse 13, the resistor R2 and the transistor Q2) performs an abnormality history operation in which the external terminal P1 and the external terminal P3 are electrically connected via the fuse 13, the resistor R2 and the transistor Q2, and a current of a level larger than a disconnection level flows through the fuse 13 to disconnect the fuse 13.

[0020] The anomaly detection circuit 14 performs an anomaly detection operation to output the aforementioned specific anomaly detection signal S14 and the anomaly detection signal SF. Although not shown, the anomaly detection circuit 14 uses the power supply voltage VD obtained from the external terminal P1 as an operating voltage. When the anomaly phenomenon that is the subject of the anomaly detection signal SF is only the specific anomaly phenomenon to be detected by the specific anomaly detection signal S14, the anomaly detection signal SF coincides with the specific anomaly detection signal S14.

[0021] As described above, according to the first preferred embodiment, the IPM 1 can leave a history of whether the specific abnormal phenomenon to be detected has occurred from a state indicating whether the fuse 13 has been cut by the abnormality history operation of the abnormality history setting unit including the fuse 13, the resistor R2, and the transistor Q2.

[0022] By providing a status check function of the fuse 13 for a control circuit (not shown) in the IPM 1, it is relatively easy to confirm whether the fuse 13 has been cut.

[0023] Since the IPM 1 can reliably determine whether the specific abnormal phenomenon to be detected has occurred from a state indicating whether the fuse 13 has been blown, the IPM 1 can immediately analyze and take appropriate action after the abnormal phenomenon occurs. Accordingly, the service life of the IPM 1 can be extended by using the IPM 1 with appropriate fault prevention measures. Second preferred embodiment

[0024] Fig. Fig. 2 is a schematic diagram of an anomaly output unit and an anomaly history setting unit of an IPM 2 and its peripherals in accordance with a second preferred embodiment of the invention. The same components as in Fig. 1 (the anomaly output unit (Q1, R1), the anomaly detection circuit 14, the power supply 21, the photocoupler 22 and the external terminals P1 to P3, etc.) are designated by the same reference numerals and will not be described again.

[0025] The abnormality history setting unit in the IPM 2 includes a latch circuit 15 in addition to the fuse 13, the resistor R2, and the transistor Q2, which are the same as in the first preferred embodiment. Furthermore, the IPM 2 includes a fuse disconnection notification unit including an external terminal P4 (a fuse disconnection notification terminal), a light-emitting diode D4 (LED; light-emitting element) connected to the external terminal P4, and a resistor R3, a transistor Q2, and the latch circuit 15 provided internally. Accordingly, the transistor Q2 and the latch circuit 15 are shared by the abnormality history setting unit and the fuse disconnection notification unit.

[0026] In the fuse disconnection notification unit, an anode of the light-emitting diode D4 is externally connected to the positive electrode of the power supply 21, a cathode thereof is connected to the external terminal P4, one end of the resistor R3 is connected to the external terminal P4, and the other end of the resistor R3 is connected to the other end of the resistor R2 (the collector of the transistor Q2).

[0027] The latch circuit 15 is composed of a flip-flop and the like. When the specific abnormality detection signal S14 is received at the H level during the occurrence of the specific abnormality to be detected, the latch circuit 15 performs a latching operation to hold this specific abnormality detection signal S14 and maintain it at the H state until a control power supply reset operation is performed. Although not shown, the latch circuit 15 uses the power supply voltage VD received from the external terminal P1 as an operating voltage. The control power supply reset operation means an operation of restarting the supply of the power supply voltage VD after the supply of the power supply voltage VD from the power supply 21 has been temporarily stopped.

[0028] The abnormality history setting unit thus configured according to the second preferred embodiment performs a similar abnormality history operation to the abnormality history setting unit according to the first preferred embodiment by using the state in which the specific abnormality detection signal S14 has been latched at the H level by the latch circuit 15 during the occurrence of the specific abnormal phenomenon to be detected as a trigger. Thus, the abnormality history setting unit can cut off the fuse 13. Since the abnormality history setting unit includes the latch circuit 15, it has an advantage of being able to ensure a sufficient period of time until the fuse 13 is cut off.

[0029] On the other hand, the H level of the specific abnormality detection signal S14 is latched by the latch circuit 15 in the fuse cut-off notification unit, whereby a current having a magnitude capable of allowing the light-emitting diode D4 to emit light flows from the power supply 21 through the current path of the light-emitting diode D4 and the resistor R3 until the control power supply reset operation is performed when or after the fuse 13 is cut upon occurrence of the specific abnormal phenomenon.

[0030] As a result, the light-emitting diode D4 emits light, and it can be easily recognized visually from the outside from a state indicating whether the light-emitting diode D4 emits light whether the specific abnormal phenomenon has occurred.

[0031] As described above, the IPM 2 according to the second preferred embodiment, like the IPM 1 according to the first preferred embodiment, can leave a history of whether the specific abnormal phenomenon has occurred from a state indicating whether the fuse 13 has been cut by the abnormality history operation of the abnormality history setting unit including the fuse 13, the resistor R2, and the transistor Q2.

[0032] In addition, in accordance with the second preferred embodiment, the IPM 2 further includes the fuse disconnection notification unit (the combination of the latch circuit 15, the transistor Q2, the resistor R3, the external terminal P4, and the light-emitting diode D4) that controls the emission of the light-emitting diode D4 in response to the indication (H level) of the occurrence of the abnormal phenomenon from the specific abnormality detection signal S14.

[0033] The fuse blow notification unit controls the emission of the light-emitting diode D4 based on whether the specific abnormality detection signal S14 has been latched at the H level by the latch circuit 15, that is, based on the content of the specific abnormality detection signal S14 indicating the occurrence of the specific abnormal phenomenon. Thus, the fuse blow notification unit can promptly alert in a visually recognizable manner that the fuse 13 has been blown due to the occurrence of the specific abnormal phenomenon. Third preferred embodiment

[0034] Fig. Fig. 3 is a schematic diagram of an anomaly output unit and an anomaly history setting unit of an IPM 3 and its peripherals in accordance with a third preferred embodiment of the invention. The same components as in Fig. 1 (the anomaly output unit, the anomaly detection circuit 14, the power supply 21, the photocoupler 22 and the external terminals P1 to P3, etc.) are designated by the same reference numerals and will not be described again.

[0035] The abnormality history setting unit in the IPM 3 includes, in addition to the fuse 13, the resistor R2 and the transistor Q2, which are the same as in the first preferred embodiment, a comparator 16 which outputs an IGBT turn-off signal SB1.

[0036] Specifically, a reference voltage Vref is applied to a positive input (+) of the comparator 16, and the other end (the collector of the transistor Q2) of the resistor R2 is connected to a negative input (-). The reference voltage Vref is set higher than the voltage (open-circuit voltage) at the other end of the resistor R2, which is in an open state when the fuse 13 is cut, and lower than the power supply voltage VD. Thus, the comparator 16 generally outputs the IGBT turn-off signal SB1 at the L level because the voltage at the other end of the resistor R2 is almost the power supply voltage VD. Although not shown, the comparator 16 uses the power supply voltage VD obtained from the external terminal P1 as an operating voltage.

[0037] The abnormality history setting unit thus configured according to the third preferred embodiment performs a similar abnormality history operation to the abnormality history setting unit according to the first preferred embodiment by using the state in which the specific abnormality detection signal S14 attains the H level during the occurrence of the specific abnormal phenomenon to be detected as a trigger. Accordingly, the abnormality history setting unit can cut off the fuse 13.

[0038] When fuse 13 is blown, the negative input of comparator 16 has an open-circuit voltage lower than the reference voltage Vref, causing IGBT turn-off signal SB1 to change from low to high. With IGBT turn-off signal SB1 at high level, turn-off control can be performed to turn off the respective semiconductor element.

[0039] Fig. 4 is an explanatory schematic diagram of a shutdown control system of the IGBT to be protected by the IGBT shutdown signal SB1. The IPM 3 includes a power supply unit 50 having an IGBT 56, which is a semiconductor element that performs a switching operation, and a control circuit 52 that controls the switching operation of the IGBT 56. Note that the IPM 1 and IPM 3, as well as the IPM 4 to IPM 10 described later, also include a structure corresponding to the power switching unit 50 and the control circuit 52.

[0040] As in Fig. 4, the control circuit 52 outputs a control signal S52 which forcibly turns off the IGBT 56 present in the power switching unit 50 in response to the IGBT turn-off signal SB1 at the H level. Fig. 4 illustrates the control circuit 52 as a circuit that also functions as a drive circuit.

[0041] As described above, the IPM 3 according to the third preferred embodiment, like the IPM 1 according to the first preferred embodiment, can leave a history of whether the specific abnormal phenomenon to be detected has occurred from a state indicating whether the fuse 13 has been cut by the abnormality history operation of the abnormality history setting unit including the fuse 13, the resistor R2, and the transistor Q2.

[0042] In addition, according to the third preferred embodiment, the abnormality history setting unit further includes the comparator 16 connected to the fuse 13 and outputting the IGBT switching signal SB at the H level instructing a shutdown setting for stopping the switching operation of the IGBT 56 when the fuse 13 is disconnected, as a shutdown instruction unit.

[0043] The control circuit 52 stops the switching operation of the IGBT 56 in response to the turn-off setting instruction H by the IGBT turn-off signal SB1.

[0044] As described above, the comparator 16, which is the shutdown instruction unit in the abnormality history setting unit, outputs the IGBT shutdown signal SB1 at the H level (disconnection instruction signal) that instructs the shutdown setting when the fuse 13 is disconnected, to safely prevent the IGBT 56 from performing the switching operation in the abnormal state in which the fuse 13 is disconnected, whereby the IPM 3 according to the third preferred embodiment can safely use the IGBT 56. Fourth Preferred Embodiment

[0045] Fig. 5 is a schematic diagram of an anomaly output unit and an anomaly history setting unit of an IPM 4 and its peripherals in accordance with a fourth preferred embodiment of the invention. The same components as in Fig. 1 (the anomaly output unit, the anomaly detection circuit 14, the power supply 21, the photocoupler 22 and the external terminals P1 to P3, etc.) are designated by the same reference numerals and will not be described again.

[0046] The abnormality history setting unit in the IPM 4 includes, in addition to the fuse 13, the resistor R2, and the transistor Q2, which are the same as in the first preferred embodiment, an external terminal P5 (an external fuse connection terminal) and a switch 23 (switch between the terminals) externally provided between the external terminals P1 and P5.

[0047] Switch 23 is implemented, for example, by a mechanical switch such as a DIP switch and can change the electrical connection between external terminals P1 and P5. In the IPM 4, fuse 13, resistor R2, and transistor Q2 are provided between external terminals P1 and P3 via switch 23 and external terminal P5.

[0048] Thus, the IPM 4 has an equivalent circuit structure as the one in Fig. 1 according to the first preferred embodiment when the switch 23 is closed (electrically connected). Specifically, the abnormality history setting unit performs a similar abnormality history operation to the abnormality history setting unit according to the first preferred embodiment by using the state in which the specific abnormality detection signal S14 becomes H upon occurrence of the abnormal phenomenon to be detected as a trigger, whereby the abnormality history setting unit can cut off the fuse 13 when the switch 23 is closed.

[0049] On the other hand, when the switch 23 is open (electrically open), the abnormal history setting unit assumes an electrically open state (groundless state), so the abnormal history operation is canceled. Thus, the abnormal history setting unit cannot break the fuse 13.

[0050] As described above, the IPM 4 according to the fourth preferred embodiment, like the IPM 1 according to the first preferred embodiment, can leave a history of whether the specific abnormal phenomenon to be detected has occurred from a state indicating whether the fuse 13 has been cut by the abnormality history operation of the abnormality history setting unit including the fuse 13, the resistor R2, and the transistor Q2 as main components.

[0051] Furthermore, in the IPM 4 according to the fourth preferred embodiment, the switch 23 can change the electrical connection between the external terminals P1 and P5 by being opened and closed, whereby the IPM 4 can be selectively set such that the abnormal history operation is valid or invalid by the abnormal history setting unit.

[0052] As a result, by canceling the abnormality history operation and intentionally generating a fault during the investigation of the IPM 4, the IPM 4 can relatively easily perform a test for verifying a protective function, thereby improving the usefulness of the device. Fifth Preferred Embodiment

[0053] Fig. Fig. 6 is a schematic diagram of an anomaly output unit and an anomaly history setting unit of an IPM 5 and its peripherals in accordance with a fifth preferred embodiment of the invention. The same components as in Fig. 1 (the anomaly output unit, the anomaly detection circuit 14, the power supply 21, the photocoupler 22 and the external terminals P1 to P3, etc.) are designated by the same reference numerals and will not be described again.

[0054] The abnormality history setting unit in the IPM 5 includes, in addition to the fuse 13, the resistor R2 and the transistor Q2 which are the same as in the first preferred embodiment, external terminals P6 and P7 (first and second external fuse disconnection detection terminals) and a resistor R11 externally provided between the external terminals P6 and P7.

[0055] As described above, the IPM 5 according to the fifth preferred embodiment, like the IPM 1 according to the first preferred embodiment, can leave a history of whether the specific abnormal phenomenon to be detected has occurred from a state indicating whether the fuse 13 has been cut by the abnormality history operation of the abnormality history setting unit including the fuse 13, the resistor R2, and the transistor Q2.

[0056] Furthermore, according to the fifth preferred embodiment, the IPM 5 can relatively easily detect from the outside whether the fuse 13 has been cut based on the state of the electrical connection (conduction state or open state) between the external terminals P6 and P7.

[0057] In addition, the IPM 5 can selectively set the anomaly history operation to be valid or invalid by controlling a shunt ratio of a current flowing through the resistor R11 and the fuse 13 according to the setting of the resistance value of the resistor R11 provided between the external terminals P6 and P7.

[0058] Specifically, the resistance value of resistor R11 is set sufficiently smaller than the combined resistance value of fuse 13 and resistor R2 to reduce the current flowing through fuse 13 when the abnormal phenomenon to be detected occurs to a level that prevents fuse 13 from being blown, thereby canceling the abnormal history operation by the abnormal history setting unit. In contrast, the abnormal history operation can be validated by the abnormal history setting unit by increasing the resistance value of resistor R11 more than the combined resistance value of fuse 13 and resistor R2. Sixth Preferred Embodiment

[0059] Fig. Fig. 7 is a schematic diagram of an anomaly output unit and an anomaly history setting unit of an IPM 6 and its peripherals in accordance with a sixth preferred embodiment of the invention. The same components as in Fig. 1 (the anomaly output unit, the power supply 21, the optocoupler 22 and the external terminals P1 to P3, etc.) are designated by the same reference numerals and will not be described again.

[0060] The IPM 6 takes countermeasures against three types (multiple types) of abnormal phenomena including an abnormal phenomenon of overtemperature, an abnormal phenomenon of short circuit, and an abnormal phenomenon of undervoltage, which are described in detail below.

[0061] The IPM 6 includes, as the abnormality history setting unit, a first abnormality history setting unit provided with a fuse 13A, a resistor R2A, an (NPN bipolar) transistor Q2A, and a latch circuit 15A, and a second abnormality history setting unit provided with a fuse 13B, a resistor R2B, an (NPN bipolar) transistor Q2B, and a latch circuit 15B.

[0062] In the first abnormality history setting unit, the fuse 13A, the resistor R2A, and the transistor Q2A are connected in series between the external terminals P1 and P3. Specifically, one end of the fuse 13A is connected to the external terminal P1, the other end is connected to one end of the resistor R2A, the other end of the resistor R2A is connected to a collector of the transistor Q2A, and an emitter of the transistor Q2A is connected to the external terminal P3 (ground voltage GND level). The output of the latch circuit 15A, which latches a specific abnormality detection signal S14A, is applied to a base of the transistor Q2A.

[0063] In the second abnormality history setting unit, the fuse 13B, the resistor R2B, and the transistor Q2B are connected in series between the external terminals P1 and P3. Specifically, one end of the fuse 13B is connected to the external terminal P1, the other end is connected to one end of the resistor R2B, the other end of the resistor R2B is connected to a collector of the transistor Q2B, and an emitter of the transistor Q2B is connected to the external terminal P3. An output of the latch circuit 15B, which latches a specific abnormality detection signal S14B, is applied to a base of the transistor Q2B.

[0064] When the specific abnormality detection signals S14A and S14B are received at the H level during the occurrence of the specific abnormality to be detected (the abnormality of overtemperature or the abnormality of short circuit), the latch circuits 15A and 15B, like the latch circuit 15 in the second preferred embodiment, perform a latch operation to hold these specific abnormality detection signals S14A and S14B and maintain the H state until a control power supply reset operation is performed. Although not shown, the latch circuits 15A and 15B use the power supply voltage VD obtained from the external terminal P1 as an operating voltage.

[0065] The transistor Q2A receives at its base, via the latch circuit 15A, the specific anomaly detection signal S14A from the anomaly detection circuit 14A. The anomaly detection circuit 14A receives a temperature detection signal S31 from an overtemperature detection circuit 31.

[0066] The temperature detection signal S31 is a detection signal for overtemperature protection (OT). If the temperature detected by a device near the IGBT 56 (see Fig. 4) provided temperature detection circuit (not shown) detects the temperature in the IPM 6 exceeds a reference temperature, the temperature detection signal S31 assumes the H state, indicating the occurrence of the abnormal phenomenon of overtemperature.

[0067] The anomaly detection circuit 14A performs a first anomaly detection operation to output the specific anomaly detection signal S14A at the H level, which turns on the transistor Q2A when the temperature detection signal S31 is at the H level, that is, when, among the three types of abnormal phenomena, the abnormal phenomenon of overtemperature occurs, which corresponds to a specific abnormal phenomenon to be detected, and to output the specific anomaly detection signal S14B at the L level, which turns off the transistor Q2A when the abnormal phenomenon of overtemperature does not occur.

[0068] Transistor Q2B receives at its base, via latch circuit 15B, the specific anomaly detection signal S14B from the anomaly detection circuit 14B. The anomaly detection circuit 14B receives a current detection signal S32 from a short-circuit detection circuit 32. The current detection signal S32 is a detection signal for short-circuit protection (SC). When a current at least equal to a reference current flows through the IGBT 56 due to a load short circuit, the current detection signal S32 assumes an H state, indicating the occurrence of the anomalous short-circuit phenomenon.

[0069] The anomaly detection circuit 14B performs a second anomaly detection operation to output the specific anomaly detection signal S14B at the H level, which turns on the transistor Q2B when the current detection signal S32 is at the H level, that is, when the anomalous phenomenon of a short circuit corresponding to a specific anomalous phenomenon to be detected occurs among three types of anomalous phenomena, and to output the specific anomaly detection signal S14B at the L level, which turns off the transistor Q2B when the anomalous phenomenon of a short circuit does not occur.

[0070] The base of transistor Q1 receives an anomaly detection signal SF from a general anomaly detection circuit 17. The general anomaly detection circuit 17 outputs the anomaly detection signal SF at the H / L level from the H / L level of a general detection signal S17 of an OR gate G17.

[0071] The OR gate G17 receives the temperature detection signal S31 at its first input, the current detection signal S32 at its second input, and a power supply detection signal S33 at its third input. The power supply detection signal S33 is a detection signal for power supply undervoltage protection (power supply UV protection). When the power supply voltage VD (more precisely, the potential difference between the power supply voltage VD and the ground potential GND) does not exceed a set value, the power supply detection signal S33 enters the "H" state, indicating the occurrence of an abnormal power supply undervoltage phenomenon.

[0072] Accordingly, the general abnormality detection circuit 17 outputs the abnormality detection signal SF at the H level when at least one of the detection signals S31 to S33 goes to the H level, that is, when at least one of the three types of abnormal phenomena, that is, the abnormal phenomenon of overtemperature, the abnormal phenomenon of short circuit, and the abnormal phenomenon of power supply undervoltage, occurs.

[0073] When the transistor Q1, which is the anomaly output unit, becomes on by the anomaly detection signal SF at the H level, the external terminal P2 (the anomaly output signal FO from the external terminal P2) is set to the L level, and the potential difference by which light can be emitted is generated between the anode and the cathode, whereby the light emitting diode D22 emits light with an intensity at least equal to the reference value as described in the first preferred embodiment.

[0074] When the transistor Q2A becomes on by latching the specific abnormality detection signal S14A at the H level, which indicates the occurrence of the abnormal phenomenon of overtemperature for the latch circuit 15A, the above-mentioned first abnormality history setting unit (the fuse 13A, the resistor R2A, the transistor Q2A, and the latch circuit 15A) performs a first abnormality history operation to electrically connect the external terminals P1 and P3 via the fuse 13A, the resistor R2A, and the transistor Q2A, and allow a current of a level exceeding a disconnection level to flow through the fuse 13A to disconnect the fuse 13A.

[0075] Similarly, the above-mentioned second abnormality history setting unit (the fuse 13B, the resistor R2B, the transistor Q2B, and the latch circuit 15B) performs a second abnormality history operation to electrically connect the external terminals P1 and P3 via the fuse 13B, the resistor R2B, and the transistor Q2B and allow a current of a level exceeding a disconnection level to flow through the fuse 13B to disconnect the fuse 13B when the transistor Q2B becomes on-state by latching the specific abnormality detection signal S14B at the H level indicating the occurrence of the abnormal phenomenon of a short circuit for the latch circuit 15B.

[0076] The latch circuits 15A and 15B function to ensure a period of time required for the safe disconnection of the fuses 13A and 13B, but the above-mentioned first and second abnormality history setting operations can be performed even by a configuration in which the specific abnormality detection signals S14A and S14B are directly applied to the bases of the transistors Q2A and Q2B without providing the latch circuits 15A and 15B.

[0077] As described above, in the IPM 6 according to the sixth preferred embodiment, the first and second abnormality history setting units independently perform the first and second abnormality history operations, thereby leaving histories indicating whether the abnormal phenomenon of overtemperature and the abnormal phenomenon of short circuit have occurred, so that these histories between the abnormal phenomenon of overtemperature and the abnormal phenomenon of short circuit can be identified from the state indicating whether the fuses 13A and 13B are disconnected. More specifically, by identifying the disconnection of the fuse 13A or the fuse 13B, it can be correctly recognized which of the two specific abnormal phenomena occurs in the IPM 6.

[0078] Whether the fuse 13A and the fuse 13B are disconnected can be relatively easily confirmed in the IPM 6 by providing a line check function of the fuses 13A and 13B for the control circuit (not shown) in the IPM 6.

[0079] As a result, the IPM 6 can immediately analyze and take appropriate measures for both the abnormal overtemperature and short circuit phenomena after they occur. Accordingly, using the IPM 6 with appropriate fault prevention measures can extend its service life.

[0080] Since the abnormality output unit (the transistor Q1 and the resistor R1) in the IPM 6 receives the abnormality detection signal SF generated by the abnormality detection circuit 17 based on the general detection signal S17 from the OR gate G17, it outputs an error output signal FO at the L level indicating the abnormal phenomenon from the external terminal P2 when at least one of the three types of abnormal phenomena (an abnormal phenomenon of overtemperature, an abnormal phenomenon of short circuit, and an abnormal phenomenon of power supply undervoltage) has occurred.

[0081] Accordingly, by detecting the error output signal FO at the L level from the external terminal P2, the IPM 6 can relatively easily detect the occurrence of any of several types of abnormal phenomena from the outside.

[0082] In the sixth preferred embodiment, two abnormality history setting units are provided. However, it should be noted that the IPM 6 according to the sixth preferred embodiment can be expanded to realize a configuration in which three or more abnormality history setting units are provided.

[0083] More specifically, the specific anomaly detection signal may include first to N-th specific anomaly detection signals detecting first to N-th (N ≥ 2) specific anomalous phenomena, the anomaly detection operation may include first to N-th anomaly detection operations, the backup may include first to N-th backup operations, and the anomaly history operation may include first to N-th anomaly history operations.

[0084] In this case, the anomaly detection circuit includes first to N-th anomaly detection circuits that perform first to N-th anomaly detection operations, outputting first to N-th anomaly detection signals indicating whether the first to N-th anomaly phenomena included in the plurality of types of anomalous phenomena occur.

[0085] The anomaly history setting unit includes first to Nth anomaly history setting units provided corresponding to the first to Nth anomaly detection circuits and including first to Nth fuses. When the first to Nth anomaly detection signals indicate the occurrence of the anomalous phenomenon, the first to Nth anomaly history setting units perform the first to Nth anomaly history operation to allow current to flow through the first to Nth fuses to disconnect these fuses. Seventh Preferred Embodiment

[0086] Fig. Fig. 8 is a schematic diagram of an anomaly output unit and an anomaly history setting unit of an IPM 7 and its peripherals in accordance with a seventh preferred embodiment of the invention. The same components as in Fig. 7 (the abnormality output unit, the abnormality detection circuits 14A and 14B, the latch circuits 15A and 15B, the general abnormality detection circuit 17, the OR gate G17, the power supply 21, the photocoupler 22, the overtemperature detection circuit 31, the short-circuit detection circuit 32, the undervoltage detection circuit 33, and the external terminals P1 to P3, etc.) are denoted by the same reference numerals and will not be described again.

[0087] A first abnormality history setting unit in the IPM 7 includes the fuse 13A, the resistor R2A, the transistor Q2A, and the latch circuit 15A, which are the same as in the sixth preferred embodiment. Furthermore, the IPM 7 includes a first fuse disconnection notification unit including an external terminal P4A (first fuse disconnection notification terminal) and a light-emitting diode D4A (LED; first light-emitting element) connected to the external terminal P4A, and a resistor R3A, the transistor Q2A, and the latch circuit 15A provided internally.

[0088] Similarly, a second abnormality history setting unit in the IPM 7 includes the fuse 13B, the resistor R2B, the transistor Q2B, and the latch circuit 15B, which are the same as in the sixth preferred embodiment. Furthermore, the IPM 7 includes a second fuse disconnection notification unit including an external terminal P4B (a second fuse disconnection notification terminal) and a light-emitting diode D4B (LED; second light-emitting element) connected to the external terminal P4B, and a resistor R3B, the transistor Q2B, and the latch circuit 15B provided internally.

[0089] The transistor Q2A and the latch circuit 15A are shared by the first abnormality history setting unit and the first fuse disconnection notification unit, and the transistor Q2B and the latch circuit 15B are shared by the second abnormality history setting unit and the second fuse disconnection notification unit.

[0090] More specifically, the anodes of the light-emitting diodes D4A and D4B are commonly connected to the positive electrode of the power supply 21, the cathodes are connected to the external terminals P4A and P4B, one end of each of the resistors R3A and R3B is connected to each of the external terminals P4A and P4B, and the other end of each of the resistors R3A and R3B is connected to the other end (a collector of the transistor Q2A and a collector of the transistor Q2B) of each of the resistors R2A and R2B.

[0091] The thus configured first abnormality history setting unit in the seventh preferred embodiment performs the same first abnormality history operation as the first abnormality history setting unit in the sixth preferred embodiment by using the state in which the specific abnormality detection signal S14A is latched at the H level upon occurrence of the abnormal phenomenon of overtemperature by the latch circuit 15A as a trigger, whereby the first abnormality history setting unit can cut off the fuse 13A.

[0092] In this case, since the H level of the specific abnormality detection signal S14A is latched by the latch circuit 15A, the current flows from the power supply 21 through the current path of the light-emitting diode D4A and the resistor R3A when and after the fuse 13A is cut off upon occurrence of the abnormal overtemperature phenomenon.

[0093] As a result, the light-emitting diode D4A emits light, which can communicate to the outside whether the abnormal phenomenon of overtemperature has occurred by visually detecting it from a state indicating whether the light-emitting diode D3A emits light.

[0094] Similarly, the second abnormality history setting unit performs the same second abnormality history operation as the second abnormality history setting unit in the sixth preferred embodiment by using the state in which the specific abnormality detection signal S14B is latched at the H level upon occurrence of the abnormal phenomenon of a short circuit by the latch circuit 15B as a trigger, whereby the second abnormality history setting unit can cut off the fuse 13B.

[0095] In this case, since the H level of the specific abnormality detection signal S14B is latched by the latch circuit 15B, the current flows from the power supply 21 through the current path of the light emitting diode D4B and the resistor R3B when and after the fuse 13B is cut off upon occurrence of the abnormal phenomenon of a short circuit.

[0096] As a result, the light-emitting diode D4B emits light, which can communicate to the outside whether the abnormal phenomenon of a short circuit has occurred by visually detecting it from the state indicating whether the light-emitting diode D4B emits light.

[0097] As described above, the IPM 7 according to the seventh preferred embodiment, like the IPM 6 according to the sixth preferred embodiment, can leave traces indicating whether the abnormal phenomenon to be detected has occurred, so that these traces can be identified between the abnormal phenomenon of overtemperature and the abnormal phenomenon of short circuit from a state indicating whether the fuses 13A and 13B have been cut off in accordance with the first and second abnormality trace operations by the first and second abnormality trace setting units including the fuses 13A and 13B, the resistors R2A and R2B, and the transistors Q2A and Q2B, respectively.

[0098] In addition, in accordance with the seventh preferred embodiment, the IPM 7 further includes the first and second fuse disconnection notification units (abnormal phenomenon notification units) that control the emission of the light emitting diodes D4A and D4B based on the content (H or L level) of the specific abnormality detection signals S14A and S14B indicating the occurrence of the abnormal phenomenon.

[0099] The first and second fuse-break notification units control the emission of the light-emitting diodes D4A and D4B based on the content of the specific abnormality detection signals S14A and S14B. Thus, the first and second fuse-break notification units can quickly inform an outsider (a user using the optocoupler 22 and the light-emitting diodes D4A and D4B) whether the fuses 13A and 13B have been blown due to the occurrence of an abnormal overtemperature phenomenon or an abnormal short circuit phenomenon. Eighth preferred embodiment

[0100] Fig. Fig. 9 is a schematic diagram of an anomaly output unit and an anomaly history setting unit of an IPM 8 and its peripherals in accordance with an eighth preferred embodiment of the invention. The same components as in Fig. 7 (the abnormality output unit, the first and second abnormality history setting units, the abnormality detection circuits 14A and 14B, the latch circuits 15A and 15B, the general abnormality detection circuit 17, the power supply 21, the photocoupler 22, and the external terminals P1 to P3, etc.) are designated by the same reference numerals and will not be described again.

[0101] The anomaly detection circuit 14A inputs a comparator detection signal S14A and outputs a specific anomaly detection signal S14A at the H / L level based on the H / L level of the comparator detection signal S14A.

[0102] The anomaly detection circuit 14B inputs a comparator detection signal S18B and outputs a specific anomaly detection signal S14B at the H / L level based on the H / L level of the comparator detection signal S18B.

[0103] Near the IGBT 56 (see Fig. 4) In the IPM 8, a temperature detection circuit 34 is provided which serves as a parameter detection circuit and which outputs a detected temperature signal S34 which indicates a voltage based on a detected temperature (a status parameter indicating the operating state of the IPM 8).

[0104] A comparator 18A receives a comparison voltage V175 (corresponding to the voltage when the detected temperature signal S34 indicates 175°C) at its negative input and the detected temperature signal S34 at its positive input. Based on the comparison result between the comparison voltage V175 and the detected temperature signal S34, it outputs the comparator detection signal S18A. Similarly, the comparator 18A outputs the comparator detection signal S18A at the H level when the detected temperature signal S34 indicates a temperature corresponding to 175°C, and the comparator detection signal S18A at the L level when this signal indicates a temperature lower than 175°C.

[0105] A comparator 18B receives a comparison voltage V150 (corresponding to a voltage when the detected temperature signal S34 indicates 150°C) at its negative input and the detected temperature signal S34 at its positive input. Based on the comparison result between the comparison voltage V150 and the detected temperature signal S34, it outputs the comparator detection signal S18B. Specifically, the comparator 18B outputs the comparator detection signal S18B at the H level when the detected temperature signal S34 indicates a temperature exceeding 150°C, and the comparator detection signal S18B at the L level when this signal indicates a temperature below 150°C.

[0106] As described above, the comparators 18A and 18B function as parameter classification units that output two parameter classification signals, ie, the comparator detection signals S18A and S18B, indicating whether two abnormal phenomena indicated by the detected temperature signal S34 classified on the basis of the detected temperature (in which the detected temperature is (exceeds) at least 150 °C and in which the detected temperature is (exceeds) at least 175 °C) have occurred.

[0107] The general anomaly detection circuit 17 sets the anomaly detection signal SF to the H / L level upon receiving the comparator detection signal S18B based on the H / L level of the comparator detection signal S18B. Accordingly, the anomaly output unit outputs the L-level error output signal FO from the external terminal P2 when the detected temperature signal S34 indicates that a temperature exceeds 150°C.

[0108] The thus-configured first abnormality history setting unit according to the eighth preferred embodiment of the invention performs a first abnormality history operation like the first abnormality history unit according to the sixth preferred embodiment by using the state in which the specific abnormality detection signal S14A transitions to the H level (and is latched by the latch circuit 15A) upon occurrence of the abnormal phenomenon of overtemperature, which is an overtemperature condition that exceeds 175°C with high significance, with the comparator detection signal S18A transitioning to the H level, as a trigger. Accordingly, the abnormality history setting unit can cut off the fuse 13A.

[0109] Similarly, the second abnormality history setting unit thus configured according to the eighth preferred embodiment of the invention performs a second abnormality history operation similarly to the second abnormality history setting unit according to the sixth preferred embodiment by using the state in which the specific abnormality detection signal S14B transitions to the H level upon occurrence of the abnormal phenomenon of overtemperature, that is, an overtemperature condition exceeding 150°C, with a medium significance with the comparator detection signal S18B transitioning to the H level as a trigger. Accordingly, the anomaly history setting unit can cut off the fuse 13B.

[0110] As described above, the IPM 8 according to the eighth preferred embodiment, like the IPM 6 according to the sixth preferred embodiment, can leave traces indicating whether the abnormal phenomenon of overtemperature has occurred and its level (significance) in such a way that these traces can be identified from a state indicating whether the fuses 13A and 13B have been disconnected in accordance with the first and second abnormality history operations by the first and second abnormality history setting units including the fuses 13A and 13B, the resistors R2A and R2B, and the transistors Q2A and Q2B, respectively, between the abnormal phenomenon of overtemperature with medium significance within a temperature range of 150°C to 175°C and the abnormal phenomenon of overtemperature with high significance with a temperature exceeding 175°C.

[0111] More specifically, the IPM 8 can identify that the abnormal phenomenon of overtemperature occurred with high significance when fuses 13A and 13B were both disconnected, that the abnormal phenomenon of overtemperature occurred with medium significance when only fuse 13B was disconnected, and that the abnormal phenomenon of overtemperature did not occur when neither fuse 13A nor fuse 13B was disconnected.

[0112] As described above, according to the eighth preferred embodiment, the IPM 8 can detect, from a state indicating whether the two fuses 13A and 13B are disconnected, the history of whether two abnormal overtemperature phenomena, each having a different temperature rise degree, have occurred, with each fuse corresponding to each of the abnormal overtemperature phenomena (at least two abnormal phenomena) with two levels (high significance and medium significance), which are classified based on the detected temperature indicated by the detected temperature signal S34, which is the common status parameter. As a result, the IPM 8 can promptly perform analysis after the occurrence of the abnormal overtemperature phenomenon with two levels and take action in accordance with the detected temperature level.Accordingly, the lifetime of the IPM 8 can be extended by using the IPM 8 with appropriate fault prevention measures. Ninth Preferred Embodiment

[0113] Fig. Fig. 10 is a schematic diagram of an abnormal phenomenon detection unit and an abnormality history setting unit of an IPM 9 and its peripherals in accordance with a ninth preferred embodiment of the invention. The same components as in Fig. 1 (the anomaly output unit, the power supply 21, the optocoupler 22 and the external terminals P1 to P3, etc.) are designated by the same reference numerals and will not be described again.

[0114] An anomaly history setting unit in the IPM 9 includes a fuse 19, a resistor R12A, an (NPN bipolar) transistor Q12A, and a latch circuit 25A, wherein the fuse 19, the resistor R12A, and the transistor Q12A are connected in series between the external terminal P1 and the external terminal P3.

[0115] Specifically, one end of fuse 19 is connected to external terminal P1, the other end is connected to one end of resistor R12A, the other end of resistor R12A is connected to a collector of transistor Q12A, and an emitter of transistor Q12A is connected to external terminal P3 (ground voltage level GND). An output from latch circuit 25A, which latches a specific anomaly detection signal S24A, is applied to a base of transistor Q12A.

[0116] The anomaly history setting unit further includes a comparator 16. A reference voltage Vref is applied to a positive input of the comparator 16, and the other end (the collector of the transistor Q12A) of the resistor R12A is connected to a negative input. The reference voltage Vref is set higher than the voltage (open-circuit voltage) at the other end of the resistor R12A, which is in an open state when the fuse 19 is blown, and lower than the power supply voltage VD. Thus, the comparator 16 generally outputs an IGBT turn-off signal SB1 at the L level when the fuse 19 is not blown.

[0117] In addition, the IPM 9 includes first to third abnormal phenomenon detection units serving as abnormal phenomenon detection units, each of which has no fuse.

[0118] The first abnormality detection unit includes a resistor R12B, an NPN bipolar transistor Q12B, a latch circuit 25B, an external terminal P14, and a light-emitting diode D5. The second abnormality detection unit includes a resistor R12C, an NPN bipolar transistor Q12C, and a latch circuit 25C.

[0119] In the first abnormality detection unit, the light-emitting diode D5 is provided between the external terminal P1 and the external terminal P14. Specifically, an anode of the light-emitting diode D5 is connected to the external terminal P1, and a cathode is connected to the external terminal P14. The resistor R12B and the transistor Q12B are connected in series between the external terminal P14 and the external terminal P3. Specifically, one end of the resistor R12B is connected to the external terminal P14, the other end of the resistor R12B is connected to the collector of the transistor Q12B, and the emitter of the transistor Q12B is connected to the external terminal P3. An output from the latch circuit 25B, which latches a specific abnormality detection signal S24B, is applied to the base of the transistor Q12B.

[0120] In the second anomaly detection unit, resistor R12C and transistor Q12C are connected in series between external terminals P2 and P3. Specifically, one end of resistor R12C is connected to external terminal P2, the other end of resistor R12C is connected to the collector of transistor Q12C, and the emitter of transistor Q12C is connected to external terminal P3. An output from latch circuit 25C, which latches a specific anomaly detection signal S24C, is applied to the base of transistor Q12C.

[0121] When the latch circuits 25A to 25C receive the specific abnormality detection signals S24A to S24C at the H level, they perform a latch operation, like the latch circuit 15 according to the second preferred embodiment, to hold these specific abnormality detection signals S24A to S24C and maintain the H state until a control power supply reset operation is performed. Although not shown, the latch circuits 25A to 25C use the power supply voltage VD received from the external terminal P1 as an operating voltage.

[0122] Resistor R1 and transistor Q1, provided between external terminals P2 and P3, are used as the third abnormality detection unit. The third abnormality detection unit has an equivalent configuration to the abnormality output unit described in the first preferred embodiment to the eighth preferred embodiment, but differs from it in that the abnormality detection signal SF (specific abnormality detection signal S24D) output from the abnormality detection circuit 24D is received by the base of transistor Q1.

[0123] The anomaly detection circuits 24A to 24D perform, based on the H / L level of the comparator detection signals S18A to S18D, first to fourth anomaly detection operations for outputting comparator detection signals S18A to S18D and for outputting a specific anomaly detection signal S24A to S24D at the H / L level.

[0124] The anomaly detection circuit 24B outputs an IGBT turn-off signal SB2 at the H level, which indicates the turn-off setting of the IGBT 56, together with the specific anomaly detection signal S24B at the H level (see Fig. 4). Similarly, the anomaly detection circuit 24C outputs an IGBT turn-off signal SB3 (see Fig. 4) at the H level, which indicates the turn-off setting of the IGBT 56, together with the signal S24C of the detection of a specific anomaly at the H level (see Fig. 4).

[0125] The temperature detection circuit 34 is provided near the IGBT 56 of the IPM 8 and outputs a detected temperature signal S34 indicating a voltage based on the detected temperature, as in the eighth preferred embodiment.

[0126] A comparator 18A receives at its negative input a comparison voltage V175 (a corresponding voltage when the detected temperature signal S34 indicates 175 °C) and at its positive input the detected temperature signal S34 and outputs the comparator detection signal S18A based on the comparison result between the comparison voltage V175 and the detected temperature signal S34.

[0127] A comparator 18B receives at its negative input a comparison voltage V150 (a corresponding voltage when the detected temperature signal S34 indicates 150 °C) and at its positive input the detected temperature signal S34, and outputs the comparator detection signal S18B based on the comparison result between the comparison voltage V150 and the detected temperature signal S34.

[0128] A comparator 18C receives at its negative input a comparison voltage V135 (a corresponding voltage when the detected temperature signal S34 indicates 135 °C) and at its positive input the detected temperature signal S34 and outputs the comparator detection signal S18C based on the comparison result between the comparison voltage V135 and the detected temperature signal S34.

[0129] A comparator 18D receives at its negative input a comparison voltage V100 (a corresponding voltage when the detected temperature signal S34 indicates 100 °C) and at its positive input the detected temperature signal S34, and outputs the comparator detection signal S18D based on the comparison result between the comparison voltage V100 and the detected temperature signal S34.

[0130] Accordingly, the anomaly detection circuit 24A serves as a significant anomaly detection circuit that performs a first anomaly detection operation for the significant anomalous phenomenon with the highest degree of abnormality in the overtemperature abnormal phenomenon, in which the detected temperature corresponds to 175°C. The second to fourth anomaly detection operations by the anomaly detection circuits 24B to 24D are the second, third, and fourth detection operations in descending order of the degree of anomaly.

[0131] Fig. 11 is an explanatory view of the anomaly history operation, the first to third anomaly detection operations, and termination conditions in the IPM 9 according to the ninth preferred embodiment in the form of a table.

[0132] First, the third anomaly detection operation (anomaly output operation) by the anomaly output unit (resistor R1 and transistor Q1), that is, the third anomaly detection unit, is described. When the detected temperature signal S34 output from the temperature detection circuit 34 indicates the state of "at least 100°C (over 100°C)", the third anomaly detection unit performs the third anomaly detection operation, which corresponds to an "alarm" mode.

[0133] Specifically, during the period (fault period) in which the anomaly detection signal SF (the specific anomaly detection signal S24D) transitions to the H level, the third anomaly detection unit performs the third anomaly detection operation to set the fault output signal FO to the L level. Accordingly, in the "alarm" mode, the IGBT 56 is not turned off, the light-emitting diode D5 does not emit light, and the fuse 19 is not blown.

[0134] Comparator 18D has a hysteresis function. When the detected temperature signal S34 falls below a reset level (e.g., approximately 70°C), that is, when the temperature falls below the detected temperature of 100°C by a predetermined hysteresis temperature (e.g., approximately 30°C) after the comparator detection signal S18D changes to high, the comparator detection signal S18D changes from high to low. As a result, the anomaly detection signal SF (S24D) falls to low, and the fault output signal FO changes from low to open, canceling the alarm mode.

[0135] The second abnormality detection operation by the second abnormality detection unit (resistor R12C, transistor Q12C, and latch circuit 25C) is described below. The second abnormality detection unit performs the second abnormality detection operation corresponding to a "risk level: low" mode when the detected temperature signal S34 indicates the state of "at least 135°C (over 135°C)."

[0136] More specifically, the second abnormality detection unit outputs an IGBT turn-off signal SB3 at the H level to turn off the IGBT 56 via the control circuit 52 (see Fig. 4) and always outputs the abnormality detection signal SF at the L level from the latch circuit 25C. In the "risk level: low" mode, the light-emitting diode D5 does not emit light, and the fuse 19 is not cut off.

[0137] Comparator 18C has a hysteresis function. When temperature detection signal S34 falls below a reset level (e.g., approximately 115°C), that is, when the temperature falls below the detected temperature of 135°C by a predetermined hysteresis temperature (e.g., approximately 20°C) after comparator detection signal S18C changes to high, comparator detection signal S18C changes to low. This causes specific abnormality detection signal S24C and IGBT shutdown signal SB3 to fall to low levels, aborting the shutdown setting of IGBT 56.

[0138] Since the specific abnormality detection signal S24 is latched at the H level by the latch circuit 25C, the state in which the error output signal FO is always output at the L level is maintained until the control power supply reset operation is executed. In other words, to cancel the state in which the error output signal FO is always output, the control power supply reset operation must be executed.

[0139] The first abnormality detection operation by the first abnormality detection unit (resistor R12B, transistor Q12B, latch circuit 25B, light-emitting diode D5, and external terminal P14) is described below. The first abnormality detection unit performs the first abnormality detection operation corresponding to a "risk level: medium" mode when the detected temperature signal S34 indicates the state of "at least 150°C (over 150°C)."

[0140] More specifically, the first abnormality detection unit outputs an IGBT shutdown signal SB2 at the H level to turn off the IGBT 56 via the control circuit 52 (see Fig. 4) and turns on transistor Q12B to allow light-emitting diode D5 to emit light. In this case, the latch circuit 25C in the second abnormality detection unit always outputs the low-level error output signal FO. However, the fuse 19 is not blown.

[0141] To cancel the shutdown of the IGBT 56, the state in which the fault output signal FO is always output, and the emission of the light-emitting diode D5 after the operation mode has changed to “Risk level: medium”, the above-mentioned control reset operation must be performed.

[0142] The following describes the abnormal history operation by the abnormal history setting unit (fuse 19, resistor R12A, transistor Q12A, latch circuit 25A, and comparator 16). The abnormal history setting unit performs the abnormal history operation corresponding to the "fatal" mode with high significance when the detected temperature signal S34 indicates the state of "at least 175°C (over 175°C)."

[0143] More specifically, the anomaly history setting unit outputs the IGBT turn-off signal SB1 at the H level from the comparator 16 to turn off the IGBT 56 via the control circuit 52 (see Fig. 4) and turns on the transistor Q12A to allow a current above the cutoff level to flow through the fuse 19 to cut off the fuse 19. In this case, the light-emitting diode D5 emits light, and the error output signal FO at the L level is always output by the first and second abnormality detection units.

[0144] In order to cancel the turning off of the IGBT 56, the state in which the fault output signal FO is always output, the emission of the light emitting diode D5 and the disconnection of the fuse 19, the above-mentioned control reset operation must be performed after the fuse 19 is replaced.

[0145] The IGBT shutdown signal SB1 is input to each of the first, second, and third abnormality detection units. The first to third abnormality detection units perform the first to third abnormality detection operations to maintain the corresponding operation mode (the "alarm" mode, the "low risk" mode, and the "medium risk" mode) while the IGBT shutdown signal SB1 is at the H level. Specifically, when a significant abnormality indicating that the "fatal" mode is occurring occurs, the first to third abnormality detection operations by the first to third abnormality detection units continue even after the control power supply reset operation is performed, until the blown fuse 19 is replaced.

[0146] The IPM 9 according to the ninth preferred embodiment can detect whether the abnormal phenomenon of fatal overtemperature (significant abnormal phenomenon) has occurred from a state indicating whether the fuse 19 has been cut by the abnormal history operation by the abnormal history setting unit.

[0147] In addition, since a plurality of detections (emission of the light-emitting diode D5, the state of the output of the error output signal FO at the L level at all times or in a certain period of time) are possible externally by a first to third history detection operation by the first to third abnormal phenomenon detection units, it is possible to detect whether the abnormal phenomenon of overtemperature has occurred by classifying the abnormal phenomenon of overtemperature using the detection degree (alarm, significance: low, significance: high) in accordance with the temperature rise.

[0148] This point will be described in detail. When the abnormal phenomenon of overtemperature occurs, the temperature rise gradient of a chip temperature of the IGBT 56 is different, so the maximum temperature achieved is different during a detection delay or during a drop until measurement, such as until the IGBT 56 is turned off. The IPM 9 according to the ninth preferred embodiment includes four comparators 18A to 18D, each having a different determination level, and the abnormality history setting unit and the first to third abnormal phenomenon detection units are provided for each of the comparators 18A to 18D. Accordingly, the IPM 9 can take various measures including turning off the IGBT 56, outputting the fault output signal FO, emitting the light-emitting diode D5, and disconnecting the fuse 19.

[0149] As a result, the IPM 9 can immediately analyze the abnormal phenomenon, which typically involves a temperature rise problem, and take appropriate measures based on its significance. Accordingly, the service life of the IPM 9 can be extended by using the IPM 9 with appropriate fault prevention measures.

[0150] The IPM 9 securely prevents the IGBT 56 from performing the switching operation during the abnormal state in which the fuse 19 has been cut off by the IGBT shutdown signal SB1 (shutdown instruction signal) whose H level instructs the shutdown setting from the comparator 16, which is the shutdown instruction unit in the abnormal history setting unit, whereby the IGBT 56 can be safely used.

[0151] In addition, the first to third abnormal phenomenon detection units perform the first to third abnormality detection operations while the IGBT shutdown signal SB1 is at the H level, whereby the IPM 9 can greatly advance the replacement of the disconnected fuse 19 even after the control power supply reset operation is performed after the occurrence of the significant abnormal phenomenon indicating the "fatal" mode. Tenth Preferred Embodiment

[0152] Fig. Fig. 12 is a schematic diagram of an anomaly output unit and an anomaly history setting unit of an IPM 10 and its peripherals in accordance with a tenth preferred embodiment of the invention. The same components as in Fig. 7 (the anomaly output unit, the first and second anomaly history setting units, the anomaly detection circuits 14A and 14B, the latch circuits 15A and 15B, the power supply 21, the photocoupler 22, and the external terminals P1 to P3, etc.) are designated by the same reference numerals and will not be described again.

[0153] A counter detection signal S44 is input to the anomaly detection circuit 14A, and a specific anomaly detection signal S14A at the H / L level is output therefrom based on the H / L level of the counter detection signal S44.

[0154] A comparator detection signal S43 is input to the anomaly detection circuit 14B, and a specific anomaly detection signal S14B at the H / L level is output therefrom based on the H / L level of the comparator detection signal S43.

[0155] A current detection circuit 35 detects a collector current Ic of the IGBT 56 (see Fig. 4) in the IPM 10 and outputs a detected current signal S35 indicating a voltage value based on the detected collector current Ic.

[0156] A comparator 42 receives a comparison voltage V2 (a corresponding voltage when the detected current signal S35 indicates a current twice the rated current) at its negative input and the detected current signal S35 at its positive input. Based on the comparison result between the comparison voltage V2 and the detected current signal S35, it outputs a comparator detection signal S42. Specifically, the comparator 42 outputs the comparator detection signal S42, which transitions to the H level when the detected current signal S35 indicates that the collector current Ic (the magnitude of the collector current Ic) exceeds twice the current, and which transitions to the L level when the detected current signal S35 indicates that the collector current Ic is less than twice the current.

[0157] A counter circuit 44 counts the number of times the comparator detection signal S42 transitions to the high level (with an initial value of 0) and outputs a high-level counter detection signal S44 when the counter value reaches a set value. Specifically, the comparator 42 first outputs the high-level counter detection signal S44 when the detected current signal S35 indicates that the collector current Ic exceeds twice the current in multiples of the set value.

[0158] A comparator 43 receives a comparison voltage V3 (a corresponding voltage when the detected current signal S35 indicates a current three times the rated current) at its negative input and the detected current signal S35 at its positive input. Based on the comparison result between the comparison voltage V3 and the detected current signal S35, it outputs a comparator detection signal S43. Specifically, the comparator 43 outputs the comparator detection signal S43, which transitions to the H level when the detected current signal S35 indicates that the collector current Ic exceeds three times the rated current, and which transitions to the L level when the detected current signal S35 indicates that the collector current Ic is less than three times the rated current.

[0159] As described above, the comparators 42, 43 and the counter circuit 44 function as a parameter classification unit that classifies two abnormal phenomena (the phenomenon in which twice the rated current is generated as many times as the set value and the phenomenon in which three times the rated current is generated once) based not only on the current magnitude of the collector current Ic, which is the status parameter, but also on the number of times it occurs, and outputs two parameter classification signals as the comparator detection signal S43 and the counter detection signal S44.

[0160] An OR gate G20 receives the counter detection signal S44 at one input and the comparator detection signal S43 at the other input, and outputs a logical OR signal of the counter detection signal S44 and the comparator detection signal S43 as a general detection signal S20.

[0161] A general abnormality detection circuit 20 outputs the abnormality detection signal SF at the H / L level based on the H / L level of the general detection signal S20. Accordingly, the abnormality output unit outputs the error output signal FO at the L level from the external terminal P2 when the detected current signal S35 indicates that the collector current Ic exceeds twice the target current, or when the detected current signal S35 indicates that the collector current Ic exceeds three times the target current.

[0162] In addition, when the anomaly detection signal SF is output at the H level, the general anomaly detection circuit 20 outputs an IGBT turn-off signal SB20 at the H level, which instructs the turn-off setting of the IGBT 56. The IGBT turn-off signal SB20 is a signal corresponding to the IGBT turn-off signals SB1 to SB3 described above. Thus, the IGBT 56 can be turned off via the control circuit 52 by the IGBT turn-off signal SB20 at the H level.

[0163] The thus-configured first abnormality history setting unit according to the tenth preferred embodiment performs a similar first abnormality history operation to the first abnormality history setting unit according to the sixth preferred embodiment by using as a trigger a state in which the specific abnormality detection signal S14A transitions to the H level when the abnormal phenomenon of a first-type short circuit occurs, in which the counter detection signal S44 transitions to the H level, and the state in which the collector current Ic exceeds twice the current the target number of times. Accordingly, the fuse 13A can be cut off.

[0164] Similarly, the second abnormality history unit thus configured according to the tenth preferred embodiment performs a similar second abnormality history operation to the second abnormality history setting unit according to the sixth preferred embodiment by using a state in which the specific abnormality detection signal S14B transitions to the H level when the abnormal phenomenon of a second type short circuit occurs, in which the comparator detection signal S43 transitions to the H level, and the state in which the collector current Ic exceeds three times the current occurs, as a trigger. Accordingly, the fuse 13B can be cut off.

[0165] As described above, the IPM 10 according to the tenth preferred embodiment, like the IPM 6 according to the sixth preferred embodiment, can leave traces indicating whether the abnormal phenomenon of a short circuit has occurred and its abnormality type, such that these traces can be identified from a state indicating whether the fuses 13A and 13B have been disconnected in accordance with the first and second abnormality history operations by the first and second abnormality history setting units including the fuses 13A and 13B, the resistors R2A and R2B, and the transistors Q2A and Q2B, respectively, between the case where the abnormal phenomenon of the short circuit is the first type and the case where the abnormal phenomenon of the short circuit is the second type.

[0166] More specifically, the IPM 10 can identify that the abnormal phenomenon of a first type short circuit occurred when the fuse 13A was disconnected, that the abnormal phenomenon of a second type short circuit occurred when the fuse 13B was disconnected, and that the abnormal phenomenon of a short circuit did not occur when neither the fuse 13A nor the fuse 13B was disconnected.

[0167] As described above, the IPM 10 according to the tenth preferred embodiment can detect, from a state indicating whether the two fuses 13A and 13B have been cut off, the history of whether the two abnormal phenomena of short circuit each having a different current increase degree have occurred, each fuse corresponding to each of the two types of abnormal phenomenon of short circuit classified based on the current magnitude of the collector current Ic indicated by the detected current signal S35 which is the status parameter.

[0168] More specifically, the IPM 10 can detect, from a state indicating whether the fuses 13A and 13B are disconnected, the history of whether each of the two abnormal phenomena of a short circuit, each having a different degree of abnormality, has occurred, including the number of times the common collector current Ic has occurred, where each fuse corresponds to each of two types of abnormal phenomena of a short circuit, which are classified based on the current magnitude and the number of times the collector current Ic has occurred, which is the status parameter.

[0169] This point will be described in detail below. If the criterion for the abnormal occurrence of a short circuit is only one (e.g., the criterion in which three times the current is defined as an SC level (short-circuit anomaly)), the IGBT 56 will not be turned off under the condition that the collector current does not reach three times the current in a short time, resulting in the short circuit (the short circuit with a level exceeding twice the current) being likely to occur repeatedly. However, the repeated short circuit with a low peak current (exceeding twice the current but not three times the current) can also be protected from if the first and second anomaly history setting units are provided as in the IPM 10 according to the tenth preferred embodiment.As a result, the IPM 10 can correctly detect which type of anomalous phenomenon of a short circuit (single occurrence of a high current (triple current) or repeated occurrence of a low current (between double current and triple current) has occurred.

[0170] As described above, according to the tenth preferred embodiment, the IPM 10 can turn off the IGBT 56 to protect it, and can output the fault output signal FO indicating the occurrence of the abnormality when the peak current is not less than twice the rated value but less than three times the rated value while the short circuit occurs multiple times (as many times as the target number), as well as when the peak current is not less than three times the rated value during the short circuit. As a result, the IPM 10 can perform analysis and take measures according to the type of short-circuit abnormality. Accordingly, the service life of the IPM 10 can be extended by using the IPM 10 with appropriate fault prevention measures.

[0171] Since the abnormality output unit (the transistor Q1 and the resistor R1) of the IPM 10 receives the abnormality detection signal SF generated by the general abnormality detection circuit 20 based on the general detection signal S20 from the OR gate G20, it outputs the error output signal FO at the L level indicating the abnormal phenomenon from the external terminal P2 when at least one of the two types of abnormal short-circuit phenomena has occurred.

[0172] Accordingly, by detecting the error output signal FO at the L level from the external terminal P2, it can be relatively easily recognized externally which type of the abnormal phenomenon of a first-type short circuit or an abnormal phenomenon of a second-type short circuit has occurred.

Claims

[1] Semiconductor device comprising: a first external power supply terminal (P1) to which a power supply voltage (VD) is applied; a second external power supply terminal (P3) which is set to a reference potential (GND); an anomaly detection circuit (14, 14A, 14B, 24A to 24D) that performs an anomaly detection operation to output a specific anomaly detection signal (S14, S14A, S14B, S14A to S14D) indicating whether a specific anomaly phenomenon to be detected occurs; and an anomaly history setting unit (13, Q2, R2) including a fuse (13, 13A, 13B, 19) provided between the first and second external power supply terminals and performing an anomaly history operation to allow current to flow through the fuse to disconnect the fuse when the specific anomaly detection signal indicates the occurrence of the specific anomalous phenomenon, wherein the semiconductor device is capable of continuing to operate after the anomaly history setting unit (13, Q2, R2) has performed the anomaly history operation. [2] A semiconductor device according to claim 1, further comprising: a fuse disconnection notification unit (P4, D4, Q2, R3) including a fuse disconnection notification terminal (P4) and a light emitting element (D4) provided externally and electrically connected to the fuse disconnection notification terminal; wherein the fuse disconnection notification unit controls emission of the light emitting element based on a content of the specific abnormality detection signal indicating occurrence of the specific abnormal phenomenon. [3] A semiconductor device according to claim 1 or 2, further comprising: a switching unit (50) containing a semiconductor element (56) that performs a switching operation; and a control circuit (52) which controls the switching operation of the semiconductor element, wherein the anomaly history setting unit includes a shutdown instruction unit (16) connected to the fuse and outputting a shutdown instruction signal (SB1) instructing a shutdown setting for stopping the switching operation of the semiconductor element when the fuse is disconnected, and the control circuit stops the switching operation of the semiconductor element in response to the instruction of the shutdown setting from the shutdown instruction signal. [4] A semiconductor device according to any one of claims 1 to 3, further comprising: an external fuse connection terminal (P5) electrically connected to one end of the fuse; and a switch (23) between terminals provided outside and switching to electrically connect or disconnect the first external power supply terminal and the external fuse connection terminal, wherein the fuse is provided between the first and second external power supply terminals via the switch between the terminals. [5] A semiconductor device according to any one of claims 1 to 4, comprising: a first external fuse break detection terminal (P6) electrically connected to one end of the fuse; and a second external fuse break detection terminal (P7) electrically connected to the other end of the fuse. [6] A semiconductor device according to claim 1, wherein the specific anomalous phenomenon contains several types of anomalous phenomena (OE, SC, UV), the specific anomaly detection signal includes a first to N-th (N ≥ 2) specific anomaly detection signal, wherein the anomaly detection operation includes a first to N-th anomaly detection operation, wherein the backup includes a first to N-th backup, and wherein the anomaly history operation includes a first to N-th anomaly history operation, wherein the anomaly detection circuit includes first to N-th anomaly detection circuits (14A, 14B) that perform the first to N-th anomaly detection operation to output the first to N-th specific anomaly detection signal (S14A, S14B) indicating whether the first to N-th anomalous phenomenon (OE, SC) included in the plurality of types of anomalous phenomena occurs, the anomaly history setting unit is provided corresponding to each of the first to N-th anomaly detection circuits and includes a first to N-th anomaly history setting unit (14A, 15A, Q2A, R2A, 14B, 15B, Q2B, R2B) with the first to N-th fuses (13A, 13B), and the first to N-th anomaly history setting unit performs the first to N-th anomaly history operation to allow a current to flow across the first to N-th fuse to disconnect the first to N-th fuse when the first to N-th specific anomaly detection signal indicates the occurrence of the anomalous phenomenon. [7] A semiconductor device according to claim 6, further comprising: a first to N-th unit (15A, Q2A, R3A, 15B, Q2B, R3B) for notifying an abnormal phenomenon, which includes a first to N-th fuse-disconnection notification terminal (P4A, P4B) and a first to N-th light-emitting element (D4A, D4B) which are provided outside corresponding to the first to N-th fuse-disconnection notification terminal and are electrically connected to the first to N-th fuse-disconnection notification terminal, wherein the first to N-th abnormal phenomenon notification units control emission of the first to N-th light emitting elements based on a content of the first to N-th specific abnormality detection signals indicating occurrence of an abnormal phenomenon. [8] A semiconductor device according to claim 6 or 7, further comprising: a parameter detection circuit (34, 35) that detects a status parameter indicating an operating state of the semiconductor device; and a parameter classification unit (18A, 18B, 42, 43) which outputs at least two parameter classification signals (S18A, S18B, S42, S43) indicating whether at least two abnormal phenomena classified on the basis of a value of the status parameter occur, wherein at least two anomaly detection circuits among the first to N-th anomaly detection circuits perform the corresponding anomaly detection operation among the first to N-th anomaly detection operation based on the at least two parameter classification signals. [9] The semiconductor device according to claim 8, wherein the parameter classification unit (42-44) classifies the at least two abnormal phenomena based not only on the value of the status parameter but also on the number of times they have occurred and the outputs of the at least two parameter classification signals. [10] A semiconductor device according to any one of claims 6 to 9, further comprising: an external detection port (P2); and an anomaly output unit (Q1, R1, 17, G17) that outputs an anomaly output signal (FO) indicating an occurrence of an abnormal phenomenon from the external detection terminal upon occurrence of at least one of the plurality of types of abnormal phenomena. [11] A semiconductor device according to claim 1, wherein the specific abnormal phenomenon includes several types of abnormal phenomena classified on the basis of a degree of abnormality relative to a common abnormal phenomenon, the anomaly detection circuit includes a plurality of anomaly detection circuits (24A-24D), each of which is provided corresponding to each of the plurality of types of anomalous phenomena, the anomaly detection circuits performing the anomaly detection operation to output a plurality of specific anomaly detection signals (S24A-S24D) indicating whether the plurality of types of anomalous phenomena have occurred as the specific anomaly detection signals, and the anomaly history setting unit (19, Q12A-Q12C, R12A-R12C) is provided corresponding to a significant anomaly detection circuit (24A) which performs the anomaly detection operation for a significant anomalous phenomenon having the highest degree of anomaly among the plurality of anomaly detection circuits, the semiconductor device further comprises at least one abnormal phenomenon detection unit (25B, Q12B, R12B and 25C, Q12C, R12C) provided corresponding to at least one of the plurality of abnormality detection circuits (14B) other than the significant abnormality detection circuit, and performing an abnormality detection operation that can be externally detected when the corresponding specific abnormality detection signal indicates the occurrence of the abnormal phenomenon. [12] A semiconductor device according to claim 11, further comprising: a switching unit (50) having a semiconductor element (56) that performs a switching operation; and a control circuit (52) which controls the switching operation of the semiconductor element, wherein the anomaly history setting unit includes a shutdown instruction unit (16) which is connected to the fuse and which, upon disconnection of the fuse, outputs a shutdown instruction signal (SB1) which instructs a shutdown setting for stopping the switching operation of the semiconductor element, and the at least one abnormal phenomenon detection unit performs the abnormality detection operation during a period in which the shutdown instruction signal instructs the shutdown setting.

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