Method for selecting turn-off speeds for turn-off processes in power semiconductors as well as computing unit, computer program, computer program product, control device, converter and electric or hybrid vehicle

Abstract

Method for temperature-dependent selection (AW) of turn-off speeds (ASG) for turn-off processes (AV) in power semiconductors (5) which are arranged on a DC voltage intermediate circuit (2) of a converter (6), wherein - a direct voltage (V DC ) of the DC voltage intermediate circuit (2) by means of a voltage source connected to a positive DC voltage potential (DC + ) of the DC link (2) and a negative DC potential (DC - ) of the DC voltage intermediate circuit (2), by a first comparison (VG1) with a reference DC voltage (V DC_ref .) and a DC voltage comparison result (RES VDC ) is provided, - a temperature (T) of at least one of the power semiconductors (5) is detected by means of a temperature detection (4), by a second comparison (VG2) with a reference temperature (T ref.) and a temperature comparison result (RES T ) is provided, - depending on the combination possibilities (KBM) of the DC voltage comparison result (RES VDC ) with the temperature comparison result (RES T ) the selection (AW) of a cut-off speed (ASG) from a number of cut-off speeds (ASG) is made and a newly determined cut-off speed (ASG new ) is provided and - by a third comparison (VG3) the newly determined shutdown speed (ASG new ) with a previous shutdown speed (ASG old ) and a shutdown speed comparison result (RES ASG ) is provided, by which, in case of a discrepancy between the newly determined cut-off speed (ASG new ) and previous shutdown speed (ASG old), a switchover (UM) to the newly determined cut-off speed (ASG new ) is triggered.

Description

[0001] The invention relates to a method for selecting turn-off speeds for turn-off processes in power semiconductors, a computing unit and a control device for carrying out the method, a converter with power semiconductors arranged on its DC voltage intermediate circuit and an electric or hybrid vehicle with an electric machine driven by the converter.

[0002] The electrical power loss in converters, which are suitable for use in electric or hybrid vehicles, for example, to operate electrical machines, is primarily generated or determined by their power semiconductors or power semiconductor modules. In addition to the type of power semiconductor used, often IGBTs (Insulated Gate Bipolar Transistors), the gate control method has a decisive influence on the level of electrical power loss and thus on the efficiency of the converter. A closer look at the switching behavior of power semiconductors shows that a comparatively long duration of the respective turn-off processes in power semiconductors can often also generate an undesirably high proportion of the electrical losses during the switching processes of power semiconductors.

[0003] During the turn-off process, the collector current of the conducting semiconductor, which flows through it in the conducting state, is reduced depending on its current gradient, which is determined by the derivative dI c / dt of the collector current I cafter time t, is reduced until it reaches a value close to zero. A small leakage current of the collector current may continue to flow. The rate of rise of the collector current, i.e. the steepness of the edge of the collector current, also serves as a placeholder for the turn-off speed, which determines the duration of the turn-off process for the power semiconductor. It can be controlled via the gate control of the power semiconductor. Depending on the turn-off speed, the collector-emitter voltage rises above the DC voltage applied to the DC link, depending on an inductance L present in the DC voltage circuit (also known as the inductance of the commutation circuit), whereby the resulting collector-emitter turn-off overvoltage ΔV CE according to the following formula: ΔVCE=L∗dIC / dt.

[0004] For power semiconductors, especially IGBTs, manufacturers specify a maximum blocking collector-emitter voltage, which, if exceeded, is expected to destroy the power semiconductor. This maximum blocking collector-emitter voltage, often referred to as the nominal blocking voltage, is usually specified in the manufacturer's data sheet at a junction temperature of the power semiconductor of +25°C. In the following, the junction temperature of power semiconductors is mainly referred to as the temperature of the power semiconductors or the temperature at the power semiconductors. The power semiconductor must therefore be used and operated in such a way that a DC voltage V occurring at the DC intermediate circuit DC , which during the turn-off process of the power semiconductor is still connected to the collector-emitter turn-off overvoltage ΔV CEis applied, does not exceed the maximum blocking collector-emitter voltage V CES exceeds, which is described by the following formula: VCES>VDC+ΔVCE.

[0005] Accordingly, the rate of rise of the collector current during operation of the power semiconductors should, if necessary, be limited with regard to the respective DC voltage value at the DC link in order to comply with the indicated condition for the turn-off of the power semiconductor. This condition therefore has a significant influence on the duration of the turn-off processes of power semiconductors for many of their applications.

[0006] To date, a robust design of the power semiconductor has been carried out in such a way that the maximum collector-emitter voltage occurring at the power semiconductor must be maintained for a switch-off process at maximum DC voltage at the DC link and at maximum current (i.e. also collector current through the power semiconductor), the maximum blocking collector-emitter voltage specified by the manufacturer.

[0007] For IGBTs operated on a higher voltage DC link, the maximum blocking collector-emitter voltage V CES for example, 650V at an ambient temperature of +25°C.

[0008] If such power semiconductors are planned for use in converters for driving electric or hybrid vehicles, for example, the power semiconductor must usually also be designed for negative temperatures. According to manufacturer specifications, the maximum blocking collector-emitter voltage is only 605V at a temperature of -40°C, for example. This now reduced maximum blocking collector-emitter voltage, which applies to low temperatures at the edge of the power semiconductor's operational capability, is generally specified across the entire temperature range for each application.

[0009] EP 2 733 849 A1 discloses a method for operating an IGBT coupled to a power source via an intermediate circuit. Turning off the IGBT at a corresponding turn-off speed is characterized by detecting a voltage in the intermediate circuit and controlling the turn-off speed as a function of the voltage. Furthermore, a control device is proposed, which has a detection device for detecting the voltage in the intermediate circuit, wherein the control device is configured to control the turn-off speed as a function of the voltage.

[0010] DE 10 2011 077 387 A1 discloses a method for controlling a semiconductor power switch. An operating state of the semiconductor power switch is detected, and a switching speed of a driver circuit providing a control voltage for controlling the semiconductor power switch is set depending on the operating state. The operating state includes a temperature of the semiconductor power switch and a voltage present in an intermediate circuit. A switching signal is generated by means of a signal generator device and transmitted to the driver circuit. The switching signal is received by the driver circuit, and the control voltage is generated during the transition from an on-level to an off-level with a time characteristic corresponding to the set switching speed.

[0011] US 6,476,683 B1 discloses a method for adjusting the slope of a falling edge for a MOSFET switch in a pulse width modulation system. An ambient temperature is detected and compared with a temperature threshold. The slope for a pulse is then adjusted according to the comparison result.

[0012] The invention is based on the object of specifying a method for selecting turn-off speeds for turn-off processes in power semiconductors as well as a suitable computing unit and control device, by means of which electrical switching losses during turn-off processes are reduced and known methods and devices for adjusting the turn-off processes for power semiconductors are improved.

[0013] This object is achieved by a method having the features specified in claim 1.

[0014] This object is further achieved by a computing unit having the features specified in claim 14, a computer program according to claim 15 and a computer program product according to claim 16.

[0015] This object is further achieved by a control device having the features specified in claim 17.

[0016] This object is further achieved by a converter according to claim 20 and an electric or hybrid vehicle with a converter and electric machine according to claim 21.

[0017] The invention is based on the finding that the ambient temperatures to which a power semiconductor is exposed during operation and depending on the application area, influence the temperatures at the power semiconductor (junction temperature) to a non-negligible extent, which in turn can affect the turn-off speed of the power semiconductor, the duration of the turn-off process, and thus the electrical losses generated by the power semiconductor. Due to the reduced maximum blocking collector-emitter voltage at low temperatures according to power semiconductor manufacturers, a decision has previously been made to ensure the safe use of power semiconductors by generally using only the collector-emitter voltage as the maximum blocking collector-emitter voltage for designing turn-off speeds, which then correlates with the corresponding lowest temperature according to the manufacturer's data sheet.An example of this has already been mentioned.

[0018] If this limitation is accepted, the actual temperatures at or within the power semiconductor during operation, especially the low temperatures, have little influence on determining and specifying turn-off speeds for the turn-off process of power semiconductors. In the solutions known to date, the DC voltage detected at the DC link during operation of the power semiconductors is taken into account for controlling turn-off processes.

[0019] The potential that a changing temperature during power semiconductor operation, especially in combination with the changing DC voltage at the DC link, has for determining and specifying shutdown speeds for shutdown processes is not utilized or is utilized only to a limited extent. As a result, it is not possible to determine whether faster shutdown speeds are possible for specific operating points of the power semiconductors than previous solutions indicate. Faster shutdown speeds for specific operating points of the power semiconductors contribute to reducing the duration of shutdown processes and can thus also avoid costly oversizing of the power semiconductors and other affected components.

[0020] To achieve the object, a method is now proposed for the temperature-dependent selection of turn-off speeds for turn-off processes in power semiconductors which are arranged on a DC intermediate circuit of a converter, wherein a DC voltage of the DC intermediate circuit is detected by means of a voltage detection, compared with a reference DC voltage by a first comparison and a DC voltage comparison result is provided, a temperature, in particular a junction temperature, of at least one of the power semiconductors is detected by means of a temperature detection,by a second comparison with a reference temperature and a temperature comparison result is provided and depending on possible combinations of the DC voltage comparison result with the temperature comparison result, a switch-off speed is selected from a number of switch-off speeds and a newly determined switch-off speed is provided.

[0021] This method demonstrates a way to further reduce electrical losses that occur during the turn-off of power semiconductors, particularly IGBTs, by incorporating the temperature measured on or in the power semiconductor during operation as a condition for selecting the turn-off speed for turn-off processes. A blanket limitation to the collector-emitter voltage, which is provided for all operating points and specifies the maximum blocking collector-emitter voltage at low temperatures and is designated accordingly by the power semiconductor manufacturers in the data sheet, is no longer mandatory.

[0022] In particular, it was recognized that with the combination options of the first comparison of the recorded DC voltage of the DC link with the reference DC voltage and the second comparison of the recorded temperature of the power semiconductor with the reference temperature, the selection of the turn-off speeds for specific operating points of the power semiconductor can be made more finely granular and therefore electrical losses during the turn-off process can be reduced in a targeted and application-oriented manner.

[0023] For example, it can be assumed that the number of turn-off speeds required to select the newly determined turn-off speeds can be determined by the number of possible combinations of the DC voltage comparison result with the temperature comparison result. However, this requires that only one DC voltage reference is provided for the first comparison and only one temperature reference is provided for the second comparison. If additional temperature references and / or DC voltage references are introduced for additionally required comparisons, this increases the number of possible combinations and thus also the number of turn-off speeds that may need to be maintained. As a result, the turn-off behavior of the power semiconductors can be controlled with greater granularity.

[0024] If, from an application-related perspective, several possible combinations can be identified in the operating case in which the shutdown speeds can be the same and this is determined as such, a uniform value can be assigned to the newly determined shutdown speeds.

[0025] According to the invention, a third comparison further compares the newly determined shutdown speed with a previous shutdown speed and provides a shutdown speed comparison result, by which, in the event of an inequality between the newly determined shutdown speed and the previous shutdown speed, a switchover to the newly determined shutdown speed is triggered.

[0026] This allows for a plausibility check of the switching of shutdown speeds, and the switch from the previous shutdown speed to the newly determined shutdown speed is thus triggered in a monitored manner. The comparison that precedes the switch can also be used to define additional conditions for the switch. For non-destructive operation of not only the power semiconductors, for example, the switch to suitable shutdown speeds must be triggered if a thermal or electrical overload of electrical machines connected to the power semiconductors is detected based on the additional condition.

[0027] Advantageous embodiments of the method are specified in the dependent claims.

[0028] In an advantageous embodiment of the method, a first shutdown speed is defined as the newly determined shutdown speed by means of the selection, which is particularly suitable for a very slow shutdown speed if, in one of the possible combinations of the temperature comparison result with the DC voltage comparison result, the temperature detected by the temperature determination is lower than the reference temperature and the DC voltage detected by the voltage determination is higher than the reference DC voltage.

[0029] The first shutdown speed, which is based on at least one specific, application-oriented operating point, is designed as a very slow shutdown speed, for example, if the measured temperature of the power semiconductor, at -40°C, is significantly lower than the reference temperature defined as 0°C, but at the same time the measured DC voltage at the DC link, at 450V, is significantly higher than the reference DC voltage defined as 400V. Therefore, in the example, there is little scope for a collector-emitter shutdown overvoltage on the power semiconductor to not exceed a maximum blocking collector-emitter voltage specified by the manufacturer. The very slow shutdown speed is therefore intended to ensure a safe shutdown process for operating points that lie at the limit of the power semiconductors.

[0030] In a further advantageous embodiment of the method, a first gate turn-off signal is formed by electrically connecting a third gate turn-off series resistor upstream of a gate of the power semiconductor by means of a gate turn-off semiconductor that can be controlled by a clocked gate control signal, if the first turn-off speed has been defined as the newly determined turn-off speed by the selection.

[0031] The turn-off speed for the turn-off process of the power semiconductor is essentially determined by the current gradient of a collector current of the power semiconductor. This current gradient of the collector current can be controlled by electrically activating or deactivating appropriately designed electrical gate pre-circuits, which in particular consist of one or more gate turn-off resistors and are electrically connected to the gate of the power semiconductor, depending on the newly determined turn-off speed. This explanation applies to all gate pre-circuits as taught below according to the invention.

[0032] The third gate turn-off series resistor that can be activated with this embodiment of the method must be designed by the user with regard to the first turn-off speed in such a way that the turn-off duration intended for this combination option can be achieved.

[0033] In a further advantageous embodiment of the method, a second shutdown speed is defined as the newly determined shutdown speed by means of the selection, which is particularly suitable for a fast shutdown speed if, in one of the possible combinations of the temperature comparison result with the DC voltage comparison result, the temperature detected by the temperature determination is lower than the reference temperature and the DC voltage detected by the voltage determination is lower than the reference DC voltage.

[0034] The second shutdown speed, which is related to at least one specific, application-oriented operating point, will be designed as a fast shutdown speed, for example, if the measured temperature of the power semiconductor is -40°C, which is significantly lower than the reference temperature defined as 0°C, but at the same time the measured DC voltage at the DC link is 370V, which is below the reference DC voltage defined as 400V. Despite the limitation of the maximum blocking collector-emitter voltage due to the low measured temperature, the collector-emitter shutdown overvoltage at the power semiconductor is granted a buffer due to the comparatively low DC voltage at the DC link, which is sufficient to prevent the maximum blocking collector-emitter voltage from being exceeded.

[0035] In a further advantageous embodiment of the method, a second gate turn-off signal is formed by electrically connecting a second gate turn-off series resistor in parallel with the third gate turn-off series resistor by means of a second semiconductor switch which is switched by a second switching signal, and by electrically connecting these gate turn-off series resistors as a parallel circuit upstream of the gate of the power semiconductor by means of the gate turn-off semiconductor which can be controlled by the clocked gate control signal, if the second turn-off speed has been defined as the newly determined turn-off speed by the selection.

[0036] The parallel circuit that can be activated with this embodiment of the method must be designed by the user with regard to the second turn-off speed, in particular with regard to the second gate turn-off series resistor and the third gate turn-off series resistor, in such a way that the duration of the turn-off process intended for this combination option can be achieved.

[0037] In a further advantageous embodiment of the method, a third shutdown speed is defined as the newly determined shutdown speed by means of the selection, which is particularly suitable for a slow shutdown speed if, in one of the possible combinations of the temperature comparison result with the DC voltage comparison result, the temperature detected by the temperature determination is greater than the reference temperature and the DC voltage detected by the voltage determination is greater than the reference DC voltage.

[0038] The third shutdown speed, which is related to at least one specific, application-oriented operating point, will be designed as a slow shutdown speed, for example, if the measured temperature of the power semiconductor, at +25°C, is significantly higher than the reference temperature defined as 0°C, but at the same time the measured DC voltage at the DC intermediate circuit, at 450V, is also significantly higher than the reference DC voltage defined as 400V. Regarding the collector-emitter shutdown overvoltage at the power semiconductor, in the example, from the perspective of the measured temperature, no temperature-related restriction of the maximum blocking collector-emitter voltage specified by the manufacturer is necessary. However, the comparatively high DC voltage at the DC intermediate circuit limits the space required to prevent the collector-emitter shutdown overvoltage from being exceeded.

[0039] In a further advantageous embodiment of the method, a third gate turn-off signal is formed by electrically connecting a first gate turn-off series resistor in parallel with the third gate turn-off series resistor by means of a first semiconductor switch which is switched by a first switching signal, and by electrically connecting these gate turn-off series resistors as a parallel circuit upstream of the gate of the power semiconductor by means of the gate turn-off semiconductor which can be controlled by the clocked gate control signal, if the third turn-off speed has been defined as the newly determined turn-off speed by the selection.

[0040] The parallel circuit that can be activated with this embodiment of the method must be designed by the user with regard to the third turn-off speed, in particular with regard to the first gate turn-off series resistor and the third gate turn-off series resistor, in such a way that the duration of the turn-off process intended for this combination option can be achieved.

[0041] In a further advantageous embodiment of the method, a fourth shutdown speed is defined as the newly determined shutdown speed by means of the selection, which is particularly suitable for a very fast shutdown speed if, in one of the possible combinations of the temperature comparison result with the DC voltage comparison result, the temperature detected by the temperature determination is greater than the reference temperature and the DC voltage detected by the voltage determination is less than the reference DC voltage.

[0042] The fourth shutdown speed, based on at least one specific, application-oriented operating point, will be designed as a very fast shutdown speed, for example, if the measured temperature of the power semiconductor, at +25°C, is significantly higher than the reference temperature defined as 0°C, but at the same time the measured DC voltage at the DC link, at 370V, is below the reference DC voltage defined as 400V. In this example, the collector-emitter shutdown overvoltage at the power semiconductor has sufficient buffer to the maximum blocking collector-emitter voltage to avoid exceeding it.

[0043] In a further advantageous embodiment of the method, a fourth gate turn-off signal is formed by electrically connecting the first gate turn-off series resistor in parallel with the third gate turn-off series resistor by means of the first semiconductor switch, which is switched by the first switching signal, by electrically connecting the second gate turn-off series resistor in parallel with the third gate turn-off series resistor by means of the second semiconductor switch, which is switched by the second switching signal, and by electrically connecting these gate turn-off series resistors as a parallel circuit upstream of the gate of the power semiconductor by means of the gate turn-off semiconductor that can be controlled by the clocked gate control signal, if the fourth turn-off speed has been defined as the newly determined turn-off speed by the selection.

[0044] The parallel circuit that can be activated with this embodiment of the method must be designed by the user, particularly with regard to the first gate turn-off series resistor, the second gate turn-off series resistor and the third gate turn-off series resistor, with regard to the fourth turn-off speed, in such a way that the duration of the turn-off process provided for this combination option can be achieved.

[0045] In a further advantageous embodiment of the method, a fifth shutdown speed is determined as a newly determined shutdown speed by means of the selection, which is particularly suitable for a uniform shutdown speed,if, in one of the possible combinations of the temperature comparison result with the DC voltage comparison result, the temperature detected by the temperature determination is lower than the reference temperature and the DC voltage detected by the voltage determination is lower than the reference DC voltage, or if, in one of the possible combinations of the temperature comparison result with the DC voltage comparison result, the temperature detected by the temperature determination is lower than the reference temperature and the DC voltage detected by the voltage determination is higher than the reference DC voltage, or if, in one of the possible combinations of the temperature comparison result with the DC voltage comparison result, the temperature detected by the temperature determination is higher than the reference temperature and the DC voltage detected by the voltage determination is higher than the reference DC voltage.

[0046] This design of the method is based on an application-related assumption. For specific applications, several possible combinations of the temperature comparison result with the DC voltage comparison result can be identified and defined, which rarely occur during operation of the power semiconductor or are often only of short duration.This assumption can, for example, lead to the common shutdown speed if the recorded temperature of the power semiconductor is -40°C, which is significantly lower than the reference temperature defined as 0°C, but at the same time the recorded DC voltage at the DC intermediate circuit is 370V, which is below the reference DC voltage defined as 400V, or if the recorded temperature of the power semiconductor is -40°C, which is significantly lower than the reference temperature defined as 0°C, but at the same time the recorded DC voltage at the DC intermediate circuit is 450V, which is above the reference DC voltage defined as 400V, or if the recorded temperature of the power semiconductor is +25°C, which is significantly higher than the reference temperature defined as 0°C, but at the same time the recorded DC voltage at the DC intermediate circuit is 450V, which is above the reference DC voltage defined as 400V.

[0047] For the uniform shutdown speed, the user must select a value that meets the corresponding shutdown processes, at least for reasons of reliability. An improved reduction of electrical losses for all these possible combinations may not be fully achievable.

[0048] In a further advantageous embodiment of the method, a fifth gate turn-off signal is formed by electrically connecting a fifth gate turn-off series resistor upstream of a gate of the power semiconductor by means of a gate turn-off semiconductor that can be controlled by a clocked gate control signal, if the fifth turn-off speed has been defined as the newly determined turn-off speed by the selection.

[0049] This embodiment follows the assumption from the user's perspective, as presented in the previous embodiment of the method. The fifth gate turn-off series resistor that can be activated with this embodiment of the method must be designed by the user with respect to the fifth turn-off speed, i.e., in particular, with respect to the uniform turn-off speed, such that the intended duration of the turn-off process can encompass several possible combinations of the temperature comparison result with the DC voltage comparison result.

[0050] In a further advantageous embodiment of the method, a sixth shutdown speed is defined as a newly determined shutdown speed by means of the selection, which is particularly suitable for a maximum shutdown speed if, in one of the possible combinations of the temperature comparison result with the DC voltage comparison result, the temperature detected by the temperature determination is greater than the reference temperature and the DC voltage detected by the voltage determination is less than the reference DC voltage.

[0051] The sixth shutdown speed, which is related to at least one specific, application-oriented operating point, will, for example, be designed as the maximum shutdown speed if the recorded temperature of the power semiconductor is +25°C and is significantly higher than the reference temperature defined as 0°C, and at the same time the recorded DC voltage at the DC link is 370V and below the reference DC voltage defined as 400V.

[0052] Generally, very fast turn-off speeds are intended for this embodiment. With regard to the uniform turn-off speed, which was proposed for the two previous embodiments, taking into account the assumptions made there from the user's perspective, the maximum turn-off speed is particularly suitable for the combination option presented here. The collector-emitter turn-off overvoltage on the power semiconductor has sufficient buffer to the maximum blocking collector-emitter voltage to avoid exceeding it.

[0053] In a further advantageous embodiment of the method, a sixth gate turn-off signal is formed by electrically connecting a fourth gate turn-off series resistor in parallel with the fifth gate turn-off series resistor by means of a first semiconductor switch which is switched by a first switching signal, and by electrically connecting these gate turn-off series resistors as a parallel circuit upstream of the gate of the power semiconductor by means of the gate turn-off semiconductor which can be controlled by the clocked gate control signal, if the sixth turn-off speed has been defined as the newly determined turn-off speed by the selection.

[0054] The parallel circuit that can be activated with this embodiment of the method must be designed by the user with regard to the turn-off speed, particularly with regard to the fourth gate turn-off series resistor and the fifth gate turn-off series resistor, in such a way that the duration of the turn-off process intended for this combination option can be achieved.

[0055] Furthermore, to achieve the object, a computing unit for carrying out the method according to the invention for temperature-dependent selection of turn-off speeds for turn-off processes in power semiconductors is proposed, which has a voltage input for receiving the DC voltage detected by means of the voltage detection, a temperature input for receiving the temperature detected by means of the temperature detection, a first switching signal output for outputting a first switching signal and optionally a second switching signal output for outputting a second switching signal.

[0056] Software designed to implement the method according to the invention runs on computer processors in the processing unit. The software performs, among other things, the comparisons demonstrated in the method according to the invention, selects the newly determined turn-off speed from the possible combinations of the comparison results, and switches in the event of a discrepancy between the newly determined turn-off speed and the previous turn-off speed. Furthermore, based on the newly determined turn-off speed, the software provides the switching signals for the semiconductor switches, which, depending on the newly determined turn-off speed, electrically connect corresponding gate turn-off series resistors to the gate to generate the gate control signals for the turn-off processes of the power semiconductors.

[0057] The second switching signal output for outputting the second switching signal is provided at least when the number of turn-off speeds, which result from the possible combinations of the DC voltage comparison result with the temperature comparison result and can assume various values, cannot be output exclusively in the form of the first switching signal via the first switching signal output for gate control during the turn-off process of the power semiconductor. This occurs at least when the first switching signal is designed, for example, as a binary signal and the number of turn-off speeds is greater than two.

[0058] Additional switching signals, which can be output via additional switching signal outputs, can be provided in the aforementioned context if required.

[0059] Furthermore, to achieve this objective, a computer program for operating the computing unit is proposed. This computer program includes, among other things, the software for implementing the inventive method for temperature-dependent selection of turn-off speeds for turn-off processes in power semiconductors. It can also be implemented as part of a higher-level computer program, with appropriate communication connections and communication protocols being provided. Integration of the computer program into distributed, cross-hardware software systems is also possible.

[0060] Furthermore, to achieve the object, a computer program product is proposed on which the computer program according to the invention is stored. In addition to electrically and mechanically fixed storage media for storing the computer program, hard disk storage is often provided here, the computer program product can also be designed as a removable data storage device. These removable data storage devices include memory sticks for USB applications, memory cards, CDs, and DVDs. For the necessary data transfer of the computer program or parts of the computer program to designated storage media, both electrically wired networks and networks that transmit data at least partially without electrical wires are used.

[0061] Furthermore, to achieve the object, a control device for temperature-dependent gate control for turn-off processes of power semiconductors is proposed, which is designed to carry out the method according to the invention with the computing unit according to the invention and at least one first switching signal input for receiving a first switching signal, if necessary.a second switching signal input for receiving a second switching signal, a gate drive signal input for a clocked gate drive signal, a gate switching signal output for a gate turn-off signal, a gate turn-off semiconductor and an electrical connection of gate turn-off series resistors, wherein this electrical connection is electrically connected by one of its first connections to a negative voltage potential of a voltage supply of the drive device and is electrically connected by one of its second connections to the gate turn-off semiconductor and is further electrically connectable to a gate of the power semiconductor via the gate switching signal output.

[0062] The second switching signal input for receiving the second switching signal is provided at least when the number of turn-off speeds, which result from the possible combinations of the DC voltage comparison result with the temperature comparison result and can assume various values, cannot be received exclusively in the form of the first switching signal via the first switching signal input for gate control during the turn-off process of the power semiconductor. This occurs at least when the first switching signal is designed, for example, as a binary signal and the number of turn-off speeds is greater than two.

[0063] Further switching signals, which can be received via additional switching signal inputs, can be provided in the above context if required.

[0064] Advantageous embodiments of the control device are specified in the dependent claims.

[0065] In a first advantageous embodiment of the control device, the electrical connection has at least one third gate turn-off resistor, a first series circuit electrically connected in parallel thereto with a second gate turn-off resistor and a second semiconductor switch, and a second series circuit likewise electrically connected in parallel thereto with a first gate turn-off resistor and a first semiconductor switch.

[0066] This design of the control device can be advantageously used when, for example, more than two shutdown signals, which should have different values, are provided for the shutdown processes of the power semiconductor. Depending on the status of the first switching signal and the second switching signal, which depend on the newly determined shutdown speed, a corresponding total resistance is formed from the respective gate shutdown resistors, which influences the current gradient of the collector current in the power semiconductor and thus the duration of its shutdown process.

[0067] In a further advantageous embodiment of the control device, the electrical connection has at least a fifth gate turn-off resistor and a series circuit electrically connected in parallel thereto with the fourth gate turn-off resistor and a first semiconductor switch.

[0068] This design of the control device can be used when the number of possible shutdown speeds achievable from the combinations of the DC voltage comparison result with the temperature comparison result is limited due to the application. Such a component-reduced electrical connection is particularly advantageous when only a maximum of two shutdown speeds, which should have different values, are provided for the selection of the newly determined shutdown speeds.

[0069] Furthermore, to achieve the object, a converter with a DC voltage intermediate circuit is proposed, which has at least the power semiconductors, the computing unit according to the invention, the computer program according to the invention, the computer program product according to the invention, the control device according to the invention, the temperature detection and the voltage detection.

[0070] Furthermore, to achieve the object, an electric or hybrid vehicle is proposed which has the converter according to the invention and an electric machine which can be operated by means of the converter.

[0071] For electric or hybrid vehicles, manufacturers of such vehicles place high demands on electrical and electronic components regarding reliability and service life. Suppliers of converters used to power electrical machines in electric or hybrid vehicles must therefore ensure that their products are operational, powerful, and durable, even under sometimes extreme environmental conditions. For example, corresponding specifications for temperature ranges of + / - 40°C are quite common for electric or hybrid vehicles. Despite these specifications, it is not only the manufacturer of electric or hybrid vehicles who is interested in ensuring a level of efficiency that makes the operation of the electric or hybrid vehicle not only technically but also economically viable.

[0072] The method according to the invention is therefore particularly well suited to ensuring safe operation of the power semiconductors and, at the same time, further reducing the electrical losses in the power semiconductors of the converter, thus meeting the requirements of the manufacturers of electric or hybrid vehicles in particular.

[0073] The above-described properties, features, and advantages of this invention, as well as the manner in which they are achieved, will become clearer and more readily understood in connection with the following description of the embodiments, which are explained in more detail in conjunction with the figures. They show: Fig. 1 a diagram with a collector-emitter voltage V CE and a collector current I C during a shutdown process AV of power semiconductors, Fig. 2 another diagram with a collector-emitter voltage V CE and a collector current IC during turn-off process AV of power semiconductors after Fig. 1, wherein the switch-off process AV depends on a temperature T detected at the power semiconductor, which is lower than a reference temperature T ref . is, Fig. 3 another diagram with a collector-emitter voltage V CE and a collector current I C during turn-off process AV of power semiconductors after Fig. 1 or Fig. 2, wherein the switch-off process AV depends on a temperature T detected at the power semiconductor, which is greater than the reference temperature T ref . is, Fig. 4 a schematic representation of an embodiment of the method according to the invention for the temperature-dependent selection AW of turn-off speeds ASG for turn-off processes AV in power semiconductors 5, Fig. 5 a further schematic representation of an embodiment of the method according to the invention, based on Fig. 4, Fig. 6 a table with possible combinations (KBM) of DC voltage comparison results RES VDC with temperature comparison results RES T , with turn-off speeds ASG, with gate turn-off resistors R Goff as well as with switching states of the first semiconductor switch T1 and the second semiconductor switch T2, Fig. 7 another table with possible combinations KBM from the DC voltage comparison results RES VDC with temperature comparison results RES T , with turn-off speeds ASG, with gate turn-off resistors R Goff as well as with switching states of the first semiconductor switch T1, Fig. 8 a schematic circuit diagram of a converter 6 with power semiconductor 5 on the DC voltage intermediate circuit 2, with computing unit 7 and control device 1, Fig. 9 a further schematic circuit diagram of the converter 6 with power semiconductor 5 on the DC voltage intermediate circuit 2, with computing unit 7 and with control device 1 and Fig. 10 is a schematic representation of an electric or hybrid vehicle 8 with converter 6 and an electric machine 17 driven by the converter 6.

[0074] In Fig. 1 shows a diagram with a collector-emitter voltage V CE and a collector current I CThis diagram illustrates a turn-off process AV of power semiconductors connected to a DC link using corresponding electrical parameters. A time t is plotted along one axis of the diagram, which represents a sequence and duration of states of the power semiconductors—i.e., a conducting state LZ and a blocking state SZ—along with the actual turn-off process of the power semiconductors.

[0075] On another axis of the diagram in Fig. 1 shows current I and voltage V, whereby in particular a collector current I C and a collector-emitter voltage V CE which can be used to describe a typical turn-off process AV in power semiconductors. For a better understanding of the turn-off process AV, further electrical parameters, such as a maximum blocking collector-emitter voltage V CESof the power semiconductor, a collector-emitter turn-off overvoltage ΔV CE on the power semiconductor and a DC voltage V DC on the DC link, shown in the diagram.

[0076] The shutdown process AV, as shown in the diagram in Fig. 1, starts from the conductive state LZ for the power semiconductor. The collector current I C flows in the conducting state LZ, depending on the required level and within specified limits, through the conducting semiconductor, while the collector-emitter voltage V CE at the power semiconductor is virtually zero. With the start of the turn-off process AV, the collector-emitter voltage V CE continuously. With a time delay, the collector current I C to fall until it reaches a value close to zero. A small leakage current may continue to flow. The collector-emitter voltage V CE exceeds when the collector current is reduced IC briefly one for the DC voltage V DC at the DC intermediate circuit characteristic value, which is determined by the Fig. 1 shown collector-emitter turn-off overvoltage ΔV CE is expressed.

[0077] Depending on the current gradient dI C / dt of the collector current I C , which is a derivative of the collector current I C after the time t, a value of the collector-emitter turn-off overvoltage ΔV CE which depends on the inductance L present in the DC circuit (also known as the inductance of a commutation circuit). It must now generally be ensured that the collector-emitter voltage V CE , in sum with the occurring collector-emitter turn-off overvoltage ΔV CE , not the maximum blocking collector-emitter voltage V defined for the power semiconductor CESThe turn-off process AV is completed when the collector current I C is virtually zero and the collector-emitter voltage V CE the DC voltage V DC at the DC voltage intermediate circuit has reached the characteristic value and thus the blocking state SZ of the power semiconductor has occurred.

[0078] Starting from Fig. 1 are shown in the diagram of the Fig. 2 Effects on the turn-off process AV of power semiconductors are shown when the temperature T prevailing at the power semiconductor is lower than a reference temperature T defined for corresponding applications ref .. In the diagram of the Fig. 2, which partially shows a shutdown process AV based on Fig. 1 shows, it is assumed that the collector current I C at the beginning of the turn-off process AV and the DC voltage V DC on the DC link with corresponding values of the Fig. 1 are comparable. The Fig. 2 shown maximum blocking collector-emitter voltage V CES is therefore in Fig. 2 smaller than in Fig. 1. For the diagram of the Fig. 2 Here it is assumed that, for example, the reference temperature T ref . is defined as 0°C. If the temperature T measured at the power semiconductor is assumed to be -40°C, for example, then, as an example, the maximum blocking collector-emitter voltage V for corresponding power semiconductors can be determined from the manufacturer's data sheet. CES from 650V to 605V.

[0079] Accordingly, the current gradient dI C / dt of the collector current I C so that the collector-emitter turn-off overvoltage ΔV CE the collector-emitter voltage V CE during the turn-off process AV does not exceed the maximum blocking collector-emitter voltage V CESThe duration of the turn-off process AV is negatively influenced in this case, so it may take longer than without limiting the maximum blocking collector-emitter voltage V CES This also has an impact on the increasing electrical losses during such a shutdown process AV.

[0080] In Fig. 3 shows a diagram in which, as already with Fig. 2, also effects on the turn-off process AV of power semiconductors can be seen. In contrast to the example from Fig. 2 will be in Fig. 3 shows that the temperature T prevailing at the power semiconductor is greater than the correspondingly defined reference temperature T ref .. Is here in Fig. 3 assume that the temperature T measured at the power semiconductor is +25°C, and the reference temperature T ref . is defined as 0°C, would, in contrast to, for example, Fig. 2, no limitation of the maximum blocking collector-emitter voltage V CES be necessary.

[0081] The current gradient dI C / dt of the collector current I C can then be compared to Fig. 2 higher, which results in a shortening of the duration of the shutdown process AV and reduces the electrical losses.

[0082] The Fig. Figure 4 shows a schematic representation of an embodiment of the method according to the invention for the temperature-dependent selection AW of turn-off speeds ASG for turn-off processes AV in power semiconductors. It is assumed that the power semiconductors are arranged on a DC voltage intermediate circuit (is shown in Fig. 4 not shown).

[0083] In the process, as shown in the schematic diagram in Fig. 4, a DC voltage V DC, which was recorded at the DC link, by a first comparison VG1 with a reference DC voltage V DC_ref . compared and using a DC voltage comparison result RES VDC In a usefully similar step, a temperature T, which was detected by at least one of the power semiconductors, is compared with a reference temperature T ref . compared and using a temperature comparison result RES T provided.

[0084] Depending on the possible combinations KBM of the DC voltage comparison result RES VDC with the temperature comparison result RES T the selection AW of a cut-off speed ASG from a number of cut-off speeds ASG is made and a newly determined cut-off speed ASG newThe newly determined shutdown speed ASG new advantageously allows the switch-off process AV for the power semiconductors to be designed more finely granular and tailored to the specific operating points of the power semiconductor, depending on the requirements.

[0085] The Fig. 5 shows, based on Fig. 4, a further schematic representation of an embodiment of the method according to the invention. By means of a third comparison VG3, the newly determined shutdown speed ASG new with a previous shutdown speed ASG old compared and a shutdown speed comparison result RES ASG In case of a discrepancy between the newly determined cut-off speed ASG new and previous shutdown speed ASG old then a switchover UM to the newly determined cut-off speed ASG newThus, an explicit check is carried out to determine whether switching UM to the newly determined cut-off speed ASG new should be done.

[0086] A concrete interpretation of comparison conditions (>, <, =, >=, <=) for the comparisons VG1, VG2, VG3 of the method according to the invention is at the discretion of the expert or is application-specific.

[0087] With the Fig. The table shown in Figure 6 shows possible combinations KBM of the DC voltage comparison results RES VDC with the temperature comparison results RES T shown as provided by the method according to the invention. Using four possible combinations KBM, the table also shows four cut-off speeds ASG for the selection AW of newly determined cut-off speeds ASG newvisualized, whereby for each of the turn-off speeds ASG an electrical connection is also shown, which includes gate turn-off resistors R Goff Furthermore, correspondingly coordinated switching states of a first semiconductor switch T1, which can be controlled by the first switching signal S1, and of a second semiconductor switch T2, which can be controlled by the second switching signal S2, are stored in the table.

[0088] The Fig. 7 shows another table with possible combinations KBM of the DC voltage comparison results RES VDC with the temperature comparison results RES T . A difference to Fig. 6 is that two cut-off speeds ASG for the selection AW of the newly determined cut-off speeds ASG newThe user can specify that for some of the combination options KBM, in this example there are three combination options KBM, a uniform shutdown speed ASG US This means that, depending on the application, it may be useful to provide a smaller number of steps regarding the turn-off speeds ASG for the turn-off process of power semiconductors, even though the number of possible combinations KBM allows for more turn-off speeds ASG.

[0089] A schematic circuit diagram of a converter 6, for which the method according to the invention with in particular four switching speeds is particularly suitable, is shown in Fig. 8. The converter 6 is connected to a DC link 2 with a DC voltage V DC which has a positive DC potential DC +and a negative DC potential DC - At the DC voltage intermediate circuit 2, power semiconductors 5, in particular IGBTs, are connected between the two DC voltage potentials DC + , DC - the DC voltage V DC arranged.

[0090] The Fig. 8 represents only a power semiconductor 5 between the positive DC voltage potential DC + and the negative DC potential DC - as this is sufficient for explanations of the application example. For the power semiconductor, which, for example, must be incorporated into the half-bridge circuit of the DC link 2 for its functionality (in Fig. 8 not shown), a dashed line is drawn at the negative DC potential DC - shown as a graphic placeholder.

[0091] The power semiconductors 5 have a gate G, a collector C, and an emitter E. Depending on the application, they are often combined into a module, allowing for a compact design. The modules can be designed, for example, as a six-pulse bridge circuit or a half-bridge circuit.

[0092] For the implementation of the method according to the invention for temperature-dependent selection AW and switching UM of turn-off speeds for turn-off processes in power semiconductors 5 shows Fig. 8 a computing unit 7 in the converter 6, which, via a voltage input 9, receives the DC voltage V detected by a voltage detector 3 at the DC voltage intermediate circuit 2 DCcan receive a temperature T detected on the power semiconductor 5 by means of temperature detection 4 via a temperature input 10, can output a switching signal S1 via a first switching signal output 11 and can output a second switching signal S2 via a second switching signal output 12.

[0093] Furthermore, Fig. 8 shows a control device 1 in the converter 6 for gate control of the gate G of power semiconductors 5 according to the method according to the invention, which is particularly suitable for four turn-off speeds. It can receive the first switching signal S1 with a first switching signal input 13, the second switching signal S2 with a second switching signal input 14, and a clocked gate control signal S with a gate control signal input 15. on / off and with a gate switching signal output 16 a gate switch-off signal S G_off hand over.

[0094] The control device 1 contains in the Fig. 8, an electrical circuit 20 which includes a third gate turn-off resistor R Goff3 , a first series circuit electrically connected in parallel with a second gate turn-off resistor R Goff2 and a second semiconductor switch T2 and a second series circuit, also electrically connected in parallel thereto, with a first gate turn-off resistor R Goff1 and a first semiconductor switch T1. The first semiconductor switch T1 can be controlled by the first switching signal S1 and the second semiconductor switch T2 by the second switching signal S2. The electrical connection 20 is connected to one of its first terminals 18 with a negative voltage potential R - a voltage supply of the control device 1, with one of its second terminals 19 to the gate turn-off semiconductor T offelectrically connected. The gate turn-off semiconductor T off is further connected to the clocked gate control signal S on / off can be controlled and electrically connected to the gate G of the power semiconductor 5 via the gate switching signal output 16. The switch-off process of the power semiconductor 5 by means of the method according to the invention can thus be carried out.

[0095] One in Fig. 8 shown gate switching semiconductor T on and one with a positive voltage potential P + Gate on-resistor R connected to the voltage supply of the control device 1 Gon is not directly relevant for the turn-off processes of the power semiconductors. As shown, the gate drive signal S on / off controllable gate turn-off semiconductors T off designed as a pnp transistor for the turn-off processes of the power semiconductors 5.

[0096] In contrast, the gate drive signal S on / off controllable gate switching semiconductors T on designed as an npn transistor for switching on the power semiconductors 5. This electrically ensures that, depending on the status of the gate control signal S on / off either only the gate turn-off semiconductor T off for the turn-off process or only the gate turn-on semiconductor T on for the switching-on process of the power semiconductor 5.

[0097] The Fig. 9 shows a further schematic circuit diagram of a converter 6 with power semiconductor 5 on the DC voltage intermediate circuit 2, with a computing unit 7 and with a control device 1, which largely corresponds in arrangement and function to the converter 6 from Fig. 8, whereby corresponding differences arise from the specific embodiment.

[0098] This specific embodiment assumes that from an application point of view, and in contrast to the embodiment according to Fig. 8, only two turn-off speeds are required for turn-off processes of the power semiconductors 5, although in principle more combination possibilities can result from DC voltage comparison result with temperature comparison result for the selection AV and the resulting switching UM of the turn-off speeds.

[0099] The converter 6 in Fig. 9 is comparable Fig. 8, with the DC voltage V applied to the DC intermediate circuit 2 DC which the positive DC voltage potential DC + and the negative DC potential DC - At the DC voltage intermediate circuit 2, power semiconductors 5, in particular IGBTs, are connected between the two DC voltage potentials DC + , DC - the DC voltage V DCThese power semiconductors 5 have at least the gate G, the collector C and the emitter E, whereby also for the embodiment in Fig. 9, comparable Fig. 8, only one power semiconductor 5 between the positive DC voltage potential DC + and the negative DC potential DC - is shown.

[0100] The computing unit 7 of the converter 6 according to Fig. 9 shows, as in Fig. 8, a voltage input 9 which receives a DC voltage V detected by a voltage detector 3 on the DC voltage intermediate circuit 2 DC can receive, a temperature input 10, which can receive a temperature T detected at the power semiconductor 5 by means of temperature detection 4 and a switching signal S1, which can be output via a first switching signal output 11. In contrast to the embodiment according to Fig. 8, additional switching signal outputs for outputting additional switching signals are not immediately required.

[0101] Furthermore, the inverter 6 contains the Fig. 9 shows a control device 1 for gate control of the gate G of power semiconductors 5 according to the method according to the invention, which is particularly suitable for the two turn-off speeds. With the first switching signal input 13, the control device 1 can receive the first switching signal S1. In contrast to Fig. 8 is not directly required. The gate control signal input 15 is used to provide the clocked gate control signal S on / off recordable and with a gate switching signal output 16, the gate switch-off signal S G_off available for sale.

[0102] The control device 1 of the Fig. 9 further includes an electrical circuit 20, which includes a fifth gate turn-off resistor RGoff5 and a series circuit electrically connected in parallel with a fourth gate turn-off resistor R Goff4 and a first semiconductor switch T1. The first semiconductor switch T1 can be controlled by means of the first switching signal S1. The electrical connection 20 is connected to a negative voltage potential R by one of its first terminals 18. - a voltage supply of the control device 1, with one of its second terminals 19 to the gate turn-off semiconductor T off electrically connected. The gate turn-off semiconductor T off is further connected to the clocked gate control signal S on / off can be controlled and electrically connected to the gate G of the power semiconductor 5 via the gate switching signal output 16.

[0103] In Fig. 9 is a gate switching semiconductor T shown there on and one with a positive voltage potential P +Gate on-resistor R connected to the voltage supply of the control device 1 Gon also not directly relevant for the shutdown processes of the power semiconductors.

[0104] The schematic representation according to Fig. 10 shows an electric or hybrid vehicle 8 having the converter 6. The converter 6 is intended to drive an electric machine 17. Furthermore, the converter 6 can feed electrical energy emitted by the electric machine 17, for example, during braking, back into the electric or hybrid vehicle 8. The method according to the invention is particularly suitable for such use in electric or hybrid vehicles 8.

Claims

[1] Method for the temperature-dependent selection (AW) of turn-off speeds (ASG) for turn-off processes (AV) in power semiconductors (5) which are arranged on a DC voltage intermediate circuit (2) of a converter (6), wherein - a direct voltage (V DC ) of the DC voltage intermediate circuit (2) by means of a voltage source connected to a positive DC voltage potential (DC + ) of the DC link (2) and a negative DC potential (DC - ) of the DC voltage intermediate circuit (2), by a first comparison (VG1) with a reference DC voltage (V DC_ref .) and a DC voltage comparison result (RES VDC ) is provided, - a temperature (T) of at least one of the power semiconductors (5) is detected by means of a temperature detection (4), by a second comparison (VG2) with a reference temperature (T ref.) and a temperature comparison result (RES T ) is provided, - depending on the combination possibilities (KBM) of the DC voltage comparison result (RES VDC ) with the temperature comparison result (RES T ) the selection (AW) of a cut-off speed (ASG) from a number of cut-off speeds (ASG) is made and a newly determined cut-off speed (ASG new ) is provided and - by a third comparison (VG3) the newly determined shutdown speed (ASG new ) with a previous shutdown speed (ASG old ) and a shutdown speed comparison result (RES ASG ) is provided, by which, in case of a discrepancy between the newly determined cut-off speed (ASG new ) and previous shutdown speed (ASG old), a switchover (UM) to the newly determined cut-off speed (ASG new ) is triggered. [2] Method according to claim 1, wherein by means of the selection (AW) a first shutdown speed (ASG1) is determined as the newly determined shutdown speed (ASG new ) is set if one of the combination options (KBM) of the temperature comparison result (RES T ) with the DC voltage comparison result (RES VDC ) the temperature (T) detected by the temperature detection (4) is lower than the reference temperature (T ref .) and the DC voltage (V DC ) is greater than the reference DC voltage (V DC_ref .) [3] The method of claim 2, wherein a first gate turn-off signal (S G_off1 ) is formed by a third gate turn-off resistor (R Goff3 ), by means of a gate control signal (S on / off) controllable gate turn-off semiconductor (T off ), a gate (G) of the power semiconductor (5) is electrically connected upstream, if the first turn-off speed (ASG1) is determined as the newly determined turn-off speed (ASG new ) was set. [4] Method according to one of the preceding claims, wherein by means of the selection (AW) a second shutdown speed (ASG2) is determined as the newly determined shutdown speed (ASG new ) is set if one of the combination options (KBM) of the temperature comparison result (RES T ) with the DC voltage comparison result (RES VDC ) the temperature (T) detected by the temperature detection (4) is lower than the reference temperature (T ref .) and the DC voltage (V DC ) is smaller than the reference DC voltage (V DC_ref .) [5] The method of claim 4, wherein a second gate shutdown signal (S G_off2 ) is formed by a second gate turn-off resistor (R Goff2 ) by means of a second semiconductor switch (T2), which is switched by a second switching signal (S2), electrically parallel with the third gate turn-off resistor (R Goff3 ) and by connecting these gate turn-off resistors (R Goff2 , R Goff3 ) as a parallel circuit, by means of the gate control signal (S on / off ) controllable gate turn-off semiconductor (T off ), the gate (G) of the power semiconductor (5) are electrically connected upstream, if the second turn-off speed (ASG2) is determined as the newly determined turn-off speed (ASG new ) was set. [6] Method according to one of the preceding claims, wherein by means of the selection (AW) a third shutdown speed (ASG3) is determined as the newly determined shutdown speed (ASGnew ) is set if one of the combination options (KBM) of the temperature comparison result (RES T ) with the DC voltage comparison result (RES VDC ) the temperature (T) detected by the temperature detection (4) is greater than the reference temperature (T ref .) and the DC voltage (V DC ) is greater than the reference DC voltage (V DC_ref .) [7] The method of claim 6, wherein a third gate shutdown signal (S G_off3 ) is formed by a first gate turn-off resistor (R Goff1 ) by means of a first semiconductor switch (T1), which is switched by a first switching signal (S1), electrically parallel with the third gate turn-off resistor (R Goff3 ) and by connecting these gate turn-off resistors (R Goff1 , R Goff3 ) as a parallel circuit, by means of the gate control signal (S on / off) controllable gate turn-off semiconductor (T off ), the gate (G) of the power semiconductor (5) are electrically connected upstream, if the third turn-off speed (ASG3) is selected as the newly determined turn-off speed (ASG new ) was set. [8] Method according to one of the preceding claims, wherein by means of the selection (AW) a fourth shutdown speed (ASG4) is determined as the newly determined shutdown speed (ASG new ) is set if one of the combination options (KBM) of the temperature comparison result (RES T ) with the DC voltage comparison result (RES VDC ) the temperature (T) detected by the temperature detection (4) is greater than the reference temperature (T ref .) and the DC voltage (V DC ) is smaller than the reference DC voltage (V DC_ref .) [9] The method of claim 8, wherein a fourth gate shutdown signal (S G_off4 ) is formed by the first gate turn-off resistor (R Goff1 ) by means of the first semiconductor switch (T1), which is switched by the first switching signal (S1), electrically parallel with the third gate turn-off resistor (R Goff3 ) by connecting the second gate turn-off resistor (R Goff2 ) by means of the second semiconductor switch (T2), which is switched by the second switching signal (S2), also electrically parallel with the third gate turn-off resistor (R Goff3 ) and by connecting these gate turn-off resistors (R Goff1 , R Goff2 , R Goff3 ) as a parallel circuit, by means of the gate control signal (S on / off ) controllable gate turn-off semiconductor (T off), the gate (G) of the power semiconductor (5) are electrically connected upstream, if the fourth turn-off speed (ASG4) is determined as the newly determined turn-off speed (ASG new ) was set. [10] Method according to claim 1, wherein by means of the selection (AW) a fifth shutdown speed (ASG5) is used as the newly determined shutdown speed (ASG new ) is set if one of the combination options (KBM) of the temperature comparison result (RES T ) with the DC voltage comparison result (RES VDC ) the temperature (T) detected by the temperature detection (4) is lower than the reference temperature (T ref .) and the DC voltage (V DC ) is smaller than the reference DC voltage (V DC_ref .) or if one of the possible combinations (KBM) of the temperature comparison result (RES T) with the DC voltage comparison result (RES VDC ) the temperature (T) detected by the temperature detection (4) is lower than the reference temperature (T ref .) and the DC voltage (V DC ) is greater than the reference DC voltage (V DC_ref .) or if one of the possible combinations (KBM) of the temperature comparison result (RES T ) with the DC voltage comparison result (RES VDC ) the temperature (T) detected by the temperature detection (4) is greater than the reference temperature (T ref .) and the DC voltage (V DC ) is greater than the reference DC voltage (V DC_ref .) [11] The method of claim 10, wherein a fifth gate shutdown signal (S G_off5 ) is formed by a fifth gate turn-off resistor (R Goff5 ) by means of a gate control signal (S on / off) controllable gate turn-off semiconductor (T off ), a gate (G) of the power semiconductor (5) is electrically connected upstream, if the fifth turn-off speed (ASG5) is selected as the newly determined turn-off speed (ASG new ) was set. [12] Method according to one of claims 1 or 10 or 11, wherein by means of the selection (AW) a sixth shutdown speed (ASG6) is selected as the newly determined shutdown speed (ASG new ) is set if one of the combination options (KBM) of the temperature comparison result (RES T ) with the DC voltage comparison result (RES VDC ) the temperature (T) detected by the temperature detection (4) is greater than the reference temperature (T ref .) and the DC voltage (V DC ) is smaller than the reference DC voltage (V DC_ref .) [13] The method of claim 12, wherein a sixth gate shutdown signal (S G_off6 ) is formed by a fourth gate turn-off resistor (R Goff4 ) by means of a first semiconductor switch (T1), which is switched by a first switching signal (S1), electrically parallel with the fifth gate turn-off resistor (R Goff5 ) and by connecting these gate turn-off resistors (R Goff4 , R GDff5 ) as a parallel circuit, by means of the gate control signal (S on / off ) controllable gate turn-off semiconductor (T off ), the gate (G) of the power semiconductor (5) are electrically connected upstream, if the sixth turn-off speed (ASG6) is selected as the newly determined turn-off speed (ASG new ) was set. [14] Computing unit (7) for carrying out the method for temperature-dependent selection (AW) of turn-off speeds (ASG) for turn-off processes (AV) in power semiconductors (5) according to one of the preceding claims, comprising - a voltage input (9) for receiving the DC voltage (V DC ), - a temperature input (10) for receiving the temperature (T) detected by the temperature detection (4) and - a first switching signal output (11) for outputting a first switching signal (S1). [15] Computer program for operating the computing unit (7) according to claim 14. [16] A computer program product on which the computer program according to claim 15 is stored. [17] Control device (1) for temperature-dependent gate control for turn-off processes (AV) of power semiconductors (5), which is designed to carry out the method according to one of the preceding claims 1 to 13 with the computing unit (7) according to claim 14, at least comprising - a first switching signal input (13) for receiving a first switching signal (S1), - a gate control signal input (15) for a clocked gate control signal (S on / off ), - a gate switching signal output (16) for a gate switch-off signal (S G_off ), - a power supply with a positive voltage potential (P+) and a negative voltage potential (P-), - a gate turn-off semiconductor (T off ) and - an electrical connection (20) of gate turn-off resistors (R Goff), wherein this electrical connection (20) is electrically connected by one of its first terminals (18) to the negative voltage potential (P-) and by one of its second terminals (19) to the gate turn-off semiconductor (T off ) and is further electrically connectable to a gate (G) of the power semiconductor (5) via the gate switching signal output (16). [18] Control device (1) according to claim 17, wherein the electrical connection (20) has at least - a third gate turn-off resistor (R Goff3 ), - a first series circuit electrically connected in parallel with a second gate turn-off resistor (R Goff2 ) and a second semiconductor switch (T2) and - a second series circuit, also electrically connected in parallel, with a first gate turn-off resistor (R Goff1 ) and a first semiconductor switch (T1). [19] Control device (1) according to claim 17, wherein the electrical connection (20) has at least - a fifth gate turn-off resistor (R Goff5 ) and - a series circuit electrically connected in parallel with the fourth gate turn-off resistor (R Goff4 ) and a first semiconductor switch (T1). [20] Converter (6) with DC voltage intermediate circuit (2) at least comprising - power semiconductors (5), - a computing unit (7) according to claim 14, - a computer program according to claim 15, - a computer program product according to claim 16, - a control device (1) according to claim 17, - the temperature detection (4) and - the voltage detection (3). [21] Electric or hybrid vehicle (8), comprising a converter (6) according to claim 20 and an electric machine (17) operable by means of the converter (6).

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