Chip mounting method and chip mounting arrangement

Abstract

Chip assembly process with the steps: Providing a carrier substrate (1) having a front side (V) and a back side (R); Applying a first plurality of groups of first solder balls (L1, L2; L3, L4) to the front side (V); Applying a second plurality of chips (C1; C2) to the front side (V) using the flip-chip method, wherein a group of first solder balls (L1, L2; L3, L4) is arranged in the periphery of an associated chip; Applying an underfill (UF) to the front side (V) for at least partially underfilling the chips (C1; C2), wherein the underfill (UF) is deposited in regions on the first solder balls (L1, L2; L3, L4); Performing a plasma cleaning step for at least partially removing the underfill (UF) from the first solder balls (L1, L2; L3, L4), wherein the chips (C1; C2) remain at least partially underfilled; and Separating the chips (C1; C2) in combination with the respective group of first solder balls (L1, L2; L3, L4) and a corresponding region (1a; 1b) of the carrier substrate (1).

Description

[0001] The present invention relates to a chip mounting method and a chip mounting arrangement. State of the art

[0002] Chip mounting assemblies, in which individual chips are applied to a carrier substrate using the flip-chip process, are typically designed such that the individual chips are underfilled with an underfill, such as an epoxy, after soldering to achieve increased process robustness. This is due to a sawing process, which is intended to prevent sawdust from getting between the chips and the carrier substrate.

[0003] If solder balls are to be applied to the carrier substrate next to the applied chips, it is important to ensure that these have a certain minimum distance from the chip (typically more than 200 µm) so that the underfill cannot contaminate the solder balls, which could pose a reliability problem for the subsequent soldering process.

[0004] DE 10 2005 051 330 A1 discloses a method for producing surface-mountable semiconductor chips for circuit carriers. A semiconductor wafer is provided with semiconductor chip positions arranged in rows and columns, which have metallic contact surfaces that are operatively connected to semiconductor element structures of the semiconductor chip positions via surface-protected conductor tracks. This involves applying an electrically conductive seed layer to the top side of the semiconductor wafer, covering the seed layer with an insulating protective layer while leaving the contact surface areas exposed, and selectively depositing external contact sockets on the seed layer in the freely accessible contact surface areas. The protective layer is then removed in a plasma ashing step, followed by plasma etching of the seed layer.

[0005] US 2008 / 0 230 921 A1 discloses a semiconductor element and a method for its production, wherein a multilayer wiring connected to a first semiconductor chip is formed on a region corresponding to the first semiconductor chip formed on a substrate, and protruding plugs are subsequently applied, which are connected to the multilayer wiring. Furthermore, a second semiconductor chip is connected to the multilayer wiring, and the second semiconductor chip is sealed with a sealing material. A sealing resin can be used.

[0006] US 2004 / 0 145 051 A1 also discloses a semiconductor component and a method for its manufacture. This involves mounting a secondary chip on a base chip, and further applying a plurality of connecting contacts to the base chip. The connecting contacts are electrically connected to the secondary chip and configured as a signal transmission system. Furthermore, a plurality of terminal contacts are formed on the connecting contacts. Disclosure of the invention

[0007] The present invention provides a chip mounting method according to claim 1 and a chip mounting arrangement according to claim 11. Advantages of the invention

[0008] The idea underlying the present invention is to remove the contamination on the solder balls by underfilling in a downstream cleaning process.

[0009] A short plasma ashing step is proposed as a cleaning process, which removes a thin layer on top of the underfill without destroying the underfill matrix. Thus, the underfill remains below the chips or in the edge area of ​​the chips, so that its function as saw protection is not lost.

[0010] The invention thus makes it possible to reduce the distance between the chips and the solder balls on the carrier substrate without having to accept reliability issues. This allows for an even smaller package size (footprint) of the product in question.

[0011] Preferred further training is the subject of the subclaims.

[0012] According to a preferred embodiment, the first solder balls are applied to respective adhesion areas formed on the front side. This increases stability.

[0013] According to a further preferred embodiment, the chips are applied with a second plurality of groups of second solder balls.

[0014] According to another preferred embodiment, the underfill is applied in a dispensing process. This allows for a relatively fast process step. The use of a jet dispensing process is particularly advantageous. This allows for very precise dosing of defined quantities.

[0015] According to another preferred embodiment, the plasma cleaning step for removing the underfill results in ashing. This ensures that no residues remain.

[0016] According to another preferred embodiment, the first solder balls project beyond the chips by a predetermined distance on the front side. This is advantageous for further assembly.

[0017] According to a further preferred embodiment, the plasma cleaning step for removing the underfilling is stopped in a defined manner by an endpoint detection controlled by a spectrometer.

[0018] According to a further preferred embodiment, the separated chips are soldered onto a circuit substrate in combination with the respective group of first solder balls and the corresponding region of the carrier substrate.

[0019] According to a further preferred embodiment, the separation takes place in a sawing process. Short description of the drawings

[0020] The present invention will be explained in more detail below with reference to the exemplary embodiments shown in the schematic figures of the drawings. Fig. 1a)-e) Cross-sectional representations of successive process stages of an embodiment of the chip mounting method according to the invention. Embodiments of the invention

[0021] In the figures, the same reference symbols denote the same or functionally identical elements.

[0022] In Fig. 1a), reference numeral 1 denotes a carrier substrate with a front side V and a back side R, for example a wafer substrate.

[0023] A first plurality of groups of first solder balls L1, L2 and L3, L4 are applied to corresponding adhesion areas P1, P2, P3, P4 on the front side.

[0024] Further with reference to Fig. 1b), a second plurality of chips C1, C2 is applied to the front side V using the flip-chip process, with a group of first solder balls L1, L2 or L3, L4 being arranged in the periphery of an associated chip. These solder balls L1, L2 or L3, L4 are later used for mounting on a circuit substrate.

[0025] For this purpose, the chips C1, C2 are each soldered via a second group of smaller solder balls S1, S2 or S3, S4 onto corresponding adhesive surfaces PS1, PS2 or PS3, PS4 of the carrier substrate 1.

[0026] In process state according to Fig. 1a), the solder balls L1, L2, L3, L4 typically protrude above the mounted chips C1, C2 by a distance d1 of 50 - 80 µm and have a height of, for example, 200 to 250 micrometers. The distance between the solder balls L1, L2, L3, L4 and the respective associated chips C1 and C2 is designated by reference symbol d2 and is typically 50 - 100 µm.

[0027] In a subsequent process step, according to Fig. 1b) an underfill UF, for example, an epoxy, is applied to the front side V by dispensing or a similar process to at least partially or completely underfill the mounted chips C1, C2. The underfill UF is also deposited on the side of the chips C1, C2 facing away from the carrier substrate 1 and on the solder balls L1, L2, L3, L4.

[0028] Further with reference to Fig. 1c) This is immediately followed by a plasma ashing step PE, in which the underfill UF is removed from the first solder balls L1, L2, L3, L4 and from the chips C1, C2. Chips C1, C2 remain at least partially underfilled, so that the underfill UF', in its etched-back state, still provides protection during a subsequent singulation and assembly process. During the plasma ashing step, the surface OF of the underfill UF is slightly damaged, but its matrix remains intact.

[0029] Subsequently, according to Fig. 1d) a sawing separation process SV of the chips C1, C2 in combination with the respective group of first solder balls L1, L2 or L3, L4 and a corresponding area 1a, 1b of the carrier substrate 1. Thus, separated chips C1, C2 are present with a respective front side Va, Vb and a respective back side Ra, Rb, which can be used individually for further assembly.

[0030] As in Fig. 1e) shows the further assembly, for example, soldering onto a circuit substrate on adhesion areas P10, P20 of a circuit substrate 100. In the process state according to Fig. 1e) after mounting the chip C1 via the solder balls L1, L2 onto the circuit substrate 100, a gap SP remains between the side facing away from the carrier substrate region 1a and the circuit substrate.

[0031] Although the present invention has been fully described above using preferred embodiments, it is not limited thereto but can be modified in many ways.

[0032] In particular, the materials and geometries described are to be considered only as examples and can be varied as desired.

Claims

[1] Chip assembly process with the steps: Providing a carrier substrate (1) having a front side (V) and a back side (R); Applying a first plurality of groups of first solder balls (L1, L2; L3, L4) to the front side (V); Applying a second plurality of chips (C1; C2) to the front side (V) using the flip-chip method, wherein a group of first solder balls (L1, L2; L3, L4) is arranged in the periphery of an associated chip; Applying an underfill (UF) to the front side (V) for at least partially underfilling the chips (C1; C2), wherein the underfill (UF) is deposited in regions on the first solder balls (L1, L2; L3, L4); Performing a plasma cleaning step for at least partially removing the underfill (UF) from the first solder balls (L1, L2; L3, L4), wherein the chips (C1; C2) remain at least partially underfilled; and Separating the chips (C1; C2) in combination with the respective group of first solder balls (L1, L2; L3, L4) and a corresponding region (1a; 1b) of the carrier substrate (1). [2] A chip mounting method according to claim 1, wherein the first solder balls (L1, L2; L3, L4) are applied to respective adhesion areas (P1-P4) formed on the front side (V). [3] Chip mounting method according to claim 1 or 2, wherein the chips (C1; C2) are applied with a second plurality of groups of second solder balls (S1, S2; S3, S4). [4] Chip mounting method according to one of the preceding claims, wherein the application of the underfill (UF) takes place in a dispensing process. [5] Chip mounting method according to one of the preceding claims, wherein the application of the underfill (UF) is carried out in a jet dispensing process. [6] Chip mounting method according to one of the preceding claims, wherein the plasma cleaning step for removing the underfill (UF) results in ashing. [7] Chip mounting method according to one of the preceding claims, wherein the first solder balls (L1, L2; L3, L4) project beyond the chips (C1; C2) by a predetermined distance (d1) on the front side (V). [8] Chip mounting method according to one of the preceding claims, wherein the plasma cleaning step for removing the underfill (UF) is stopped in a defined manner by an endpoint detection controlled by a spectrometer. [9] Chip mounting method according to one of the preceding claims, wherein the separated chips (C1; C2) are soldered onto a circuit substrate (100) in combination with the respective group of first solder balls (L1, L2; L3, L4) and the corresponding region (1a; 1b) of the carrier substrate (1). [10] Chip mounting method according to one of the preceding claims, wherein the singulation is carried out in a sawing process. [11] Chip mounting arrangement with: a region (1a; 1b) of a carrier substrate (1) having a front side (Va; Vb) and a back side (Ra; Rb); a chip (C1; C2) which is applied to the front side (Va; Vb) using the flip-chip method; a group of first solder balls (L1, L2; L3, L4) arranged in the periphery of the chip (C1; C2); and an underfill (UF) on the front side (V), which at least partially underfills the chip (C1; C2); wherein the underfill (UF') has a plasma-etched surface (OF). [12] Chip mounting assembly according to claim 11, wherein the group of first solder balls (L1, L2; L3, L4) is soldered to a circuit substrate (100).

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