Method for manufacturing a silicon carbide device with a shielded gate

Abstract

A method for manufacturing a MOSFET, wherein the method comprises: Producing a silicon carbide semiconductor substrate (102) with a plurality of buried regions (104) spaced laterally apart and arranged below a main surface (105) of the silicon carbide semiconductor substrate (102), a source region (106) extending from the main surface (105) of the silicon carbide semiconductor substrate (102) to a body region (108) arranged above the buried regions (104), and contact regions (122) extending from the main surface (105) to the buried regions (104), wherein the source region (106) has a first conductivity type and the buried regions (104), the body region (108) and the contact regions (122) have a second conductivity type; Annealing of the silicon carbide semiconductor substrate (102) to activate dopant atoms in the source region (106), the body region (108) and the contact regions (122); Constructing several gate trenches (142) extending through the source area (106) and the body area (108), each having a bottom (112), the bottoms (112) of the gate trenches being arranged over a section of the buried areas (104); Performing a high-temperature step in a non-oxide-forming and a non-nitride-forming atmosphere to realign silicon carbide atoms along sidewalls (124, 144) of the gate trenches (142) and to produce rounded corners between the bottom (112) and the sidewalls (124, 144) of a gate trench (142); and Removal of a surface layer that forms during the high-temperature step along the side walls (124, 144) of the gate grooves (142) from the silicon carbide semiconductor substrate (102).

Description

[0001] The present application relates generally to the fabrication of components in silicon carbide substrates and in particular to techniques for fabricating a silicon carbide-based switching component with an electrically shielded gate structure.

[0002] Semiconductor transistors, especially field-effect controlled switching devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs), have been used in a wide variety of applications, including power supplies, power converters, electric vehicles, and air conditioning units. Many of these applications are high-power applications that require the transistors to be designed for considerable currents and / or voltages.

[0003] Power transistors capable of reverse voltage withstands of up to several hundred volts and current handling exceeding one ampere can be implemented as vertical MOS trench transistors. In a vertical transistor, a gate electrode is located in a trench extending vertically along the semiconductor body. The gate electrode is dielectrically isolated from the source region, the body region, and the drift region of the transistor and is adjacent to the body region along a lateral direction. A drain region may be adjacent to the drift region, and a source electrode may be connected to the source region.

[0004] Silicon carbide (SiC) offers certain advantageous properties as a substrate material for power transistors. The specific properties of SiC can be used to implement power transistors with a higher reverse voltage withstand capability at a given on-resistance than semiconductor devices using other substrate materials such as silicon. For example, SiC offers a critical electric field (i.e., the electric field at which an avalanche breakdown occurs) of 2 × 10 6 Volts per centimeter (V / cm), which is higher than that of conventional silicon. Therefore, a comparably designed silicon-based transistor exhibits a higher avalanche breakdown threshold than a conventional silicon-based transistor.

[0005] While silicon carbide (SiC) offers favorable breakdown voltage properties, it also presents several design challenges. For example, in a SiC-based device, the interface between the SiC and the gate dielectric (e.g., SiO2) is susceptible to thermal oxidation, leading to defects in the SiC. These defects result in reduced electron mobility and higher on-resistance. Furthermore, the corners of the gate groove in a SiC-based device are not smooth, a consequence of difficulties with groove etching techniques. Consequently, it is challenging to achieve a uniform thickness of gate dielectric in the corners of the gate groove. This, in turn, leads to increased electric fields in the corners, making the device more prone to failure.The electric field in the gate dielectric can increase by a factor of 2.5 once the electric field in the SiC is nearly equal to the critical electric field. Therefore, to fully exploit the beneficial avalanche breakdown properties of SiC, appropriate measures must be taken to shield the gate dielectric against the high voltages tolerated by the SiC material.

[0006] German patent DE 10 2013 224 134 A1 describes a method for fabricating a SiC-based power transistor. In this method, gate grooves are fabricated in a substrate such that they extend through a source region and a body region into a drift region, each bordering a semiconductor region doped complementarily to the substrate at its bottom and sidewall. A gate dielectric is fabricated in each gate groove, and a gate electrode is fabricated on the gate dielectric.

[0007] US patent 2008 / 0220620A1 describes a method for fabricating a SiC-based MOS transistor. To fabricate a gate electrode, the method includes creating a trench in a substrate and a first annealing process in an inert atmosphere and a second annealing process in a hydrogen-containing atmosphere.

[0008] US Patent 2013 / 0168701A1 describes a method for fabricating a SiC-based power transistor having a gate electrode located in a trench and partially outside the trench, mounted on a gate dielectric. The gate dielectric is thicker inside the trench than outside the trench.

[0009] Further methods for manufacturing SiC-based power transistors, each having a gate electrode arranged in a trench, are described in DE 10 2011 082 289 A1 or US 2010 / 0 006 861 A1.

[0010] The object underlying the invention is to manufacture a power transistor according to SiC technology with minimal defects in the channel region and a shielded gate structure, using minimal effort. This object is achieved by a method according to claim 1.

[0011] The process is explained below with reference to the drawings. The elements in the drawings are not necessarily to scale relative to one another. Identical reference numerals denote corresponding similar parts. The features of the various illustrated embodiments can be combined unless they are mutually exclusive. The drawings depict embodiments, which are described in detail in the following description.

[0012] Fig. Figure 1 illustrates a cross-sectional view of a vertical power transistor with a shielded gate electrode according to one embodiment.

[0013] Fig. Figure 2 illustrates a processing step for producing an oxide layer on a silicon carbide substrate according to one embodiment.

[0014] Fig. Figure 3 illustrates a processing step for masking the oxide layer of Fig. 2 according to one embodiment.

[0015] Fig. Figure 4 illustrates a processing step for etching the oxide layer according to one embodiment.

[0016] Fig. Figure 5 illustrates a processing step for producing buried doped areas in the substrate using the oxide layer as an implantation mask according to one embodiment.

[0017] Fig. Figure 6 illustrates further processing steps carried out on the substrate to create component areas and an electrical connection to the buried doped areas, according to one embodiment.

[0018] Fig. Figure 7 illustrates a processing step for producing an oxide layer over the substrate of Fig. 6 according to one embodiment.

[0019] Fig. Figure 8 illustrates a processing step for masking the oxide layer of Fig. 7 according to one embodiment.

[0020] Fig. Figure 9 illustrates a processing step for etching the oxide layer of Fig. 8 according to one embodiment.

[0021] Fig. Figure 10 illustrates a processing step for etching the substrate using the oxide layer of Fig. 9 as an etching mask to produce gate trenches, according to one embodiment.

[0022] Fig. Figure 11 illustrates a processing step for removing the oxide layer from the substrate according to one embodiment.

[0023] Fig. Figure 12 illustrates a processing step for carrying out a high-temperature step in a non-oxide and non-nitride forming atmosphere to produce rounded corners in the gate grooves, according to one embodiment.

[0024] Fig. Figure 13 illustrates an alternative design of the gate trenches according to one embodiment.

[0025] Fig. Figure 14 illustrates a processing step for producing a sacrificial oxide in the gate grooves according to one embodiment.

[0026] Fig. Figure 15 illustrates a processing step for masking the substrate in order to selectively remove sections of the sacrificial oxide, according to one embodiment.

[0027] Fig. Figure 16 illustrates the substrate after the removal of sections of the sacrificial oxide according to one embodiment.

[0028] Fig. Figure 17 illustrates further processing steps carried out on the substrate to produce a gate dielectric in the gate grooves such that the total thickness of the dielectric in the gate groove is greater at the bottom of the gate groove than along the side walls, according to one embodiment.

[0029] The embodiments disclosed herein provide a method for manufacturing a semiconductor device from a silicon carbide semiconductor substrate 102. Fig. Figure 1 shows an exemplary semiconductor device 100 that can be fabricated according to the methods described herein. The device 100 comprises a plurality of first doped regions 104, spaced apart laterally and located below a main surface 105 of the substrate 102. A second doped region 106 extends from the main surface 105 to a third doped region 108, which is located above the first doped regions 104. The second doped region 106 exhibits a first conductivity type (e.g., the n-type). The first doped regions 104 and the third doped region 108 exhibit a second conductivity type (e.g., the p-type). The device 100 further comprises a gate trench 110 that extends through the second doped region 106 and the third doped region 108 and has a bottom 112 that is positioned over a portion of one of the first doped regions 104.An electrically conductive gate electrode 114 is arranged in the gate groove 110 and is dielectrically insulated from the substrate 102 by a gate dielectric 116. A multitude of fourth-doped regions 122 extend from the main surface 105 to the first-doped regions 104. The fourth-doped regions 122 exhibit the second conductivity type and can be highly doped relative to the other regions (e.g., P++), such that the fourth-doped regions 122 are electrically conductive.

[0030] According to one embodiment, the component 100 is of Fig. Figure 1 is an n-channel MOSFET (of the depletion type), wherein the second doped region 106 is an n-source region and the third doped region 108 is a p-body (channel) region. The substrate 102 is intrinsically doped with n-dopers such that a section 118 of the substrate, located below the body region 104 and adjacent to the first doped regions 104, forms an n-drift region of the device 100. The drift region 118 is coupled (either directly or indirectly) to a more heavily doped n-drain region 120. The source region 106 and the drain region 120 can be coupled to a source and a drain potential, respectively, via external electrodes (not shown). The fourth doped regions 122 are configured as electrically conductive p-contact regions. The contact areas 122 form an ohmic connection to the first doped areas 104 and therefore allow the first doped areas 104 to be connected to an external potential (e.g. a source potential).

[0031] The gate electrode 114 is configured in a generally known manner to provide or remove an electrically conductive channel in the body region 108. A bias voltage of the gate electrode 114 relative to a source potential provides two-point control of the device 100. The first doped regions 104 are configured as buried p-regions, which shield the gate dielectric 116 from the electric fields that build up in the substrate 102 during operation of the device 100. If the device is in the OFF state and a high reverse voltage is applied to the source and drain terminals, the high reverse voltage is distributed across the drift region 118. The buried p-regions 104, together with the surrounding n-material, provide a space charge region (i.e., a depletion region). This space charge region provides a protective covering that shields the gate dielectric 116 from the large electric field in the drift region 118.Thus, by providing the buried p-regions 104 as shown, the advantageous breakdown behavior of the SiC material can be utilized, and the blocking capability of the gate dielectric 116 becomes less of a limiting factor for the overall reverse blocking capability of the device 100. In other words, the buried p-regions 104 improve the breakdown behavior of the device 100.

[0032] According to the methods described herein, the gate groove 110 can be formed such that a first side wall 124, adjacent to the channel of the device 100, is aligned with a crystal plane of the substrate 102, for example, the 11-20 crystal plane. In the SiC material, the 11-20 crystal plane offers high electron mobility compared to other crystal planes. If the channel can be designed such that carriers move in the 11-20 direction, the performance of the device 100 can therefore be improved.

[0033] Advantageously, the methods described herein employ a two-stage process to produce the gate grooves 110 such that the first sidewall 124 is closely or precisely aligned with a desired crystal plane, such as the 11-20 crystal plane. In the first step, the gate groove 110 is formed by an etching technique with masking, so that the first sidewall 124 has an angle of approximately 86 degrees relative to the main surface 105 and is approximately aligned with the 11-20 crystal plane. In the second step, the substrate 102 is exposed to a non-oxidizing and non-nitride-forming atmosphere, such as hydrogen (H2) or argon (Ar), at a high temperature (e.g., 1500 degrees Celsius) to realign silicon carbide atoms on the first sidewall 124. This brings the first sidewall 124 into closer alignment with the 11-20 crystal plane.However, this high-temperature step alters the SiC material near the first sidewall 124. The rearrangement of the silicon carbide atoms leads to a rearrangement of the dopant atoms in a surface layer of the gate groove. This surface layer is a layer of SiC material, for example, 20–40 nm thick, and extends to the surfaces of the gate groove 110, which includes the first sidewall 124. The high-temperature step can cause this surface layer to become completely undoped or at least to have a non-uniform and unpredictable doping concentration. Because the surface layer encloses the channel region of the device 100, the rearrangement of the dopant atoms associated with the high-temperature step can result in undesirable device behavior, such as increased leakage current and inaccurate threshold voltage control.

[0034] Advantageously, the methods described herein include a process step for removing the surface layer that forms during the high-temperature process step in which silicon carbide atoms are realigned on the first sidewall 124. According to one embodiment, the removal of the surface layer is carried out by oxidizing the substrate 102 to produce a sacrificial oxide layer 126, and subsequently removing the sacrificial oxide layer 126 from at least a portion of the gate grooves 110. Alternatively, techniques such as wet chemical etching can be used to remove the surface layer. As a result of removing the surface layer, the first sidewall 124 of the gate groove 110 can be formed in close or exact alignment with the 11-20 crystal plane, without the disadvantages of increased leakage current and inaccurate threshold voltage control.

[0035] A further advantage of the high-temperature step and the subsequent removal of the surface layer that forms during the high-temperature step is that the robustness of the device 100 is improved, as it is less susceptible to acute failures (e.g., due to leakage current) and permanent failures (e.g., due to dielectric breakdown). This is at least partly due to the fact that the gate groove 110 is formed with smooth surfaces and rounded transitions, so that the gate dielectric 116 has a relatively uniform thickness, and the fact that the interface between the gate dielectric 116 and the SiC material is essentially defect-free.

[0036] According to an advantageous embodiment, the gate trench 110 is formed after the buried doped regions 104 have been produced and after the source region 106, the body region 108, and the contact regions 122 have been produced. The production of these regions may require an annealing process to activate dopant atoms in the source region 106, the body region 108, and the contact regions 122. Such an annealing process may require the substrate to be exposed to temperatures between 1700 and 1800 degrees Celsius. By producing the gate trench 110 after this annealing process, the shape of the gate trench 110, and in particular the orientation of the sidewalls to a respective crystal plane, are not affected by the high temperatures required to activate the dopant atoms.

[0037] The Fig. Figures 2-17 illustrate selected process steps used to manufacture the semiconductor device 100 of Fig. 1 can be used.

[0038] With reference to Fig. 2 A silicon carbide (SiC) semiconductor substrate 102 is provided. The semiconductor substrate 102 can be formed by an epitaxial growth process. According to one embodiment, the semiconductor substrate 102 is doped with dopants of a first conductivity type (e.g., n-type dopants) during the epitaxial growth process, such that the substrate 102 has an intrinsic concentration of majority carriers of a first conductivity type.

[0039] A first dielectric layer 128 is formed along a main surface 105 of the substrate 102. The first dielectric layer 128 can be an oxide, such as SiO2. According to one embodiment, the first dielectric layer 128 is formed by depositing SiO2 on the main surface 105. The first dielectric layer 128 can be between 2 and 4 µm thick, e.g., 3 µm.

[0040] With reference to Fig. 3. A first mask 130 is formed on the first dielectric layer 128. The first mask 130 can be a photoresist mask produced using generally known techniques. The first mask 130 is structured such that sections of the first dielectric layer 128 are exposed by openings 132 in the first mask 130, and other sections of the first dielectric layer 128 are covered by the first mask 130.

[0041] With reference to Fig. 4. The unmasked sections of the first dielectric layer 128 are removed. This can be accomplished using wet or dry etching techniques. The etching is carried out such that the main surface 105 of the substrate 102 is exposed by openings 134 in the first dielectric layer 128.

[0042] With reference to Fig. In step 5, a plurality of first doped regions 104 are formed in the substrate 102. The first doped regions 104 are laterally spaced apart and are located below the main surface 105 of the substrate 102. The first doped regions 104 are formed by implanting dopant atoms into the substrate 102. The dopant atoms have a second conductivity type that is opposite to the conductivity type of the substrate 102, i.e., the first conductivity type. The first dielectric layer 128 prevents the dopant atoms from penetrating the sections of the substrate 102 that are covered by the first dielectric layer 128. That is, the first dielectric layer 128 is used as an implantation mask, with the openings 134 in the first dielectric layer 128 defining the shape of the first doped regions 104.According to one embodiment, the first doped region 104 is doped with a dopant concentration that increases with its distance from the main surface 105. That is, the doping concentration of the first doped region 104 is much higher at the bottom than at the top. This profile prevents the dopants in the first doped region 104 from affecting the body region 108, which is produced immediately above the first doped region 104 and has the same conductivity profile.

[0043] With reference to Fig. In step 6, the first dielectric layer 128 was removed, and further processing steps were carried out on the substrate 102. These further processing steps include the fabrication of the second doped region 106 and the third doped region 108 in the substrate 102, as well as the fabrication of a plurality of the fourth doped regions 122. The second doped region 106, the third doped region 108, and the fourth doped regions 122 can each be fabricated by ion implantation. A doping concentration of the fourth doped regions 122 can be selected such that these regions 122 are electrically conductive and form an ohmic connection to the first doped regions 104. The fourth doped regions 122 are, for example, possibly P++ regions.After dopant atoms of the first and second conductivity types have been implanted into substrate 102 to create these regions, substrate 102 can, for example, be annealed at a temperature between 1700 and 1800 degrees Celsius to activate the dopant atoms.

[0044] With reference to Fig. 7. A second dielectric layer 136 is formed along the main surface 105 of the substrate 102. According to one embodiment, the second dielectric layer 136 is formed by depositing SiO2 on the main surface 105. The thickness of the second dielectric layer 136 can be selected to achieve the required depth of the gate trenches 110. For example, the dielectric layer 136 can be produced with a thickness of at least 1.5 µm to provide a gate trench 100 that is 1.0 µm deep. This provides a buffer thickness for the dielectric layer 136 in the event that the substrate 102 cannot be selectively etched to the dielectric layer 136.

[0045] With reference to Fig. In step 8, a second mask 138 is formed on the second dielectric layer 136. The second mask 138 can be a photoresist mask produced using generally known techniques. The second mask 138 is structured such that sections of the second dielectric layer 136 are exposed by openings 140 in the second mask 138, and other sections of the second dielectric layer 136 are covered by the second mask 138.

[0046] With reference to Fig. 9. The unmasked sections of the second dielectric layer 136 are removed. This can be accomplished using wet or dry etching techniques. The etching is performed such that the main surface 105 of the substrate 102 is exposed by openings 142 in the second dielectric layer 136. According to one embodiment, the etching process is an anisotropic etching process in which the sidewalls of the second dielectric layer 136 are substantially perpendicular to the main surface 105. This allows for a close correlation between the structuring of the second mask 138 and the shape of the sections of the substrate 102 exposed by the openings 142.

[0047] With reference to Fig. In step 10, the second mask 138 is removed, and the exposed sections of substrate 102 are etched to create gate grooves 110 in substrate 102. That is, the second dielectric layer 136 is used as an etching mask for the production of the gate grooves 110. The gate grooves 110 are formed by etching away a section of substrate 102 that includes the second doped region 106, 108. Additionally, during the etching of the gate grooves 110, an upper section of one of the first doped regions 104 is removed. According to one embodiment, the gate grooves 110 are formed by an anisotropic dry etching technique.

[0048] The gate trench 110 comprises a first side wall 124 and a second side wall 144 extending through the second and third doped areas 106, 108, and a base 112 situated over a section of one of the first doped areas 104. The first side wall 124 extends through the second and third doped areas 106, 108 in a lateral subsection of the substrate 102, located between adjacent first doped areas 104, to a first lower corner 148 situated between adjacent first doped areas 104. The second side wall 144 extends through the second and third doped areas 106, 108 in a lateral subsection of the substrate 102, partially overlapping with one of the first doped areas 104, to a second lower corner 150 situated within one of the first doped areas 104.In other words, the gate trench 110 can be formed such that the soil 112 extends through the n-drift region 118 and one of the buried p-regions 104. The soil 112 can also extend through the contact region 122. Alternatively, the contact region 122 can be located beyond a lateral end of the gate trench 110, so that the contact region 122 is connected only to the first doped region 104 in a lateral section of the substrate 102 that does not overlap with the gate trench 110.

[0049] According to one embodiment, the substrate 102 is etched such that, within the manufacturing tolerances of the etching process, the first side wall 124 of the gate groove 110 is aligned approximately with a crystal plane of the substrate 102. For example, the substrate 102 may be etched such that the first side wall 124 has an angle of approximately 86 degrees relative to the main surface 105 and / or the bottom 112 of the gate groove 110. This orientation is in Fig. Figure 11 shows that in this embodiment, the first sidewall 124 is not perpendicular to the main surface 105 of the substrate 102 or to the bottom 112 of the gate trench 110 (if the bottom 112 is perpendicular to the main surface 105), but is offset by an angle of approximately 4 degrees to a perpendicular plane. This 86-degree angle results in the first sidewall 124 being aligned approximately with the 11-20 crystal plane of the substrate 102. The 11-20 crystal plane offers higher electron mobility compared to other crystal planes, such as the 1-100 or 1-120 planes. Thus, by manufacturing the gate trench 110 such that the first sidewall 124 is aligned approximately with the 11-20 crystal plane, the performance of the device (e.g., the on-resistance) can be improved.

[0050] Due to tolerances in the etching process, it is not possible to produce the first sidewall 124 at exactly an 86-degree angle relative to the main surface 105 (and therefore exactly along the 11-20 crystal plane). Known etching techniques only allow a process window of + / - 1 degree. This means that, within the achievable process window, the first sidewall 124 can be oriented at any angle from 85 to 87 degrees relative to the main surface 105. Furthermore, the etching process offers only limited possibilities for optimizing the shape of the first corner 148 and the second corner 150. As in Fig. As shown in Figure 10, the angles at the first corner 148 and the second corner 150 are abrupt, so that the surface of the gate trench 110 is not smooth near the first corner 148 and the second corner 150. That is, the first side wall 124, the second side wall 144, and the bottom 112 of the gate trench 110 deviate from their respective planes near the first corner 148 and the second corner 150. Fig. Figure 10 shows two notch-shaped areas at the first corner 148 and the second corner 150 as examples. This shape is not conducive to the fabrication of a gate dielectric (e.g., SiO2) in the gate groove 110. It may be difficult or impossible to produce an oxide near the first corner 148 and the second corner 150. Thus, the gate dielectric 116 may be thinner at the first corner 148 and the second corner 150, increasing the probability of device failure (e.g., due to leakage currents or dielectric breakdown). In conclusion, relying solely on an etching technique to fabricate the gate groove 110 without further measures results in a less than optimal shape for the gate groove 110.

[0051] With reference to Fig. 12. The substrate 102 was exposed to a non-oxide- and non-nitride-forming atmosphere at a high temperature to align the first sidewall 124 more closely with the 11-20 crystal plane. This can be achieved by specifying the time, temperature, and atmosphere of the high-temperature step. According to one embodiment, the substrate 102 is exposed to a hydrogen (H2) or argon (Ar) atmosphere for approximately five to seven minutes at a temperature between 1400 and 1600 degrees Celsius. For example, the substrate 102 may be exposed to a hydrogen (H2) atmosphere for six minutes at a temperature of 1500 degrees Celsius.

[0052] The high-temperature step, in which the substrate 102 is exposed to a non-oxide- and non-nitride-forming atmosphere as described above, triggers the realignment of silicon carbide atoms along the surfaces of the gate groove 110. The silicon carbide atoms realign such that the first sidewall 124 extends uniformly along the 11-20 crystal plane. Furthermore, this realignment causes a rounding of the first corner 148 and the second corner 150, so that the notched areas that were in Fig. Figure 10 is shown and eliminated. In other words, there is a curved transition between the first side wall 124 or the second side wall 144 and the bottom 112 of the gate trench 110. If the first corner 148 and the second corner 150 are rounded, oxide can be deposited more easily there than in the notch shapes shown in Fig. Figure 10 illustrates this, and therefore this enables the production of a uniformly thick gate dielectric 116 at the first corner 148 and the second corner 150. Thus, the electric field peaks occurring in the gate dielectric 116 at the first corner 148 and the second corner 150 can be reduced. In summary, the high-temperature step improves the process window for producing the first side wall 124 at precisely an 86-degree angle relative to the main surface 105 (and therefore precisely along the 11-20 crystal plane) and additionally improves the shape of the first corner 148 and the second corner 150 for the production of the gate dielectric 116.

[0053] Fig. Figure 13 depicts an alternative embodiment in which the gate trench 110 is constructed such that both the first side wall 124 and the second side wall 144 extend through the second doped region 106 and the third doped region 108 in a lateral section of the substrate 102 located between adjacent first doped regions 104. That is to say, in comparison to the gate trench 110 of the Fig. 9-12 is the gate trench 110 of Fig. 13 is shifted laterally, so that the first side wall 124 and the second side wall 144 each extend into the n-drift area 118 and are spaced apart from the buried doped areas 104. Thus, the entire gate trench 110 is formed in a lateral section of the substrate 102, which is located between adjacent buried doped areas 104.

[0054] The design of the Gategraben 110 by Fig. Figure 13 enables the production of a channel of the component 100 along both the first side wall 124 and the second side wall 144. In this embodiment, the first side wall 124 and the second side wall 144 must be formed along a different crystal plane than the 11-20 crystal plane. In particular, the gate channel 110 can be formed such that the first side wall 124 is aligned with the 1-100 crystal plane of the substrate 102 and the second side wall 144 is aligned with the -1100 crystal plane of the substrate 102. This is achieved by etching the substrate 102 as described above, such that both the first side wall 124 and the second side wall 144 have angles of approximately 90 degrees (i.e., are perpendicular) to the main surface 105. This etching technique, like the one described above, is subject to limitations insofar as an angle of exactly 90 degrees cannot be achieved and the angle can deviate by + / - 1 degree.Subsequently, a high-temperature process is carried out in which the substrate 102 is exposed to a non-oxide- and non-nitride-forming atmosphere as described above (e.g., by exposing the substrate 102 to a hydrogen (H2) atmosphere at a temperature of 1500 degrees Celsius for six minutes). During this high-temperature step, the first side wall 124 and the second side wall 144 are pressed tightly or exactly at the 1-100 and 1-100 respectively. aligned with the -1100 crystal plane. Furthermore, in this high-temperature step, the rounded first and second corners 148, 150 are produced, as previously discussed.

[0055] With reference to Fig. 14. After the production of the gate trench 110 and the high-temperature step, the substrate 102 is oxidized, e.g., by thermal oxidation. This produces a sacrificial oxide layer 126. The sacrificial oxide layer 126 is formed in at least one section of the gate trench 110. According to one embodiment, the entire substrate 102 is thermally oxidized so that the sacrificial oxide layer 126 forms along the main surface 105 and throughout the entire gate trench 110. The sacrificial oxide layer 126 is sufficiently thick (e.g., at least 30 nm thick) to enclose the surface layer that forms during the high-temperature step. Thus, the sacrificial oxide layer 126 can be used to remove the surface layer that forms in the gate trench 110 during the high-temperature step.

[0056] The Fig. Figures 15-16 illustrate further processing steps from the perspective of a top view of the substrate 102 that can be carried out to remove the sacrificial oxide layer 126 from at least one section of the gate trench 110. Fig. Figure 15 shows a top view of the substrate 102, in which a plurality of the gate trenches 110 are arranged in a cell field. The cell field is spaced from an edge of the substrate 102. As in Fig. As shown in Figure 15, a mask 152 is provided over a section of the substrate that partially overlaps the cell field. The mask 152 can, for example, be any conventional, known photolithography mask. According to one embodiment, the mask 152 is formed on the substrate 102 such that it covers lateral ends of the gate trench 110 and exposes a central partial section 154 of the gate trench 110 between the lateral ends.

[0057] With reference to Fig. In step 16, the sacrificial oxide layer 126 is removed from the unmasked sections of the substrate 102, and then the mask 152 is removed. The sacrificial oxide layer 126 can be removed, for example, by a wet chemical etching technique.

[0058] Due to the mask design of Fig. In configuration 15, where the lateral ends of the gate trench are covered by the mask 152, the sacrificial oxide 126 is etched only from the central subsection 154 of the gate trenches 110. The lateral ends of the gate trenches 110 (i.e., the two ends of the gate trench 110 that are opposite each other and located outside the central subsection 154) remain lined with the sacrificial oxide layer 126 after the etching process. By retaining the sacrificial oxide layer 126 at the lateral ends of the gate trenches 110, the reliability and robustness of the device 100 are improved. This is because it is difficult or impossible to produce the gate dielectric 116 with a uniform thickness at the lateral ends of the gate trenches 110. This results in field peaks occurring in the gate dielectric 116 at the lateral ends of the gate grooves 110, which in turn make the component more susceptible to leakage currents and / or breakdowns.By retaining the sacrificial oxide layer 126 at the lateral ends of the gate channels 110, the thickness of the dielectric is increased, enabling the device to withstand larger electric fields. Furthermore, the inclusion of the sacrificial oxide layer 126 in the device 100 does not significantly impair the switching capability of the device 100, since it is absent along a large portion of the channel region of the device 100.

[0059] According to another embodiment, the sacrificial oxide layer 126 is completely removed from the gate grooves 110. In this embodiment, the mask 152 does not cover any part of the lateral ends of the gate grooves 110, so that the entire sacrificial oxide layer 126 is etched away during the etching process.

[0060] With reference to Fig. In the gate groove 110, a gate dielectric 116 is formed. According to one embodiment, the gate dielectric 116 is formed by depositing a layer of silicon dioxide (SiO2). One deposition technique may be preferred over others, such as thermal oxidation, which can exhibit different oxide growth rates along different crystal planes (e.g., between a crystal plane of the bottom of the gate groove 110 and a crystal plane of the first side wall 124 and the second side wall 144). The gate dielectric 116 can be deposited anywhere in the gate groove 110 after the sacrificial oxide layer 126 has been etched only from the central subsection 154 as described above.This results in the gate dielectric 116 being directly adjacent to the bottom 112 and the side walls 124, 144 of the gate trench 110 in the central section, and the sacrificial oxide layer 126 being inserted between the bottom 112 and the side walls 124, 144 and the gate dielectric 126 at the lateral ends of the gate trench 110.

[0061] According to one embodiment, the gate dielectric 116 comprises two layers 1161 and 1162. A first dielectric layer 1161 is formed only along the bottom 112 of the gate groove 110 and not along the side walls 124, 144. This configuration can be achieved using a high-density plasma (HDP) deposition process, in which oxide is first deposited throughout the gate groove 110 and then removed from the side walls 124, 144 of the gate groove 110. Subsequently, a second dielectric layer 1162 is deposited in the gate groove 110 above the first dielectric layer 1161 and along the side walls 124, 144. By forming the gate dielectric 116 with the two layers 1161 and 1162 as described above, the total thickness of the dielectric in the gate trench 110 is greater at the bottom 112 of the gate trench 110 than along the side walls 124, 144.Therefore, the gradient of the electric field in the section of gate trench 110, which is exposed to the high electric fields of the SiC material, can be reduced.

[0062] Then this can be done in Fig. The substrate 102 shown in Figure 17 is annealed in a gas atmosphere to passivate an interface between the gate dielectric 116 and the silicon carbide semiconductor substrate 102. For example, the substrate 102 may be exposed to a nitrogen monoxide (NO) atmosphere for five minutes to six hours at a temperature between 1100 and 1250 degrees Celsius.

[0063] The gate electrode 114 can be formed in a conventional, known way in the gate groove 116.

[0064] In this description, n-doped is referred to as the first conductivity type, while p-doped is referred to as the second conductivity type. Alternatively, the semiconductor device 100 can be fabricated with opposite doping relationships, so that the first conductivity type can be p-doped and the second conductivity type n-doped. Furthermore, some figures illustrate relative doping concentrations, for which "-" or "+" is indicated next to the conductivity type. For example, "n" denotes - “a doping concentration that is lower than the doping concentration of an “n” doping area, while an “n +The “-doping region has a higher doping concentration than the “n” doping region. However, specifying the relative doping concentration does not mean that doping regions with the same relative doping concentration must also have the same absolute doping concentration, unless otherwise stated. For example, two different n + -Doped areas may exhibit different absolute doping concentrations. The same applies, for example, to an n + -Doping area and a p + -Doping area.

[0065] The specific embodiments described herein relate, but are not limited to, semiconductor devices, in particular semiconductor field-effect transistors, and manufacturing processes for them. In this patent specification, the terms "semiconductor device" and "semiconductor component" are used synonymously. The semiconductor device formed may be a vertical semiconductor device, such as a vertical MOSFET, with a source metallization arranged on the first surface, an insulated gate electrode arranged in a vertical trench adjacent to the first surface, and a drain metallization arranged on a second surface opposite the first surface. The semiconductor device formed may be a power semiconductor device having an active area with a plurality of MOSFET cells for conducting and / or controlling a load current.Furthermore, the power semiconductor device can typically have a peripheral area with at least one edge termination structure that at least partially surrounds the active area in the top view.

[0066] The following numbered examples reproduce some of the examples described herein.

[0067] Example 1. Method for fabricating a semiconductor device comprising: fabricating a silicon carbide semiconductor substrate with a plurality of first doped regions spaced laterally apart and below a major surface of the substrate, a second doped region extending from the major surface to a third doped region above the first doped regions, and a plurality of fourth doped regions in the substrate extending from the major surface to the first doped regions, wherein the second doped regions have a first conductivity type and the first doped regions, the third doped region, and the fourth doped regions have a second conductivity type; annealing the substrate to activate dopant atoms in the second doped region, the third doped region, and the fourth doped regions;Creating a gate trench extending through the second doped region and the third doped region, with a bottom positioned over a section of one of the first doped regions; performing a high-temperature step in a non-oxide- and non-nitride-forming atmosphere to realign silicon carbide atoms along the gate trench sidewalls and create rounded corners between the bottom and the gate trench sidewalls; and removing a surface layer that forms along the gate trench sidewalls during the high-temperature step from the substrate.

[0068] Example 2. Method according to Example 1, wherein the removal of the surface layer comprises: oxidizing the surface layer to produce a sacrificial oxide layer in the gate trench; and removing the sacrificial oxide layer from at least one section of the gate trench.

[0069] Example 3. Method according to Example 2, wherein the oxidizing of the surface layer comprises lining the entire gate trench with the sacrificial oxide layer, and wherein the removal of the sacrificial oxide layer comprises removing the sacrificial oxide layer only from a central subsection of the gate trench, such that lateral ends of the gate trench are lined by the sacrificial oxide layer after the sacrificial oxide layer has been removed.

[0070] Example 4. Method according to Example 3, wherein the removal of the sacrificial oxide layer only involves: producing a mask on the substrate covering the lateral ends of the gate trench and exposing the central section; and etching the sacrificial oxide from the central section.

[0071] Example 5. Method according to Example 3, further comprising: depositing a gate dielectric throughout the gate trench after the sacrificial oxide layer has been removed, such that the gate dielectric is directly adjacent to the bottom and side walls of the gate trench in the central subsection and such that the sacrificial oxide layer is inserted between the bottom and side walls and the gate dielectric at the lateral ends of the gate trench; and annealing the substrate in a gas atmosphere to passivate an interface between the gate dielectric and the silicon carbide semiconductor substrate.

[0072] Example 6. Method according to Example 5, wherein the deposition of the gate dielectric comprises: producing a first dielectric layer only along the bottom of the gate trench; and producing a second dielectric layer over the first dielectric layer and along the side walls, such that the total thickness of the dielectric in the gate trench is greater at the bottom of the gate trench than along the side walls.

[0073] Example 7. Method according to Example 2, wherein the oxidizing of the surface layer comprises lining the entire gate trench with the sacrificial oxide layer, and wherein the removal of the sacrificial oxide layer comprises the complete removal of the sacrificial oxide layer from the gate trench.

[0074] Example 8. Method according to one of the preceding examples, wherein the first doped regions are produced by implanting dopant atoms into the substrate, and wherein the gate trench is produced after the implantation of the dopant atoms.

[0075] Example 9. Method according to Example 8, wherein the preparation of the first doped regions comprises the preparation of a first mask on the substrate, and wherein the preparation of the gate trench comprises the preparation of a second mask on the substrate after the removal of the first mask and etching off a section of the substrate that includes the second doped region and the third doped region.

[0076] Example 10. Method according to Example 9, wherein the substrate is etched such that, within the limits of manufacturing tolerances in the etching process, a first side wall of the gate trench is approximately aligned with a crystal plane of the substrate, and wherein the time, temperature and atmosphere of the high-temperature step are controlled such that the first side wall is aligned more closely with the crystal plane.

[0077] Example 11. Method according to Example 10, wherein the substrate is etched such that the first sidewall has an angle of approximately 86 degrees relative to the main surface in order to be aligned approximately with an 11-20 crystal plane of the substrate, and wherein the high-temperature step comprises exposing the substrate to a hydrogen or argon atmosphere at a temperature between 1400 and 1600 degrees Celsius for approximately five to seven minutes in order to align the first sidewall more closely with the 11-20 crystal plane.

[0078] Example 12. Method according to Example 11, wherein the gate trench is produced such that the first side wall extends to a first lower corner which is between adjacent of the first doped areas, and that the second side wall extends to a second lower corner which is located within one of the first doped areas.

[0079] Example 13. Method according to Example 10, wherein the substrate is etched such that the first side wall of the gate trench is aligned approximately with the 1-100 crystal plane of the substrate and the second side wall is aligned approximately with the -1100 crystal plane of the substrate, and wherein the time, temperature and atmosphere of the high-temperature step are controlled such that the first and second side walls are aligned more closely with the 1-100 and -1100 crystal planes, respectively.

[0080] Example 14. Method according to Example 13, wherein the entire gate trench is produced in a lateral subsection of the substrate that is between adjacent of the first doped areas, such that both the first and the second side wall are spaced away from the first doped areas.

[0081] Example 15. Method according to one of the preceding examples, wherein the gate trench is produced after annealing the substrate in order to activate dopant atoms in the second doped region, in the third doped region and in the fourth doped regions.

[0082] Example 16. Method for fabricating a semiconductor device from a silicon carbide semiconductor substrate of a first conductivity type having a main surface, the method comprising: fabricating a plurality of buried regions of a second conductivity type below the main surface, spaced laterally apart from one another; fabricating a source region of a first conductivity type and a body region of a second conductivity type in the substrate, the source region extending from the main surface to the body region, the body region being located above the buried regions; fabricating contact regions of a second conductivity type in the substrate, extending from the main surface to the buried regions of a second conductivity type; annealing the substrate to activate dopant atoms in the source region, the body region, and the contact regions;Creating a gate trench extending through the source region and the body region, with a bottom positioned over a section of the buried regions; performing a high-temperature step in a non-oxide- and non-nitride-forming atmosphere to realign silicon carbide atoms along the gate trench sidewalls and create rounded corners between the bottom and the gate trench sidewalls; and removing a surface layer that forms along the gate trench sidewalls during the high-temperature step from the substrate.

[0083] Example 17. Method according to Example 16, wherein the removal of the surface layer comprises: oxidizing the surface layer to produce a sacrificial oxide layer in the gate trench; and removing the sacrificial oxide layer from at least one section of the gate trench.

[0084] Example 18. Method according to Example 16, wherein the gate trench is produced after annealing the substrate in order to activate dopant atoms in the source region, the body region and the contact regions.

Claims

[1] Method for manufacturing a MOSFET, wherein the method comprises: Producing a silicon carbide semiconductor substrate (102) with a plurality of buried regions (104) spaced laterally apart and arranged below a main surface (105) of the silicon carbide semiconductor substrate (102), a source region (106) extending from the main surface (105) of the silicon carbide semiconductor substrate (102) to a body region (108) arranged above the buried regions (104), and contact regions (122) extending from the main surface (105) to the buried regions (104), wherein the source region (106) has a first conductivity type and the buried regions (104), the body region (108) and the contact regions (122) have a second conductivity type; Annealing of the silicon carbide semiconductor substrate (102) to activate dopant atoms in the source region (106), the body region (108) and the contact regions (122); Constructing several gate trenches (142) extending through the source area (106) and the body area (108), each having a bottom (112), the bottoms (112) of the gate trenches being arranged over a section of the buried areas (104); Performing a high-temperature step in a non-oxide-forming and a non-nitride-forming atmosphere to realign silicon carbide atoms along sidewalls (124, 144) of the gate trenches (142) and to produce rounded corners between the bottom (112) and the sidewalls (124, 144) of a gate trench (142); and Removal of a surface layer that forms during the high-temperature step along the side walls (124, 144) of the gate grooves (142) from the silicon carbide semiconductor substrate (102). [2] The method of claim 1, wherein the removal of the surface layer comprises: Oxidizing the surface layer to produce a sacrificial oxide layer (126) in the gate grooves (142); and Removal of the sacrificial oxide layer (126) from at least one section of the gate trenches (142). [3] Method according to claim 2, in which the oxidation of the surface layer involves lining each entire gate trench (142) with the sacrificial oxide layer (126), and in which the removal of the sacrificial oxide layer (126) involves the removal of the sacrificial oxide layer (126) only from a central section of the gate trench (126), so that lateral ends of the gate trench are lined by the sacrificial oxide layer (126) after the sacrificial oxide layer (126) has been removed. [4] The method of claim 3, wherein the removal of the sacrificial oxide layer (126) comprises only the removal of the middle subsection: Producing a mask (152) on the silicon carbide semiconductor substrate (102) that covers the lateral ends of the respective gate groove (142) and exposes the central section; and Etching off the sacrificial oxide layer (126) from the middle section. [5] The method of claim 3, further comprising: Deposition of a gate dielectric (116) throughout the respective gate trench (142) after the sacrificial oxide layer (126) has been removed, such that the gate dielectric (116) is directly adjacent to the bottom (112) and the side walls (124, 144) of the gate trench (142) in the central section, and such that the sacrificial oxide layer (126) is inserted between the bottom (112) and the side walls (124, 144) and the gate dielectric (116) at the lateral ends of the gate trench (142); and Annealing the silicon carbide semiconductor substrate (102) in a gas atmosphere to passivate an interface between the gate dielectric (116) and the silicon carbide semiconductor substrate (102). [6] Method according to claim 5, wherein the deposition of the gate dielectric (116) comprises: Establishing a first dielectric layer (1161) only along the bottom (112) of the respective gate trench (142); and Producing a second dielectric layer (1162) over the first dielectric layer (1161) and along the side walls (124, 144), so that the total thickness of the gate dielectric (116) at the bottom of the gate trench (142) is greater than along the side walls (124, 144). [7] Method according to claim 2, wherein the oxidizing of the surface layer comprises lining each entire gate trench (142) with the sacrificial oxide layer (126), and wherein the removal of the sacrificial oxide layer (126) comprises the complete removal of the sacrificial oxide layer (126) from the gate trench (142). [8] Method according to any one of claims 1 to 7, in which the buried areas (104) are produced by implanting dopant atoms into the silicon carbide semiconductor substrate (102), and in which the gate grooves (142) are produced after the implantation of the dopant atoms. [9] Method according to claim 8, in which the production of the buried areas (104) involves the production of a first mask (128) on the silicon carbide semiconductor substrate (102), and in which the production of the gate trenches (142) involves the production of a second mask (136) on the silicon carbide semiconductor substrate (102) after the removal of the first mask (128) and etching off a section of the silicon carbide semiconductor substrate (102) which includes the source region (106) and the body region (108). [10] Method according to claim 9, in which the silicon carbide semiconductor substrate (102) is etched such that, within the limits of manufacturing tolerances during the etching process, a first side wall (124) of the gate grooves (142) is aligned approximately with a crystal plane of the silicon carbide semiconductor substrate (102), and in which the time, temperature and atmosphere of the high-temperature step are controlled such that the first side wall (124) is aligned more closely to the crystal plane. [11] Method according to claim 10, in which the silicon carbide semiconductor substrate (102) is etched such that the first side wall (124) has an angle of approximately 86 degrees relative to the main surface (105) in order to be approximately aligned with an 11-20 crystal plane of the substrate, and in which the high-temperature step involves exposing the silicon carbide semiconductor substrate (102) to a hydrogen or argon atmosphere at a temperature between 1400 and 1600 degrees Celsius for approximately five to seven minutes in order to align the first side wall (124) more closely with the 11-20 crystal plane. [12] Method according to claim 11, wherein the gate trenches (142) are produced such that the first side wall (124) extends to a first lower corner (148) arranged between adjacent of the buried areas (104), and that the second side wall (144) extends to a second lower corner (150) arranged within one of the buried areas (104). [13] Method according to claim 10, in which the silicon carbide semiconductor substrate (102) is etched such that the first side wall (124) of the gate grooves (142) is aligned approximately with a 1-100 crystal plane of the substrate and the second side wall is aligned approximately with the -1100 crystal plane of the silicon carbide semiconductor substrate (102), and in which the time, temperature and atmosphere of the high-temperature step are controlled so that the first and second sidewalls (124, 144) are more closely aligned with the 1-100 and -1100 crystal planes, respectively. [14] Method according to claim 13, wherein an entire gate trench (142) is produced in a lateral subsection of the silicon carbide semiconductor substrate (102) which is arranged between adjacent of the buried areas (104), such that both the first and the second side wall (124, 144) are spaced apart from the buried areas (104). [15] Method according to any one of claims 1 to 14, wherein the gate grooves (142) are produced after annealing the silicon carbide semiconductor substrate (102) to activate dopant atoms in the source region (106), in the body region (108) and in the contact regions (122).

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